diff options
Diffstat (limited to 'core/cortex-m0')
| -rw-r--r-- | core/cortex-m0/ec.lds.S | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S index 42e0b2e034..953433459a 100644 --- a/core/cortex-m0/ec.lds.S +++ b/core/cortex-m0/ec.lds.S @@ -191,16 +191,36 @@ SECTIONS . = ALIGN(4); } > FLASH __data_lma_start = . ; - - .bss : { + .vtable : { /* - * Vector table must be at the beginning of bss section. The vector + * Vector table must be at the base of SRAM. The vector * table section contains a RAM copy of the vector table used on * STM chips for relocating the vector table. */ . = ALIGN(8); - __bss_start = .; *(.bss.vector_table) + . = ALIGN(8); + } > IRAM + +#ifdef CONFIG_PRESERVE_LOGS + .preserve_logs(NOLOAD) : { + /* + * The size of the vector table is fixed. Thus, the address of + * the preserved logs is also fixed. + */ + . = ALIGN(8); + *(SORT(.preserved_logs.*)) + . = ALIGN(8); + __preserved_logs_end = .; + } > IRAM + + ASSERT((SIZEOF(.vtable) + SIZEOF(.preserve_logs) + CONFIG_RAM_BASE) == + __preserved_logs_end, "preserve_logs must be right after vtable") +#endif + + .bss : { + . = ALIGN(8); + __bss_start = .; /* Stacks must be 64-bit aligned */ . = ALIGN(8); *(.bss.system_stack) |