diff options
Diffstat (limited to 'core/riscv-rv32i/build.mk')
| -rw-r--r-- | core/riscv-rv32i/build.mk | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk index 34f059e70c..7e5ce0e8a7 100644 --- a/core/riscv-rv32i/build.mk +++ b/core/riscv-rv32i/build.mk @@ -12,8 +12,11 @@ $(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ # Enable FPU extension if config option of FPU is enabled. _FPU_EXTENSION=$(if $(CONFIG_FPU),f,) +# Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled. +_M_EXTENSION=$(if $(CONFIG_RISCV_EXTENSION_M),m,) # CPU specific compilation flags -CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os +CFLAGS_CPU+=-march=rv32i$(_M_EXTENSION)a$(_FPU_EXTENSION)c +CFLAGS_CPU+=-mabi=ilp32$(_FPU_EXTENSION) -Os # RISC-V does not trap division by zero, enable the sanitizer to check those. # With `-fsanitize-undefined-trap-on-error`, we lose a bit of specificity on the # exact issue, but the added code is as small as it gets. @@ -27,3 +30,4 @@ LDFLAGS_EXTRA+=-flto endif core-y=cpu.o init.o panic.o task.o switch.o __builtin.o math.o +core-$(CONFIG_IT8XXX2_MUL_WORKAROUND)+=__it8xxx2_arithmetic.o |