diff options
Diffstat (limited to 'core/riscv-rv32i')
-rw-r--r-- | core/riscv-rv32i/__builtin.c | 2 | ||||
-rw-r--r-- | core/riscv-rv32i/__it8xxx2_arithmetic.S | 2 | ||||
-rw-r--r-- | core/riscv-rv32i/atomic.h | 4 | ||||
-rw-r--r-- | core/riscv-rv32i/build.mk | 6 | ||||
-rw-r--r-- | core/riscv-rv32i/config_core.h | 2 | ||||
-rw-r--r-- | core/riscv-rv32i/cpu.c | 4 | ||||
-rw-r--r-- | core/riscv-rv32i/cpu.h | 8 | ||||
-rw-r--r-- | core/riscv-rv32i/ec.lds.S | 12 | ||||
-rw-r--r-- | core/riscv-rv32i/include/fpu.h | 4 | ||||
-rw-r--r-- | core/riscv-rv32i/init.S | 2 | ||||
-rw-r--r-- | core/riscv-rv32i/irq_chip.h | 2 | ||||
-rw-r--r-- | core/riscv-rv32i/irq_handler.h | 18 | ||||
-rw-r--r-- | core/riscv-rv32i/math.c | 7 | ||||
-rw-r--r-- | core/riscv-rv32i/panic.c | 96 | ||||
-rw-r--r-- | core/riscv-rv32i/switch.S | 2 | ||||
-rw-r--r-- | core/riscv-rv32i/task.c | 115 | ||||
-rw-r--r-- | core/riscv-rv32i/toolchain.mk | 7 |
17 files changed, 147 insertions, 146 deletions
diff --git a/core/riscv-rv32i/__builtin.c b/core/riscv-rv32i/__builtin.c index 4bf495a011..8e2bf984ff 100644 --- a/core/riscv-rv32i/__builtin.c +++ b/core/riscv-rv32i/__builtin.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/core/riscv-rv32i/__it8xxx2_arithmetic.S b/core/riscv-rv32i/__it8xxx2_arithmetic.S index 8e477863fc..de6dd220ad 100644 --- a/core/riscv-rv32i/__it8xxx2_arithmetic.S +++ b/core/riscv-rv32i/__it8xxx2_arithmetic.S @@ -1,5 +1,5 @@ /* - * Copyright 2022 The ChromiumOS Authors. + * Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/core/riscv-rv32i/atomic.h b/core/riscv-rv32i/atomic.h index 4d6114cd53..edd27f20e8 100644 --- a/core/riscv-rv32i/atomic.h +++ b/core/riscv-rv32i/atomic.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -53,4 +53,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk index 7e5ce0e8a7..99171a422d 100644 --- a/core/riscv-rv32i/build.mk +++ b/core/riscv-rv32i/build.mk @@ -1,15 +1,11 @@ # -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # # RISC-V core OS files build # -# Select RISC-V bare-metal toolchain -$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ - /opt/coreboot-sdk/bin/riscv64-elf-) - # Enable FPU extension if config option of FPU is enabled. _FPU_EXTENSION=$(if $(CONFIG_FPU),f,) # Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled. diff --git a/core/riscv-rv32i/config_core.h b/core/riscv-rv32i/config_core.h index fe6135683d..2adcd2783f 100644 --- a/core/riscv-rv32i/config_core.h +++ b/core/riscv-rv32i/config_core.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/core/riscv-rv32i/cpu.c b/core/riscv-rv32i/cpu.c index fd18896846..911d170801 100644 --- a/core/riscv-rv32i/cpu.c +++ b/core/riscv-rv32i/cpu.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,5 +10,5 @@ void cpu_init(void) { /* bit3: Global interrupt enable (M-mode) */ - asm volatile ("csrsi mstatus, 0x8"); + asm volatile("csrsi mstatus, 0x8"); } diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h index e46b893ad6..39ee3fe126 100644 --- a/core/riscv-rv32i/cpu.h +++ b/core/riscv-rv32i/cpu.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -25,7 +25,7 @@ /* write Exception Program Counter register */ static inline void set_mepc(uint32_t val) { - asm volatile ("csrw mepc, %0" : : "r"(val)); + asm volatile("csrw mepc, %0" : : "r"(val)); } /* read Exception Program Counter register */ @@ -33,7 +33,7 @@ static inline uint32_t get_mepc(void) { uint32_t ret; - asm volatile ("csrr %0, mepc" : "=r"(ret)); + asm volatile("csrr %0, mepc" : "=r"(ret)); return ret; } @@ -42,7 +42,7 @@ static inline uint32_t get_mcause(void) { uint32_t ret; - asm volatile ("csrr %0, mcause" : "=r"(ret)); + asm volatile("csrr %0, mcause" : "=r"(ret)); return ret; } diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S index 1e629a5779..e62a7d1427 100644 --- a/core/riscv-rv32i/ec.lds.S +++ b/core/riscv-rv32i/ec.lds.S @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -233,6 +233,10 @@ SECTIONS KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; KEEP(*(.rodata.deferred)) __deferred_funcs_end = .; @@ -334,6 +338,12 @@ SECTIONS __bss_end = .; /* + * _sbrk in newlib expects "end" symbol to point to start of + * free memory. + */ + end = .; + + /* * Shared memory buffer must be at the end of preallocated RAM, * so it can expand to use all the remaining RAM. */ diff --git a/core/riscv-rv32i/include/fpu.h b/core/riscv-rv32i/include/fpu.h index 25d83f228f..da48139d1c 100644 --- a/core/riscv-rv32i/include/fpu.h +++ b/core/riscv-rv32i/include/fpu.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,4 +10,4 @@ float sqrtf(float x); -#endif /* __CROS_EC_FPU_H */ +#endif /* __CROS_EC_FPU_H */ diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S index 8ee5479e0e..6231ad94c0 100644 --- a/core/riscv-rv32i/init.S +++ b/core/riscv-rv32i/init.S @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/core/riscv-rv32i/irq_chip.h b/core/riscv-rv32i/irq_chip.h index 45cabf346e..b45a754f45 100644 --- a/core/riscv-rv32i/irq_chip.h +++ b/core/riscv-rv32i/irq_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/core/riscv-rv32i/irq_handler.h b/core/riscv-rv32i/irq_handler.h index 6fe7769684..b980e8e0bc 100644 --- a/core/riscv-rv32i/irq_handler.h +++ b/core/riscv-rv32i/irq_handler.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,12 +20,12 @@ * Macro to connect the interrupt handler "routine" to the irq number "irq" and * ensure it is enabled in the interrupt controller with the right priority. */ -#define DECLARE_IRQ(irq, routine, priority) \ - static void __keep routine(void); \ - void IRQ_HANDLER(CPU_INT(irq))(void) \ - __attribute__ ((alias(STRINGIFY(routine)))); \ - const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \ - __attribute__((section(".rodata.irqprio"))) \ - = {CPU_INT(irq), priority} +#define DECLARE_IRQ(irq, routine, priority) \ + static void __keep routine(void); \ + void IRQ_HANDLER(CPU_INT(irq))(void) \ + __attribute__((alias(STRINGIFY(routine)))); \ + const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \ + __attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \ + priority } -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#endif /* __CROS_EC_IRQ_HANDLER_H */ diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c index 591a67eb8f..425814f185 100644 --- a/core/riscv-rv32i/math.c +++ b/core/riscv-rv32i/math.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,10 +9,7 @@ /* Single precision floating point square root. */ float sqrtf(float x) { - asm volatile ( - "fsqrt.s %0, %1" - : "=f" (x) - : "f" (x)); + asm volatile("fsqrt.s %0, %1" : "=f"(x) : "f"(x)); return x; } diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c index 5860fba072..a2ce9213d9 100644 --- a/core/riscv-rv32i/panic.c +++ b/core/riscv-rv32i/panic.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,7 +13,7 @@ /** * bit[3-0] @ mcause, general exception type information. */ -static const char * const exc_type[16] = { +static const char *const exc_type[16] = { "Instruction address misaligned", "Instruction access fault", "Illegal instruction", @@ -38,12 +38,12 @@ static const char * const exc_type[16] = { /* General purpose register (s0) for saving software panic reason */ #define SOFT_PANIC_GPR_REASON 11 /* General purpose register (s1) for saving software panic information */ -#define SOFT_PANIC_GPR_INFO 10 +#define SOFT_PANIC_GPR_INFO 10 void software_panic(uint32_t reason, uint32_t info) { - asm volatile ("mv s0, %0" : : "r"(reason) : "s0"); - asm volatile ("mv s1, %0" : : "r"(info) : "s1"); + asm volatile("mv s0, %0" : : "r"(reason) : "s0"); + asm volatile("mv s1, %0" : : "r"(info) : "s1"); if (in_interrupt_context()) asm("j excep_handler"); else @@ -58,7 +58,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) * If it was called earlier (eg. when saving riscv.mepc) calling it * once again won't remove any data */ - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); uint32_t warning_mepc; uint32_t *regs; @@ -85,7 +85,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); uint32_t *regs; if (pdata && pdata->struct_version == 2) { @@ -100,34 +100,34 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) #endif /* CONFIG_SOFTWARE_PANIC */ static void print_panic_information(uint32_t *regs, uint32_t mcause, - uint32_t mepc) + uint32_t mepc) { panic_printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause); - panic_printf("S11 %08x S10 %08x S9 %08x S8 %08x\n", - regs[0], regs[1], regs[2], regs[3]); - panic_printf("S7 %08x S6 %08x S5 %08x S4 %08x\n", - regs[4], regs[5], regs[6], regs[7]); - panic_printf("S3 %08x S2 %08x S1 %08x S0 %08x\n", - regs[8], regs[9], regs[10], regs[11]); - panic_printf("T6 %08x T5 %08x T4 %08x T3 %08x\n", - regs[12], regs[13], regs[14], regs[15]); - panic_printf("T2 %08x T1 %08x T0 %08x A7 %08x\n", - regs[16], regs[17], regs[18], regs[19]); - panic_printf("A6 %08x A5 %08x A4 %08x A3 %08x\n", - regs[20], regs[21], regs[22], regs[23]); - panic_printf("A2 %08x A1 %08x A0 %08x TP %08x\n", - regs[24], regs[25], regs[26], regs[27]); - panic_printf("GP %08x RA %08x SP %08x MEPC %08x\n", - regs[28], regs[29], regs[30], mepc); + panic_printf("S11 %08x S10 %08x S9 %08x S8 %08x\n", regs[0], + regs[1], regs[2], regs[3]); + panic_printf("S7 %08x S6 %08x S5 %08x S4 %08x\n", regs[4], + regs[5], regs[6], regs[7]); + panic_printf("S3 %08x S2 %08x S1 %08x S0 %08x\n", regs[8], + regs[9], regs[10], regs[11]); + panic_printf("T6 %08x T5 %08x T4 %08x T3 %08x\n", regs[12], + regs[13], regs[14], regs[15]); + panic_printf("T2 %08x T1 %08x T0 %08x A7 %08x\n", regs[16], + regs[17], regs[18], regs[19]); + panic_printf("A6 %08x A5 %08x A4 %08x A3 %08x\n", regs[20], + regs[21], regs[22], regs[23]); + panic_printf("A2 %08x A1 %08x A0 %08x TP %08x\n", regs[24], + regs[25], regs[26], regs[27]); + panic_printf("GP %08x RA %08x SP %08x MEPC %08x\n", regs[28], + regs[29], regs[30], mepc); #ifdef CONFIG_DEBUG_EXCEPTIONS if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) { #ifdef CONFIG_SOFTWARE_PANIC panic_printf("Software panic reason: %s\n", - panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - - PANIC_SW_BASE)]); + panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - + PANIC_SW_BASE)]); panic_printf("Software panic info: %d\n", - regs[SOFT_PANIC_GPR_INFO]); + regs[SOFT_PANIC_GPR_INFO]); #endif } else { panic_printf("Exception type: %s\n", exc_type[(mcause & 0xf)]); @@ -138,7 +138,7 @@ static void print_panic_information(uint32_t *regs, uint32_t mcause, void report_panic(uint32_t *regs) { uint32_t i, mcause, mepc; - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); mepc = get_mepc(); mcause = get_mcause(); @@ -171,36 +171,36 @@ void panic_data_print(const struct panic_data *pdata) #ifdef CONFIG_PANIC_CONSOLE_OUTPUT static void ccprint_panic_information(uint32_t *regs, uint32_t mcause, - uint32_t mepc) + uint32_t mepc) { ccprintf("=== EXCEPTION: MCAUSE=%x ===\n", mcause); - ccprintf("S11 %08x S10 %08x S9 %08x S8 %08x\n", - regs[0], regs[1], regs[2], regs[3]); - ccprintf("S7 %08x S6 %08x S5 %08x S4 %08x\n", - regs[4], regs[5], regs[6], regs[7]); - ccprintf("S3 %08x S2 %08x S1 %08x S0 %08x\n", - regs[8], regs[9], regs[10], regs[11]); - ccprintf("T6 %08x T5 %08x T4 %08x T3 %08x\n", - regs[12], regs[13], regs[14], regs[15]); - ccprintf("T2 %08x T1 %08x T0 %08x A7 %08x\n", - regs[16], regs[17], regs[18], regs[19]); + ccprintf("S11 %08x S10 %08x S9 %08x S8 %08x\n", regs[0], regs[1], + regs[2], regs[3]); + ccprintf("S7 %08x S6 %08x S5 %08x S4 %08x\n", regs[4], regs[5], + regs[6], regs[7]); + ccprintf("S3 %08x S2 %08x S1 %08x S0 %08x\n", regs[8], regs[9], + regs[10], regs[11]); + ccprintf("T6 %08x T5 %08x T4 %08x T3 %08x\n", regs[12], regs[13], + regs[14], regs[15]); + ccprintf("T2 %08x T1 %08x T0 %08x A7 %08x\n", regs[16], regs[17], + regs[18], regs[19]); cflush(); - ccprintf("A6 %08x A5 %08x A4 %08x A3 %08x\n", - regs[20], regs[21], regs[22], regs[23]); - ccprintf("A2 %08x A1 %08x A0 %08x TP %08x\n", - regs[24], regs[25], regs[26], regs[27]); - ccprintf("GP %08x RA %08x SP %08x MEPC %08x\n", - regs[28], regs[29], regs[30], mepc); + ccprintf("A6 %08x A5 %08x A4 %08x A3 %08x\n", regs[20], regs[21], + regs[22], regs[23]); + ccprintf("A2 %08x A1 %08x A0 %08x TP %08x\n", regs[24], regs[25], + regs[26], regs[27]); + ccprintf("GP %08x RA %08x SP %08x MEPC %08x\n", regs[28], regs[29], + regs[30], mepc); #ifdef CONFIG_DEBUG_EXCEPTIONS if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) { #ifdef CONFIG_SOFTWARE_PANIC ccprintf("Software panic reason: %s\n", - panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - - PANIC_SW_BASE)]); + panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - + PANIC_SW_BASE)]); ccprintf("Software panic info: %d\n", - regs[SOFT_PANIC_GPR_INFO]); + regs[SOFT_PANIC_GPR_INFO]); #endif /* CONFIG_SOFTWARE_PANIC */ } else { ccprintf("Exception type: %s\n", exc_type[(mcause & 0xf)]); diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S index f58ac26e63..f8b88f9235 100644 --- a/core/riscv-rv32i/switch.S +++ b/core/riscv-rv32i/switch.S @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c index edc31a872e..84415dcda9 100644 --- a/core/riscv-rv32i/task.c +++ b/core/riscv-rv32i/task.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,10 +6,12 @@ /* Task scheduling / events module for Chrome EC operating system */ #include "atomic.h" +#include "builtin/assert.h" #include "console.h" #include "cpu.h" #include "irq_chip.h" #include "link_defs.h" +#include "panic.h" #include "task.h" #include "timer.h" #include "util.h" @@ -19,10 +21,10 @@ typedef struct { * Note that sp must be the first element in the task struct * for __switchto() to work. */ - uint32_t sp; /* Saved stack pointer for context switch */ - atomic_t events; /* Bitmaps of received events */ - uint64_t runtime; /* Time spent in task */ - uint32_t *stack; /* Start of stack */ + uint32_t sp; /* Saved stack pointer for context switch */ + atomic_t events; /* Bitmaps of received events */ + uint64_t runtime; /* Time spent in task */ + uint32_t *stack; /* Start of stack */ } task_; /* Value to store in unused stack */ @@ -36,11 +38,9 @@ CONFIG_TEST_TASK_LIST #undef TASK /* Task names for easier debugging */ -#define TASK(n, r, d, s) #n, -static const char * const task_names[] = { - "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST +#define TASK(n, r, d, s) #n, +static const char *const task_names[] = { + "<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK @@ -48,12 +48,12 @@ static const char * const task_names[] = { static int task_will_switch; static uint32_t exc_sub_time; static uint64_t task_start_time; /* Time task scheduling started */ -static uint32_t exc_start_time; /* Time of task->exception transition */ -static uint32_t exc_end_time; /* Time of exception->task transition */ -static uint64_t exc_total_time; /* Total time in exceptions */ -static uint32_t svc_calls; /* Number of service calls */ -static uint32_t task_switches; /* Number of times active task changed */ -static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ +static uint32_t exc_start_time; /* Time of task->exception transition */ +static uint32_t exc_end_time; /* Time of exception->task transition */ +static uint64_t exc_total_time; /* Total time in exceptions */ +static uint32_t svc_calls; /* Number of service calls */ +static uint32_t task_switches; /* Number of times active task changed */ +static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif extern int __task_start(void); @@ -96,41 +96,36 @@ static void task_exit_trap(void) } /* Startup parameters for all tasks. */ -#define TASK(n, r, d, s) { \ - .a0 = (uint32_t)d, \ - .pc = (uint32_t)r, \ - .stack_size = s, \ -}, +#define TASK(n, r, d, s) \ + { \ + .a0 = (uint32_t)d, \ + .pc = (uint32_t)r, \ + .stack_size = s, \ + }, static const struct { uint32_t a0; uint32_t pc; uint16_t stack_size; -} tasks_init[] = { - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -}; +} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK /* Contexts for all tasks */ -static task_ tasks[TASK_ID_COUNT] __attribute__ ((section(".bss.tasks"))); +static task_ tasks[TASK_ID_COUNT] __attribute__((section(".bss.tasks"))); /* Validity checks about static task invariants */ BUILD_ASSERT(TASK_ID_COUNT <= (sizeof(unsigned) * 8)); BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8))); /* Stacks for all tasks */ -#define TASK(n, r, d, s) + s -uint8_t task_stacks[0 - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -] __aligned(8); +#define TASK(n, r, d, s) +s +uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8); #undef TASK /* Reserve space to discard context on first context switch. */ -uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__ - ((section(".bss.task_scratchpad"))); +uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] + __attribute__((section(".bss.task_scratchpad"))); task_ *current_task = (task_ *)scratchpad; @@ -162,7 +157,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS); */ static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE); -int start_called; /* Has task swapping started */ +int start_called; /* Has task swapping started */ /* in interrupt context */ volatile bool in_interrupt; @@ -188,22 +183,22 @@ static inline task_ *__task_id_to_ptr(task_id_t id) void __ram_code interrupt_disable(void) { /* bit11: disable MEIE */ - asm volatile ("li t0, 0x800"); - asm volatile ("csrc mie, t0"); + asm volatile("li t0, 0x800"); + asm volatile("csrc mie, t0"); } void __ram_code interrupt_enable(void) { /* bit11: enable MEIE */ - asm volatile ("li t0, 0x800"); - asm volatile ("csrs mie, t0"); + asm volatile("li t0, 0x800"); + asm volatile("csrs mie, t0"); } inline bool is_interrupt_enabled(void) { int mie = 0; - asm volatile ("csrr %0, mie" : "=r"(mie)); + asm volatile("csrr %0, mie" : "=r"(mie)); /* Check if MEIE bit is set in MIE register */ return mie & 0x800; @@ -229,7 +224,7 @@ task_id_t __ram_code task_get_current(void) return current_task - tasks; } -atomic_t * __ram_code task_get_event_bitmap(task_id_t tskid) +atomic_t *__ram_code task_get_event_bitmap(task_id_t tskid) { task_ *tsk = __task_id_to_ptr(tskid); @@ -247,7 +242,7 @@ int task_start_called(void) * Also includes emulation of software triggering interrupt vector */ void __ram_code __keep syscall_handler(int desched, task_id_t resched, - int swirq) + int swirq) { /* are we emulating an interrupt ? */ if (swirq) { @@ -279,14 +274,14 @@ void __ram_code __keep syscall_handler(int desched, task_id_t resched, set_mepc(get_mepc() + 4); } -task_ * __ram_code next_sched_task(void) +task_ *__ram_code next_sched_task(void) { task_ *new_task = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled)); #ifdef CONFIG_TASK_PROFILING if (current_task != new_task) { current_task->runtime += - (exc_start_time - exc_end_time - exc_sub_time); + (exc_start_time - exc_end_time - exc_sub_time); task_will_switch = 1; } #endif @@ -466,14 +461,14 @@ uint32_t __ram_code read_clear_int_mask(void) uint32_t mie, meie = BIT(11); /* Read and clear MEIE bit of MIE register. */ - asm volatile ("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie)); + asm volatile("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie)); return mie; } void __ram_code set_int_mask(uint32_t val) { - asm volatile ("csrw mie, %0" : : "r"(val)); + asm volatile("csrw mie, %0" : : "r"(val)); } void task_enable_all_tasks(void) @@ -553,12 +548,12 @@ void __ram_code mutex_lock(struct mutex *mtx) atomic_or(&mtx->waiters, id); while (1) { - asm volatile ( + asm volatile( /* set lock value */ "li %0, 2\n\t" /* attempt to acquire lock */ "amoswap.w.aq %0, %0, %1\n\t" - : "=&r" (locked), "+A" (mtx->lock)); + : "=&r"(locked), "+A"(mtx->lock)); /* we got it ! */ if (!locked) break; @@ -576,9 +571,7 @@ void __ram_code mutex_unlock(struct mutex *mtx) task_ *tsk = current_task; /* give back the lock */ - asm volatile ( - "amoswap.w.aqrl zero, zero, %0\n\t" - : "+A" (mtx->lock)); + asm volatile("amoswap.w.aqrl zero, zero, %0\n\t" : "+A"(mtx->lock)); waiters = mtx->waiters; while (waiters) { @@ -618,7 +611,7 @@ void task_print_list(void) } } -static int command_task_info(int argc, char **argv) +static int command_task_info(int argc, const char **argv) { #ifdef CONFIG_TASK_PROFILING unsigned int total = 0; @@ -648,11 +641,9 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, - "Print task info"); +DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); -static int command_task_ready(int argc, char **argv) +static int command_task_ready(int argc, const char **argv) { if (argc < 2) { ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready); @@ -664,8 +655,7 @@ static int command_task_ready(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, - "[setmask]", +DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]", "Print/set ready tasks"); void task_pre_init(void) @@ -688,9 +678,10 @@ void task_pre_init(void) tasks[i].sp = (uint32_t)sp; /* Initial context on stack (see __switchto()) */ - sp[TASK_SCRATCHPAD_SIZE-2] = tasks_init[i].a0; /* a0 */ - sp[TASK_SCRATCHPAD_SIZE-1] = (uint32_t)task_exit_trap; /* ra */ - sp[0] = tasks_init[i].pc; /* pc/mepc */ + sp[TASK_SCRATCHPAD_SIZE - 2] = tasks_init[i].a0; /* a0 */ + sp[TASK_SCRATCHPAD_SIZE - 1] = (uint32_t)task_exit_trap; /* ra + */ + sp[0] = tasks_init[i].pc; /* pc/mepc */ /* Fill unused stack; also used to detect stack overflow. */ for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++) diff --git a/core/riscv-rv32i/toolchain.mk b/core/riscv-rv32i/toolchain.mk new file mode 100644 index 0000000000..aa833d1ca3 --- /dev/null +++ b/core/riscv-rv32i/toolchain.mk @@ -0,0 +1,7 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Select RISC-V bare-metal toolchain +$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ + /opt/coreboot-sdk/bin/riscv64-elf-) |