diff options
Diffstat (limited to 'core')
-rw-r--r-- | core/cortex-m/task.c | 10 | ||||
-rw-r--r-- | core/cortex-m0/task.c | 10 | ||||
-rw-r--r-- | core/host/task.c | 5 | ||||
-rw-r--r-- | core/minute-ia/task.c | 12 | ||||
-rw-r--r-- | core/nds32/task.c | 10 | ||||
-rw-r--r-- | core/riscv-rv32i/task.c | 10 |
6 files changed, 57 insertions, 0 deletions
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index b88baf4511..e64063dc15 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -227,6 +227,16 @@ void interrupt_enable(void) asm("cpsie i"); } +inline int is_interrupt_enabled(void) +{ + int primask; + + /* Interrupts are enabled when PRIMASK bit is 0 */ + asm("mrs %0, primask":"=r"(primask)); + + return !(primask & 0x1); +} + inline int in_interrupt_context(void) { int ret; diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c index 16922e10eb..5c9893ace8 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c @@ -161,6 +161,16 @@ void interrupt_enable(void) asm("cpsie i"); } +inline int is_interrupt_enabled(void) +{ + int primask; + + /* Interrupts are enabled when PRIMASK bit is 0 */ + asm("mrs %0, primask":"=r"(primask)); + + return !(primask & 0x1); +} + inline int in_interrupt_context(void) { int ret; diff --git a/core/host/task.c b/core/host/task.c index 36cb3467c0..be7ed3c579 100644 --- a/core/host/task.c +++ b/core/host/task.c @@ -138,6 +138,11 @@ test_mockable void interrupt_enable(void) pthread_mutex_unlock(&interrupt_lock); } +inline int is_interrupt_enabled(void) +{ + return !interrupt_disabled; +} + static void _task_execute_isr(int sig) { in_interrupt = 1; diff --git a/core/minute-ia/task.c b/core/minute-ia/task.c index 0cdc8a41e5..fdbe37485b 100644 --- a/core/minute-ia/task.c +++ b/core/minute-ia/task.c @@ -173,6 +173,18 @@ void interrupt_enable(void) __asm__ __volatile__ ("sti"); } +inline int is_interrupt_enabled(void) +{ + uint32_t eflags = 0; + + __asm__ __volatile__ ("pushfl\n" + "popl %0\n" + : "=r"(eflags)); + + /* Check Interrupt Enable flag */ + return !!(eflags & 0x200); +} + inline int in_interrupt_context(void) { return !!__in_isr; diff --git a/core/nds32/task.c b/core/nds32/task.c index 9969db34bc..edacb7975e 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -224,6 +224,16 @@ void __ram_code interrupt_enable(void) asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); } +inline int is_interrupt_enabled(void) +{ + uint32_t val = 0; + + asm volatile ("mfsr %0, $INT_MASK" : "=r"(val)); + + /* Interrupts are enabled if any of HW2 ~ HW15 is enabled */ + return !!(val & 0xFFFC); +} + inline int in_interrupt_context(void) { /* check INTL (Interrupt Stack Level) bits */ diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c index cb9532f6dd..558177e969 100644 --- a/core/riscv-rv32i/task.c +++ b/core/riscv-rv32i/task.c @@ -199,6 +199,16 @@ void __ram_code interrupt_enable(void) asm volatile ("csrs mie, t0"); } +inline int is_interrupt_enabled(void) +{ + int mie = 0; + + asm volatile ("csrr %0, mie" : "=r"(mie)); + + /* Check if MEIE bit is set in MIE register */ + return !!(mie & 0x800); +} + inline int in_interrupt_context(void) { return in_interrupt; |