diff options
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/cpu.h | 9 | ||||
| -rw-r--r-- | core/cortex-m0/cpu.h | 4 |
2 files changed, 12 insertions, 1 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index 47c7d0bca1..4cef402f85 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -25,9 +25,16 @@ #define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) #define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x)) #define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) +/* SCB AIRCR : Application interrupt and reset control register */ #define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10)) +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) +/* NVIC STIR : Software Trigger Interrupt Register */ #define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) - +/* SCB SCR : System Control Register */ #define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) #define CPU_NVIC_CCR CPUREG(0xe000ed14) diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index 71c0ce495d..ba27c1bc82 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -26,6 +26,10 @@ /* SCB AIRCR : Application interrupt and reset control register */ #define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0U) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) /* SCB SCR : System Control Register */ #define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) #define CPU_NVIC_CCR CPUREG(0xe000ed14) |