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Diffstat (limited to 'docs/write_protection.md')
| -rw-r--r-- | docs/write_protection.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/write_protection.md b/docs/write_protection.md index 95c4bb0476..a71b3d095a 100644 --- a/docs/write_protection.md +++ b/docs/write_protection.md @@ -41,7 +41,7 @@ firmware jumps to it. On modern Chrome OS devices, the Cr50 (aka GSC / TPM) provides a "hardware write protect" GPIO that is connected to the AP SPI flash, EC SPI flash, EEPROM, and FPMCU via a [GPIO][write_protect_gpio]. This "hardware write protect" can only -be disabled with [Servo] or [SuzyQ] (["CCD open"]) and corresponds to +be disabled with [Servo] or [SuzyQ](["CCD open"]) and corresponds to [`OverrideWP`] in ccd. Disabling this write protect disables it for everything connected to this signal. |