diff options
Diffstat (limited to 'driver/als_cm32183.h')
| -rw-r--r-- | driver/als_cm32183.h | 70 |
1 files changed, 35 insertions, 35 deletions
diff --git a/driver/als_cm32183.h b/driver/als_cm32183.h index 57802e9f96..f0dbaf3c03 100644 --- a/driver/als_cm32183.h +++ b/driver/als_cm32183.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -9,27 +9,27 @@ #define __CROS_EC_ALS_CM32183_H /* I2C interface */ -#define CM32183_I2C_ADDR 0x29 +#define CM32183_I2C_ADDR 0x29 /* CM32183 registers */ -#define CM32183_REG_CONFIGURE 0x00 +#define CM32183_REG_CONFIGURE 0x00 -#define CM32183_REG_CONFIGURE_CH_EN 0x0004 +#define CM32183_REG_CONFIGURE_CH_EN 0x0004 /* ALS Sensitivity_mode (BIT 12:11) */ -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_MASK GENMASK(12, 11) -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_SHIFT 11 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1 0 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_2 1 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_8 2 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_4 3 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_MASK GENMASK(12, 11) +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_SHIFT 11 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1 0 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_2 1 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_8 2 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_4 3 /* * Gain mode * 0 Gain*1 * 1 Gain*2 (bit 10) */ -#define CM32183_REG_CONFIGURE_GAIN BIT(10) +#define CM32183_REG_CONFIGURE_GAIN BIT(10) /* * ALS integration time setting which represents how long @@ -40,12 +40,12 @@ * 0010 400ms * 0011 800ms */ -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_MASK GENMASK(9, 6) -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SHIFT 6 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET100MS 0 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET200MS 1 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET400MS 2 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET800MS 3 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_MASK GENMASK(9, 6) +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SHIFT 6 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET100MS 0 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET200MS 1 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET400MS 2 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET800MS 3 /* * ALS interrupt persistence setting.The interrupt pin is @@ -57,47 +57,47 @@ * 10 4 * 11 8 */ -#define CM32183_REG_CONFIGURE_MEASUREMENT_MASK GENMASK(5, 4) -#define CM32183_REG_CONFIGURE_MEASUREMENT_SHIFT 4 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_1 0 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_2 1 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_4 2 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_8 3 +#define CM32183_REG_CONFIGURE_MEASUREMENT_MASK GENMASK(5, 4) +#define CM32183_REG_CONFIGURE_MEASUREMENT_SHIFT 4 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_1 0 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_2 1 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_4 2 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_8 3 /* * channel selection of interrupt (BIT 3) * 0 ALS CH interrupt * 1 White CH interrupt */ -#define CM32183_REG_CONFIGURE_CHANNEL_SELECTION BIT(3) +#define CM32183_REG_CONFIGURE_CHANNEL_SELECTION BIT(3) /* * Channel enable (BIT 2) * 0 ALS CH enable only * 1 ALS & White CH enable */ -#define CM32183_REG_CONFIGURE_CHANNEL_ENABLE BIT(2) +#define CM32183_REG_CONFIGURE_CHANNEL_ENABLE BIT(2) /* enable/disable interrupt function (BIT 1) */ -#define CM32183_REG_CONFIGURE_INTERRUPT_ENABLE BIT(1) +#define CM32183_REG_CONFIGURE_INTERRUPT_ENABLE BIT(1) /* * how to power on and shutdown sensor (BIT 0) * 0 power on * 1 shutdown */ -#define CM32183_REG_CONFIGURE_POWER BIT(0) +#define CM32183_REG_CONFIGURE_POWER BIT(0) -#define CM32183_REG_INT_HSB 0x01 -#define CM32183_REG_INT_LSB 0x02 -#define CM32183_REG_ALS_RESULT 0x04 -#define CM32183_REG_WHITE_RESULT 0x05 +#define CM32183_REG_INT_HSB 0x01 +#define CM32183_REG_INT_LSB 0x02 +#define CM32183_REG_ALS_RESULT 0x04 +#define CM32183_REG_WHITE_RESULT 0x05 -#define CM32183_REG_TRIGGER 0x06 +#define CM32183_REG_TRIGGER 0x06 -#define CM32183_REG_TRIGGER_LOW_THRESHOLD BIT(15) -#define CM32183_REG_TRIGGER_HIGH_THRESHOLD BIT(14) +#define CM32183_REG_TRIGGER_LOW_THRESHOLD BIT(15) +#define CM32183_REG_TRIGGER_HIGH_THRESHOLD BIT(14) extern const struct accelgyro_drv cm32183_drv; -#endif /* __CROS_EC_ALS_CM32183_H */ +#endif /* __CROS_EC_ALS_CM32183_H */ |