diff options
Diffstat (limited to 'driver/tcpm/rt1718s.h')
| -rw-r--r-- | driver/tcpm/rt1718s.h | 60 |
1 files changed, 59 insertions, 1 deletions
diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h index 0f868f0598..daaab5935c 100644 --- a/driver/tcpm/rt1718s.h +++ b/driver/tcpm/rt1718s.h @@ -2,10 +2,10 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ - #ifndef __CROS_EC_USB_PD_TCPM_RT1718S_H #define __CROS_EC_USB_PD_TCPM_RT1718S_H +#include "usb_charge.h" #include "usb_pd_tcpm.h" /* RT1718S Private RegMap */ @@ -32,8 +32,21 @@ #define RT1718S_RT_MASK4 0x94 #define RT1718S_RT_MASK5 0x95 #define RT1718S_RT_MASK6 0x96 +#define RT1718S_RT_MASK6_M_BC12_SNK_DONE BIT(7) +#define RT1718S_RT_MASK6_M_HVDCP_CHK_DONE BIT(6) +#define RT1718S_RT_MASK6_M_BC12_TA_CHG BIT(5) #define RT1718S_RT_MASK7 0x97 +#define RT1718S_RT_INT6 0x9D +#define RT1718S_RT_INT6_INT_BC12_SNK_DONE BIT(7) +#define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE BIT(6) +#define RT1718S_RT_INT6_INT_BC12_TA_CHG BIT(5) + +#define RT1718S_RT_ST6 0xA4 +#define RT1718S_RT_ST6_BC12_SNK_DONE BIT(7) +#define RT1718S_RT_ST6_HVDCP_CHK_DONE BIT(6) +#define RT1718S_RT_ST6_BC12_TA_CHG BIT(5) + #define RT1718S_PHYCTRL9 0xAC #define RT1718S_SYS_CTRL3 0xB0 @@ -65,7 +78,52 @@ #define RT1718S_RT2_VBUS_OCP_CTRL1 0xF216 #define RT1718S_RT2_VBUS_OCP_CTRL4 0xF219 +#define RT1718S_RT2_SBU_CTRL_01 0xF23A +#define RT1718S_RT2_SBU_CTRL_01_SBU_VIEN BIT(7) +#define RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN BIT(6) +#define RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN BIT(3) +#define RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN BIT(2) +#define RT1718S_RT2_SBU_CTRL_01_DM_SWEN BIT(1) +#define RT1718S_RT2_SBU_CTRL_01_DP_SWEN BIT(0) + +#define RT1718S_RT2_BC12_SNK_FUNC 0xF260 +#define RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN BIT(7) +#define RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN BIT(6) +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK 0x30 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_DISABLE 0x00 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_300MS 0x10 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS 0x20 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_WAIT_DATA 0x30 +#define RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT BIT(3) +#define RT1718S_RT2_BC12_SNK_FUNC_VPORT_SEL BIT(2) +#define RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS BIT(1) + +#define RT1718S_RT2_BC12_STAT 0xF261 +#define RT1718S_RT2_BC12_STAT_DCDT BIT(4) +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK 0x0F +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE 0x00 +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP 0x0D +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP 0x0E +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP 0x0F + + +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET 0xF263 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK 0x03 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_55V 0x00 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_60V 0x01 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V 0x02 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_70V 0x03 + +#define RT1718S_RT2_BC12_SRC_FUNC 0xF26D +#define RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN BIT(7) +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_MASK 0x70 +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_SDP 0x00 +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_CDP 0x10 +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_DCP 0x20 +#define RT1718S_RT2_BC12_SRC_FUNC_WAIT_VBUS_ON BIT(0) + extern const struct tcpm_drv rt1718s_tcpm_drv; +extern const struct bc12_drv rt1718s_bc12_drv; int rt1718s_write8(int port, int reg, int val); int rt1718s_read8(int port, int reg, int *val); |