diff options
Diffstat (limited to 'driver/tcpm/tcpci.h')
| -rw-r--r-- | driver/tcpm/tcpci.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/driver/tcpm/tcpci.h b/driver/tcpm/tcpci.h index f0970639a8..44af755c8b 100644 --- a/driver/tcpm/tcpci.h +++ b/driver/tcpm/tcpci.h @@ -51,6 +51,7 @@ #define TCPC_REG_CONFIG_STD_OUTPUT 0x18 #define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) +#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) @@ -92,6 +93,7 @@ #define TCPC_REG_POWER_CTRL 0x1c #define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) #define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) +#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) #define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) #define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn) @@ -149,6 +151,29 @@ #define TCPC_REG_COMMAND_I2CIDLE 0xFF #define TCPC_REG_DEV_CAP_1 0x24 +#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) +#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) +#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) +#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) +#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) +#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8)|BIT(9)) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) +#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5)|BIT(6)|BIT(7)) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) +#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) +#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) +#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) +#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) +#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) #define TCPC_REG_DEV_CAP_2 0x26 #define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) |