diff options
Diffstat (limited to 'driver')
62 files changed, 833 insertions, 833 deletions
diff --git a/driver/accel_kx022.h b/driver/accel_kx022.h index 1d3e817f64..f7f2f848a8 100644 --- a/driver/accel_kx022.h +++ b/driver/accel_kx022.h @@ -75,34 +75,34 @@ #define KX022_INTERNAL 0x7f -#define KX022_CNTL1_PC1 (1 << 7) -#define KX022_CNTL1_WUFE (1 << 1) -#define KX022_CNTL1_TPE (1 << 0) +#define KX022_CNTL1_PC1 BIT(7) +#define KX022_CNTL1_WUFE BIT(1) +#define KX022_CNTL1_TPE BIT(0) /* TSCP orientations */ -#define KX022_ORIENT_PORTRAIT (1 << 2) -#define KX022_ORIENT_INVERT_PORTRAIT (1 << 3) -#define KX022_ORIENT_LANDSCAPE (1 << 4) -#define KX022_ORIENT_INVERT_LANDSCAPE (1 << 5) +#define KX022_ORIENT_PORTRAIT BIT(2) +#define KX022_ORIENT_INVERT_PORTRAIT BIT(3) +#define KX022_ORIENT_LANDSCAPE BIT(4) +#define KX022_ORIENT_INVERT_LANDSCAPE BIT(5) #define KX022_ORIENT_MASK (KX022_ORIENT_PORTRAIT | \ KX022_ORIENT_INVERT_PORTRAIT | \ KX022_ORIENT_LANDSCAPE | \ KX022_ORIENT_INVERT_LANDSCAPE) -#define KX022_CNTL2_SRST (1 << 7) +#define KX022_CNTL2_SRST BIT(7) #define KX022_CNTL3_OWUF_FIELD 7 -#define KX022_INC1_IEA (1 << 4) -#define KX022_INC1_IEN (1 << 5) +#define KX022_INC1_IEA BIT(4) +#define KX022_INC1_IEN BIT(5) #define KX022_GSEL_2G (0 << 3) -#define KX022_GSEL_4G (1 << 3) +#define KX022_GSEL_4G BIT(3) #define KX022_GSEL_8G (2 << 3) #define KX022_GSEL_FIELD (3 << 3) #define KX022_RES_8BIT (0 << 6) -#define KX022_RES_16BIT (1 << 6) +#define KX022_RES_16BIT BIT(6) #define KX022_OSA_0_781HZ 8 #define KX022_OSA_1_563HZ 9 @@ -127,12 +127,12 @@ #define KX022_OWUF_50_00HZ 6 #define KX022_OWUF_100_0HZ 7 -#define KX022_INC2_ZPWUE (1 << 0) -#define KX022_INC2_ZNWUE (1 << 1) -#define KX022_INC2_YPWUE (1 << 2) -#define KX022_INC2_YNWUE (1 << 3) -#define KX022_INC2_XPWUE (1 << 4) -#define KX022_INC2_XNWUE (1 << 5) +#define KX022_INC2_ZPWUE BIT(0) +#define KX022_INC2_ZNWUE BIT(1) +#define KX022_INC2_YPWUE BIT(2) +#define KX022_INC2_YNWUE BIT(3) +#define KX022_INC2_XPWUE BIT(4) +#define KX022_INC2_XNWUE BIT(5) /* Min and Max sampling frequency in mHz */ #define KX022_ACCEL_MIN_FREQ 781 diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h index e36119ccc1..823ef5dc39 100644 --- a/driver/accel_kxcj9.h +++ b/driver/accel_kxcj9.h @@ -40,34 +40,34 @@ #define KXCJ9_SELF_TEST 0x3a #define KXCJ9_WAKEUP_THRESHOLD 0x6a -#define KXCJ9_INT_SRC1_WUFS (1 << 1) -#define KXCJ9_INT_SRC1_DRDY (1 << 4) +#define KXCJ9_INT_SRC1_WUFS BIT(1) +#define KXCJ9_INT_SRC1_DRDY BIT(4) -#define KXCJ9_INT_SRC2_ZPWU (1 << 0) -#define KXCJ9_INT_SRC2_ZNWU (1 << 1) -#define KXCJ9_INT_SRC2_YPWU (1 << 2) -#define KXCJ9_INT_SRC2_YNWU (1 << 3) -#define KXCJ9_INT_SRC2_XPWU (1 << 4) -#define KXCJ9_INT_SRC2_XNWU (1 << 5) +#define KXCJ9_INT_SRC2_ZPWU BIT(0) +#define KXCJ9_INT_SRC2_ZNWU BIT(1) +#define KXCJ9_INT_SRC2_YPWU BIT(2) +#define KXCJ9_INT_SRC2_YNWU BIT(3) +#define KXCJ9_INT_SRC2_XPWU BIT(4) +#define KXCJ9_INT_SRC2_XNWU BIT(5) -#define KXCJ9_STATUS_INT (1 << 4) +#define KXCJ9_STATUS_INT BIT(4) -#define KXCJ9_CTRL1_WUFE (1 << 1) -#define KXCJ9_CTRL1_DRDYE (1 << 5) -#define KXCJ9_CTRL1_PC1 (1 << 7) +#define KXCJ9_CTRL1_WUFE BIT(1) +#define KXCJ9_CTRL1_DRDYE BIT(5) +#define KXCJ9_CTRL1_PC1 BIT(7) #define KXCJ9_GSEL_2G (0 << 3) -#define KXCJ9_GSEL_4G (1 << 3) +#define KXCJ9_GSEL_4G BIT(3) #define KXCJ9_GSEL_8G (2 << 3) #define KXCJ9_GSEL_8G_14BIT (3 << 3) #define KXCJ9_GSEL_ALL (3 << 3) #define KXCJ9_RES_8BIT (0 << 6) -#define KXCJ9_RES_12BIT (1 << 6) +#define KXCJ9_RES_12BIT BIT(6) #define KXCJ9_CTRL2_OWUF (7 << 0) -#define KXCJ9_CTRL2_DCST (1 << 4) -#define KXCJ9_CTRL2_SRST (1 << 7) +#define KXCJ9_CTRL2_DCST BIT(4) +#define KXCJ9_CTRL2_SRST BIT(7) #define KXCJ9_OWUF_0_781HZ 0 #define KXCJ9_OWUF_1_563HZ 1 @@ -78,16 +78,16 @@ #define KXCJ9_OWUF_50_00HZ 6 #define KXCJ9_OWUF_100_0HZ 7 -#define KXCJ9_INT_CTRL1_IEL (1 << 3) -#define KXCJ9_INT_CTRL1_IEA (1 << 4) -#define KXCJ9_INT_CTRL1_IEN (1 << 5) +#define KXCJ9_INT_CTRL1_IEL BIT(3) +#define KXCJ9_INT_CTRL1_IEA BIT(4) +#define KXCJ9_INT_CTRL1_IEN BIT(5) -#define KXCJ9_INT_CTRL2_ZPWUE (1 << 0) -#define KXCJ9_INT_CTRL2_ZNWUE (1 << 1) -#define KXCJ9_INT_CTRL2_YPWUE (1 << 2) -#define KXCJ9_INT_CTRL2_YNWUE (1 << 3) -#define KXCJ9_INT_CTRL2_XPWUE (1 << 4) -#define KXCJ9_INT_CTRL2_XNWUE (1 << 5) +#define KXCJ9_INT_CTRL2_ZPWUE BIT(0) +#define KXCJ9_INT_CTRL2_ZNWUE BIT(1) +#define KXCJ9_INT_CTRL2_YPWUE BIT(2) +#define KXCJ9_INT_CTRL2_YNWUE BIT(3) +#define KXCJ9_INT_CTRL2_XPWUE BIT(4) +#define KXCJ9_INT_CTRL2_XNWUE BIT(5) #define KXCJ9_OSA_0_000HZ 0 #define KXCJ9_OSA_0_781HZ 8 diff --git a/driver/accelgyro_bmi160.h b/driver/accelgyro_bmi160.h index 5b934b57a2..db6179be3e 100644 --- a/driver/accelgyro_bmi160.h +++ b/driver/accelgyro_bmi160.h @@ -78,30 +78,30 @@ #define BMI160_SENSORTIME_2 0x1a #define BMI160_STATUS 0x1b -#define BMI160_POR_DETECTED (1 << 0) -#define BMI160_GYR_SLF_TST (1 << 1) -#define BMI160_MAG_MAN_OP (1 << 2) -#define BMI160_FOC_RDY (1 << 3) -#define BMI160_NVM_RDY (1 << 4) -#define BMI160_DRDY_MAG (1 << 5) -#define BMI160_DRDY_GYR (1 << 6) -#define BMI160_DRDY_ACC (1 << 7) +#define BMI160_POR_DETECTED BIT(0) +#define BMI160_GYR_SLF_TST BIT(1) +#define BMI160_MAG_MAN_OP BIT(2) +#define BMI160_FOC_RDY BIT(3) +#define BMI160_NVM_RDY BIT(4) +#define BMI160_DRDY_MAG BIT(5) +#define BMI160_DRDY_GYR BIT(6) +#define BMI160_DRDY_ACC BIT(7) #define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) #define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) /* first 2 bytes are the interrupt reasons, next 2 some qualifier */ #define BMI160_INT_STATUS_0 0x1c -#define BMI160_STEP_INT (1 << 0) -#define BMI160_SIGMOT_INT (1 << 1) -#define BMI160_ANYM_INT (1 << 2) -#define BMI160_PMU_TRIGGER_INT (1 << 3) -#define BMI160_D_TAP_INT (1 << 4) -#define BMI160_S_TAP_INT (1 << 5) -#define BMI160_ORIENT_INT (1 << 6) -#define BMI160_FLAT_INT (1 << 7) +#define BMI160_STEP_INT BIT(0) +#define BMI160_SIGMOT_INT BIT(1) +#define BMI160_ANYM_INT BIT(2) +#define BMI160_PMU_TRIGGER_INT BIT(3) +#define BMI160_D_TAP_INT BIT(4) +#define BMI160_S_TAP_INT BIT(5) +#define BMI160_ORIENT_INT BIT(6) +#define BMI160_FLAT_INT BIT(7) #define BMI160_ORIENT_XY_MASK 0x30 #define BMI160_ORIENT_PORTRAIT (0 << 4) -#define BMI160_ORIENT_PORTRAIT_INVERT (1 << 4) +#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) #define BMI160_ORIENT_LANDSCAPE (2 << 4) #define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) @@ -138,7 +138,7 @@ #define BMI160_FIFO_LENGTH_0 0x22 #define BMI160_FIFO_LENGTH_1 0x23 -#define BMI160_FIFO_LENGTH_MASK ((1 << 11) - 1) +#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) #define BMI160_FIFO_DATA 0x24 enum fifo_header { BMI160_EMPTY = 0x80, @@ -200,13 +200,13 @@ enum fifo_header { #define BMI160_FIFO_DOWNS 0x45 #define BMI160_FIFO_CONFIG_0 0x46 #define BMI160_FIFO_CONFIG_1 0x47 -#define BMI160_FIFO_TAG_TIME_EN (1 << 1) -#define BMI160_FIFO_TAG_INT2_EN (1 << 2) -#define BMI160_FIFO_TAG_INT1_EN (1 << 3) -#define BMI160_FIFO_HEADER_EN (1 << 4) -#define BMI160_FIFO_MAG_EN (1 << 5) -#define BMI160_FIFO_ACC_EN (1 << 6) -#define BMI160_FIFO_GYR_EN (1 << 7) +#define BMI160_FIFO_TAG_TIME_EN BIT(1) +#define BMI160_FIFO_TAG_INT2_EN BIT(2) +#define BMI160_FIFO_TAG_INT1_EN BIT(3) +#define BMI160_FIFO_HEADER_EN BIT(4) +#define BMI160_FIFO_MAG_EN BIT(5) +#define BMI160_FIFO_ACC_EN BIT(6) +#define BMI160_FIFO_GYR_EN BIT(7) #define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) #define BMI160_FIFO_SENSOR_EN(_sensor) \ ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \ @@ -224,7 +224,7 @@ enum fifo_header { #define BMI160_MAG_READ_BURST_8 3 #define BMI160_MAG_OFFSET_OFF 3 #define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) -#define BMI160_MAG_MANUAL_EN (1 << 7) +#define BMI160_MAG_MANUAL_EN BIT(7) #define BMI160_MAG_IF_2 0x4d #define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 @@ -235,60 +235,60 @@ enum fifo_header { #define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G #define BMI160_INT_EN_0 0x50 -#define BMI160_INT_ANYMO_X_EN (1 << 0) -#define BMI160_INT_ANYMO_Y_EN (1 << 1) -#define BMI160_INT_ANYMO_Z_EN (1 << 2) -#define BMI160_INT_D_TAP_EN (1 << 4) -#define BMI160_INT_S_TAP_EN (1 << 5) -#define BMI160_INT_ORIENT_EN (1 << 6) -#define BMI160_INT_FLAT_EN (1 << 7) +#define BMI160_INT_ANYMO_X_EN BIT(0) +#define BMI160_INT_ANYMO_Y_EN BIT(1) +#define BMI160_INT_ANYMO_Z_EN BIT(2) +#define BMI160_INT_D_TAP_EN BIT(4) +#define BMI160_INT_S_TAP_EN BIT(5) +#define BMI160_INT_ORIENT_EN BIT(6) +#define BMI160_INT_FLAT_EN BIT(7) #define BMI160_INT_EN_1 0x51 -#define BMI160_INT_HIGHG_X_EN (1 << 0) -#define BMI160_INT_HIGHG_Y_EN (1 << 1) -#define BMI160_INT_HIGHG_Z_EN (1 << 2) -#define BMI160_INT_LOW_EN (1 << 3) -#define BMI160_INT_DRDY_EN (1 << 4) -#define BMI160_INT_FFUL_EN (1 << 5) -#define BMI160_INT_FWM_EN (1 << 6) +#define BMI160_INT_HIGHG_X_EN BIT(0) +#define BMI160_INT_HIGHG_Y_EN BIT(1) +#define BMI160_INT_HIGHG_Z_EN BIT(2) +#define BMI160_INT_LOW_EN BIT(3) +#define BMI160_INT_DRDY_EN BIT(4) +#define BMI160_INT_FFUL_EN BIT(5) +#define BMI160_INT_FWM_EN BIT(6) #define BMI160_INT_EN_2 0x52 -#define BMI160_INT_NOMOX_EN (1 << 0) -#define BMI160_INT_NOMOY_EN (1 << 1) -#define BMI160_INT_NOMOZ_EN (1 << 2) -#define BMI160_INT_STEP_DET_EN (1 << 3) +#define BMI160_INT_NOMOX_EN BIT(0) +#define BMI160_INT_NOMOY_EN BIT(1) +#define BMI160_INT_NOMOZ_EN BIT(2) +#define BMI160_INT_STEP_DET_EN BIT(3) #define BMI160_INT_OUT_CTRL 0x53 -#define BMI160_INT_EDGE_CTRL (1 << 0) -#define BMI160_INT_LVL_CTRL (1 << 1) -#define BMI160_INT_OD (1 << 2) -#define BMI160_INT_OUTPUT_EN (1 << 3) +#define BMI160_INT_EDGE_CTRL BIT(0) +#define BMI160_INT_LVL_CTRL BIT(1) +#define BMI160_INT_OD BIT(2) +#define BMI160_INT_OUTPUT_EN BIT(3) #define BMI160_INT1_CTRL_OFFSET 0 #define BMI160_INT2_CTRL_OFFSET 4 #define BMI160_INT_CTRL(_i, _bit) \ (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) #define BMI160_INT_LATCH 0x54 -#define BMI160_INT1_INPUT_EN (1 << 4) -#define BMI160_INT2_INPUT_EN (1 << 5) +#define BMI160_INT1_INPUT_EN BIT(4) +#define BMI160_INT2_INPUT_EN BIT(5) #define BMI160_LATCH_MASK 0xf #define BMI160_LATCH_NONE 0 #define BMI160_LATCH_5MS 5 #define BMI160_LATCH_FOREVER 0xf #define BMI160_INT_MAP_0 0x55 -#define BMI160_INT_LOWG_STEP (1 << 0) -#define BMI160_INT_HIGHG (1 << 1) -#define BMI160_INT_ANYMOTION (1 << 2) -#define BMI160_INT_NOMOTION (1 << 3) -#define BMI160_INT_D_TAP (1 << 4) -#define BMI160_INT_S_TAP (1 << 5) -#define BMI160_INT_ORIENT (1 << 6) -#define BMI160_INT_FLAT (1 << 7) +#define BMI160_INT_LOWG_STEP BIT(0) +#define BMI160_INT_HIGHG BIT(1) +#define BMI160_INT_ANYMOTION BIT(2) +#define BMI160_INT_NOMOTION BIT(3) +#define BMI160_INT_D_TAP BIT(4) +#define BMI160_INT_S_TAP BIT(5) +#define BMI160_INT_ORIENT BIT(6) +#define BMI160_INT_FLAT BIT(7) #define BMI160_INT_MAP_1 0x56 -#define BMI160_INT_PMU_TRIG (1 << 0) -#define BMI160_INT_FFULL (1 << 1) -#define BMI160_INT_FWM (1 << 2) -#define BMI160_INT_DRDY (1 << 3) +#define BMI160_INT_PMU_TRIG BIT(0) +#define BMI160_INT_FFULL BIT(1) +#define BMI160_INT_FWM BIT(2) +#define BMI160_INT_DRDY BIT(3) #define BMI160_INT1_MAP_OFFSET 4 #define BMI160_INT2_MAP_OFFSET 0 #define BMI160_INT_MAP(_i, _bit) \ @@ -318,8 +318,8 @@ enum fifo_header { (MIN(((_mg) * 1000) / ((_s)->drv->get_range(_s) * 1953), 0xff)) #define BMI160_INT_MOTION_2 0x61 #define BMI160_INT_MOTION_3 0x62 -#define BMI160_MOTION_NO_MOT_SEL (1 << 0) -#define BMI160_MOTION_SIG_MOT_SEL (1 << 1) +#define BMI160_MOTION_NO_MOT_SEL BIT(0) +#define BMI160_MOTION_SIG_MOT_SEL BIT(1) #define BMI160_MOTION_SKIP_OFF 2 #define BMI160_MOTION_SKIP_MASK 0x3 #define BMI160_MOTION_SKIP_TIME(_ms) \ @@ -353,7 +353,7 @@ enum fifo_header { #define BMI160_INT_FLAT_1 0x68 #define BMI160_FOC_CONF 0x69 -#define BMI160_FOC_GYRO_EN (1 << 6) +#define BMI160_FOC_GYRO_EN BIT(6) #define BMI160_FOC_ACC_PLUS_1G 1 #define BMI160_FOC_ACC_MINUS_1G 2 #define BMI160_FOC_ACC_0G 3 @@ -379,8 +379,8 @@ enum fifo_header { #define BMI160_OFFSET_GYRO_MULTI_MDS (61 * 1024) #define BMI160_OFFSET_GYRO_DIV_MDS 1000 #define BMI160_OFFSET_EN_GYR98 0x77 -#define BMI160_OFFSET_ACC_EN (1 << 6) -#define BMI160_OFFSET_GYRO_EN (1 << 7) +#define BMI160_OFFSET_ACC_EN BIT(6) +#define BMI160_OFFSET_GYRO_EN BIT(7) #define BMI160_CMD_REG 0x7e @@ -410,8 +410,8 @@ enum fifo_header { #define BMI160_CMD_EXT_MODE_EN_B2 0xc0 #define BMI160_CMD_EXT_MODE_ADDR 0x7f -#define BMI160_CMD_PAGING_EN (1 << 7) -#define BMI160_CMD_TARGET_PAGE (1 << 4) +#define BMI160_CMD_PAGING_EN BIT(7) +#define BMI160_CMD_TARGET_PAGE BIT(4) #define BMI160_COM_C_TRIM_ADDR 0x85 #define BMI160_COM_C_TRIM (3 << 4) @@ -450,7 +450,7 @@ enum bmi160_running_mode { APPLICATION_INDOOR_NAVIGATION = 8, }; -#define BMI160_FLAG_SEC_I2C_ENABLED (1 << 0) +#define BMI160_FLAG_SEC_I2C_ENABLED BIT(0) #define BMI160_FIFO_FLAG_OFFSET 4 #define BMI160_FIFO_ALL_MASK 7 diff --git a/driver/accelgyro_lsm6ds0.h b/driver/accelgyro_lsm6ds0.h index cd1fefb199..bc5574d8c1 100644 --- a/driver/accelgyro_lsm6ds0.h +++ b/driver/accelgyro_lsm6ds0.h @@ -72,7 +72,7 @@ #define LSM6DS0_INT_GEN_DUR_G 0x37 #define LSM6DS0_DPS_SEL_245 (0 << 3) -#define LSM6DS0_DPS_SEL_500 (1 << 3) +#define LSM6DS0_DPS_SEL_500 BIT(3) #define LSM6DS0_DPS_SEL_1000 (2 << 3) #define LSM6DS0_DPS_SEL_2000 (3 << 3) #define LSM6DS0_GSEL_2G (0 << 3) @@ -82,8 +82,8 @@ #define LSM6DS0_RANGE_MASK (3 << 3) #define LSM6DS0_ODR_PD (0 << 5) -#define LSM6DS0_ODR_10HZ (1 << 5) -#define LSM6DS0_ODR_15HZ (1 << 5) +#define LSM6DS0_ODR_10HZ BIT(5) +#define LSM6DS0_ODR_15HZ BIT(5) #define LSM6DS0_ODR_50HZ (2 << 5) #define LSM6DS0_ODR_59HZ (2 << 5) #define LSM6DS0_ODR_119HZ (3 << 5) diff --git a/driver/als_si114x.h b/driver/als_si114x.h index e3a19895ba..d3fcf1d64a 100644 --- a/driver/als_si114x.h +++ b/driver/als_si114x.h @@ -75,7 +75,7 @@ #define SI114X_REG_PS2_DATA1 0x29 #define SI114X_REG_PS3_DATA0 0x2a #define SI114X_REG_PS3_DATA1 0x2b -#define SI114X_PS_INVERSION(_data) ((1 << 16) / (_data)) +#define SI114X_PS_INVERSION(_data) (BIT(16) / (_data)) #define SI114X_REG_AUX_DATA0 0x2c #define SI114X_REG_AUX_DATA1 0x2d #define SI114X_REG_PARAM_RD 0x2e diff --git a/driver/battery/bq27541.c b/driver/battery/bq27541.c index 760a367b9c..2731b908bf 100644 --- a/driver/battery/bq27541.c +++ b/driver/battery/bq27541.c @@ -312,7 +312,7 @@ enum battery_disconnect_state battery_get_disconnect_state(void) rv = bq27541_read(REG_PROTECTOR, &val); if (rv) return BATTERY_DISCONNECT_ERROR; - if (!(val & (1 << 6))) { + if (!(val & BIT(6))) { not_disconnected = 1; return BATTERY_NOT_DISCONNECTED; } diff --git a/driver/battery/max17055.h b/driver/battery/max17055.h index f223fa15e8..ba18af56d5 100644 --- a/driver/battery/max17055.h +++ b/driver/battery/max17055.h @@ -55,16 +55,16 @@ #define REG_MODELCFG 0xdb /* Status reg (0x00) flags */ -#define STATUS_POR (1 << 1) -#define STATUS_IMN (1 << 2) -#define STATUS_BST (1 << 3) -#define STATUS_IMX (1 << 6) -#define STATUS_VMN (1 << 8) -#define STATUS_TMN (1 << 9) -#define STATUS_SMN (1 << 10) -#define STATUS_VMX (1 << 12) -#define STATUS_TMX (1 << 13) -#define STATUS_SMX (1 << 14) +#define STATUS_POR BIT(1) +#define STATUS_IMN BIT(2) +#define STATUS_BST BIT(3) +#define STATUS_IMX BIT(6) +#define STATUS_VMN BIT(8) +#define STATUS_TMN BIT(9) +#define STATUS_SMN BIT(10) +#define STATUS_VMX BIT(12) +#define STATUS_TMX BIT(13) +#define STATUS_SMX BIT(14) #define STATUS_ALL_ALRT \ (STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN | \ STATUS_TMX | STATUS_SMN | STATUS_SMX) @@ -76,12 +76,12 @@ #define IALRT_DISABLE 0x7f80 /* Config reg (0x1d) flags */ -#define CONF_AEN (1 << 2) -#define CONF_IS (1 << 11) -#define CONF_VS (1 << 12) -#define CONF_TS (1 << 13) -#define CONF_SS (1 << 14) -#define CONF_TSEL (1 << 15) +#define CONF_AEN BIT(2) +#define CONF_IS BIT(11) +#define CONF_VS BIT(12) +#define CONF_TS BIT(13) +#define CONF_SS BIT(14) +#define CONF_TSEL BIT(15) #define CONF_ALL_STICKY (CONF_IS | CONF_VS | CONF_TS | CONF_SS) /* FStat reg (0x3d) flags */ diff --git a/driver/battery/mm8013.h b/driver/battery/mm8013.h index 1915c81832..4dedfbd4a3 100644 --- a/driver/battery/mm8013.h +++ b/driver/battery/mm8013.h @@ -24,17 +24,17 @@ #define REG_PRODUCT_INFORMATION 0x64 /* Over Temperature in charge */ -#define MM8013_FLAG_OTC (1 << 15) +#define MM8013_FLAG_OTC BIT(15) /* Over Temperature in discharge */ -#define MM8013_FLAG_OTD (1 << 14) +#define MM8013_FLAG_OTD BIT(14) /* Over-charge */ -#define MM8013_FLAG_BATHI (1 << 13) +#define MM8013_FLAG_BATHI BIT(13) /* Full Charge */ -#define MM8013_FLAG_FC (1 << 9) +#define MM8013_FLAG_FC BIT(9) /* Charge allowed */ -#define MM8013_FLAG_CHG (1 << 8) +#define MM8013_FLAG_CHG BIT(8) /* Discharge */ -#define MM8013_FLAG_DSG (1 << 0) +#define MM8013_FLAG_DSG BIT(0) #endif /* __CROS_EC_MM8013_H */ diff --git a/driver/bc12/max14637.h b/driver/bc12/max14637.h index 7013e46fb1..38e88b4ee2 100644 --- a/driver/bc12/max14637.h +++ b/driver/bc12/max14637.h @@ -7,8 +7,8 @@ #include "gpio.h" -#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW (1 << 0) -#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW (1 << 1) +#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW BIT(0) +#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW BIT(1) struct max14637_config_t { /* diff --git a/driver/bc12/pi3usb9201.h b/driver/bc12/pi3usb9201.h index 71b235c8d1..1e60e63c47 100644 --- a/driver/bc12/pi3usb9201.h +++ b/driver/bc12/pi3usb9201.h @@ -17,19 +17,19 @@ #define PI3USB9201_REG_HOST_STS 0x3 /* Control_1 regiter bit definitions */ -#define PI3USB9201_REG_CTRL_1_INT_MASK (1 << 0) +#define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0) #define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1 #define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \ PI3USB9201_REG_CTRL_1_MODE_SHIFT) /* Control_2 regiter bit definitions */ -#define PI3USB9201_REG_CTRL_2_AUTO_SW (1 << 1) -#define PI3USB9201_REG_CTRL_2_START_DET (1 << 3) +#define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1) +#define PI3USB9201_REG_CTRL_2_START_DET BIT(3) /* Host status register bit definitions */ -#define PI3USB9201_REG_HOST_STS_BC12_DET (1 << 0) -#define PI3USB9201_REG_HOST_STS_DEV_PLUG (1 << 1) -#define PI3USB9201_REG_HOST_STS_DEV_UNPLUG (1 << 2) +#define PI3USB9201_REG_HOST_STS_BC12_DET BIT(0) +#define PI3USB9201_REG_HOST_STS_DEV_PLUG BIT(1) +#define PI3USB9201_REG_HOST_STS_DEV_UNPLUG BIT(2) struct pi3usb2901_config_t { const int i2c_port; diff --git a/driver/charger/bd9995x.h b/driver/charger/bd9995x.h index f9fb092b24..6719fd8661 100644 --- a/driver/charger/bd9995x.h +++ b/driver/charger/bd9995x.h @@ -71,13 +71,13 @@ enum bd9995x_charge_port { #define BD9995X_CMD_CHGSTM_STATUS 0x00 #define BD9995X_CMD_VBAT_VSYS_STATUS 0x01 #define BD9995X_CMD_VBUS_VCC_STATUS 0x02 -#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT (1 << 8) -#define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT (1 << 0) +#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT BIT(8) +#define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT BIT(0) #define BD9995X_CMD_CHGOP_STATUS 0x03 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 (1 << 10) -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 (1 << 9) -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 (1 << 8) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 BIT(10) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 BIT(9) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 BIT(8) #define BD9995X_BATTTEMP_MASK 0x700 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP 0 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1 1 @@ -87,7 +87,7 @@ enum bd9995x_charge_port { #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2 5 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE 6 #define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN 7 -#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV (1 << 1) +#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV BIT(1) #define BD9995X_CMD_WDT_STATUS 0x04 #define BD9995X_CMD_CUR_ILIM_VAL 0x05 @@ -96,29 +96,29 @@ enum bd9995x_charge_port { #define BD9995X_CMD_EXT_ICC_LIM_SET 0x08 #define BD9995X_CMD_IOTG_LIM_SET 0x09 #define BD9995X_CMD_VIN_CTRL_SET 0x0A -#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY (1 << 4) +#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY BIT(4) -#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU (1 << 11) -#define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY (1 << 7) -#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN (1 << 6) -#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN (1 << 5) +#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU BIT(11) +#define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY BIT(7) +#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN BIT(6) +#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN BIT(5) #define BD9995X_CMD_CHGOP_SET1 0x0B -#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL (1 << 15) -#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL (1 << 14) -#define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN (1 << 13) -#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN (1 << 11) -#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN (1 << 10) -#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN (1 << 9) -#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG (1 << 8) +#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL BIT(15) +#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL BIT(14) +#define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN BIT(13) +#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN BIT(11) +#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN BIT(10) +#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN BIT(9) +#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG BIT(8) #define BD9995X_CMD_CHGOP_SET2 0x0C -#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN (1 << 8) -#define BD9995X_CMD_CHGOP_SET2_CHG_EN (1 << 7) -#define BD9995X_CMD_CHGOP_SET2_USB_SUS (1 << 6) +#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN BIT(8) +#define BD9995X_CMD_CHGOP_SET2_CHG_EN BIT(7) +#define BD9995X_CMD_CHGOP_SET2_USB_SUS BIT(6) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL (3 << 2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600 (0 << 2) -#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 (1 << 2) +#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 BIT(2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1000 (2 << 2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1200 (3 << 2) @@ -145,27 +145,27 @@ enum bd9995x_charge_port { #define BD9995X_CMD_VBATOVP_SET 0x1E #define BD9995X_CMD_IBATSHORT_SET 0x1F #define BD9995X_CMD_PROCHOT_CTRL_SET 0x20 -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 (1 << 4) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 (1 << 3) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 (1 << 2) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 (1 << 1) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 (1 << 0) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 BIT(4) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 BIT(3) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 BIT(2) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 BIT(1) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 BIT(0) #define BD9995X_CMD_PROCHOT_ICRIT_SET 0x21 #define BD9995X_CMD_PROCHOT_INORM_SET 0x22 #define BD9995X_CMD_PROCHOT_IDCHG_SET 0x23 #define BD9995X_CMD_PROCHOT_VSYS_SET 0x24 #define BD9995X_CMD_PMON_IOUT_CTRL_SET 0x25 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL (1 << 9) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL (1 << 8) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN (1 << 7) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL (1 << 6) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL BIT(9) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL BIT(8) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN BIT(7) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL BIT(6) #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK 0x30 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V 0x03 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V 0x02 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V 0x01 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V 0x00 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN (1 << 3) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN BIT(3) #define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK 0x07 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW 0x06 #define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW 0x05 @@ -181,21 +181,21 @@ enum bd9995x_charge_port { #define BD9995X_CMD_VCC_UCD_SET 0x28 /* Bits for both VCC_UCD_SET and VBUS_UCD_SET regs */ /* Retry BC1.2 detection on set */ -#define BD9995X_CMD_UCD_SET_BCSRETRY (1 << 12) +#define BD9995X_CMD_UCD_SET_BCSRETRY BIT(12) /* Enable BC1.2 detection, will automatically occur on VBUS detect */ -#define BD9995X_CMD_UCD_SET_USBDETEN (1 << 7) +#define BD9995X_CMD_UCD_SET_USBDETEN BIT(7) /* USB switch state auto-control */ -#define BD9995X_CMD_UCD_SET_USB_SW_EN (1 << 1) +#define BD9995X_CMD_UCD_SET_USB_SW_EN BIT(1) /* USB switch state, 1 = ON, only meaningful when USB_SW_EN = 0 */ -#define BD9995X_CMD_UCD_SET_USB_SW (1 << 0) +#define BD9995X_CMD_UCD_SET_USB_SW BIT(0) #define BD9995X_CMD_VCC_UCD_STATUS 0x29 /* Bits for both VCC_UCD_STATUS and VBUS_UCD_STATUS regs */ -#define BD9995X_CMD_UCD_STATUS_DCDFAIL (1 << 15) -#define BD9995X_CMD_UCD_STATUS_CHGPORT1 (1 << 13) -#define BD9995X_CMD_UCD_STATUS_CHGPORT0 (1 << 12) -#define BD9995X_CMD_UCD_STATUS_PUPDET (1 << 11) -#define BD9995X_CMD_UCD_STATUS_CHGDET (1 << 6) +#define BD9995X_CMD_UCD_STATUS_DCDFAIL BIT(15) +#define BD9995X_CMD_UCD_STATUS_CHGPORT1 BIT(13) +#define BD9995X_CMD_UCD_STATUS_CHGPORT0 BIT(12) +#define BD9995X_CMD_UCD_STATUS_PUPDET BIT(11) +#define BD9995X_CMD_UCD_STATUS_CHGDET BIT(6) #define BD9995X_TYPE_MASK (BD9995X_CMD_UCD_STATUS_DCDFAIL | \ BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ @@ -235,17 +235,17 @@ enum bd9995x_charge_port { #define BD9995X_CMD_IC_SET1 0x3A #define BD9995X_CMD_IC_SET2 0x3B #define BD9995X_CMD_SYSTEM_STATUS 0x3C -#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE (1 << 1) -#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE (1 << 0) +#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE BIT(1) +#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE BIT(0) #define BD9995X_CMD_SYSTEM_CTRL_SET 0x3D -#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD (1 << 1) -#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST (1 << 0) +#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD BIT(1) +#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST BIT(0) #define BD9995X_CMD_EXT_PROTECT_SET 0x3E #define BD9995X_CMD_EXT_MAP_SET 0x3F #define BD9995X_CMD_VM_CTRL_SET 0x40 -#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN (1 << 9) +#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN BIT(9) #define BD9995X_CMD_THERM_WINDOW_SET1 0x41 #define BD9995X_CMD_THERM_WINDOW_SET2 0x42 #define BD9995X_CMD_THERM_WINDOW_SET3 0x43 @@ -287,16 +287,16 @@ enum bd9995x_charge_port { #define BD9995X_CMD_EXTIADP_AVE_VAL 0x63 #define BD9995X_CMD_VACPCLPS_TH_SET 0x64 #define BD9995X_CMD_INT0_SET 0x68 -#define BD9995X_CMD_INT0_SET_INT2_EN (1 << 2) -#define BD9995X_CMD_INT0_SET_INT1_EN (1 << 1) -#define BD9995X_CMD_INT0_SET_INT0_EN (1 << 0) +#define BD9995X_CMD_INT0_SET_INT2_EN BIT(2) +#define BD9995X_CMD_INT0_SET_INT1_EN BIT(1) +#define BD9995X_CMD_INT0_SET_INT0_EN BIT(0) #define BD9995X_CMD_INT1_SET 0x69 /* Bits for both INT1 & INT2 reg */ -#define BD9995X_CMD_INT_SET_TH_DET (1 << 9) -#define BD9995X_CMD_INT_SET_TH_RES (1 << 8) -#define BD9995X_CMD_INT_SET_DET (1 << 1) -#define BD9995X_CMD_INT_SET_RES (1 << 0) +#define BD9995X_CMD_INT_SET_TH_DET BIT(9) +#define BD9995X_CMD_INT_SET_TH_RES BIT(8) +#define BD9995X_CMD_INT_SET_DET BIT(1) +#define BD9995X_CMD_INT_SET_RES BIT(0) #define BD9995X_CMD_INT_VBUS_DET (BD9995X_CMD_INT_SET_RES | \ BD9995X_CMD_INT_SET_DET) #define BD9995X_CMD_INT_VBUS_TH (BD9995X_CMD_INT_SET_TH_RES | \ @@ -311,8 +311,8 @@ enum bd9995x_charge_port { #define BD9995X_CMD_INT0_STATUS 0x70 #define BD9995X_CMD_INT1_STATUS 0x71 /* Bits for both INT1_STATUS & INT2_STATUS reg */ -#define BD9995X_CMD_INT_STATUS_DET (1 << 1) -#define BD9995X_CMD_INT_STATUS_RES (1 << 0) +#define BD9995X_CMD_INT_STATUS_DET BIT(1) +#define BD9995X_CMD_INT_STATUS_RES BIT(0) #define BD9995X_CMD_INT2_STATUS 0x72 #define BD9995X_CMD_INT3_STATUS 0x73 diff --git a/driver/charger/bq24192.c b/driver/charger/bq24192.c index 8c82b84475..5d7ca58862 100644 --- a/driver/charger/bq24192.c +++ b/driver/charger/bq24192.c @@ -53,7 +53,7 @@ static int bq24192_watchdog_reset(void) rv = bq24192_read(BQ24192_REG_POWER_ON_CFG, &val); if (rv) return rv; - val |= (1 << 6); + val |= BIT(6); return bq24192_write(BQ24192_REG_POWER_ON_CFG, val) || bq24192_write(BQ24192_REG_POWER_ON_CFG, val); } diff --git a/driver/charger/bq24707a.h b/driver/charger/bq24707a.h index 14e89ed136..ac3293e04d 100644 --- a/driver/charger/bq24707a.h +++ b/driver/charger/bq24707a.h @@ -15,28 +15,28 @@ #define BQ24707_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) +#define OPTION_CHARGE_INHIBIT BIT(0) #define OPTION_ACOC_THRESHOLD (3 << 1) -#define OPTION_COMPARATOR_THRESHOLD (1 << 4) -#define OPTION_IOUT_SELECTION (1 << 5) +#define OPTION_COMPARATOR_THRESHOLD BIT(4) +#define OPTION_IOUT_SELECTION BIT(5) #define OPTION_IFAULT_HI_THRESHOLD (3 << 7) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_AOC_DELITCH_TIME (1 << 15) +#define OPTION_AOC_DELITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) #define ACOC_THRESHOLD_166X_DEFAULT (2 << 1) #define ACOC_THRESHOLD_222X (3 << 1) /* OPTION_IFAULT_HI_THRESHOLD */ #define IFAULT_THRESHOLD_300MV (0 << 7) -#define IFAULT_THRESHOLD_500MV (1 << 7) +#define IFAULT_THRESHOLD_500MV BIT(7) #define IFAULT_THRESHOLD_700MV_DEFAULT (2 << 7) #define IFAULT_THRESHOLD_900MV (3 << 7) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) diff --git a/driver/charger/bq24715.h b/driver/charger/bq24715.h index bb5deec902..669dc542ed 100644 --- a/driver/charger/bq24715.h +++ b/driver/charger/bq24715.h @@ -23,63 +23,63 @@ #define BQ24715_DEVICE_ID 0xff /* ChargeOption Register - 0x12 */ -#define OPT_LOWPOWER_MASK (1 << 15) +#define OPT_LOWPOWER_MASK BIT(15) #define OPT_LOWPOWER_DSCHRG_I_MON_ON (0 << 15) -#define OPT_LOWPOWER_DSCHRG_I_MON_OFF (1 << 15) +#define OPT_LOWPOWER_DSCHRG_I_MON_OFF BIT(15) #define OPT_WATCHDOG_MASK (3 << 13) #define OPT_WATCHDOG_DISABLE (0 << 13) -#define OPT_WATCHDOG_44SEC (1 << 13) +#define OPT_WATCHDOG_44SEC BIT(13) #define OPT_WATCHDOG_88SEC (2 << 13) #define OPT_WATCHDOG_175SEC (3 << 13) -#define OPT_SYSOVP_MASK (1 << 12) +#define OPT_SYSOVP_MASK BIT(12) #define OPT_SYSOVP_15P1_3SEC_10P1_2SEC (0 << 12) -#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC (1 << 12) -#define OPT_SYSOVP_STATUS_MASK (1 << 11) -#define OPT_SYSOVP_STATUS (1 << 11) -#define OPT_AUDIO_FREQ_LIMIT_MASK (1 << 10) +#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC BIT(12) +#define OPT_SYSOVP_STATUS_MASK BIT(11) +#define OPT_SYSOVP_STATUS BIT(11) +#define OPT_AUDIO_FREQ_LIMIT_MASK BIT(10) #define OPT_AUDIO_FREQ_NO_LIMIT (0 << 10) -#define OPT_AUDIO_FREQ_40KHZ_LIMIT (1 << 10) +#define OPT_AUDIO_FREQ_40KHZ_LIMIT BIT(10) #define OPT_SWITCH_FREQ_MASK (3 << 8) #define OPT_SWITCH_FREQ_600KHZ (0 << 8) -#define OPT_SWITCH_FREQ_800KHZ (1 << 8) +#define OPT_SWITCH_FREQ_800KHZ BIT(8) #define OPT_SWITCH_FREQ_1MHZ (2 << 8) #define OPT_SWITCH_FREQ_800KHZ_DUP (3 << 8) -#define OPT_ACOC_MASK (1 << 7) +#define OPT_ACOC_MASK BIT(7) #define OPT_ACOC_DISABLED (0 << 7) -#define OPT_ACOC_333PCT_IPDM (1 << 7) -#define OPT_LSFET_OCP_MASK (1 << 6) +#define OPT_ACOC_333PCT_IPDM BIT(7) +#define OPT_LSFET_OCP_MASK BIT(6) #define OPT_LSFET_OCP_250MV (0 << 6) -#define OPT_LSFET_OCP_350MV (1 << 6) -#define OPT_LEARN_MASK (1 << 5) +#define OPT_LSFET_OCP_350MV BIT(6) +#define OPT_LEARN_MASK BIT(5) #define OPT_LEARN_DISABLE (0 << 5) -#define OPT_LEARN_ENABLE (1 << 5) -#define OPT_IOUT_MASK (1 << 4) +#define OPT_LEARN_ENABLE BIT(5) +#define OPT_IOUT_MASK BIT(4) #define OPT_IOUT_40X (0 << 4) -#define OPT_IOUT_16X (1 << 4) -#define OPT_FIX_IOUT_MASK (1 << 3) +#define OPT_IOUT_16X BIT(4) +#define OPT_FIX_IOUT_MASK BIT(3) #define OPT_FIX_IOUT_IDPM_EN (0 << 3) -#define OPT_FIX_IOUT_ALWAYS (1 << 3) -#define OPT_LDO_MODE_MASK (1 << 2) +#define OPT_FIX_IOUT_ALWAYS BIT(3) +#define OPT_LDO_MODE_MASK BIT(2) #define OPT_LDO_DISABLE (0 << 2) -#define OPT_LDO_ENABLE (1 << 2) -#define OPT_IDPM_MASK (1 << 1) +#define OPT_LDO_ENABLE BIT(2) +#define OPT_IDPM_MASK BIT(1) #define OPT_IDPM_DISABLE (0 << 1) -#define OPT_IDPM_ENABLE (1 << 1) -#define OPT_CHARGE_INHIBIT_MASK (1 << 0) +#define OPT_IDPM_ENABLE BIT(1) +#define OPT_CHARGE_INHIBIT_MASK BIT(0) #define OPT_CHARGE_ENABLE (0 << 0) -#define OPT_CHARGE_DISABLE (1 << 0) +#define OPT_CHARGE_DISABLE BIT(0) /* ChargeCurrent Register - 0x14 * The ChargeCurrent register controls a DAC. Therefore * the below definitions are cummulative. */ -#define CHARGE_I_64MA (1 << 6) -#define CHARGE_I_128MA (1 << 7) -#define CHARGE_I_256MA (1 << 8) -#define CHARGE_I_512MA (1 << 9) -#define CHARGE_I_1024MA (1 << 10) -#define CHARGE_I_2048MA (1 << 11) -#define CHARGE_I_4096MA (1 << 12) +#define CHARGE_I_64MA BIT(6) +#define CHARGE_I_128MA BIT(7) +#define CHARGE_I_256MA BIT(8) +#define CHARGE_I_512MA BIT(9) +#define CHARGE_I_1024MA BIT(10) +#define CHARGE_I_2048MA BIT(11) +#define CHARGE_I_4096MA BIT(12) #define CHARGE_I_OFF (0) #define CHARGE_I_MIN (128) #define CHARGE_I_MAX (8128) @@ -88,16 +88,16 @@ /* MaxChargeVoltage Register - 0x15 * The MaxChargeVoltage register controls a DAC. Therefore * the below definitions are cummulative. */ -#define CHARGE_V_16MV (1 << 4) -#define CHARGE_V_32MV (1 << 5) -#define CHARGE_V_64MV (1 << 6) -#define CHARGE_V_128MV (1 << 7) -#define CHARGE_V_256MV (1 << 8) -#define CHARGE_V_512MV (1 << 9) -#define CHARGE_V_1024MV (1 << 10) -#define CHARGE_V_2048MV (1 << 11) -#define CHARGE_V_4096MV (1 << 12) -#define CHARGE_V_8192MV (1 << 13) +#define CHARGE_V_16MV BIT(4) +#define CHARGE_V_32MV BIT(5) +#define CHARGE_V_64MV BIT(6) +#define CHARGE_V_128MV BIT(7) +#define CHARGE_V_256MV BIT(8) +#define CHARGE_V_512MV BIT(9) +#define CHARGE_V_1024MV BIT(10) +#define CHARGE_V_2048MV BIT(11) +#define CHARGE_V_4096MV BIT(12) +#define CHARGE_V_8192MV BIT(13) #define CHARGE_V_MIN (4096) #define CHARGE_V_MAX (0x3ff0) #define CHARGE_V_STEP (16) @@ -105,24 +105,24 @@ /* MinSystemVoltage Register - 0x3e * The MinSystemVoltage register controls a DAC. Therefore * the below definitions are cummulative. */ -#define MIN_SYS_V_256MV (1 << 8) -#define MIN_SYS_V_512MV (1 << 9) -#define MIN_SYS_V_1024MV (1 << 10) -#define MIN_SYS_V_2048MV (1 << 11) -#define MIN_SYS_V_4096MV (1 << 12) -#define MIN_SYS_V_8192MV (1 << 13) +#define MIN_SYS_V_256MV BIT(8) +#define MIN_SYS_V_512MV BIT(9) +#define MIN_SYS_V_1024MV BIT(10) +#define MIN_SYS_V_2048MV BIT(11) +#define MIN_SYS_V_4096MV BIT(12) +#define MIN_SYS_V_8192MV BIT(13) #define MIN_SYS_V_MIN (4096) /* InputCurrent Register - 0x3f * The InputCurrent register controls a DAC. Therefore * the below definitions are cummulative. */ -#define INPUT_I_64MA (1 << 6) -#define INPUT_I_128MA (1 << 7) -#define INPUT_I_256MA (1 << 8) -#define INPUT_I_512MA (1 << 9) -#define INPUT_I_1024MA (1 << 10) -#define INPUT_I_2048MA (1 << 11) -#define INPUT_I_4096MA (1 << 12) +#define INPUT_I_64MA BIT(6) +#define INPUT_I_128MA BIT(7) +#define INPUT_I_256MA BIT(8) +#define INPUT_I_512MA BIT(9) +#define INPUT_I_1024MA BIT(10) +#define INPUT_I_2048MA BIT(11) +#define INPUT_I_4096MA BIT(12) #define INPUT_I_MIN (128) #define INPUT_I_MAX (8064) #define INPUT_I_STEP (64) diff --git a/driver/charger/bq24725.h b/driver/charger/bq24725.h index b935501a20..c53019a2aa 100644 --- a/driver/charger/bq24725.h +++ b/driver/charger/bq24725.h @@ -15,34 +15,34 @@ #define BQ24725_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) +#define OPTION_CHARGE_INHIBIT BIT(0) #define OPTION_ACOC_THRESHOLD (3 << 1) -#define OPTION_IOUT_SELECTION (1 << 5) -#define OPTION_LEARN_ENABLE (1 << 6) +#define OPTION_IOUT_SELECTION BIT(5) +#define OPTION_LEARN_ENABLE BIT(6) #define OPTION_IFAULT_HI_THRESHOLD (3 << 7) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_BAT_DEPLETION_THRESHOLD (3 << 11) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_AOC_DELITCH_TIME (1 << 15) +#define OPTION_AOC_DELITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) #define ACOC_THRESHOLD_166X_DEFAULT (2 << 1) #define ACOC_THRESHOLD_222X (3 << 1) /* OPTION_IFAULT_HI_THRESHOLD */ #define IFAULT_THRESHOLD_300MV (0 << 7) -#define IFAULT_THRESHOLD_500MV (1 << 7) +#define IFAULT_THRESHOLD_500MV BIT(7) #define IFAULT_THRESHOLD_700MV_DEFAULT (2 << 7) #define IFAULT_THRESHOLD_900MV (3 << 7) /* OPTION_BAT_DEPLETION_THRESHOLD */ #define FALLING_THRESHOLD_5919 (0 << 11) -#define FALLING_THRESHOLD_6265 (1 << 11) +#define FALLING_THRESHOLD_6265 BIT(11) #define FALLING_THRESHOLD_6655 (2 << 11) #define FALLING_THRESHOLD_7097_DEFAULT (3 << 11) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) diff --git a/driver/charger/bq24735.h b/driver/charger/bq24735.h index 05336cb41c..e29b9aa692 100644 --- a/driver/charger/bq24735.h +++ b/driver/charger/bq24735.h @@ -15,43 +15,43 @@ #define BQ24735_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) -#define OPTION_ACOC_THRESHOLD (1 << 1) -#define OPTION_BOOST_MODE_STATE (1 << 2) -#define OPTION_BOOST_MODE_ENABLE (1 << 3) -#define OPTION_ACDET_STATE (1 << 4) -#define OPTION_IOUT_SELECTION (1 << 5) -#define OPTION_LEARN_ENABLE (1 << 6) -#define OPTION_IFAULT_LOW_THRESHOLD (1 << 7) -#define OPTION_IFAULT_HI_ENABLE (1 << 8) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_CHARGE_INHIBIT BIT(0) +#define OPTION_ACOC_THRESHOLD BIT(1) +#define OPTION_BOOST_MODE_STATE BIT(2) +#define OPTION_BOOST_MODE_ENABLE BIT(3) +#define OPTION_ACDET_STATE BIT(4) +#define OPTION_IOUT_SELECTION BIT(5) +#define OPTION_LEARN_ENABLE BIT(6) +#define OPTION_IFAULT_LOW_THRESHOLD BIT(7) +#define OPTION_IFAULT_HI_ENABLE BIT(8) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_BAT_DEPLETION_THRESHOLD (3 << 11) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_ACPRES_DEGLITCH_TIME (1 << 15) +#define OPTION_ACPRES_DEGLITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) /* OPTION_IFAULT_LOW_THRESHOLD */ #define IFAULT_LOW_135MV_DEFAULT (0 << 7) -#define IFAULT_LOW_230MV (1 << 7) +#define IFAULT_LOW_230MV BIT(7) /* OPTION_BAT_DEPLETION_THRESHOLD */ #define FALLING_THRESHOLD_5919 (0 << 11) -#define FALLING_THRESHOLD_6265 (1 << 11) +#define FALLING_THRESHOLD_6265 BIT(11) #define FALLING_THRESHOLD_6655 (2 << 11) #define FALLING_THRESHOLD_7097_DEFAULT (3 << 11) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) /* OPTION_ACPRES_DEGLITCH_TIME */ #define ACPRES_DEGLITCH_150MS (0 << 15) -#define ACPRES_DEGLITCH_1300MS_DEFAULT (1 << 15) +#define ACPRES_DEGLITCH_1300MS_DEFAULT BIT(15) #endif /* __CROS_EC_BQ24735_H */ diff --git a/driver/charger/bq24738.h b/driver/charger/bq24738.h index a40a9e193f..194a2941c0 100644 --- a/driver/charger/bq24738.h +++ b/driver/charger/bq24738.h @@ -15,43 +15,43 @@ #define BQ24738_DEVICE_ID 0xff /* ChargeOption 0x12 */ -#define OPTION_CHARGE_INHIBIT (1 << 0) -#define OPTION_ACOC_THRESHOLD (1 << 1) -#define OPTION_BOOST_MODE_STATE (1 << 2) -#define OPTION_BOOST_MODE_ENABLE (1 << 3) -#define OPTION_ACDET_STATE (1 << 4) -#define OPTION_IOUT_SELECTION (1 << 5) -#define OPTION_LEARN_ENABLE (1 << 6) -#define OPTION_IFAULT_LOW_THRESHOLD (1 << 7) -#define OPTION_IFAULT_HI_ENABLE (1 << 8) -#define OPTION_EMI_FREQ_ENABLE (1 << 9) -#define OPTION_EMI_FREQ_ADJ (1 << 10) +#define OPTION_CHARGE_INHIBIT BIT(0) +#define OPTION_ACOC_THRESHOLD BIT(1) +#define OPTION_BOOST_MODE_STATE BIT(2) +#define OPTION_BOOST_MODE_ENABLE BIT(3) +#define OPTION_ACDET_STATE BIT(4) +#define OPTION_IOUT_SELECTION BIT(5) +#define OPTION_LEARN_ENABLE BIT(6) +#define OPTION_IFAULT_LOW_THRESHOLD BIT(7) +#define OPTION_IFAULT_HI_ENABLE BIT(8) +#define OPTION_EMI_FREQ_ENABLE BIT(9) +#define OPTION_EMI_FREQ_ADJ BIT(10) #define OPTION_BAT_DEPLETION_THRESHOLD (3 << 11) #define OPTION_WATCHDOG_TIMER (3 << 13) -#define OPTION_ACPRES_DEGLITCH_TIME (1 << 15) +#define OPTION_ACPRES_DEGLITCH_TIME BIT(15) /* OPTION_ACOC_THRESHOLD */ #define ACOC_THRESHOLD_DISABLE (0 << 1) -#define ACOC_THRESHOLD_133X (1 << 1) +#define ACOC_THRESHOLD_133X BIT(1) /* OPTION_IFAULT_LOW_THRESHOLD */ #define IFAULT_LOW_135MV_DEFAULT (0 << 7) -#define IFAULT_LOW_230MV (1 << 7) +#define IFAULT_LOW_230MV BIT(7) /* OPTION_BAT_DEPLETION_THRESHOLD */ #define FALLING_THRESHOLD_5919 (0 << 11) -#define FALLING_THRESHOLD_6265 (1 << 11) +#define FALLING_THRESHOLD_6265 BIT(11) #define FALLING_THRESHOLD_6655 (2 << 11) #define FALLING_THRESHOLD_7097_DEFAULT (3 << 11) /* OPTION_WATCHDOG_TIMER */ #define CHARGE_WATCHDOG_DISABLE (0 << 13) -#define CHARGE_WATCHDOG_44SEC (1 << 13) +#define CHARGE_WATCHDOG_44SEC BIT(13) #define CHARGE_WATCHDOG_88SEC (2 << 13) #define CHARGE_WATCHDOG_175SEC_DEFAULT (3 << 13) /* OPTION_ACPRES_DEGLITCH_TIME */ #define ACPRES_DEGLITCH_150MS (0 << 15) -#define ACPRES_DEGLITCH_1300MS_DEFAULT (1 << 15) +#define ACPRES_DEGLITCH_1300MS_DEFAULT BIT(15) #endif /* __CROS_EC_BQ24738_H */ diff --git a/driver/charger/bq24773.h b/driver/charger/bq24773.h index 216e3d4c77..2f1a7ffad2 100644 --- a/driver/charger/bq24773.h +++ b/driver/charger/bq24773.h @@ -41,15 +41,15 @@ #define BQ24773_CHARGE_OPTION2 0x10 /* Option bits */ -#define OPTION0_CHARGE_INHIBIT (1 << 0) -#define OPTION0_LEARN_ENABLE (1 << 5) +#define OPTION0_CHARGE_INHIBIT BIT(0) +#define OPTION0_LEARN_ENABLE BIT(5) #define OPTION0_SWITCHING_FREQ_MASK (3 << 8) #define OPTION0_SWITCHING_FREQ_600KHZ (0 << 8) -#define OPTION0_SWITCHING_FREQ_800KHZ (1 << 8) +#define OPTION0_SWITCHING_FREQ_800KHZ BIT(8) #define OPTION0_SWITCHING_FREQ_1000KHZ (2 << 8) #define OPTION0_SWITCHING_FREQ_1200KHZ (3 << 8) -#define OPTION2_EN_EXTILIM (1 << 7) +#define OPTION2_EN_EXTILIM BIT(7) /* Prochot Option bits */ #define PROCHOT_OPTION1_SELECTOR_MASK 0x7f /* [6:0] PROCHOT SELECTOR */ diff --git a/driver/charger/bq25703.h b/driver/charger/bq25703.h index db2c246658..54d64a81c7 100644 --- a/driver/charger/bq25703.h +++ b/driver/charger/bq25703.h @@ -24,9 +24,9 @@ /* ChargeOption0 Register */ #define BQ25703_REG_CHARGE_OPTION_0 0x00 -#define BQ25703_CHARGE_OPTION_0_LOW_POWER_MODE (1 << 15) -#define BQ25703_CHARGE_OPTION_0_EN_LEARN (1 << 5) -#define BQ25703_CHARGE_OPTION_0_CHRG_INHIBIT (1 << 0) +#define BQ25703_CHARGE_OPTION_0_LOW_POWER_MODE BIT(15) +#define BQ25703_CHARGE_OPTION_0_EN_LEARN BIT(5) +#define BQ25703_CHARGE_OPTION_0_CHRG_INHIBIT BIT(0) #define BQ25703_REG_CHARGE_CURRENT 0x02 #define BQ25703_REG_MAX_CHARGE_VOLTAGE 0x04 @@ -34,23 +34,23 @@ /* ChargeOption2 Register */ #define BQ25703_REG_CHARGE_OPTION_2 0x32 -#define BQ25703_CHARGE_OPTION_2_EN_EXTILIM (1 << 7) +#define BQ25703_CHARGE_OPTION_2_EN_EXTILIM BIT(7) /* ChargeOption3 Register */ #define BQ25703_REG_CHARGE_OPTION_3 0x34 -#define BQ25703_CHARGE_OPTION_3_EN_ICO_MODE (1 << 11) +#define BQ25703_CHARGE_OPTION_3_EN_ICO_MODE BIT(11) #define BQ25703_REG_PROCHOT_OPTION_0 0x36 #define BQ25703_REG_PROCHOT_OPTION_1 0x38 /* ADCOption Register */ #define BQ25703_REG_ADC_OPTION 0x3A -#define BQ25703_ADC_OPTION_ADC_START (1 << 14) -#define BQ25703_ADC_OPTION_EN_ADC_IIN (1 << 4) +#define BQ25703_ADC_OPTION_ADC_START BIT(14) +#define BQ25703_ADC_OPTION_EN_ADC_IIN BIT(4) /* ChargeStatus Register */ #define BQ25703_REG_CHARGER_STATUS 0x20 -#define BQ25703_CHARGE_STATUS_ICO_DONE (1 << 14) +#define BQ25703_CHARGE_STATUS_ICO_DONE BIT(14) #define BQ25703_REG_PROCHOT_STATUS 0x22 #define BQ25703_REG_IIN_DPM 0x25 diff --git a/driver/charger/bq25710.h b/driver/charger/bq25710.h index 086bf13edb..73d7545c06 100644 --- a/driver/charger/bq25710.h +++ b/driver/charger/bq25710.h @@ -40,27 +40,27 @@ #define BQ25710_REG_DEVICE_ADDRESS 0xFF /* ChargeOption0 Register */ -#define BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE (1 << 15) -#define BQ25710_CHARGE_OPTION_0_EN_LEARN (1 << 5) -#define BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT (1 << 0) +#define BQ25710_CHARGE_OPTION_0_LOW_POWER_MODE BIT(15) +#define BQ25710_CHARGE_OPTION_0_EN_LEARN BIT(5) +#define BQ25710_CHARGE_OPTION_0_CHRG_INHIBIT BIT(0) /* ChargeOption2 Register */ -#define BQ25710_CHARGE_OPTION_2_EN_EXTILIM (1 << 7) +#define BQ25710_CHARGE_OPTION_2_EN_EXTILIM BIT(7) /* ChargeOption3 Register */ -#define BQ25710_CHARGE_OPTION_3_EN_ICO_MODE (1 << 11) +#define BQ25710_CHARGE_OPTION_3_EN_ICO_MODE BIT(11) /* ChargeStatus Register */ -#define BQ25710_CHARGE_STATUS_ICO_DONE (1 << 14) +#define BQ25710_CHARGE_STATUS_ICO_DONE BIT(14) /* IIN_DPM Register */ #define BQ25710_CHARGE_IIN_BIT_0FFSET 8 #define BQ25710_CHARGE_MA_PER_STEP 50 /* ADCOption Register */ -#define BQ25710_ADC_OPTION_ADC_START (1 << 14) -#define BQ25710_ADC_OPTION_EN_ADC_VBUS (1 << 6) -#define BQ25710_ADC_OPTION_EN_ADC_IIN (1 << 4) +#define BQ25710_ADC_OPTION_ADC_START BIT(14) +#define BQ25710_ADC_OPTION_EN_ADC_VBUS BIT(6) +#define BQ25710_ADC_OPTION_EN_ADC_IIN BIT(4) #define BQ25710_ADC_OPTION_EN_ADC_ALL 0xFF /* ADCVBUS/PSYS Register */ @@ -73,6 +73,6 @@ #define BQ25710_ADC_IIN_STEP_BIT_OFFSET 8 /* ProchotOption1 Register */ -#define BQ25710_PROCHOT_PROFILE_VDPM (1 << 7) +#define BQ25710_PROCHOT_PROFILE_VDPM BIT(7) #endif /* __CROS_EC_BQ25710_H */ diff --git a/driver/charger/bq2589x.h b/driver/charger/bq2589x.h index ed49aeb661..c13d34ec7d 100644 --- a/driver/charger/bq2589x.h +++ b/driver/charger/bq2589x.h @@ -52,7 +52,7 @@ #define BQ2589X_IR_BAT_COMP_80MOHM (4 << 5) #define BQ2589X_IR_BAT_COMP_60MOHM (3 << 5) #define BQ2589X_IR_BAT_COMP_40MOHM (2 << 5) -#define BQ2589X_IR_BAT_COMP_20MOHM (1 << 5) +#define BQ2589X_IR_BAT_COMP_20MOHM BIT(5) #define BQ2589X_IR_BAT_COMP_0MOHM (0 << 5) #define BQ2589X_IR_VCLAMP_224MV (7 << 2) #define BQ2589X_IR_VCLAMP_192MV (6 << 2) @@ -60,11 +60,11 @@ #define BQ2589X_IR_VCLAMP_128MV (4 << 2) #define BQ2589X_IR_VCLAMP_96MV (3 << 2) #define BQ2589X_IR_VCLAMP_64MV (2 << 2) -#define BQ2589X_IR_VCLAMP_32MV (1 << 2) +#define BQ2589X_IR_VCLAMP_32MV BIT(2) #define BQ2589X_IR_VCLAMP_0MV (0 << 2) #define BQ2589X_IR_TREG_120C (3 << 0) #define BQ2589X_IR_TREG_100C (2 << 0) -#define BQ2589X_IR_TREG_80C (1 << 0) +#define BQ2589X_IR_TREG_80C BIT(0) #define BQ2589X_IR_TREG_60C (0 << 0) #define BQ2589X_IR_COMP_DEFAULT (BQ2589X_IR_TREG_120C | BQ2589X_IR_VCLAMP_0MV |\ diff --git a/driver/charger/isl923x.h b/driver/charger/isl923x.h index 118f22b77d..7947ce07bb 100644 --- a/driver/charger/isl923x.h +++ b/driver/charger/isl923x.h @@ -63,7 +63,7 @@ /* PROCHOT# debounce time and duration time in micro seconds */ #define ISL923X_PROCHOT_DURATION_10000 (0 << 6) -#define ISL923X_PROCHOT_DURATION_20000 (1 << 6) +#define ISL923X_PROCHOT_DURATION_20000 BIT(6) #define ISL923X_PROCHOT_DURATION_15000 (2 << 6) #define ISL923X_PROCHOT_DURATION_5000 (3 << 6) #define ISL923X_PROCHOT_DURATION_1000 (4 << 6) @@ -73,7 +73,7 @@ #define ISL923X_PROCHOT_DURATION_MASK (7 << 6) #define ISL923X_PROCHOT_DEBOUNCE_10 (0 << 9) -#define ISL923X_PROCHOT_DEBOUNCE_100 (1 << 9) +#define ISL923X_PROCHOT_DEBOUNCE_100 BIT(9) #define ISL923X_PROCHOT_DEBOUNCE_500 (2 << 9) #define ISL923X_PROCHOT_DEBOUNCE_1000 (3 << 9) #define ISL923X_PROCHOT_DEBOUNCE_MASK (3 << 9) @@ -90,35 +90,35 @@ #define ISL9237_C0_VREG_REF_MASK 0x03 /* Control0: disable adapter voltaqe regulation */ -#define ISL923X_C0_DISABLE_VREG (1 << 2) +#define ISL923X_C0_DISABLE_VREG BIT(2) /* Control0: battery DCHOT reference for RS2 == 20mOhm */ #define ISL923X_C0_DCHOT_6A (0 << 3) -#define ISL923X_C0_DCHOT_5A (1 << 3) +#define ISL923X_C0_DCHOT_5A BIT(3) #define ISL923X_C0_DCHOT_4A (2 << 3) #define ISL923X_C0_DCHOT_3A (3 << 3) #define ISL923X_C0_DCHOT_MASK (3 << 3) /* Control1: general purpose comparator debounce time in micro second */ #define ISL923X_C1_GP_DEBOUNCE_2 (0 << 14) -#define ISL923X_C1_GP_DEBOUNCE_12 (1 << 14) +#define ISL923X_C1_GP_DEBOUNCE_12 BIT(14) #define ISL923X_C1_GP_DEBOUNCE_2000 (2 << 14) #define ISL923X_C1_GP_DEBOUNCE_5000000 (3 << 14) #define ISL923X_C1_GP_DEBOUNCE_MASK (3 << 14) /* Control1: learn mode */ -#define ISL923X_C1_LEARN_MODE_AUTOEXIT (1 << 13) -#define ISL923X_C1_LEARN_MODE_ENABLE (1 << 12) +#define ISL923X_C1_LEARN_MODE_AUTOEXIT BIT(13) +#define ISL923X_C1_LEARN_MODE_ENABLE BIT(12) /* Control1: OTG enable */ -#define ISL923X_C1_OTG (1 << 11) +#define ISL923X_C1_OTG BIT(11) /* Control1: audio filter */ -#define ISL923X_C1_AUDIO_FILTER (1 << 10) +#define ISL923X_C1_AUDIO_FILTER BIT(10) /* Control1: switch frequency, ISL9238 defines bit 7 as unused */ #define ISL923X_C1_SWITCH_FREQ_PROG (0 << 7) /* 1000kHz or PROG */ -#define ISL9237_C1_SWITCH_FREQ_913K (1 << 7) +#define ISL9237_C1_SWITCH_FREQ_913K BIT(7) #define ISL923X_C1_SWITCH_FREQ_839K (2 << 7) #define ISL9237_C1_SWITCH_FREQ_777K (3 << 7) #define ISL923X_C1_SWITCH_FREQ_723K (4 << 7) @@ -128,15 +128,15 @@ #define ISL923X_C1_SWITCH_FREQ_MASK (7 << 7) /* Control1: turbo mode */ -#define ISL923X_C1_TURBO_MODE (1 << 6) +#define ISL923X_C1_TURBO_MODE BIT(6) /* Control1: AMON & BMON */ -#define ISL923X_C1_DISABLE_MON (1 << 5) -#define ISL923X_C1_SELECT_BMON (1 << 4) +#define ISL923X_C1_DISABLE_MON BIT(5) +#define ISL923X_C1_SELECT_BMON BIT(4) /* Control1: PSYS, VSYS, VSYSLO */ -#define ISL923X_C1_ENABLE_PSYS (1 << 3) -#define ISL923X_C1_ENABLE_VSYS (1 << 2) +#define ISL923X_C1_ENABLE_PSYS BIT(3) +#define ISL923X_C1_ENABLE_VSYS BIT(2) #define ISL923X_C1_VSYSLO_REF_6000 0 #define ISL923X_C1_VSYSLO_REF_6300 1 #define ISL923X_C1_VSYSLO_REF_6600 2 @@ -145,35 +145,35 @@ /* Control2: trickle charging current in mA */ #define ISL923X_C2_TRICKLE_256 (0 << 14) -#define ISL923X_C2_TRICKLE_128 (1 << 14) +#define ISL923X_C2_TRICKLE_128 BIT(14) #define ISL923X_C2_TRICKLE_64 (2 << 14) #define ISL923X_C2_TRICKLE_512 (3 << 14) #define ISL923X_C2_TRICKLE_MASK (3 << 14) /* Control2: OTGEN debounce time in ms */ #define ISL923X_C2_OTG_DEBOUNCE_1300 (0 << 13) -#define ISL923X_C2_OTG_DEBOUNCE_150 (1 << 13) -#define ISL923X_C2_OTG_DEBOUNCE_MASK (1 << 13) +#define ISL923X_C2_OTG_DEBOUNCE_150 BIT(13) +#define ISL923X_C2_OTG_DEBOUNCE_MASK BIT(13) /* Control2: 2-level adapter over current */ -#define ISL923X_C2_2LVL_OVERCURRENT (1 << 12) +#define ISL923X_C2_2LVL_OVERCURRENT BIT(12) /* Control2: adapter insertion debounce time in ms */ #define ISL923X_C2_ADAPTER_DEBOUNCE_1300 (0 << 11) -#define ISL923X_C2_ADAPTER_DEBOUNCE_150 (1 << 11) -#define ISL923X_C2_ADAPTER_DEBOUNCE_MASK (1 << 11) +#define ISL923X_C2_ADAPTER_DEBOUNCE_150 BIT(11) +#define ISL923X_C2_ADAPTER_DEBOUNCE_MASK BIT(11) /* Control2: PROCHOT debounce time in uS */ #define ISL9238_C2_PROCHOT_DEBOUNCE_7 (0 << 9) #define ISL9237_C2_PROCHOT_DEBOUNCE_10 (0 << 9) -#define ISL923X_C2_PROCHOT_DEBOUNCE_100 (1 << 9) +#define ISL923X_C2_PROCHOT_DEBOUNCE_100 BIT(9) #define ISL923X_C2_PROCHOT_DEBOUNCE_500 (2 << 9) #define ISL923X_C2_PROCHOT_DEBOUNCE_1000 (3 << 9) #define ISL923X_C2_PROCHOT_DEBOUNCE_MASK (3 << 9) /* Control2: min PROCHOT duration in uS */ #define ISL923X_C2_PROCHOT_DURATION_10000 (0 << 6) -#define ISL923X_C2_PROCHOT_DURATION_20000 (1 << 6) +#define ISL923X_C2_PROCHOT_DURATION_20000 BIT(6) #define ISL923X_C2_PROCHOT_DURATION_15000 (2 << 6) #define ISL923X_C2_PROCHOT_DURATION_5000 (3 << 6) #define ISL923X_C2_PROCHOT_DURATION_1000 (4 << 6) @@ -183,35 +183,35 @@ #define ISL923X_C2_PROCHOT_DURATION_MASK (7 << 6) /* Control2: turn off ASGATE in OTG mode */ -#define ISL923X_C2_ASGATE_OFF (1 << 5) +#define ISL923X_C2_ASGATE_OFF BIT(5) /* Control2: CMIN, general purpose comparator reference in mV */ #define ISL923X_C2_CMIN_2000 (0 << 4) -#define ISL923X_C2_CMIN_1200 (1 << 4) +#define ISL923X_C2_CMIN_1200 BIT(4) /* Control2: general purpose comparator enable */ -#define ISL923X_C2_COMPARATOR (1 << 3) +#define ISL923X_C2_COMPARATOR BIT(3) /* Control2: invert CMOUT, general purpose comparator output, polarity */ -#define ISL923X_C2_INVERT_CMOUT (1 << 2) +#define ISL923X_C2_INVERT_CMOUT BIT(2) /* Control2: disable WOC, way over current */ -#define ISL923X_C2_WOC_OFF (1 << 1) +#define ISL923X_C2_WOC_OFF BIT(1) /* Control2: PSYS gain in uA/W (ISL9237 only) */ -#define ISL9237_C2_PSYS_GAIN (1 << 0) +#define ISL9237_C2_PSYS_GAIN BIT(0) /* * Control3: Buck-Boost switching period * 0: x1 frequency, 1: half frequency. */ -#define ISL9238_C3_BB_SWITCHING_PERIOD (1 << 1) +#define ISL9238_C3_BB_SWITCHING_PERIOD BIT(1) /* * Control3: AMON/BMON direction. * 0: adapter/charging, 1:OTG/discharging (ISL9238 only) */ -#define ISL9238_C3_AMON_BMON_DIRECTION (1 << 3) +#define ISL9238_C3_AMON_BMON_DIRECTION BIT(3) /* * Control3: Disables Autonomous Charing @@ -219,16 +219,16 @@ * Note: This is disabled automatically when ever we set the current limit * manually (which we always do). */ -#define ISL9238_C3_DISABLE_AUTO_CHARING (1 << 7) +#define ISL9238_C3_DISABLE_AUTO_CHARING BIT(7) /* Control3: PSYS gain in uA/W (ISL9238 only) */ -#define ISL9238_C3_PSYS_GAIN (1 << 9) +#define ISL9238_C3_PSYS_GAIN BIT(9) /* Control3: Don't reload ACLIM on ACIN. */ -#define ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN (1 << 14) +#define ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN BIT(14) /* Control3: Don't reread PROG pin. */ -#define ISL9238_C3_NO_REREAD_PROG_PIN (1 << 15) +#define ISL9238_C3_NO_REREAD_PROG_PIN BIT(15) /* OTG voltage limit in mV, current limit in mA */ #define ISL9237_OTG_VOLTAGE_MIN 4864 @@ -247,7 +247,7 @@ /* Info register fields */ #define ISL9237_INFO_PROG_RESISTOR_MASK 0xf -#define ISL923X_INFO_TRICKLE_ACTIVE_MASK (1 << 4) +#define ISL923X_INFO_TRICKLE_ACTIVE_MASK BIT(4) #define ISL9237_INFO_PSTATE_SHIFT 5 #define ISL9237_INFO_PSTATE_MASK 3 @@ -272,9 +272,9 @@ enum isl9237_fsm_state { FSM_OTG }; -#define ISL923X_INFO_VSYSLO (1 << 10) -#define ISL923X_INFO_DCHOT (1 << 11) -#define ISL9237_INFO_ACHOT (1 << 12) +#define ISL923X_INFO_VSYSLO BIT(10) +#define ISL923X_INFO_DCHOT BIT(11) +#define ISL9237_INFO_ACHOT BIT(12) #if defined(CONFIG_CHARGER_ISL9237) #define CHARGER_NAME "isl9237" diff --git a/driver/charger/sy21612.h b/driver/charger/sy21612.h index 9d531a1ee2..d685406fcf 100644 --- a/driver/charger/sy21612.h +++ b/driver/charger/sy21612.h @@ -41,25 +41,25 @@ enum sy21612_vbus_adj { }; #define SY21612_CTRL1 0x00 -#define SY21612_CTRL1_REG_EN (1 << 7) +#define SY21612_CTRL1_REG_EN BIT(7) #define SY21612_CTRL1_LOW_BAT_MASK (7 << 4) #define SY21612_CTRL1_LOW_BAT_10_2V (0 << 4) -#define SY21612_CTRL1_LOW_BAT_10_7V (1 << 4) +#define SY21612_CTRL1_LOW_BAT_10_7V BIT(4) #define SY21612_CTRL1_LOW_BAT_11_2V (2 << 4) #define SY21612_CTRL1_LOW_BAT_11_7V (3 << 4) #define SY21612_CTRL1_LOW_BAT_22_0V (4 << 4) #define SY21612_CTRL1_LOW_BAT_22_5V (5 << 4) #define SY21612_CTRL1_LOW_BAT_23_0V (6 << 4) #define SY21612_CTRL1_LOW_BAT_23_5V (7 << 4) -#define SY21612_CTRL1_ADC_EN (1 << 3) -#define SY21612_CTRL1_ADC_AUTO_MODE (1 << 2) -#define SY21612_CTRL1_VBUS_NDISCHG (1 << 1) +#define SY21612_CTRL1_ADC_EN BIT(3) +#define SY21612_CTRL1_ADC_AUTO_MODE BIT(2) +#define SY21612_CTRL1_VBUS_NDISCHG BIT(1) #define SY21612_CTRL2 0x01 #define SY21612_CTRL2_FREQ_MASK (3 << 6) #define SY21612_CTRL2_FREQ_SHIFT 6 #define SY21612_CTRL2_FREQ_250K (0 << 6) -#define SY21612_CTRL2_FREQ_500K (1 << 6) +#define SY21612_CTRL2_FREQ_500K BIT(6) #define SY21612_CTRL2_FREQ_750K (2 << 6) #define SY21612_CTRL2_FREQ_1M (3 << 6) #define SY21612_CTRL2_VBUS_MASK (7 << 3) @@ -83,7 +83,7 @@ enum sy21612_vbus_adj { #define SY21612_PROT1 0x02 #define SY21612_PROT1_I_THRESH_MASK (7 << 5) #define SY21612_PROT1_I_THRESH_18MV (0 << 5) -#define SY21612_PROT1_I_THRESH_22MV (1 << 5) +#define SY21612_PROT1_I_THRESH_22MV BIT(5) #define SY21612_PROT1_I_THRESH_27MV (2 << 5) #define SY21612_PROT1_I_THRESH_31MV (3 << 5) #define SY21612_PROT1_I_THRESH_36MV (4 << 5) @@ -92,12 +92,12 @@ enum sy21612_vbus_adj { #define SY21612_PROT1_I_THRESH_64MV (7 << 5) #define SY21612_PROT1_OVP_THRESH_MASK (3 << 3) #define SY21612_PROT1_OVP_THRESH_110 (0 << 3) -#define SY21612_PROT1_OVP_THRESH_115 (1 << 3) +#define SY21612_PROT1_OVP_THRESH_115 BIT(3) #define SY21612_PROT1_OVP_THRESH_120 (2 << 3) #define SY21612_PROT1_OVP_THRESH_125 (3 << 3) #define SY21612_PROT1_UVP_THRESH_MASK (3 << 1) #define SY21612_PROT1_UVP_THRESH_50 (0 << 1) -#define SY21612_PROT1_UVP_THRESH_60 (1 << 1) +#define SY21612_PROT1_UVP_THRESH_60 BIT(1) #define SY21612_PROT1_UVP_THRESH_70 (2 << 1) #define SY21612_PROT1_UVP_THRESH_80 (3 << 1) @@ -106,22 +106,22 @@ enum sy21612_vbus_adj { #define SY21612_PROT2_I_LIMIT_6A (0 << 6) #define SY21612_PROT2_I_LIMIT_8A (2 << 6) #define SY21612_PROT2_I_LIMIT_10A (3 << 6) -#define SY21612_PROT2_OCP_AUTORECOVER (1 << 5) -#define SY21612_PROT2_UVP_AUTORECOVER (1 << 4) -#define SY21612_PROT2_OTP_AUTORECOVER (1 << 3) -#define SY21612_PROT2_SINK_MODE (1 << 2) +#define SY21612_PROT2_OCP_AUTORECOVER BIT(5) +#define SY21612_PROT2_UVP_AUTORECOVER BIT(4) +#define SY21612_PROT2_OTP_AUTORECOVER BIT(3) +#define SY21612_PROT2_SINK_MODE BIT(2) #define SY21612_STATE 0x04 -#define SY21612_STATE_POWER_GOOD (1 << 7) -#define SY21612_STATE_VBAT_LT_VBUS (1 << 6) -#define SY21612_STATE_VBAT_LOW (1 << 5) +#define SY21612_STATE_POWER_GOOD BIT(7) +#define SY21612_STATE_VBAT_LT_VBUS BIT(6) +#define SY21612_STATE_VBAT_LOW BIT(5) #define SY21612_INT 0x05 -#define SY21612_INT_ADC_READY (1 << 7) -#define SY21612_INT_VBUS_OCP (1 << 6) -#define SY21612_INT_INDUCTOR_OCP (1 << 5) -#define SY21612_INT_UVP (1 << 4) -#define SY21612_INT_OTP (1 << 3) +#define SY21612_INT_ADC_READY BIT(7) +#define SY21612_INT_VBUS_OCP BIT(6) +#define SY21612_INT_INDUCTOR_OCP BIT(5) +#define SY21612_INT_UVP BIT(4) +#define SY21612_INT_OTP BIT(3) /* Battery voltage range: 0 ~ 25V */ #define SY21612_VBAT_VOLT 0x06 diff --git a/driver/gyro_l3gd20h.c b/driver/gyro_l3gd20h.c index 2afe948f27..d7d3663ab2 100644 --- a/driver/gyro_l3gd20h.c +++ b/driver/gyro_l3gd20h.c @@ -75,7 +75,7 @@ static inline int get_ctrl_reg(enum motionsensor_type type) static inline int get_xyz_reg(enum motionsensor_type type) { - return L3GD20_OUT_X_L | (1 << 7); + return L3GD20_OUT_X_L | BIT(7); } /** @@ -240,8 +240,8 @@ static int set_data_rate(const struct motion_sensor_t *s, if (ret != EC_SUCCESS) goto gyro_cleanup; - val |= (1 << 4); /* high-pass filter enabled */ - val |= (1 << 0); /* data in data reg are high-pass filtered */ + val |= BIT(4); /* high-pass filter enabled */ + val |= BIT(0); /* data in data reg are high-pass filtered */ ret = raw_write8(s->port, s->addr, L3GD20_CTRL_REG5, val); if (ret != EC_SUCCESS) goto gyro_cleanup; diff --git a/driver/gyro_l3gd20h.h b/driver/gyro_l3gd20h.h index 24ad81a693..1864c5afac 100644 --- a/driver/gyro_l3gd20h.h +++ b/driver/gyro_l3gd20h.h @@ -51,25 +51,25 @@ #define L3GD20_LOW_ODR 0x39 #define L3GD20_DPS_SEL_245 (0 << 4) -#define L3GD20_DPS_SEL_500 (1 << 4) +#define L3GD20_DPS_SEL_500 BIT(4) #define L3GD20_DPS_SEL_2000_0 (2 << 4) #define L3GD20_DPS_SEL_2000_1 (3 << 4) #define L3GD20_ODR_PD (0 << 3) #define L3GD20_ODR_12_5HZ (0 << 6) -#define L3GD20_ODR_25HZ (1 << 6) +#define L3GD20_ODR_25HZ BIT(6) #define L3GD20_ODR_50HZ_0 (2 << 6) #define L3GD20_ODR_50HZ_1 (3 << 6) #define L3GD20_ODR_100HZ (0 << 6) -#define L3GD20_ODR_200HZ (1 << 6) +#define L3GD20_ODR_200HZ BIT(6) #define L3GD20_ODR_400HZ (2 << 6) #define L3GD20_ODR_800HZ (3 << 6) #define L3GD20_ODR_MASK (3 << 6) -#define L3GD20_STS_ZYXDA_MASK (1 << 3) +#define L3GD20_STS_ZYXDA_MASK BIT(3) #define L3GD20_RANGE_MASK (3 << 4) -#define L3GD20_LOW_ODR_MASK (1 << 0) -#define L3GD20_ODR_PD_MASK (1 << 3) +#define L3GD20_LOW_ODR_MASK BIT(0) +#define L3GD20_ODR_PD_MASK BIT(3) /* Min and Max sampling frequency in mHz */ #define L3GD20_GYRO_MIN_FREQ 12500 diff --git a/driver/ina2xx.h b/driver/ina2xx.h index b1ddbd1368..9af3ab06df 100644 --- a/driver/ina2xx.h +++ b/driver/ina2xx.h @@ -19,10 +19,10 @@ #define INA2XX_CONFIG_MODE_MASK (7 << 0) #define INA2XX_CONFIG_MODE_PWRDWN (0 << 0) -#define INA2XX_CONFIG_MODE_SHUNT (1 << 0) -#define INA2XX_CONFIG_MODE_BUS (1 << 1) +#define INA2XX_CONFIG_MODE_SHUNT BIT(0) +#define INA2XX_CONFIG_MODE_BUS BIT(1) #define INA2XX_CONFIG_MODE_TRG (0 << 2) -#define INA2XX_CONFIG_MODE_CONT (1 << 2) +#define INA2XX_CONFIG_MODE_CONT BIT(2) /* Conversion time for bus and shunt in micro-seconds */ enum ina2xx_conv_time { @@ -40,7 +40,7 @@ enum ina2xx_conv_time { #define INA2XX_CONFIG_BUS_CONV_TIME(t) ((t) << 6) #define INA2XX_CONFIG_AVG_1 (0 << 9) -#define INA2XX_CONFIG_AVG_4 (1 << 9) +#define INA2XX_CONFIG_AVG_4 BIT(9) #define INA2XX_CONFIG_AVG_16 (2 << 9) #define INA2XX_CONFIG_AVG_64 (3 << 9) #define INA2XX_CONFIG_AVG_128 (4 << 9) @@ -48,17 +48,17 @@ enum ina2xx_conv_time { #define INA2XX_CONFIG_AVG_512 (6 << 9) #define INA2XX_CONFIG_AVG_1024 (7 << 9) -#define INA2XX_MASK_EN_LEN (1 << 0) -#define INA2XX_MASK_EN_APOL (1 << 1) -#define INA2XX_MASK_EN_OVF (1 << 2) -#define INA2XX_MASK_EN_CVRF (1 << 3) -#define INA2XX_MASK_EN_AFF (1 << 4) -#define INA2XX_MASK_EN_CNVR (1 << 10) -#define INA2XX_MASK_EN_POL (1 << 11) -#define INA2XX_MASK_EN_BUL (1 << 12) -#define INA2XX_MASK_EN_BOL (1 << 13) -#define INA2XX_MASK_EN_SUL (1 << 14) -#define INA2XX_MASK_EN_SOL (1 << 15) +#define INA2XX_MASK_EN_LEN BIT(0) +#define INA2XX_MASK_EN_APOL BIT(1) +#define INA2XX_MASK_EN_OVF BIT(2) +#define INA2XX_MASK_EN_CVRF BIT(3) +#define INA2XX_MASK_EN_AFF BIT(4) +#define INA2XX_MASK_EN_CNVR BIT(10) +#define INA2XX_MASK_EN_POL BIT(11) +#define INA2XX_MASK_EN_BUL BIT(12) +#define INA2XX_MASK_EN_BOL BIT(13) +#define INA2XX_MASK_EN_SUL BIT(14) +#define INA2XX_MASK_EN_SOL BIT(15) #if defined(CONFIG_INA231) && defined(CONFIG_INA219) diff --git a/driver/ioexpander_it8300.h b/driver/ioexpander_it8300.h index b457d89ddc..2b47e7f3e1 100644 --- a/driver/ioexpander_it8300.h +++ b/driver/ioexpander_it8300.h @@ -68,10 +68,10 @@ #define IT8300_GPCR_E5 0x37 #define IT8300_GPCR_E6 0x38 -#define IT8300_GPCR_GPI_MODE (1 << 7) -#define IT8300_GPCR_GP0_MODE (1 << 6) -#define IT8300_GPCR_PULL_UP_EN (1 << 2) -#define IT8300_GPCR_PULL_DN_EN (1 << 1) +#define IT8300_GPCR_GPI_MODE BIT(7) +#define IT8300_GPCR_GP0_MODE BIT(6) +#define IT8300_GPCR_PULL_UP_EN BIT(2) +#define IT8300_GPCR_PULL_DN_EN BIT(1) /* EXGPIO Clear Alert */ #define IT8300_ECA 0x30 @@ -94,13 +94,13 @@ #define IT8300_OODER_E 0x3D /* IT83200 Port GPIOs */ -#define IT8300_GPX_0 (1 << 0) -#define IT8300_GPX_1 (1 << 1) -#define IT8300_GPX_2 (1 << 2) -#define IT8300_GPX_3 (1 << 3) -#define IT8300_GPX_4 (1 << 4) -#define IT8300_GPX_5 (1 << 5) -#define IT8300_GPX_6 (1 << 6) -#define IT8300_GPX_7 (1 << 7) +#define IT8300_GPX_0 BIT(0) +#define IT8300_GPX_1 BIT(1) +#define IT8300_GPX_2 BIT(2) +#define IT8300_GPX_3 BIT(3) +#define IT8300_GPX_4 BIT(4) +#define IT8300_GPX_5 BIT(5) +#define IT8300_GPX_6 BIT(6) +#define IT8300_GPX_7 BIT(7) #endif /* __CROS_EC_IOEXPANDER_IT8300_H */ diff --git a/driver/ioexpander_pca9555.h b/driver/ioexpander_pca9555.h index 3a932ceef0..874f24356a 100644 --- a/driver/ioexpander_pca9555.h +++ b/driver/ioexpander_pca9555.h @@ -19,14 +19,14 @@ #define PCA9555_CMD_CONFIGURATION_PORT_0 6 #define PCA9555_CMD_CONFIGURATION_PORT_1 7 -#define PCA9555_IO_0 (1 << 0) -#define PCA9555_IO_1 (1 << 1) -#define PCA9555_IO_2 (1 << 2) -#define PCA9555_IO_3 (1 << 3) -#define PCA9555_IO_4 (1 << 4) -#define PCA9555_IO_5 (1 << 5) -#define PCA9555_IO_6 (1 << 6) -#define PCA9555_IO_7 (1 << 7) +#define PCA9555_IO_0 BIT(0) +#define PCA9555_IO_1 BIT(1) +#define PCA9555_IO_2 BIT(2) +#define PCA9555_IO_3 BIT(3) +#define PCA9555_IO_4 BIT(4) +#define PCA9555_IO_5 BIT(5) +#define PCA9555_IO_6 BIT(6) +#define PCA9555_IO_7 BIT(7) static inline int pca9555_read(int port, int addr, int reg, int *data_ptr) { diff --git a/driver/led/lm3630a.h b/driver/led/lm3630a.h index 38fc52e111..d43304b66e 100644 --- a/driver/led/lm3630a.h +++ b/driver/led/lm3630a.h @@ -27,37 +27,37 @@ #define LM3630A_REG_FILTER_STRENGTH 0x50 /* Control register bits */ -#define LM3630A_CTRL_BIT_SLEEP_CMD (1 << 7) -#define LM3630A_CTRL_BIT_SLEEP_STAT (1 << 6) -#define LM3630A_CTRL_BIT_LINEAR_A (1 << 4) -#define LM3630A_CTRL_BIT_LINEAR_B (1 << 3) -#define LM3630A_CTRL_BIT_LED_EN_A (1 << 2) -#define LM3630A_CTRL_BIT_LED_EN_B (1 << 1) -#define LM3630A_CTRL_BIT_LED2_ON_A (1 << 0) +#define LM3630A_CTRL_BIT_SLEEP_CMD BIT(7) +#define LM3630A_CTRL_BIT_SLEEP_STAT BIT(6) +#define LM3630A_CTRL_BIT_LINEAR_A BIT(4) +#define LM3630A_CTRL_BIT_LINEAR_B BIT(3) +#define LM3630A_CTRL_BIT_LED_EN_A BIT(2) +#define LM3630A_CTRL_BIT_LED_EN_B BIT(1) +#define LM3630A_CTRL_BIT_LED2_ON_A BIT(0) /* Config register bits */ -#define LM3630A_CFG_BIT_FB_EN_B (1 << 4) -#define LM3630A_CFG_BIT_FB_EN_A (1 << 3) -#define LM3630A_CFG_BIT_PWM_LOW (1 << 2) -#define LM3630A_CFG_BIT_PWM_EN_B (1 << 1) -#define LM3630A_CFG_BIT_PWM_EN_A (1 << 0) +#define LM3630A_CFG_BIT_FB_EN_B BIT(4) +#define LM3630A_CFG_BIT_FB_EN_A BIT(3) +#define LM3630A_CFG_BIT_PWM_LOW BIT(2) +#define LM3630A_CFG_BIT_PWM_EN_B BIT(1) +#define LM3630A_CFG_BIT_PWM_EN_A BIT(0) /* Boost control register bits */ #define LM3630A_BOOST_OVP_16V (0 << 5) -#define LM3630A_BOOST_OVP_24V (1 << 5) +#define LM3630A_BOOST_OVP_24V BIT(5) #define LM3630A_BOOST_OVP_32V (2 << 5) #define LM3630A_BOOST_OVP_40V (3 << 5) #define LM3630A_BOOST_OCP_600MA (0 << 3) -#define LM3630A_BOOST_OCP_800MA (1 << 3) +#define LM3630A_BOOST_OCP_800MA BIT(3) #define LM3630A_BOOST_OCP_1000MA (2 << 3) #define LM3630A_BOOST_OCP_1200MA (3 << 3) -#define LM3630A_BOOST_SLOW_START (1 << 2) +#define LM3630A_BOOST_SLOW_START BIT(2) #define LM3630A_SHIFT_500KHZ (0 << 1) /* FMODE=0 */ -#define LM3630A_SHIFT_560KHZ (1 << 1) /* FMODE=0 */ +#define LM3630A_SHIFT_560KHZ BIT(1) /* FMODE=0 */ #define LM3630A_SHIFT_1000KHZ (0 << 1) /* FMODE=1 */ -#define LM3630A_SHIFT_1120KHZ (1 << 1) /* FMODE=1 */ +#define LM3630A_SHIFT_1120KHZ BIT(1) /* FMODE=1 */ #define LM3630A_FMODE_500KHZ (0 << 0) -#define LM3630A_FMODE_1000KHZ (1 << 0) +#define LM3630A_FMODE_1000KHZ BIT(0) /* Power on and initialize LM3630A. */ int lm3630a_poweron(void); diff --git a/driver/mag_bmm150.c b/driver/mag_bmm150.c index cb53641c00..9598d85105 100644 --- a/driver/mag_bmm150.c +++ b/driver/mag_bmm150.c @@ -149,7 +149,7 @@ void bmm150_temp_compensate_xy(const struct motion_sensor_t *s, if (r == 0) inter = 0; else - inter = ((int)regs->dig_xyz1 << 14) / r - (1 << 14); + inter = ((int)regs->dig_xyz1 << 14) / r - BIT(14); for (axis = X; axis <= Y; axis++) { if (raw[axis] == BMM150_FLIP_OVERFLOW_ADCVAL) { @@ -195,16 +195,16 @@ void bmm150_temp_compensate_z(const struct motion_sensor_t *s, * ((z - dig_z4) * 131072 - dig_z3 * (r - dig_xyz1)) / * ((dig_z2 + dig_z1 * r / 32768) * 4); * - * We spread 4 so we multiply by 131072 / 4 == (1<<15) only. + * We spread 4 so we multiply by 131072 / 4 == BIT(15) only. */ dividend = (raw[Z] - (int)regs->dig_z4) << 15; dividend -= (regs->dig_z3 * (r - (int)regs->dig_xyz1)) >> 2; - /* add 1 << 15 to round to next integer. */ - divisor = (int)regs->dig_z1 * (r << 1) + (1 << 15); + /* add BIT(15) to round to next integer. */ + divisor = (int)regs->dig_z1 * (r << 1) + BIT(15); divisor >>= 16; divisor += (int)regs->dig_z2; comp[Z] = dividend / divisor; - if (comp[Z] > (1 << 15) || comp[Z] < -(1 << 15)) + if (comp[Z] > BIT(15) || comp[Z] < -(BIT(15))) comp[Z] = BMM150_OVERFLOW_OUTPUT; } diff --git a/driver/mag_bmm150.h b/driver/mag_bmm150.h index c15cbc065b..94777e1b61 100644 --- a/driver/mag_bmm150.h +++ b/driver/mag_bmm150.h @@ -23,8 +23,8 @@ #define BMM150_INT_STATUS 0x4a #define BMM150_PWR_CTRL 0x4b -#define BMM150_SRST ((1 << 7) | (1 << 1)) -#define BMM150_PWR_ON (1 << 0) +#define BMM150_SRST (BIT(7) | BIT(1)) +#define BMM150_PWR_ON BIT(0) #define BMM150_OP_CTRL 0x4c #define BMM150_OP_MODE_OFFSET 1 diff --git a/driver/pi3usb30532.h b/driver/pi3usb30532.h index 15a9241239..7f120a9f85 100644 --- a/driver/pi3usb30532.h +++ b/driver/pi3usb30532.h @@ -21,9 +21,9 @@ #define PI3USB30532_VENDOR_ID 0 /* PI3USB30532 control flags */ -#define PI3USB30532_BIT_SWAP (1 << 0) -#define PI3USB30532_BIT_DP (1 << 1) -#define PI3USB30532_BIT_USB (1 << 2) +#define PI3USB30532_BIT_SWAP BIT(0) +#define PI3USB30532_BIT_DP BIT(1) +#define PI3USB30532_BIT_USB BIT(2) /* PI3USB30532 modes */ /* Power down, switch open */ diff --git a/driver/pi3usb9281.h b/driver/pi3usb9281.h index 8ed4c77c57..980c565e21 100644 --- a/driver/pi3usb9281.h +++ b/driver/pi3usb9281.h @@ -21,40 +21,40 @@ #define PI3USB9281_DEV_ID 0x10 #define PI3USB9281_DEV_ID_A 0x18 -#define PI3USB9281_CTRL_INT_DIS (1 << 0) -#define PI3USB9281_CTRL_AUTO (1 << 2) -#define PI3USB9281_CTRL_SWITCH_AUTO (1 << 4) +#define PI3USB9281_CTRL_INT_DIS BIT(0) +#define PI3USB9281_CTRL_AUTO BIT(2) +#define PI3USB9281_CTRL_SWITCH_AUTO BIT(4) /* Bits 5 thru 7 are read X, write 0 */ #define PI3USB9281_CTRL_MASK 0x1f /* Bits 1 and 3 are read 1, write 1 */ #define PI3USB9281_CTRL_RSVD_1 0x0a #define PI3USB9281_PIN_MANUAL_VBUS (3 << 0) -#define PI3USB9281_PIN_MANUAL_DP (1 << 2) -#define PI3USB9281_PIN_MANUAL_DM (1 << 5) +#define PI3USB9281_PIN_MANUAL_DP BIT(2) +#define PI3USB9281_PIN_MANUAL_DM BIT(5) -#define PI3USB9281_INT_ATTACH (1 << 0) -#define PI3USB9281_INT_DETACH (1 << 1) -#define PI3USB9281_INT_OVP (1 << 5) -#define PI3USB9281_INT_OCP (1 << 6) -#define PI3USB9281_INT_OVP_OC (1 << 7) +#define PI3USB9281_INT_ATTACH BIT(0) +#define PI3USB9281_INT_DETACH BIT(1) +#define PI3USB9281_INT_OVP BIT(5) +#define PI3USB9281_INT_OCP BIT(6) +#define PI3USB9281_INT_OVP_OC BIT(7) #define PI3USB9281_INT_ATTACH_DETACH (PI3USB9281_INT_ATTACH | \ PI3USB9281_INT_DETACH) #define PI3USB9281_TYPE_NONE 0 -#define PI3USB9281_TYPE_MHL (1 << 0) -#define PI3USB9281_TYPE_OTG (1 << 1) -#define PI3USB9281_TYPE_SDP (1 << 2) -#define PI3USB9281_TYPE_CAR (1 << 4) -#define PI3USB9281_TYPE_CDP (1 << 5) -#define PI3USB9281_TYPE_DCP (1 << 6) +#define PI3USB9281_TYPE_MHL BIT(0) +#define PI3USB9281_TYPE_OTG BIT(1) +#define PI3USB9281_TYPE_SDP BIT(2) +#define PI3USB9281_TYPE_CAR BIT(4) +#define PI3USB9281_TYPE_CDP BIT(5) +#define PI3USB9281_TYPE_DCP BIT(6) #define PI3USB9281_CHG_NONE 0 -#define PI3USB9281_CHG_CAR_TYPE1 (1 << 1) +#define PI3USB9281_CHG_CAR_TYPE1 BIT(1) #define PI3USB9281_CHG_CAR_TYPE2 (3 << 0) -#define PI3USB9281_CHG_APPLE_1A (1 << 2) -#define PI3USB9281_CHG_APPLE_2A (1 << 3) -#define PI3USB9281_CHG_APPLE_2_4A (1 << 4) +#define PI3USB9281_CHG_APPLE_1A BIT(2) +#define PI3USB9281_CHG_APPLE_2A BIT(3) +#define PI3USB9281_CHG_APPLE_2_4A BIT(4) /* Check if charge status has any connection */ #define PI3USB9281_CHG_STATUS_ANY(x) (((x) & 0x1f) > 1) diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h index a59160bf29..e00ea1d252 100644 --- a/driver/pmic_bd99992gw.h +++ b/driver/pmic_bd99992gw.h @@ -26,6 +26,6 @@ #define BD99992GW_REG_DISCHGCNT3 0x3e #define BD99992GW_REG_DISCHGCNT4 0x3f #define BD99992GW_REG_SDWNCTRL 0x49 -#define BD99992GW_SDWNCTRL_SWDN (1 << 0) /* SWDN mask */ +#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */ #endif /* __CROS_EC_PMIC_BD99992GW_H */ diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c index 35202c8fe8..3423b77f53 100644 --- a/driver/ppc/nx20p348x.c +++ b/driver/ppc/nx20p348x.c @@ -27,7 +27,7 @@ static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */ #define NX20P348X_DB_EXIT_FAIL_THRESHOLD 10 static int db_exit_fail_count[CONFIG_USB_PD_PORT_COUNT]; -#define NX20P348X_FLAGS_SOURCE_ENABLED (1 << 0) +#define NX20P348X_FLAGS_SOURCE_ENABLED BIT(0) static uint8_t flags[CONFIG_USB_PD_PORT_COUNT]; static int read_reg(uint8_t port, int reg, int *regval) diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h index 68048be6ea..531842d766 100644 --- a/driver/ppc/nx20p348x.h +++ b/driver/ppc/nx20p348x.h @@ -40,10 +40,10 @@ #define NX20P348X_DEVICE_CONTROL_REG 0x0B /* Device Control Register */ -#define NX20P348X_CTRL_FRS_AT (1 << 3) -#define NX20P348X_CTRL_DB_EXIT (1 << 2) -#define NX20P348X_CTRL_VBUSDIS_EN (1 << 1) -#define NX20P348X_CTRL_LDO_SD (1 << 0) +#define NX20P348X_CTRL_FRS_AT BIT(3) +#define NX20P348X_CTRL_DB_EXIT BIT(2) +#define NX20P348X_CTRL_VBUSDIS_EN BIT(1) +#define NX20P348X_CTRL_LDO_SD BIT(0) /* Device Status Modes */ #define NX20P348X_DEVICE_MODE_MASK 0x7 @@ -59,14 +59,14 @@ #define NX20P3483_MODE_STANDBY 4 /* Switch Control Register */ -#define NX20P348X_SWITCH_CONTROL_HVSNK (1 << 0) -#define NX20P348X_SWITCH_CONTROL_HVSRC (1 << 1) -#define NX20P348X_SWITCH_CONTROL_5VSRC (1 << 2) +#define NX20P348X_SWITCH_CONTROL_HVSNK BIT(0) +#define NX20P348X_SWITCH_CONTROL_HVSRC BIT(1) +#define NX20P348X_SWITCH_CONTROL_5VSRC BIT(2) /* Switch Status Register */ -#define NX20P348X_HVSNK_STS (1 << 0) -#define NX20P348X_HVSRC_STS (1 << 1) -#define NX20P348X_5VSRC_STS (1 << 2) +#define NX20P348X_HVSNK_STS BIT(0) +#define NX20P348X_HVSRC_STS BIT(1) +#define NX20P348X_5VSRC_STS BIT(2) #define NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC 25 #define NX20P348X_SWITCH_STATUS_MASK 0x7 @@ -100,23 +100,23 @@ #define NX20P348X_OVLO_23_0 6 /* Interrupt 1 Register Bits */ -#define NX20P348X_INT1_DBEXIT_ERR (1 << 7) -#define NX20P348X_INT1_FRS_DET (1 << 6) -#define NX20P348X_INT1_OV_5VSRC (1 << 4) -#define NX20P348X_INT1_RCP_5VSRC (1 << 3) -#define NX20P348X_INT1_SC_5VSRC (1 << 2) -#define NX20P348X_INT1_OC_5VSRC (1 << 1) -#define NX20P348X_INT1_OTP (1 << 0) +#define NX20P348X_INT1_DBEXIT_ERR BIT(7) +#define NX20P348X_INT1_FRS_DET BIT(6) +#define NX20P348X_INT1_OV_5VSRC BIT(4) +#define NX20P348X_INT1_RCP_5VSRC BIT(3) +#define NX20P348X_INT1_SC_5VSRC BIT(2) +#define NX20P348X_INT1_OC_5VSRC BIT(1) +#define NX20P348X_INT1_OTP BIT(0) /* Interrupt 2 Register Bits */ -#define NX20P348X_INT2_EN_ERR (1 << 7) -#define NX20P348X_INT2_RCP_HVSNK (1 << 6) -#define NX20P348X_INT2_SC_HVSNK (1 << 5) -#define NX20P348X_INT2_OV_HVSNK (1 << 4) -#define NX20P348X_INT2_RCP_HVSRC (1 << 3) -#define NX20P348X_INT2_SC_HVSRC (1 << 2) -#define NX20P348X_INT2_OC_HVSRC (1 << 1) -#define NX20P348X_INT2_OV_HVSRC (1 << 0) +#define NX20P348X_INT2_EN_ERR BIT(7) +#define NX20P348X_INT2_RCP_HVSNK BIT(6) +#define NX20P348X_INT2_SC_HVSNK BIT(5) +#define NX20P348X_INT2_OV_HVSNK BIT(4) +#define NX20P348X_INT2_RCP_HVSRC BIT(3) +#define NX20P348X_INT2_SC_HVSRC BIT(2) +#define NX20P348X_INT2_OC_HVSRC BIT(1) +#define NX20P348X_INT2_OV_HVSRC BIT(0) struct ppc_drv; extern const struct ppc_drv nx20p348x_drv; diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h index c5b16ea73b..6c79aa46ed 100644 --- a/driver/ppc/sn5s330.h +++ b/driver/ppc/sn5s330.h @@ -86,44 +86,44 @@ enum sn5s330_pp_idx { #define SN5S330_ILIM_3_30 12 /* FUNC_SET_2 */ -#define SN5S330_SBU_EN (1 << 4) +#define SN5S330_SBU_EN BIT(4) /* FUNC_SET_3 */ -#define SN5S330_PP1_EN (1 << 0) -#define SN5S330_PP2_EN (1 << 1) -#define SN5S330_VBUS_DISCH_EN (1 << 2) -#define SN5S330_SET_RCP_MODE_PP1 (1 << 5) -#define SN5S330_SET_RCP_MODE_PP2 (1 << 6) +#define SN5S330_PP1_EN BIT(0) +#define SN5S330_PP2_EN BIT(1) +#define SN5S330_VBUS_DISCH_EN BIT(2) +#define SN5S330_SET_RCP_MODE_PP1 BIT(5) +#define SN5S330_SET_RCP_MODE_PP2 BIT(6) /* FUNC_SET_4 */ -#define SN5S330_VCONN_EN (1 << 0) -#define SN5S330_CC_POLARITY (1 << 1) -#define SN5S330_CC_EN (1 << 4) -#define SN5S330_VCONN_ILIM_SEL (1 << 5) +#define SN5S330_VCONN_EN BIT(0) +#define SN5S330_CC_POLARITY BIT(1) +#define SN5S330_CC_EN BIT(4) +#define SN5S330_VCONN_ILIM_SEL BIT(5) /* FUNC_SET_8 */ #define SN5S330_VCONN_DEGLITCH_MASK (3 << 6) #define SN5S330_VCONN_DEGLITCH_63_US (0 << 6) -#define SN5S330_VCONN_DEGLITCH_125_US (1 << 6) +#define SN5S330_VCONN_DEGLITCH_125_US BIT(6) #define SN5S330_VCONN_DEGLITCH_640_US (2 << 6) #define SN5S330_VCONN_DEGLITCH_1280_US (3 << 6) /* FUNC_SET_9 */ -#define SN5S330_FORCE_OVP_EN_SBU (1 << 1) -#define SN5S330_PP2_CONFIG (1 << 2) -#define SN5S330_OVP_EN_CC (1 << 4) -#define SN5S330_CONFIG_UVP (1 << 5) -#define SN5S330_FORCE_ON_VBUS_OVP (1 << 6) -#define SN5S330_FORCE_ON_VBUS_UVP (1 << 7) +#define SN5S330_FORCE_OVP_EN_SBU BIT(1) +#define SN5S330_PP2_CONFIG BIT(2) +#define SN5S330_OVP_EN_CC BIT(4) +#define SN5S330_CONFIG_UVP BIT(5) +#define SN5S330_FORCE_ON_VBUS_OVP BIT(6) +#define SN5S330_FORCE_ON_VBUS_UVP BIT(7) /* INT_STATUS_REG3 */ -#define SN5S330_VBUS_GOOD (1 << 0) +#define SN5S330_VBUS_GOOD BIT(0) /* INT_STATUS_REG4 */ -#define SN5S330_DIG_RES (1 << 0) -#define SN5S330_DB_BOOT (1 << 1) -#define SN5S330_VSAFE0V_STAT (1 << 2) -#define SN5S330_VSAFE0V_MASK (1 << 3) +#define SN5S330_DIG_RES BIT(0) +#define SN5S330_DB_BOOT BIT(1) +#define SN5S330_VSAFE0V_STAT BIT(2) +#define SN5S330_VSAFE0V_MASK BIT(3) /* * INT_MASK_RISE/FALL_EDGE_1 @@ -133,7 +133,7 @@ enum sn5s330_pp_idx { * occured; similarly for falling edge, it means the overcurrent condition is no * longer present. */ -#define SN5S330_ILIM_PP1_MASK (1 << 4) +#define SN5S330_ILIM_PP1_MASK BIT(4) /* * INT_MASK_RISE/FALL_EDGE2 @@ -150,7 +150,7 @@ enum sn5s330_pp_idx { * For rising edge registers, this indicates VBUS has risen above 4.0V. * For falling edge registers, this indicates VBUS has fallen below 4.0V. */ -#define SN5S330_VBUS_GOOD_MASK (1 << 0) +#define SN5S330_VBUS_GOOD_MASK BIT(0) extern const struct ppc_drv sn5s330_drv; diff --git a/driver/ppc/syv682x.c b/driver/ppc/syv682x.c index d7c050cbce..24a8b9a3ee 100644 --- a/driver/ppc/syv682x.c +++ b/driver/ppc/syv682x.c @@ -13,10 +13,10 @@ #include "usbc_ppc.h" #include "util.h" -#define SYV682X_FLAGS_SOURCE_ENABLED (1 << 0) +#define SYV682X_FLAGS_SOURCE_ENABLED BIT(0) /* 0 -> CC1, 1 -> CC2 */ -#define SYV682X_FLAGS_CC_POLARITY (1 << 1) -#define SYV682X_FLAGS_VBUS_PRESENT (1 << 2) +#define SYV682X_FLAGS_CC_POLARITY BIT(1) +#define SYV682X_FLAGS_VBUS_PRESENT BIT(2) static uint8_t flags[CONFIG_USB_PD_PORT_COUNT]; #define SYV682X_VBUS_DET_THRESH_MV 4000 diff --git a/driver/ppc/syv682x.h b/driver/ppc/syv682x.h index 5188a75b79..98bb67d522 100644 --- a/driver/ppc/syv682x.h +++ b/driver/ppc/syv682x.h @@ -22,13 +22,13 @@ #define SYV682X_CONTROL_4_REG 0x04 /* Status Register */ -#define SYV682X_STATUS_VSAFE_5V (1 << 1) -#define SYV682X_STATUS_VSAFE_0V (1 << 0) +#define SYV682X_STATUS_VSAFE_5V BIT(1) +#define SYV682X_STATUS_VSAFE_0V BIT(0) /* Control Register 1 */ -#define SYV682X_CONTROL_1_CH_SEL (1 << 1) -#define SYV682X_CONTROL_1_HV_DR (1 << 2) -#define SYV682X_CONTROL_1_PWR_ENB (1 << 7) +#define SYV682X_CONTROL_1_CH_SEL BIT(1) +#define SYV682X_CONTROL_1_HV_DR BIT(2) +#define SYV682X_CONTROL_1_PWR_ENB BIT(7) #define SYV682X_ILIM_MASK 0x18 #define SYV682X_ILIM_BIT_SHIFT 3 @@ -38,8 +38,8 @@ #define SYV682X_ILIM_3_30 3 /* Control Register 2 */ -#define SYV682X_CONTROL_2_SDSG (1 << 1) -#define SYV682X_CONTROL_2_FDSG (1 << 0) +#define SYV682X_CONTROL_2_SDSG BIT(1) +#define SYV682X_CONTROL_2_FDSG BIT(0) /* Control Register 3 */ #define SYV682X_OVP_MASK 0x70 @@ -54,13 +54,13 @@ #define SYV682X_OVP_23_7 7 /* Control Register 4 */ -#define SYV682X_CONTROL_4_CC1_BPS (1 << 7) -#define SYV682X_CONTROL_4_CC2_BPS (1 << 6) -#define SYV682X_CONTROL_4_VCONN1 (1 << 5) -#define SYV682X_CONTROL_4_VCONN2 (1 << 4) -#define SYV682X_CONTROL_4_VBAT_OVP (1 << 3) -#define SYV682X_CONTROL_4_VCONN_OCP (1 << 2) -#define SYV682X_CONTROL_4_CC_FRS (1 << 1) +#define SYV682X_CONTROL_4_CC1_BPS BIT(7) +#define SYV682X_CONTROL_4_CC2_BPS BIT(6) +#define SYV682X_CONTROL_4_VCONN1 BIT(5) +#define SYV682X_CONTROL_4_VCONN2 BIT(4) +#define SYV682X_CONTROL_4_VBAT_OVP BIT(3) +#define SYV682X_CONTROL_4_VCONN_OCP BIT(2) +#define SYV682X_CONTROL_4_CC_FRS BIT(1) struct ppc_drv; extern const struct ppc_drv syv682x_drv; diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c index 3eac7732af..5b49cd685e 100644 --- a/driver/tcpm/anx7447.c +++ b/driver/tcpm/anx7447.c @@ -18,15 +18,15 @@ #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) #define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) -#define ANX7447_VENDOR_ALERT (1 << 15) +#define ANX7447_VENDOR_ALERT BIT(15) #define ANX7447_REG_STATUS 0x82 -#define ANX7447_REG_STATUS_LINK (1 << 0) +#define ANX7447_REG_STATUS_LINK BIT(0) #define ANX7447_REG_HPD 0x83 -#define ANX7447_REG_HPD_HIGH (1 << 0) -#define ANX7447_REG_HPD_IRQ (1 << 1) -#define ANX7447_REG_HPD_ENABLE (1 << 2) +#define ANX7447_REG_HPD_HIGH BIT(0) +#define ANX7447_REG_HPD_IRQ BIT(1) +#define ANX7447_REG_HPD_ENABLE BIT(2) #define vsafe5v_min (3800/25) #define vsafe0v_max (800/25) diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h index deaebf3f1d..18708d38b4 100644 --- a/driver/tcpm/anx74xx.h +++ b/driver/tcpm/anx74xx.h @@ -30,16 +30,16 @@ #define ANX74XX_REG_INTP_VCONN_CTRL 0x33 #define ANX74XX_REG_VCONN_DISABLE 0x0f -#define ANX74XX_REG_VCONN_1_ENABLE (1 << 4) -#define ANX74XX_REG_VCONN_2_ENABLE (1 << 5) -#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN (1 << 2) +#define ANX74XX_REG_VCONN_1_ENABLE BIT(4) +#define ANX74XX_REG_VCONN_2_ENABLE BIT(5) +#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN BIT(2) #define ANX74XX_STANDBY_MODE (0) #define ANX74XX_NORMAL_MODE (1) #define ANX74XX_REG_TX_CTRL_1 0x81 -#define ANX74XX_REG_TX_HARD_RESET_REQ (1 << 1) -#define ANX74XX_REG_TX_CABLE_RESET_REQ (1 << 2) +#define ANX74XX_REG_TX_HARD_RESET_REQ BIT(1) +#define ANX74XX_REG_TX_CABLE_RESET_REQ BIT(2) #define ANX74XX_REG_TX_CTRL_2 0x82 #define ANX74XX_REG_TX_WR_FIFO 0x83 @@ -50,36 +50,36 @@ #define ANX74XX_REG_TX_START_ADDR_1 0xd0 #define ANX74XX_REG_CTRL_COMMAND 0xdb -#define ANX74XX_REG_TX_SEND_DATA_REQ (1 << 0) -#define ANX74XX_REG_TX_HARD_RST_REQ (1 << 1) +#define ANX74XX_REG_TX_SEND_DATA_REQ BIT(0) +#define ANX74XX_REG_TX_HARD_RST_REQ BIT(1) #define ANX74XX_REG_TX_BIST_CTRL 0x9D -#define ANX74XX_REG_TX_BIST_MODE (1 << 4) -#define ANX74XX_REG_TX_BIST_STOP (1 << 3) -#define ANX74XX_REG_TX_BIXT_FOREVER (1 << 2) -#define ANX74XX_REG_TX_BIST_ENABLE (1 << 1) -#define ANX74XX_REG_TX_BIST_START (1 << 0) +#define ANX74XX_REG_TX_BIST_MODE BIT(4) +#define ANX74XX_REG_TX_BIST_STOP BIT(3) +#define ANX74XX_REG_TX_BIXT_FOREVER BIT(2) +#define ANX74XX_REG_TX_BIST_ENABLE BIT(1) +#define ANX74XX_REG_TX_BIST_START BIT(0) #define ANX74XX_REG_PD_HEADER 0x69 #define ANX74XX_REG_PD_RX_DATA_OBJ 0x11 #define ANX74XX_REG_PD_RX_DATA_OBJ_M 0x4d #define ANX74XX_REG_ANALOG_STATUS 0x40 -#define ANX74XX_REG_VBUS_STATUS (1 << 4) +#define ANX74XX_REG_VBUS_STATUS BIT(4) #define ANX74XX_REG_CC_PULL_RD 0xfd #define ANX74XX_REG_CC_PULL_RP 0x02 #define ANX74XX_REG_TX_AUTO_GOODCRC_2 0x94 -#define ANX74XX_REG_REPLY_SOP_EN (1 << 3) -#define ANX74XX_REG_REPLY_SOP_1_EN (1 << 4) -#define ANX74XX_REG_REPLY_SOP_2_EN (1 << 5) +#define ANX74XX_REG_REPLY_SOP_EN BIT(3) +#define ANX74XX_REG_REPLY_SOP_1_EN BIT(4) +#define ANX74XX_REG_REPLY_SOP_2_EN BIT(5) #define ANX74XX_REG_TX_AUTO_GOODCRC_1 0x9c #define ANX74XX_REG_SPEC_REV_BIT_POS (3) #define ANX74XX_REG_DATA_ROLE_BIT_POS (2) #define ANX74XX_REG_PWR_ROLE_BIT_POS (1) -#define ANX74XX_REG_AUTO_GOODCRC_EN (1 << 0) +#define ANX74XX_REG_AUTO_GOODCRC_EN BIT(0) #define ANX74XX_REG_AUTO_GOODCRC_SET(drole, prole) \ ((PD_REV20 << ANX74XX_REG_SPEC_REV_BIT_POS) | \ ((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS) | \ @@ -88,7 +88,7 @@ #define ANX74XX_REG_ANALOG_CTRL_0 0x41 -#define ANX74XX_REG_R_PIN_CABLE_DET (1 << 7) +#define ANX74XX_REG_R_PIN_CABLE_DET BIT(7) #define ANX74XX_REG_ANALOG_CTRL_1 0x42 #define ANX74XX_REG_ANALOG_CTRL_5 0x46 @@ -106,19 +106,19 @@ #define ANX74XX_REG_ANALOG_CTRL_11 0x4c #define ANX74XX_REG_ANALOG_CTRL_12 0x4d -#define ANX74XX_REG_MUX_ML0_RX2 (1 << 0) -#define ANX74XX_REG_MUX_ML0_RX1 (1 << 1) -#define ANX74XX_REG_MUX_ML3_RX2 (1 << 2) -#define ANX74XX_REG_MUX_ML3_RX1 (1 << 3) -#define ANX74XX_REG_MUX_SSRX_RX2 (1 << 4) -#define ANX74XX_REG_MUX_SSRX_RX1 (1 << 5) -#define ANX74XX_REG_MUX_ML1_TX2 (1 << 6) -#define ANX74XX_REG_MUX_ML1_TX1 (1 << 7) +#define ANX74XX_REG_MUX_ML0_RX2 BIT(0) +#define ANX74XX_REG_MUX_ML0_RX1 BIT(1) +#define ANX74XX_REG_MUX_ML3_RX2 BIT(2) +#define ANX74XX_REG_MUX_ML3_RX1 BIT(3) +#define ANX74XX_REG_MUX_SSRX_RX2 BIT(4) +#define ANX74XX_REG_MUX_SSRX_RX1 BIT(5) +#define ANX74XX_REG_MUX_ML1_TX2 BIT(6) +#define ANX74XX_REG_MUX_ML1_TX1 BIT(7) -#define ANX74XX_REG_MUX_ML2_TX2 (1 << 4) -#define ANX74XX_REG_MUX_ML2_TX1 (1 << 5) -#define ANX74XX_REG_MUX_SSTX_TX2 (1 << 6) -#define ANX74XX_REG_MUX_SSTX_TX1 (1 << 7) +#define ANX74XX_REG_MUX_ML2_TX2 BIT(4) +#define ANX74XX_REG_MUX_ML2_TX1 BIT(5) +#define ANX74XX_REG_MUX_SSTX_TX2 BIT(6) +#define ANX74XX_REG_MUX_SSTX_TX1 BIT(7) #define ANX74XX_REG_CC_SOFTWARE_CTRL 0x4a #define ANX74XX_REG_CC_SW_CTRL_ENABLE 0x01 @@ -133,29 +133,29 @@ #define ANX74XX_REG_IRQ_EXT_MASK_1 0x3b #define ANX74XX_REG_IRQ_EXT_MASK_2 0x3c #define ANX74XX_REG_IRQ_EXT_SOURCE_1 0x3e -#define ANX74XX_REG_EXT_SOP (1 << 6) -#define ANX74XX_REG_EXT_SOP_PRIME (1 << 7) +#define ANX74XX_REG_EXT_SOP BIT(6) +#define ANX74XX_REG_EXT_SOP_PRIME BIT(7) #define ANX74XX_REG_IRQ_EXT_SOURCE_2 0x4e -#define ANX74XX_REG_EXT_SOP_PRIME_PRIME (1 << 0) -#define ANX74XX_REG_EXT_HARD_RST (1 << 2) +#define ANX74XX_REG_EXT_SOP_PRIME_PRIME BIT(0) +#define ANX74XX_REG_EXT_HARD_RST BIT(2) #define ANX74XX_REG_IRQ_EXT_SOURCE_3 0x4f -#define ANX74XX_REG_CLEAR_SOFT_IRQ (1 << 2) +#define ANX74XX_REG_CLEAR_SOFT_IRQ BIT(2) #define ANX74XX_REG_IRQ_SOURCE_RECV_MSG 0x6b -#define ANX74XX_REG_IRQ_CC_MSG_INT (1 << 0) -#define ANX74XX_REG_IRQ_CC_STATUS_INT (1 << 1) -#define ANX74XX_REG_IRQ_GOOD_CRC_INT (1 << 2) -#define ANX74XX_REG_IRQ_TX_FAIL_INT (1 << 3) +#define ANX74XX_REG_IRQ_CC_MSG_INT BIT(0) +#define ANX74XX_REG_IRQ_CC_STATUS_INT BIT(1) +#define ANX74XX_REG_IRQ_GOOD_CRC_INT BIT(2) +#define ANX74XX_REG_IRQ_TX_FAIL_INT BIT(3) #define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK 0x6c #define ANX74XX_REG_CLEAR_SET_BITS 0xff -#define ANX74XX_REG_ALERT_HARD_RST_RECV (1 << 6) -#define ANX74XX_REG_ALERT_MSG_RECV (1 << 5) -#define ANX74XX_REG_ALERT_TX_MSG_ERROR (1 << 4) -#define ANX74XX_REG_ALERT_TX_ACK_RECV (1 << 3) -#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK (1 << 2) -#define ANX74XX_REG_ALERT_TX_HARD_RESETOK (1 << 1) -#define ANX74XX_REG_ALERT_CC_CHANGE (1 << 0) +#define ANX74XX_REG_ALERT_HARD_RST_RECV BIT(6) +#define ANX74XX_REG_ALERT_MSG_RECV BIT(5) +#define ANX74XX_REG_ALERT_TX_MSG_ERROR BIT(4) +#define ANX74XX_REG_ALERT_TX_ACK_RECV BIT(3) +#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK BIT(2) +#define ANX74XX_REG_ALERT_TX_HARD_RESETOK BIT(1) +#define ANX74XX_REG_ALERT_CC_CHANGE BIT(0) #define ANX74XX_REG_ANALOG_CTRL_2 0x43 #define ANX74XX_REG_MODE_TRANS 0x01 @@ -181,12 +181,12 @@ #define ANX74XX_REG_CTRL_FW 0x2E #define CLEAR_RX_BUFFER (1) #define ANX74XX_REG_POWER_DOWN_CTRL 0x0d -#define ANX74XX_REG_STATUS_CC1_VRD_USB (1 << 7) -#define ANX74XX_REG_STATUS_CC1_VRD_1P5 (1 << 6) -#define ANX74XX_REG_STATUS_CC1_VRD_3P0 (1 << 5) -#define ANX74XX_REG_STATUS_CC2_VRD_USB (1 << 4) -#define ANX74XX_REG_STATUS_CC2_VRD_1P5 (1 << 3) -#define ANX74XX_REG_STATUS_CC2_VRD_3P0 (1 << 2) +#define ANX74XX_REG_STATUS_CC1_VRD_USB BIT(7) +#define ANX74XX_REG_STATUS_CC1_VRD_1P5 BIT(6) +#define ANX74XX_REG_STATUS_CC1_VRD_3P0 BIT(5) +#define ANX74XX_REG_STATUS_CC2_VRD_USB BIT(4) +#define ANX74XX_REG_STATUS_CC2_VRD_1P5 BIT(3) +#define ANX74XX_REG_STATUS_CC2_VRD_3P0 BIT(2) /* defined in the inter-bock Spec: 4.2.10 CC Detect Status */ #define ANX74XX_REG_CC_STATUS_MASK 0xf diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c index c9d6045b44..bac65892de 100644 --- a/driver/tcpm/anx7688.c +++ b/driver/tcpm/anx7688.c @@ -11,19 +11,19 @@ #include "timer.h" #include "usb_mux.h" -#define ANX7688_VENDOR_ALERT (1 << 15) +#define ANX7688_VENDOR_ALERT BIT(15) #define ANX7688_REG_STATUS 0x82 -#define ANX7688_REG_STATUS_LINK (1 << 0) +#define ANX7688_REG_STATUS_LINK BIT(0) #define ANX7688_REG_HPD 0x83 -#define ANX7688_REG_HPD_HIGH (1 << 0) -#define ANX7688_REG_HPD_IRQ (1 << 1) -#define ANX7688_REG_HPD_ENABLE (1 << 2) +#define ANX7688_REG_HPD_HIGH BIT(0) +#define ANX7688_REG_HPD_IRQ BIT(1) +#define ANX7688_REG_HPD_ENABLE BIT(2) #define ANX7688_USBC_ADDR 0x50 #define ANX7688_REG_RAMCTRL 0xe7 -#define ANX7688_REG_RAMCTRL_BOOT_DONE (1 << 6) +#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6) static int anx7688_init(int port) { diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c index f63e9e38bb..b31a9192f7 100644 --- a/driver/tcpm/it83xx.c +++ b/driver/tcpm/it83xx.c @@ -45,7 +45,7 @@ void it83xx_disable_pd_module(int port) if (*usbpd_ctrl_regs[port].cc1 == IT83XX_USBPD_CC_PIN_CONFIG && *usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) { /* Disable PD PHY */ - IT83XX_USBPD_GCR(port) &= ~((1 << 0) | (1 << 4)); + IT83XX_USBPD_GCR(port) &= ~(BIT(0) | BIT(4)); /* Power down CC1/CC2 */ IT83XX_USBPD_CCGCR(port) |= 0x1f; /* Disable CC1/CC2 voltage detector */ @@ -70,10 +70,10 @@ static enum tcpc_cc_voltage_status it83xx_get_cc( /* select Rp */ if (pull) - CLEAR_MASK(cc_state, (1 << 2)); + CLEAR_MASK(cc_state, BIT(2)); /* select Rd */ else - SET_MASK(cc_state, (1 << 2)); + SET_MASK(cc_state, BIT(2)); /* sink */ if (USBPD_GET_POWER_ROLE(port) == USBPD_POWER_ROLE_CONSUMER) { @@ -181,7 +181,7 @@ static enum tcpc_transmit_complete it83xx_tx_data( if (length) { /* set data bit */ - IT83XX_USBPD_MTSR0(port) |= (1 << 4); + IT83XX_USBPD_MTSR0(port) |= BIT(4); /* set data length setting */ IT83XX_USBPD_MTSR1(port) |= length; /* set data */ @@ -279,9 +279,9 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled) static void it83xx_enable_cc(enum usbpd_port port, int enable) { if (enable) - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 4)); + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(4)); else - SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 4)); + SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(4)); } static void it83xx_set_power_role(enum usbpd_port port, int power_role) @@ -300,11 +300,11 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role) */ IT83XX_USBPD_CCADCR(port) = 0x08; /* bit0: source */ - SET_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0)); + SET_MASK(IT83XX_USBPD_PDMSR(port), BIT(0)); /* bit1: CC1 select Rp */ - SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 1)); + SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(1)); /* bit3: CC2 select Rp */ - SET_MASK(IT83XX_USBPD_BMCSR(port), (1 << 3)); + SET_MASK(IT83XX_USBPD_BMCSR(port), BIT(3)); } else { /* * bit[2,3] BMC Rx threshold setting @@ -318,11 +318,11 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role) */ IT83XX_USBPD_CCADCR(port) = 0x04; /* bit0: sink */ - CLEAR_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0)); + CLEAR_MASK(IT83XX_USBPD_PDMSR(port), BIT(0)); /* bit1: CC1 select Rd */ - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 1)); + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(1)); /* bit3: CC2 select Rd */ - CLEAR_MASK(IT83XX_USBPD_BMCSR(port), (1 << 3)); + CLEAR_MASK(IT83XX_USBPD_BMCSR(port), BIT(3)); } } @@ -339,10 +339,10 @@ static void it83xx_init(enum usbpd_port port, int role) invalidate_last_message_id(port); #ifdef IT83XX_USBPD_CC_PARAMETER_RELOAD /* bit7: Reload CC parameter setting. */ - IT83XX_USBPD_CCPSR0(port) |= (1 << 7); + IT83XX_USBPD_CCPSR0(port) |= BIT(7); #endif /* reset and disable HW auto generate message header */ - IT83XX_USBPD_GCR(port) = (1 << 5); + IT83XX_USBPD_GCR(port) = BIT(5); USBPD_SW_RESET(port); /* set SOP: receive SOP message only. * bit[7]: SOP" support enable. @@ -379,7 +379,7 @@ static void it83xx_init(enum usbpd_port port, int role) /* disable vconn */ it83xx_enable_vconn(port, 0); /* TX start from high */ - IT83XX_USBPD_CCADCR(port) |= (1 << 6); + IT83XX_USBPD_CCADCR(port) |= BIT(6); /* enable cc1/cc2 */ *usbpd_ctrl_regs[port].cc1 = IT83XX_USBPD_CC_PIN_CONFIG; *usbpd_ctrl_regs[port].cc2 = IT83XX_USBPD_CC_PIN_CONFIG; @@ -393,9 +393,9 @@ static void it83xx_select_polarity(enum usbpd_port port, { /* cc1/cc2 selection */ if (cc_pin == USBPD_CC_PIN_1) - SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 0)); + SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(0)); else - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 0)); + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(0)); } static int it83xx_set_cc(enum usbpd_port port, int pull) @@ -457,7 +457,7 @@ static int it83xx_tcpm_select_rp_value(int port, int rp_sel) rp = 2 << 2; break; case TYPEC_RP_3A0: - rp = 1 << 2; + rp = BIT(2); break; case TYPEC_RP_USB: default: diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h index 0f6be9b24f..73c613ff0e 100644 --- a/driver/tcpm/it83xx_pd.h +++ b/driver/tcpm/it83xx_pd.h @@ -14,7 +14,7 @@ */ #define IT83XX_USBPD_CC_PIN_CONFIG 0x86 -#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM((1 << 17)) +#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM(BIT(17)) #define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) #define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) @@ -51,9 +51,9 @@ #define USBPD_GET_POWER_ROLE(port) \ (IT83XX_USBPD_PDMSR(port) & 1) #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \ - (IT83XX_USBPD_CCGCR(port) & (1 << 1)) + (IT83XX_USBPD_CCGCR(port) & BIT(1)) #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \ - (IT83XX_USBPD_BMCSR(port) & (1 << 3)) + (IT83XX_USBPD_BMCSR(port) & BIT(3)) #define USBPD_GET_PULL_CC_SELECTION(port) \ (IT83XX_USBPD_CCGCR(port) & 1) diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h index 5fdcffbdca..1d30d27f8f 100644 --- a/driver/tcpm/mt6370.h +++ b/driver/tcpm/mt6370.h @@ -63,45 +63,45 @@ * MT6370_REG_CLK_CTRL2 0x87 */ -#define MT6370_REG_CLK_DIV_600K_EN (1 << 7) -#define MT6370_REG_CLK_BCLK2_EN (1 << 6) -#define MT6370_REG_CLK_BCLK2_TG_EN (1 << 5) -#define MT6370_REG_CLK_DIV_300K_EN (1 << 3) -#define MT6370_REG_CLK_CK_300K_EN (1 << 2) -#define MT6370_REG_CLK_BCLK_EN (1 << 1) -#define MT6370_REG_CLK_BCLK_TH_EN (1 << 0) +#define MT6370_REG_CLK_DIV_600K_EN BIT(7) +#define MT6370_REG_CLK_BCLK2_EN BIT(6) +#define MT6370_REG_CLK_BCLK2_TG_EN BIT(5) +#define MT6370_REG_CLK_DIV_300K_EN BIT(3) +#define MT6370_REG_CLK_CK_300K_EN BIT(2) +#define MT6370_REG_CLK_BCLK_EN BIT(1) +#define MT6370_REG_CLK_BCLK_TH_EN BIT(0) /* * MT6370_REG_CLK_CTRL3 0x88 */ -#define MT6370_REG_CLK_OSCMUX_RG_EN (1 << 7) -#define MT6370_REG_CLK_CK_24M_EN (1 << 6) -#define MT6370_REG_CLK_OSC_RG_EN (1 << 5) -#define MT6370_REG_CLK_DIV_2P4M_EN (1 << 4) -#define MT6370_REG_CLK_CK_2P4M_EN (1 << 3) -#define MT6370_REG_CLK_PCLK_EN (1 << 2) -#define MT6370_REG_CLK_PCLK_RG_EN (1 << 1) -#define MT6370_REG_CLK_PCLK_TG_EN (1 << 0) +#define MT6370_REG_CLK_OSCMUX_RG_EN BIT(7) +#define MT6370_REG_CLK_CK_24M_EN BIT(6) +#define MT6370_REG_CLK_OSC_RG_EN BIT(5) +#define MT6370_REG_CLK_DIV_2P4M_EN BIT(4) +#define MT6370_REG_CLK_CK_2P4M_EN BIT(3) +#define MT6370_REG_CLK_PCLK_EN BIT(2) +#define MT6370_REG_CLK_PCLK_RG_EN BIT(1) +#define MT6370_REG_CLK_PCLK_TG_EN BIT(0) /* * MT6370_REG_RX_TX_DBG 0x8b */ -#define MT6370_REG_RX_TX_DBG_RX_BUSY (1 << 7) -#define MT6370_REG_RX_TX_DBG_TX_BUSY (1 << 6) +#define MT6370_REG_RX_TX_DBG_RX_BUSY BIT(7) +#define MT6370_REG_RX_TX_DBG_TX_BUSY BIT(6) /* * MT6370_REG_BMC_CTRL 0x90 */ -#define MT6370_REG_IDLE_EN (1 << 6) -#define MT6370_REG_DISCHARGE_EN (1 << 5) -#define MT6370_REG_BMCIO_LPRPRD (1 << 4) -#define MT6370_REG_BMCIO_LPEN (1 << 3) -#define MT6370_REG_BMCIO_BG_EN (1 << 2) -#define MT6370_REG_VBUS_DET_EN (1 << 1) -#define MT6370_REG_BMCIO_OSC_EN (1 << 0) +#define MT6370_REG_IDLE_EN BIT(6) +#define MT6370_REG_DISCHARGE_EN BIT(5) +#define MT6370_REG_BMCIO_LPRPRD BIT(4) +#define MT6370_REG_BMCIO_LPEN BIT(3) +#define MT6370_REG_BMCIO_BG_EN BIT(2) +#define MT6370_REG_VBUS_DET_EN BIT(1) +#define MT6370_REG_BMCIO_OSC_EN BIT(0) #define MT6370_REG_BMC_CTRL_DEFAULT \ (MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN | \ MT6370_REG_BMCIO_OSC_EN) @@ -111,41 +111,41 @@ */ #define MT6370_MASK_DISCHARGE_LVL 0x03 -#define MT6370_REG_DISCHARGE_LVL (1 << 0) +#define MT6370_REG_DISCHARGE_LVL BIT(0) /* * MT6370_REG_RT_STATUS 0x97 */ -#define MT6370_REG_RA_DETACH (1 << 5) -#define MT6370_REG_VBUS_80 (1 << 1) +#define MT6370_REG_RA_DETACH BIT(5) +#define MT6370_REG_VBUS_80 BIT(1) /* * MT6370_REG_RT_INT 0x98 */ -#define MT6370_REG_INT_RA_DETACH (1 << 5) -#define MT6370_REG_INT_WATCHDOG (1 << 2) -#define MT6370_REG_INT_VBUS_80 (1 << 1) -#define MT6370_REG_INT_WAKEUP (1 << 0) +#define MT6370_REG_INT_RA_DETACH BIT(5) +#define MT6370_REG_INT_WATCHDOG BIT(2) +#define MT6370_REG_INT_VBUS_80 BIT(1) +#define MT6370_REG_INT_WAKEUP BIT(0) /* * MT6370_REG_RT_MASK 0x99 */ -#define MT6370_REG_M_RA_DETACH (1 << 5) -#define MT6370_REG_M_WATCHDOG (1 << 2) -#define MT6370_REG_M_VBUS_80 (1 << 1) -#define MT6370_REG_M_WAKEUP (1 << 0) +#define MT6370_REG_M_RA_DETACH BIT(5) +#define MT6370_REG_M_WATCHDOG BIT(2) +#define MT6370_REG_M_VBUS_80 BIT(1) +#define MT6370_REG_M_WAKEUP BIT(0) /* * MT6370_REG_IDLE_CTRL 0x9B */ -#define MT6370_REG_CK_300K_SEL (1 << 7) -#define MT6370_REG_SHIPPING_OFF (1 << 5) -#define MT6370_REG_ENEXTMSG (1 << 4) -#define MT6370_REG_AUTOIDLE_EN (1 << 3) +#define MT6370_REG_CK_300K_SEL BIT(7) +#define MT6370_REG_SHIPPING_OFF BIT(5) +#define MT6370_REG_ENEXTMSG BIT(4) +#define MT6370_REG_AUTOIDLE_EN BIT(3) /* timeout = (tout*2+1) * 6.4ms */ #ifdef CONFIG_USB_PD_REV30 @@ -161,7 +161,7 @@ * MT6370_REG_INTRST_CTRL 0x9C */ -#define MT6370_REG_INTRST_EN (1 << 7) +#define MT6370_REG_INTRST_EN BIT(7) /* timeout = (tout+1) * 0.2sec */ #define MT6370_REG_INTRST_SET(en, tout) ((en << 7) | (tout & 0x03)) @@ -170,7 +170,7 @@ * MT6370_REG_WATCHDOG_CTRL 0x9D */ -#define MT6370_REG_WATCHDOG_EN (1 << 7) +#define MT6370_REG_WATCHDOG_EN BIT(7) /* timeout = (tout+1) * 0.4sec */ #define MT6370_REG_WATCHDOG_CTRL_SET(en, tout) ((en << 7) | (tout & 0x07)) @@ -179,7 +179,7 @@ * MT6370_REG_I2CRST_CTRL 0x9E */ -#define MT6370_REG_I2CRST_EN (1 << 7) +#define MT6370_REG_I2CRST_EN BIT(7) /* timeout = (tout+1) * 12.5ms */ #define MT6370_REG_I2CRST_SET(en, tout) ((en << 7) | (tout & 0x0f)) diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index 6d0faab56f..6b94b56094 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -43,8 +43,8 @@ #define PS8XXX_REG_VENDOR_ID_L 0x00 #define PS8XXX_REG_VENDOR_ID_H 0x01 #define MUX_IN_HPD_ASSERTION_REG 0xD0 -#define IN_HPD (1 << 0) -#define HPD_IRQ (1 << 1) +#define IN_HPD BIT(0) +#define HPD_IRQ BIT(1) #define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3 #define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7 #define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8 @@ -55,8 +55,8 @@ #define FW_VER_REG 0x82 #define MUX_IN_HPD_ASSERTION_REG 0xD0 -#define IN_HPD (1 << 0) -#define HPD_IRQ (1 << 1) +#define IN_HPD BIT(0) +#define HPD_IRQ BIT(1) #endif diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c index f20fbd91e3..59393a62a9 100644 --- a/driver/tcpm/tcpci.c +++ b/driver/tcpm/tcpci.c @@ -420,7 +420,7 @@ struct cached_tcpm_message { }; /* Cache depth needs to be power of 2 */ -#define CACHE_DEPTH (1 << 2) +#define CACHE_DEPTH BIT(2) #define CACHE_DEPTH_MASK (CACHE_DEPTH - 1) struct queue { diff --git a/driver/tcpm/tcpci.h b/driver/tcpm/tcpci.h index 8084e92232..600e28f284 100644 --- a/driver/tcpm/tcpci.h +++ b/driver/tcpm/tcpci.h @@ -43,9 +43,9 @@ #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB (1 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED (1 << 0) +#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0) #define TCPC_REG_TCPC_CTRL 0x19 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity) @@ -62,7 +62,7 @@ #define TCPC_REG_FAULT_CTRL 0x1b #define TCPC_REG_POWER_CTRL 0x1c -#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE (1 << 2) +#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn) #define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1) diff --git a/driver/temp_sensor/adt7481.h b/driver/temp_sensor/adt7481.h index 11e9856b9c..45da88560e 100644 --- a/driver/temp_sensor/adt7481.h +++ b/driver/temp_sensor/adt7481.h @@ -55,18 +55,18 @@ #define ADT7481_MANUFACTURER_ID 0x3e /* Config1 register bits */ -#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK (1 << 0) -#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK (1 << 1) -#define ADT7481_CONFIG1_TEMP_RANGE (1 << 2) -#define ADT7481_CONFIG1_SEL_REMOTE2 (1 << 3) +#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK BIT(0) +#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK BIT(1) +#define ADT7481_CONFIG1_TEMP_RANGE BIT(2) +#define ADT7481_CONFIG1_SEL_REMOTE2 BIT(3) /* ADT7481_CONFIG1_MODE bit is use to enable THERM mode */ -#define ADT7481_CONFIG1_MODE (1 << 5) -#define ADT7481_CONFIG1_RUN_L (1 << 6) +#define ADT7481_CONFIG1_MODE BIT(5) +#define ADT7481_CONFIG1_RUN_L BIT(6) /* mask all alerts on ALERT# pin */ -#define ADT7481_CONFIG1_ALERT_MASK_L (1 << 7) +#define ADT7481_CONFIG1_ALERT_MASK_L BIT(7) /* Config2 register bits */ -#define ADT7481_CONFIG2_LOCK (1 << 7) +#define ADT7481_CONFIG2_LOCK BIT(7) /* Conversion Rate/Channel Select Register */ #define ADT7481_CONV_RATE_MASK (0x0f) @@ -85,28 +85,28 @@ #define ADT7481_CONV_RATE_73MS_AVE (0x0b) #define ADT7481_CONV_CHAN_SELECT_MASK (0x30) #define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN (0 << 4) -#define ADT7481_CONV_CHAN_SEL_LOCAL (1 << 4) +#define ADT7481_CONV_CHAN_SEL_LOCAL BIT(4) #define ADT7481_CONV_CHAN_SEL_REMOTE1 (2 << 4) #define ADT7481_CONV_CHAN_SEL_REMOTE2 (3 << 4) -#define ADT7481_CONV_AVERAGING_L (1 << 7) +#define ADT7481_CONV_AVERAGING_L BIT(7) /* Status1 register bits */ -#define ADT7481_STATUS1_LOCAL_THERM_ALARM (1 << 0) -#define ADT7481_STATUS1_REMOTE1_THERM_ALARM (1 << 1) -#define ADT7481_STATUS1_REMOTE1_OPEN (1 << 2) -#define ADT7481_STATUS1_REMOTE1_LOW_ALARM (1 << 3) -#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM (1 << 4) -#define ADT7481_STATUS1_LOCAL_LOW_ALARM (1 << 5) -#define ADT7481_STATUS1_LOCAL_HIGH_ALARM (1 << 6) -#define ADT7481_STATUS1_BUSY (1 << 7) +#define ADT7481_STATUS1_LOCAL_THERM_ALARM BIT(0) +#define ADT7481_STATUS1_REMOTE1_THERM_ALARM BIT(1) +#define ADT7481_STATUS1_REMOTE1_OPEN BIT(2) +#define ADT7481_STATUS1_REMOTE1_LOW_ALARM BIT(3) +#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM BIT(4) +#define ADT7481_STATUS1_LOCAL_LOW_ALARM BIT(5) +#define ADT7481_STATUS1_LOCAL_HIGH_ALARM BIT(6) +#define ADT7481_STATUS1_BUSY BIT(7) /* Status2 register bits */ -#define ADT7481_STATUS2_ALERT (1 << 0) -#define ADT7481_STATUS2_REMOTE2_THERM_ALARM (1 << 1) -#define ADT7481_STATUS2_REMOTE2_OPEN (1 << 2) -#define ADT7481_STATUS2_REMOTE2_LOW_ALARM (1 << 3) -#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM (1 << 4) +#define ADT7481_STATUS2_ALERT BIT(0) +#define ADT7481_STATUS2_REMOTE2_THERM_ALARM BIT(1) +#define ADT7481_STATUS2_REMOTE2_OPEN BIT(2) +#define ADT7481_STATUS2_REMOTE2_LOW_ALARM BIT(3) +#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM BIT(4) /* Consecutive Alert register */ #define ADT7481_CONSEC_MASK (0xf) @@ -114,9 +114,9 @@ #define ADT7481_CONSEC_2 (0x2) #define ADT7481_CONSEC_3 (0x6) #define ADT7481_CONSEC_4 (0xe) -#define ADT7481_CONSEC_EN_SCL_TIMEOUT (1 << 5) -#define ADT7481_CONSEC_EN_SDA_TIMEOUT (1 << 6) -#define ADT7481_CONSEC_MASK_LOCAL_ALERT (1 << 7) +#define ADT7481_CONSEC_EN_SCL_TIMEOUT BIT(5) +#define ADT7481_CONSEC_EN_SDA_TIMEOUT BIT(6) +#define ADT7481_CONSEC_MASK_LOCAL_ALERT BIT(7) /* Limits */ diff --git a/driver/temp_sensor/bd99992gw.h b/driver/temp_sensor/bd99992gw.h index 27a9943de1..7db3990e07 100644 --- a/driver/temp_sensor/bd99992gw.h +++ b/driver/temp_sensor/bd99992gw.h @@ -26,26 +26,26 @@ enum bd99992gw_adc_channel { /* Registers */ #define BD99992GW_REG_IRQLVL1 0x02 -#define BD99992GW_IRQLVL1_ADC (1 << 1) /* ADC IRQ asserted */ +#define BD99992GW_IRQLVL1_ADC BIT(1) /* ADC IRQ asserted */ #define BD99992GW_REG_ADC1INT 0x03 -#define BD99992GW_ADC1INT_RND (1 << 0) /* RR cycle completed */ +#define BD99992GW_ADC1INT_RND BIT(0) /* RR cycle completed */ #define BD99992GW_REG_MADC1INT 0x0a -#define BD99992GW_MADC1INT_RND (1 << 0) /* RR cycle mask */ +#define BD99992GW_MADC1INT_RND BIT(0) /* RR cycle mask */ #define BD99992GW_REG_IRQLVL1MSK 0x13 -#define BD99992GW_IRQLVL1MSK_MADC (1 << 1) /* ADC IRQ mask */ +#define BD99992GW_IRQLVL1MSK_MADC BIT(1) /* ADC IRQ mask */ #define BD99992GW_REG_ADC1CNTL1 0x80 #define BD99992GW_ADC1CNTL1_SLP27MS (0x6 << 3) /* 27ms between pass */ #define BD99992GW_ADC1CNTL1_NOLOOP (0x7 << 3) /* Single loop pass only */ -#define BD99992GW_ADC1CNTL1_ADPAUSE (1 << 2) /* ADC pause */ -#define BD99992GW_ADC1CNTL1_ADSTRT (1 << 1) /* ADC start */ -#define BD99992GW_ADC1CNTL1_ADEN (1 << 0) /* ADC enable */ +#define BD99992GW_ADC1CNTL1_ADPAUSE BIT(2) /* ADC pause */ +#define BD99992GW_ADC1CNTL1_ADSTRT BIT(1) /* ADC start */ +#define BD99992GW_ADC1CNTL1_ADEN BIT(0) /* ADC enable */ #define BD99992GW_REG_ADC1CNTL2 0x81 -#define BD99992GW_ADC1CNTL2_ADCTHERM (1 << 0) /* Enable ADC sequencing */ +#define BD99992GW_ADC1CNTL2_ADCTHERM BIT(0) /* Enable ADC sequencing */ /* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */ #define BD99992GW_ADC_POINTER_REG_COUNT 8 @@ -57,7 +57,7 @@ enum bd99992gw_adc_channel { #define BD99992GW_REG_ADC1ADDR5 0x87 #define BD99992GW_REG_ADC1ADDR6 0x88 #define BD99992GW_REG_ADC1ADDR7 0x89 -#define BD99992GW_ADC1ADDR_STOP (1 << 3) /* Last conversion channel */ +#define BD99992GW_ADC1ADDR_STOP BIT(3) /* Last conversion channel */ /* Result registers */ #define BD99992GW_REG_ADC1DATA0L 0x95 diff --git a/driver/temp_sensor/g78x.h b/driver/temp_sensor/g78x.h index 8fa78ffa83..2ef75f1da9 100644 --- a/driver/temp_sensor/g78x.h +++ b/driver/temp_sensor/g78x.h @@ -49,18 +49,18 @@ #define G78X_DEVICE_ID 0xFF /* Config register bits */ -#define G78X_CONFIGURATION_STANDBY (1 << 6) -#define G78X_CONFIGURATION_ALERT_MASK (1 << 7) +#define G78X_CONFIGURATION_STANDBY BIT(6) +#define G78X_CONFIGURATION_ALERT_MASK BIT(7) /* Status register bits */ -#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM (1 << 0) -#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM (1 << 1) -#define G78X_STATUS_REMOTE1_TEMP_FAULT (1 << 2) -#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM (1 << 3) -#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM (1 << 4) -#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM (1 << 5) -#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM (1 << 6) -#define G78X_STATUS_BUSY (1 << 7) +#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(0) +#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(1) +#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(2) +#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(3) +#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(4) +#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) +#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) +#define G78X_STATUS_BUSY BIT(7) #elif defined(CONFIG_TEMP_SENSOR_G782) /* G782 register */ @@ -105,25 +105,25 @@ #define G78X_DEVICE_ID 0xFF /* Config register bits */ -#define G78X_CONFIGURATION_REMOTE2_DIS (1 << 5) -#define G78X_CONFIGURATION_STANDBY (1 << 6) -#define G78X_CONFIGURATION_ALERT_MASK (1 << 7) +#define G78X_CONFIGURATION_REMOTE2_DIS BIT(5) +#define G78X_CONFIGURATION_STANDBY BIT(6) +#define G78X_CONFIGURATION_ALERT_MASK BIT(7) /* Status register bits */ -#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM (1 << 0) -#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM (1 << 1) -#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM (1 << 2) -#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM (1 << 3) -#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM (1 << 4) -#define G78X_STATUS_REMOTE2_TEMP_FAULT (1 << 5) -#define G78X_STATUS_REMOTE1_TEMP_FAULT (1 << 6) -#define G78X_STATUS_BUSY (1 << 7) +#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(0) +#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(1) +#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(2) +#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM BIT(3) +#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(4) +#define G78X_STATUS_REMOTE2_TEMP_FAULT BIT(5) +#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(6) +#define G78X_STATUS_BUSY BIT(7) /* Status1 register bits */ -#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM (1 << 4) -#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM (1 << 5) -#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM (1 << 6) -#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM (1 << 7) +#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM BIT(4) +#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM BIT(5) +#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(6) +#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(7) #endif /** diff --git a/driver/temp_sensor/tmp006.c b/driver/temp_sensor/tmp006.c index 67b31dfa98..fd81647c41 100644 --- a/driver/temp_sensor/tmp006.c +++ b/driver/temp_sensor/tmp006.c @@ -30,10 +30,10 @@ #define ALGORITHM_PARAMS 12 /* Flags for tdata->fail */ -#define FAIL_INIT (1 << 0) /* Just initialized */ -#define FAIL_POWER (1 << 1) /* Sensor not powered */ -#define FAIL_I2C (1 << 2) /* I2C communication error */ -#define FAIL_NOT_READY (1 << 3) /* Data not ready */ +#define FAIL_INIT BIT(0) /* Just initialized */ +#define FAIL_POWER BIT(1) /* Sensor not powered */ +#define FAIL_I2C BIT(2) /* I2C communication error */ +#define FAIL_NOT_READY BIT(3) /* Data not ready */ /* State and conversion factors to track for each sensor */ struct tmp006_data_t { diff --git a/driver/temp_sensor/tmp112.c b/driver/temp_sensor/tmp112.c index f567e2433c..32ffc1ced6 100644 --- a/driver/temp_sensor/tmp112.c +++ b/driver/temp_sensor/tmp112.c @@ -74,7 +74,7 @@ static void tmp112_init(void) set_mask = (3 << 5); /* not oneshot mode */ - clr_mask = (1 << 7); + clr_mask = BIT(7); raw_read16(TMP112_REG_CONF, &tmp); raw_write16(TMP112_REG_CONF, (tmp & ~clr_mask) | set_mask); diff --git a/driver/temp_sensor/tmp411.h b/driver/temp_sensor/tmp411.h index a0ad95a5d8..52635e810f 100644 --- a/driver/temp_sensor/tmp411.h +++ b/driver/temp_sensor/tmp411.h @@ -67,20 +67,20 @@ #define TMP411d_DEVICE_ID_VAL 0x12 /* Config register bits */ -#define TMP411_CONFIG1_TEMP_RANGE (1 << 2) +#define TMP411_CONFIG1_TEMP_RANGE BIT(2) /* TMP411_CONFIG1_MODE bit is use to enable THERM mode */ -#define TMP411_CONFIG1_MODE (1 << 5) -#define TMP411_CONFIG1_RUN_L (1 << 6) -#define TMP411_CONFIG1_ALERT_MASK_L (1 << 7) +#define TMP411_CONFIG1_MODE BIT(5) +#define TMP411_CONFIG1_RUN_L BIT(6) +#define TMP411_CONFIG1_ALERT_MASK_L BIT(7) /* Status register bits */ -#define TMP411_STATUS_TEMP_THERM_ALARM (1 << 1) -#define TMP411_STATUS_OPEN (1 << 2) -#define TMP411_STATUS_TEMP_LOW_ALARM (1 << 3) -#define TMP411_STATUS_TEMP_HIGH_ALARM (1 << 4) -#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM (1 << 5) -#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM (1 << 6) -#define TMP411_STATUS_BUSY (1 << 7) +#define TMP411_STATUS_TEMP_THERM_ALARM BIT(1) +#define TMP411_STATUS_OPEN BIT(2) +#define TMP411_STATUS_TEMP_LOW_ALARM BIT(3) +#define TMP411_STATUS_TEMP_HIGH_ALARM BIT(4) +#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) +#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) +#define TMP411_STATUS_BUSY BIT(7) /* Limits */ #define TMP411_HYSTERESIS_HIGH_LIMIT 255 diff --git a/driver/temp_sensor/tmp432.h b/driver/temp_sensor/tmp432.h index 2d8d2515dc..f9bd03dd32 100644 --- a/driver/temp_sensor/tmp432.h +++ b/driver/temp_sensor/tmp432.h @@ -67,22 +67,22 @@ #define TMP432_MANUFACTURER_ID 0xfe /* Config register bits */ -#define TMP432_CONFIG1_TEMP_RANGE (1 << 2) +#define TMP432_CONFIG1_TEMP_RANGE BIT(2) /* TMP432_CONFIG1_MODE bit is use to enable THERM mode */ -#define TMP432_CONFIG1_MODE (1 << 5) -#define TMP432_CONFIG1_RUN_L (1 << 6) -#define TMP432_CONFIG1_ALERT_MASK_L (1 << 7) -#define TMP432_CONFIG2_RESISTANCE_CORRECTION (1 << 2) -#define TMP432_CONFIG2_LOCAL_ENABLE (1 << 3) -#define TMP432_CONFIG2_REMOTE1_ENABLE (1 << 4) -#define TMP432_CONFIG2_REMOTE2_ENABLE (1 << 5) +#define TMP432_CONFIG1_MODE BIT(5) +#define TMP432_CONFIG1_RUN_L BIT(6) +#define TMP432_CONFIG1_ALERT_MASK_L BIT(7) +#define TMP432_CONFIG2_RESISTANCE_CORRECTION BIT(2) +#define TMP432_CONFIG2_LOCAL_ENABLE BIT(3) +#define TMP432_CONFIG2_REMOTE1_ENABLE BIT(4) +#define TMP432_CONFIG2_REMOTE2_ENABLE BIT(5) /* Status register bits */ -#define TMP432_STATUS_TEMP_THERM_ALARM (1 << 1) -#define TMP432_STATUS_OPEN (1 << 2) -#define TMP432_STATUS_TEMP_LOW_ALARM (1 << 3) -#define TMP432_STATUS_TEMP_HIGH_ALARM (1 << 4) -#define TMP432_STATUS_BUSY (1 << 7) +#define TMP432_STATUS_TEMP_THERM_ALARM BIT(1) +#define TMP432_STATUS_OPEN BIT(2) +#define TMP432_STATUS_TEMP_LOW_ALARM BIT(3) +#define TMP432_STATUS_TEMP_HIGH_ALARM BIT(4) +#define TMP432_STATUS_BUSY BIT(7) /* Limintaions */ #define TMP432_HYSTERESIS_HIGH_LIMIT 255 diff --git a/driver/temp_sensor/tmp468.h b/driver/temp_sensor/tmp468.h index ec528d0dcc..4b7f6bb814 100644 --- a/driver/temp_sensor/tmp468.h +++ b/driver/temp_sensor/tmp468.h @@ -77,7 +77,7 @@ #define TMP468_DEVICE_ID 0xfd #define TMP468_MANUFACTURER_ID 0xfe -#define TMP468_SHUTDOWN (1 << 5) +#define TMP468_SHUTDOWN BIT(5) enum tmp468_channel_id { TMP468_CHANNEL_LOCAL, diff --git a/driver/touchpad_elan.c b/driver/touchpad_elan.c index f0e456b525..848985109e 100644 --- a/driver/touchpad_elan.c +++ b/driver/touchpad_elan.c @@ -74,15 +74,15 @@ #define ETP_I2C_IAP_RESET_CMD 0x0314 #define ETP_I2C_IAP_RESET 0xF0F0 #define ETP_I2C_IAP_CTRL_CMD 0x0310 -#define ETP_I2C_MAIN_MODE_ON (1 << 9) +#define ETP_I2C_MAIN_MODE_ON BIT(9) #define ETP_I2C_IAP_CMD 0x0311 #define ETP_I2C_IAP_PASSWORD 0x1EA5 #define ETP_I2C_IAP_REG_L 0x01 #define ETP_I2C_IAP_REG_H 0x06 -#define ETP_FW_IAP_PAGE_ERR (1 << 5) -#define ETP_FW_IAP_INTF_ERR (1 << 4) +#define ETP_FW_IAP_PAGE_ERR BIT(5) +#define ETP_FW_IAP_INTF_ERR BIT(4) #ifdef CONFIG_USB_UPDATE /* The actual FW_SIZE depends on IC. */ diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c index d4ba6e7d5b..8c4a5cf2dd 100644 --- a/driver/touchpad_st.c +++ b/driver/touchpad_st.c @@ -55,26 +55,26 @@ static void touchpad_power_control(void); */ static int system_state; -#define SYSTEM_STATE_DEBUG_MODE (1 << 0) -#define SYSTEM_STATE_ENABLE_HEAT_MAP (1 << 1) -#define SYSTEM_STATE_ENABLE_DOME_SWITCH (1 << 2) -#define SYSTEM_STATE_ACTIVE_MODE (1 << 3) -#define SYSTEM_STATE_DOME_SWITCH_LEVEL (1 << 4) -#define SYSTEM_STATE_READY (1 << 5) +#define SYSTEM_STATE_DEBUG_MODE BIT(0) +#define SYSTEM_STATE_ENABLE_HEAT_MAP BIT(1) +#define SYSTEM_STATE_ENABLE_DOME_SWITCH BIT(2) +#define SYSTEM_STATE_ACTIVE_MODE BIT(3) +#define SYSTEM_STATE_DOME_SWITCH_LEVEL BIT(4) +#define SYSTEM_STATE_READY BIT(5) /* * Pending action for touchpad. */ static int tp_control; -#define TP_CONTROL_SHALL_HALT (1 << 0) -#define TP_CONTROL_SHALL_RESET (1 << 1) -#define TP_CONTROL_SHALL_INIT (1 << 2) -#define TP_CONTROL_SHALL_INIT_FULL (1 << 3) -#define TP_CONTROL_SHALL_DUMP_ERROR (1 << 4) -#define TP_CONTROL_RESETTING (1 << 5) -#define TP_CONTROL_INIT (1 << 6) -#define TP_CONTROL_INIT_FULL (1 << 7) +#define TP_CONTROL_SHALL_HALT BIT(0) +#define TP_CONTROL_SHALL_RESET BIT(1) +#define TP_CONTROL_SHALL_INIT BIT(2) +#define TP_CONTROL_SHALL_INIT_FULL BIT(3) +#define TP_CONTROL_SHALL_DUMP_ERROR BIT(4) +#define TP_CONTROL_RESETTING BIT(5) +#define TP_CONTROL_INIT BIT(6) +#define TP_CONTROL_INIT_FULL BIT(7) /* * Number of times we have reset the touchpad because of errors. @@ -124,7 +124,7 @@ static struct { struct packet_header_t { uint8_t index; -#define HEADER_FLAGS_NEW_FRAME (1 << 0) +#define HEADER_FLAGS_NEW_FRAME BIT(0) uint8_t flags; } __packed; BUILD_ASSERT(sizeof(struct packet_header_t) < USB_ISO_PACKET_SIZE); @@ -133,7 +133,7 @@ static struct packet_header_t packet_header; /* What will be sent to USB interface. */ struct st_tp_usb_packet_t { -#define USB_FRAME_FLAGS_BUTTON (1 << 0) +#define USB_FRAME_FLAGS_BUTTON BIT(0) /* * This will be true if user clicked on touchpad. * TODO(b/70482333): add corresponding code for button signal. @@ -375,14 +375,14 @@ static int st_tp_update_system_state(int new_state, int mask) }; if (new_state & SYSTEM_STATE_ENABLE_HEAT_MAP) { CPRINTS("Heatmap enabled"); - tx_buf[2] |= 1 << 0; + tx_buf[2] |= BIT(0); need_locked_scan_mode = 1; } else { CPRINTS("Heatmap disabled"); } if (new_state & SYSTEM_STATE_ENABLE_DOME_SWITCH) - tx_buf[2] |= 1 << 1; + tx_buf[2] |= BIT(1); ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0); if (ret) return ret; @@ -1782,7 +1782,7 @@ static int get_heat_map_addr(void) } struct st_tp_interrupt_t { -#define ST_TP_INT_FRAME_AVAILABLE (1 << 0) +#define ST_TP_INT_FRAME_AVAILABLE BIT(0) uint8_t flags; } __packed; diff --git a/driver/touchpad_st.h b/driver/touchpad_st.h index 6ae612be11..ecbddcb324 100644 --- a/driver/touchpad_st.h +++ b/driver/touchpad_st.h @@ -33,10 +33,10 @@ /* Max number of bytes that can be written in I2C to the DMA */ #define ST_TP_DMA_CHUNK_SIZE 32 -#define ST_HOST_BUFFER_DATA_VALID (1 << 0) -#define ST_HOST_BUFFER_MT_READY (1 << 3) -#define ST_HOST_BUFFER_SF_READY (1 << 4) -#define ST_HOST_BUFFER_SS_READY (1 << 5) +#define ST_HOST_BUFFER_DATA_VALID BIT(0) +#define ST_HOST_BUFFER_MT_READY BIT(3) +#define ST_HOST_BUFFER_SF_READY BIT(4) +#define ST_HOST_BUFFER_SS_READY BIT(5) #define ST_TP_SCAN_MODE_ACTIVE 0x00 #define ST_TP_SCAN_MODE_LOW_POWER 0x01 @@ -171,13 +171,13 @@ struct st_tp_system_info_t { ST_TP_SYSTEM_INFO_PART_1_RESERVED) struct st_tp_host_buffer_header_t { -#define ST_TP_BUFFER_HEADER_DATA_VALID (1 << 0) -#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY (1 << 1) -#define ST_TP_BUFFER_HEADER_SYS_FAULT (1 << 2) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY (1 << 3) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY (1 << 4) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY (1 << 5) -#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL (1 << 6) +#define ST_TP_BUFFER_HEADER_DATA_VALID BIT(0) +#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY BIT(1) +#define ST_TP_BUFFER_HEADER_SYS_FAULT BIT(2) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY BIT(3) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY BIT(4) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY BIT(5) +#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL BIT(6) uint8_t flags; uint8_t reserved[3]; uint8_t heatmap_miss_count; diff --git a/driver/usb_mux.c b/driver/usb_mux.c index fd3f4381c4..43ebd9841a 100644 --- a/driver/usb_mux.c +++ b/driver/usb_mux.c @@ -23,7 +23,7 @@ static int enable_debug_prints; */ static uint8_t flags[CONFIG_USB_PD_PORT_COUNT]; -#define USB_MUX_FLAG_IN_LPM (1 << 0) /* Device is in low power mode. */ +#define USB_MUX_FLAG_IN_LPM BIT(0) /* Device is in low power mode. */ static void enter_low_power_mode(int port) diff --git a/driver/usb_mux_it5205.h b/driver/usb_mux_it5205.h index 2c26f7ca41..dbc30466d6 100644 --- a/driver/usb_mux_it5205.h +++ b/driver/usb_mux_it5205.h @@ -20,11 +20,11 @@ /* MUX power down register */ #define IT5205_REG_MUXPDR 0x10 -#define IT5205_MUX_POWER_DOWN (1 << 0) +#define IT5205_MUX_POWER_DOWN BIT(0) /* MUX control register */ #define IT5205_REG_MUXCR 0x11 -#define IT5205_POLARITY_INVERTED (1 << 4) +#define IT5205_POLARITY_INVERTED BIT(4) #define IT5205_DP_USB_CTRL_MASK 0x0f #define IT5205_DP 0x0f diff --git a/driver/usb_mux_ps874x.h b/driver/usb_mux_ps874x.h index e9d4c1ff36..2b98ebcb63 100644 --- a/driver/usb_mux_ps874x.h +++ b/driver/usb_mux_ps874x.h @@ -11,17 +11,17 @@ /* Mode register for setting mux */ #define PS874X_REG_MODE 0x00 #ifdef CONFIG_USB_MUX_PS8740 - #define PS874X_MODE_POLARITY_INVERTED (1 << 4) - #define PS874X_MODE_USB_ENABLED (1 << 5) - #define PS874X_MODE_DP_ENABLED (1 << 6) - #define PS874X_MODE_POWER_DOWN (1 << 7) + #define PS874X_MODE_POLARITY_INVERTED BIT(4) + #define PS874X_MODE_USB_ENABLED BIT(5) + #define PS874X_MODE_DP_ENABLED BIT(6) + #define PS874X_MODE_POWER_DOWN BIT(7) #elif defined(CONFIG_USB_MUX_PS8743) - #define PS874X_MODE_POLARITY_INVERTED (1 << 2) - #define PS874X_MODE_FLIP_PIN_ENABLED (1 << 3) - #define PS874X_MODE_USB_ENABLED (1 << 4) - #define PS874X_MODE_CE_USB_ENABLED (1 << 5) - #define PS874X_MODE_DP_ENABLED (1 << 6) - #define PS874X_MODE_CE_DP_ENABLED (1 << 7) + #define PS874X_MODE_POLARITY_INVERTED BIT(2) + #define PS874X_MODE_FLIP_PIN_ENABLED BIT(3) + #define PS874X_MODE_USB_ENABLED BIT(4) + #define PS874X_MODE_CE_USB_ENABLED BIT(5) + #define PS874X_MODE_DP_ENABLED BIT(6) + #define PS874X_MODE_CE_DP_ENABLED BIT(7) /* To reset the state machine to default */ #define PS874X_MODE_POWER_DOWN (PS874X_MODE_CE_USB_ENABLED | \ PS874X_MODE_CE_DP_ENABLED) @@ -29,10 +29,10 @@ /* Status register for checking mux state */ #define PS874X_REG_STATUS 0x09 -#define PS874X_STATUS_POLARITY_INVERTED (1 << 2) -#define PS874X_STATUS_USB_ENABLED (1 << 3) -#define PS874X_STATUS_DP_ENABLED (1 << 4) -#define PS874X_STATUS_HPD_ASSERTED (1 << 7) +#define PS874X_STATUS_POLARITY_INVERTED BIT(2) +#define PS874X_STATUS_USB_ENABLED BIT(3) +#define PS874X_STATUS_DP_ENABLED BIT(4) +#define PS874X_STATUS_HPD_ASSERTED BIT(7) /* Chip ID / revision registers and expected fused values */ #define PS874X_REG_REVISION_ID1 0xf0 @@ -62,7 +62,7 @@ #define PS874X_USB_EQ_TX_9_5_DB 0xc0 #define PS874X_USB_EQ_TX_7_5_DB 0xe0 #define PS874X_USB_EQ_TERM_100_OHM (0 << 2) - #define PS874X_USB_EQ_TERM_85_OHM (1 << 2) + #define PS874X_USB_EQ_TERM_85_OHM BIT(2) #elif defined(CONFIG_USB_MUX_PS8743) #define PS874X_USB_EQ_TX_12_8_DB 0x00 #define PS874X_USB_EQ_TX_17_DB 0x20 |