diff options
Diffstat (limited to 'include/driver/retimer')
| -rw-r--r-- | include/driver/retimer/anx7483_public.h | 18 | ||||
| -rw-r--r-- | include/driver/retimer/bb_retimer.h | 68 | ||||
| -rw-r--r-- | include/driver/retimer/bb_retimer_public.h | 10 | ||||
| -rw-r--r-- | include/driver/retimer/ps8818_public.h | 96 |
4 files changed, 149 insertions, 43 deletions
diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index 8c3b9eaf60..83ad32508e 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -13,10 +13,10 @@ #include "usb_mux.h" /* I2C interface addresses */ -#define ANX7483_I2C_ADDR0_FLAGS 0x3E -#define ANX7483_I2C_ADDR1_FLAGS 0x38 -#define ANX7483_I2C_ADDR2_FLAGS 0x40 -#define ANX7483_I2C_ADDR3_FLAGS 0x44 +#define ANX7483_I2C_ADDR0_FLAGS 0x3E +#define ANX7483_I2C_ADDR1_FLAGS 0x38 +#define ANX7483_I2C_ADDR2_FLAGS 0x40 +#define ANX7483_I2C_ADDR3_FLAGS 0x44 /* Equalization tuning */ enum anx7483_eq_setting { @@ -52,9 +52,11 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, enum anx7483_tune_pin pin, enum anx7483_eq_setting eq); -/* Configure datasheet defaults for tuning registers at this mux setting */ -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state); +/* + * Configure datasheet defaults for tuning registers at this mux setting. + * Return int so function can be used directly for board_set. + */ +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state); extern const struct usb_mux_driver anx7483_usb_retimer_driver; #endif /* __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H */ diff --git a/include/driver/retimer/bb_retimer.h b/include/driver/retimer/bb_retimer.h index 6a311bd2ca..460156803e 100644 --- a/include/driver/retimer/bb_retimer.h +++ b/include/driver/retimer/bb_retimer.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,44 +12,44 @@ #include "driver/retimer/bb_retimer_public.h" /* Burnside Bridge I2C Configuration Space */ -#define BB_RETIMER_REG_VENDOR_ID 0 -#define BB_RETIMER_VENDOR_ID_1 0x8086 -#define BB_RETIMER_VENDOR_ID_2 0x8087 +#define BB_RETIMER_REG_VENDOR_ID 0 +#define BB_RETIMER_VENDOR_ID_1 0x8086 +#define BB_RETIMER_VENDOR_ID_2 0x8087 -#define BB_RETIMER_REG_DEVICE_ID 1 -#ifdef CONFIG_USBC_RETIMER_INTEL_HB +#define BB_RETIMER_REG_DEVICE_ID 1 +#ifdef CONFIG_USBC_RETIMER_INTEL_HB /* HB has no Device ID field instead it is combined with Vendor ID */ -#define BB_RETIMER_DEVICE_ID 0x0D9C8087 +#define BB_RETIMER_DEVICE_ID 0x0D9C8087 #else -#define BB_RETIMER_DEVICE_ID 0x15EE +#define BB_RETIMER_DEVICE_ID 0x15EE #endif /* Connection State Register Attributes */ -#define BB_RETIMER_REG_CONNECTION_STATE 4 -#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) -#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) -#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) -#define BB_RETIMER_USB_2_CONNECTION BIT(4) -#define BB_RETIMER_USB_3_CONNECTION BIT(5) -#define BB_RETIMER_USB_3_SPEED BIT(6) -#define BB_RETIMER_USB_DATA_ROLE BIT(7) -#define BB_RETIMER_DP_CONNECTION BIT(8) -#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) -#define BB_RETIMER_IRQ_HPD BIT(14) -#define BB_RETIMER_HPD_LVL BIT(15) -#define BB_RETIMER_TBT_CONNECTION BIT(16) -#define BB_RETIMER_TBT_TYPE BIT(17) -#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) -#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) -#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) -#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) -#define BB_RETIMER_USB4_ENABLED BIT(23) -#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x) & 0x7) << 25) -#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x) & 0x3) << 28) - -#define BB_RETIMER_REG_TBT_CONTROL 5 -#define BB_RETIMER_REG_EXT_CONNECTION_MODE 6 - -#define BB_RETIMER_REG_COUNT 7 +#define BB_RETIMER_REG_CONNECTION_STATE 4 +#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) +#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) +#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) +#define BB_RETIMER_USB_2_CONNECTION BIT(4) +#define BB_RETIMER_USB_3_CONNECTION BIT(5) +#define BB_RETIMER_USB_3_SPEED BIT(6) +#define BB_RETIMER_USB_DATA_ROLE BIT(7) +#define BB_RETIMER_DP_CONNECTION BIT(8) +#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) +#define BB_RETIMER_IRQ_HPD BIT(14) +#define BB_RETIMER_HPD_LVL BIT(15) +#define BB_RETIMER_TBT_CONNECTION BIT(16) +#define BB_RETIMER_TBT_TYPE BIT(17) +#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) +#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) +#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) +#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) +#define BB_RETIMER_USB4_ENABLED BIT(23) +#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x)&0x7) << 25) +#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x)&0x3) << 28) + +#define BB_RETIMER_REG_TBT_CONTROL 5 +#define BB_RETIMER_REG_EXT_CONNECTION_MODE 7 + +#define BB_RETIMER_REG_COUNT 8 #endif /* __CROS_EC_BB_RETIMER_H */ diff --git a/include/driver/retimer/bb_retimer_public.h b/include/driver/retimer/bb_retimer_public.h index d79b051504..2d2893fb49 100644 --- a/include/driver/retimer/bb_retimer_public.h +++ b/include/driver/retimer/bb_retimer_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -56,4 +56,12 @@ __override_proto int bb_retimer_power_enable(const struct usb_mux *me, void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required); +/** + * Enable/disable the USB3 state of BB retimer + * + * @param me Pointer to USB mux + * @param enable BB retimer USB3 state to be changed + */ +void bb_retimer_set_usb3(const struct usb_mux *me, bool enable); + #endif /* __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H */ diff --git a/include/driver/retimer/ps8818_public.h b/include/driver/retimer/ps8818_public.h new file mode 100644 index 0000000000..3f0aba963b --- /dev/null +++ b/include/driver/retimer/ps8818_public.h @@ -0,0 +1,96 @@ +/* Copyright 2019 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * PS8818 retimer. + */ +#include "usb_mux.h" + +#ifndef __CROS_EC_USB_RETIMER_PS8818_H +#define __CROS_EC_USB_RETIMER_PS8818_H + +#define PS8818_I2C_ADDR_FLAGS 0x28 + +/* + * PAGE 0 Register Definitions + */ +#define PS8818_REG_PAGE0 0x00 + +#define PS8818_REG0_FLIP 0x00 +#define PS8818_FLIP_CONFIG BIT(7) +#define PS8818_FLIP_NON_RESERVED_MASK 0xE0 + +#define PS8818_REG0_MODE 0x01 +#define PS8818_MODE_DP_ENABLE BIT(7) +#define PS8818_MODE_USB_ENABLE BIT(6) +#define PS8818_MODE_NON_RESERVED_MASK 0xC0 + +#define PS8818_REG0_DPHPD_CONFIG 0x02 +#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7) +#define PS8818_DPHPD_PLUGGED BIT(6) +#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC + +/* + * PAGE 1 Register Definitions + */ +#define PS8818_REG_PAGE1 0x01 + +#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00 +#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02 +#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08 +#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A +#define PS8818_REG1_APRX1_DE_LEVEL 0x0C +#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70 +#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72 +#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78 +#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A +#define PS8818_EQ_LEVEL_UP_9DB (0) +#define PS8818_EQ_LEVEL_UP_10DB (1) +#define PS8818_EQ_LEVEL_UP_12DB (2) +#define PS8818_EQ_LEVEL_UP_13DB (3) +#define PS8818_EQ_LEVEL_UP_16DB (4) +#define PS8818_EQ_LEVEL_UP_17DB (5) +#define PS8818_EQ_LEVEL_UP_18DB (6) +#define PS8818_EQ_LEVEL_UP_19DB (7) +#define PS8818_EQ_LEVEL_UP_20DB (8) +#define PS8818_EQ_LEVEL_UP_21DB (9) +#define PS8818_EQ_LEVEL_UP_MASK (0x0F) + +#define PS8818_REG1_RX_PHY 0x6D +#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6) +#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6) +#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6) +#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6) +#define PS8818_RX_INPUT_TERM_MASK (3 << 6) + +#define PS8818_REG1_DPEQ_LEVEL 0xB6 +#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3) +#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3) +#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3) +#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3) +#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3) +#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3) +#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3) +#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3) +#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3) +#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3) +#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3) + +/* + * PAGE 2 Register Definitions + */ +#define PS8818_REG_PAGE2 0x02 + +#define PS8818_REG2_TX_STATUS 0x42 +#define PS8818_REG2_RX_STATUS 0x46 +#define PS8818_STATUS_NORMAL_OPERATION BIT(7) +#define PS8818_STATUS_10_GBPS BIT(5) + +extern const struct usb_mux_driver ps8818_usb_retimer_driver; + +int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data); +int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data); +int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset, + uint8_t field_mask, uint8_t set_value); + +#endif /* __CROS_EC_USB_RETIMER_PS8818_H */ |