diff options
Diffstat (limited to 'include')
305 files changed, 8082 insertions, 7315 deletions
diff --git a/include/2id.h b/include/2id.h index 8daa4d27db..8d05f96e56 100644 --- a/include/2id.h +++ b/include/2id.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -25,8 +25,23 @@ struct vb2_id { #define EXPECTED_ID_SIZE VB2_ID_NUM_BYTES /* IDs to use for "keys" with sig_alg==VB2_SIG_NONE */ -#define VB2_ID_NONE_SHA1 {{0x00, 0x01,}} -#define VB2_ID_NONE_SHA256 {{0x02, 0x56,}} -#define VB2_ID_NONE_SHA512 {{0x05, 0x12,}} +#define VB2_ID_NONE_SHA1 \ + { \ + { \ + 0x00, 0x01, \ + } \ + } +#define VB2_ID_NONE_SHA256 \ + { \ + { \ + 0x02, 0x56, \ + } \ + } +#define VB2_ID_NONE_SHA512 \ + { \ + { \ + 0x05, 0x12, \ + } \ + } -#endif /* VBOOT_REFERENCE_VBOOT_2ID_H_ */ +#endif /* VBOOT_REFERENCE_VBOOT_2ID_H_ */ diff --git a/include/accel_cal.h b/include/accel_cal.h index 80f0161a04..2f7b5d6bbf 100644 --- a/include/accel_cal.h +++ b/include/accel_cal.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/accelgyro.h b/include/accelgyro.h index be6b8061c3..74824b2611 100644 --- a/include/accelgyro.h +++ b/include/accelgyro.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -60,9 +60,7 @@ struct accelgyro_drv { * * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_range)(struct motion_sensor_t *s, - int range, - int rnd); + int (*set_range)(struct motion_sensor_t *s, int range, int rnd); /** * Setter and getter methods for the sensor resolution. @@ -72,9 +70,8 @@ struct accelgyro_drv { * value. Otherwise, it rounds down. * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_resolution)(const struct motion_sensor_t *s, - int res, - int rnd); + int (*set_resolution)(const struct motion_sensor_t *s, int res, + int rnd); int (*get_resolution)(const struct motion_sensor_t *s); /** @@ -86,12 +83,10 @@ struct accelgyro_drv { * value. Otherwise, it rounds down. * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_data_rate)(const struct motion_sensor_t *s, - int rate, - int rnd); + int (*set_data_rate)(const struct motion_sensor_t *s, int rate, + int rnd); int (*get_data_rate)(const struct motion_sensor_t *s); - /** * Setter and getter methods for the sensor offset. * @s Pointer to sensor data. @@ -100,11 +95,9 @@ struct accelgyro_drv { * @return EC_SUCCESS if successful, non-zero if error. */ int (*set_offset)(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp); - int (*get_offset)(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp); + const int16_t *offset, int16_t temp); + int (*get_offset)(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp); /** * Setter and getter methods for the sensor scale. * @s Pointer to sensor data. @@ -112,19 +105,16 @@ struct accelgyro_drv { * @temp: temperature when calibration was done. * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_scale)(const struct motion_sensor_t *s, - const uint16_t *scale, - int16_t temp); - int (*get_scale)(const struct motion_sensor_t *s, - uint16_t *scale, - int16_t *temp); + int (*set_scale)(const struct motion_sensor_t *s, const uint16_t *scale, + int16_t temp); + int (*get_scale)(const struct motion_sensor_t *s, uint16_t *scale, + int16_t *temp); /** * Request performing/entering calibration. * Either a one shot mode (enable is not used), * or enter/exit a calibration state. */ - int (*perform_calib)(struct motion_sensor_t *s, - int enable); + int (*perform_calib)(struct motion_sensor_t *s, int enable); /** * Function that probes if supported chip is present. @@ -161,8 +151,7 @@ struct accelgyro_drv { * @data additional data if needed, activity dependent. */ int (*manage_activity)(const struct motion_sensor_t *s, - enum motionsensor_activity activity, - int enable, + enum motionsensor_activity activity, int enable, const struct ec_motion_sense_activity *data); /** * List activities managed by the sensors. @@ -171,8 +160,7 @@ struct accelgyro_drv { * @disabled bit mask of activities currently disabled. */ int (*list_activities)(const struct motion_sensor_t *s, - uint32_t *enabled, - uint32_t *disabled); + uint32_t *enabled, uint32_t *disabled); /** * Get the root mean square of current noise (ug/mdps) in the sensor. @@ -248,9 +236,9 @@ struct rgb_calibration_t { /* als driver data */ struct als_drv_data_t { - int rate; /* holds current sensor rate */ - int last_value; /* holds last als clear channel value */ - struct als_calibration_t als_cal; /* calibration data */ + int rate; /* holds current sensor rate */ + int last_value; /* holds last als clear channel value */ + struct als_calibration_t als_cal; /* calibration data */ }; #define SENSOR_APPLY_DIV_SCALE(_input, _scale) \ @@ -260,6 +248,6 @@ struct als_drv_data_t { (((_input) * (uint64_t)(_scale)) / MOTION_SENSE_DEFAULT_SCALE) /* Individual channel scale value between 0 and 2 represented in 16 bits */ -#define ALS_CHANNEL_SCALE(_x) ((_x) * MOTION_SENSE_DEFAULT_SCALE) +#define ALS_CHANNEL_SCALE(_x) ((_x)*MOTION_SENSE_DEFAULT_SCALE) #endif /* __CROS_EC_ACCELGYRO_H */ diff --git a/include/acpi.h b/include/acpi.h index 56930c4b2d..b99fe9a235 100644 --- a/include/acpi.h +++ b/include/acpi.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -74,4 +74,4 @@ int acpi_dptf_set_profile_num(int n); */ int acpi_dptf_get_profile_num(void); -#endif /* __CROS_EC_ACPI_H */ +#endif /* __CROS_EC_ACPI_H */ diff --git a/include/adc.h b/include/adc.h index 890b6662d4..ddb6c8246e 100644 --- a/include/adc.h +++ b/include/adc.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,7 +11,7 @@ #include "adc_chip.h" #include "common.h" -#define ADC_READ_ERROR -1 /* Value returned by adc_read_channel() on error */ +#define ADC_READ_ERROR -1 /* Value returned by adc_read_channel() on error */ #ifdef CONFIG_ZEPHYR #include <zephyr_adc.h> @@ -80,4 +80,4 @@ int adc_disable_watchdog(void); */ int adc_set_watchdog_delay(int delay_ms); -#endif /* __CROS_EC_ADC_H */ +#endif /* __CROS_EC_ADC_H */ diff --git a/include/als.h b/include/als.h index 4ff3fcdb4f..21c373c9b6 100644 --- a/include/als.h +++ b/include/als.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,4 +34,4 @@ extern struct als_t als[]; */ int als_read(enum als_id id, int *lux); -#endif /* __CROS_EC_ALS_H */ +#endif /* __CROS_EC_ALS_H */ diff --git a/include/ap_hang_detect.h b/include/ap_hang_detect.h index 9526bb0a84..8dfcce6d74 100644 --- a/include/ap_hang_detect.h +++ b/include/ap_hang_detect.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,4 +17,4 @@ */ void hang_detect_stop_on_host_command(void); -#endif /* __CROS_EC_AP_HANG_DETECT_H */ +#endif /* __CROS_EC_AP_HANG_DETECT_H */ diff --git a/include/atkbd_protocol.h b/include/atkbd_protocol.h new file mode 100644 index 0000000000..a33e6e455e --- /dev/null +++ b/include/atkbd_protocol.h @@ -0,0 +1,45 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * ATKBD keyboard protocol constants. + * + * See the IBL PC AT Technical Reference Manual Section 4. + * i.e., 6183355_PC_AT_Technical_Reference_Mar86.pdf + * + * https://archive.org/details/bitsavers_ibmpcat618ferenceMar86_25829277/page/n151/mode/2up + */ + +#ifndef __CROS_EC_ATKBD_PROTOCOL_H +#define __CROS_EC_ATKBD_PROTOCOL_H + +#define ATKBD_CMD_OK_GETID 0xe8 +#define ATKBD_CMD_EX_ENABLE 0xea +#define ATKBD_CMD_EX_SETLEDS 0xeb +#define ATKBD_CMD_SETLEDS 0xed +#define ATKBD_CMD_DIAG_ECHO 0xee +#define ATKBD_CMD_GSCANSET 0xf0 +#define ATKBD_CMD_SSCANSET 0xf0 +#define ATKBD_CMD_GETID 0xf2 +#define ATKBD_CMD_SETREP 0xf3 +#define ATKBD_CMD_ENABLE 0xf4 +#define ATKBD_CMD_RESET_DIS 0xf5 +#define ATKBD_CMD_RESET_DEF 0xf6 +#define ATKBD_CMD_ALL_TYPEM 0xf7 +#define ATKBD_CMD_SETALL_MB 0xf8 +#define ATKBD_CMD_SETALL_MBR 0xfa +#define ATKBD_CMD_SET_A_KEY_T 0xfb +#define ATKBD_CMD_SET_A_KEY_MR 0xfc +#define ATKBD_CMD_SET_A_KEY_M 0xfd +#define ATKBD_CMD_RESEND 0xfe +#define ATKBD_CMD_RESET 0xff + +#define ATKBD_RET_OVERFLOW 0x00 +#define ATKBD_RET_TEST_SUCCESS 0xaa +#define ATKBD_RET_ECHO 0xee +#define ATKBD_RET_ACK 0xfa +#define ATKBD_RET_TEST_FAIL 0xfc +#define ATKBD_RET_INTERNAL_FAIL 0xfd +#define ATKBD_RET_RESEND 0xfe + +#endif /* __CROS_EC_ATKBD_PROTOCOL_H */ diff --git a/include/atomic_bit.h b/include/atomic_bit.h index 3aeaa6c5b6..34416a2f89 100644 --- a/include/atomic_bit.h +++ b/include/atomic_bit.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/atomic_t.h b/include/atomic_t.h index d7c1a99147..7f95665f46 100644 --- a/include/atomic_t.h +++ b/include/atomic_t.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,4 +19,4 @@ typedef atomic_t atomic_val_t; #include <zephyr/sys/atomic.h> #endif -#endif /* __CROS_EC_ATOMIC_T_H */ +#endif /* __CROS_EC_ATOMIC_T_H */ diff --git a/include/audio_codec.h b/include/audio_codec.h index b80d1c0f57..431f776247 100644 --- a/include/audio_codec.h +++ b/include/audio_codec.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -41,8 +41,8 @@ int audio_codec_capable(uint8_t cap); * EC_ERROR_INVAL if invalid cap. * EC_ERROR_BUSY if the shm_id has been registered. */ -int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, - uintptr_t *addr, uint32_t len, uint8_t type); +int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, uintptr_t *addr, + uint32_t len, uint8_t type); /* * Translates the physical address from AP to EC's memory space. Required if @@ -63,7 +63,6 @@ int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr); */ int16_t audio_codec_s16_scale_and_clip(int16_t orig, uint8_t scalar); - /* * DMIC abstract layer */ @@ -120,7 +119,6 @@ int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain); */ int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain); - /* * I2S RX abstract layer */ @@ -181,7 +179,6 @@ int audio_codec_i2s_rx_set_daifmt(uint8_t daifmt); */ int audio_codec_i2s_rx_set_bclk(uint32_t bclk); - /* * WoV abstract layer */ diff --git a/include/backlight.h b/include/backlight.h index 1bfafbdd2c..4d37af01c0 100644 --- a/include/backlight.h +++ b/include/backlight.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,7 +19,9 @@ #ifdef CONFIG_BACKLIGHT_REQ_GPIO void backlight_interrupt(enum gpio_signal signal); #else -static inline void backlight_interrupt(enum gpio_signal signal) { } +static inline void backlight_interrupt(enum gpio_signal signal) +{ +} #endif /* !CONFIG_BACKLIGHT_REQ_GPIO */ /** @@ -27,4 +29,4 @@ static inline void backlight_interrupt(enum gpio_signal signal) { } */ void enable_backlight(int enabled); -#endif /* __CROS_EC_BACKLIGHT_H */ +#endif /* __CROS_EC_BACKLIGHT_H */ diff --git a/include/base32.h b/include/base32.h index ac04ce9c70..a1816afb60 100644 --- a/include/base32.h +++ b/include/base32.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -41,9 +41,8 @@ uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc); * must be a multiple of add_crc_every. * @return EC_SUCCESS, or non-zero error code. */ -int base32_encode(char *dest, int destlen_chars, - const void *srcbits, int srclen_bits, - int add_crc_every); +int base32_encode(char *dest, int destlen_chars, const void *srcbits, + int srclen_bits, int add_crc_every); /** * base32-decode data from a null-terminated string diff --git a/include/base_state.h b/include/base_state.h index d8c72e5663..60b499ecd0 100644 --- a/include/base_state.h +++ b/include/base_state.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/battery.h b/include/battery.h index 9daf1ce981..51fcd68696 100644 --- a/include/battery.h +++ b/include/battery.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -23,38 +23,41 @@ #else /* !CONFIG_ZEPHYR */ /* Stop charge when charging and battery level >= this percentage */ -#define BATTERY_LEVEL_FULL 100 +#define BATTERY_LEVEL_FULL 100 /* Tell host we're charged when battery level >= this percentage */ #ifdef CONFIG_BATTERY_LEVEL_NEAR_FULL -#define BATTERY_LEVEL_NEAR_FULL CONFIG_BATTERY_LEVEL_NEAR_FULL +#define BATTERY_LEVEL_NEAR_FULL CONFIG_BATTERY_LEVEL_NEAR_FULL #else -#define BATTERY_LEVEL_NEAR_FULL 97 +#define BATTERY_LEVEL_NEAR_FULL 97 #endif /* * Send battery-low host event when discharging and battery level <= this level */ -#define BATTERY_LEVEL_LOW 10 +#define BATTERY_LEVEL_LOW 10 /* * Send battery-critical host event when discharging and battery level <= this * level. */ -#define BATTERY_LEVEL_CRITICAL 5 +#define BATTERY_LEVEL_CRITICAL 5 /* * Shut down main processor and/or hibernate EC when discharging and battery * level < this level. Setting this too low makes the battery discharge too * deeply, which isn't good for the battery health. */ -#define BATTERY_LEVEL_SHUTDOWN 3 +#define BATTERY_LEVEL_SHUTDOWN 3 #endif /* CONFIG_ZEPHYR */ /* Full-capacity change reqd for host event */ #define LFCC_EVENT_THRESH 5 +/* Max string size in the SB spec is 31. */ +#define SB_MAX_STR_SIZE 31 + /* Battery index, only used with CONFIG_BATTERY_V2. */ enum battery_index { BATT_IDX_INVALID = -1, @@ -66,7 +69,7 @@ enum battery_index { * Sometimes we have hardware to detect battery present, sometimes we have to * wait until we've been able to talk to the battery. */ -FORWARD_DECLARE_ENUM(battery_present) { +FORWARD_DECLARE_ENUM(battery_present){ BP_NOT_INIT = -1, BP_NO = 0, BP_YES = 1, @@ -96,13 +99,12 @@ struct battery_static_info { * char device_name[32]; * char chemistry[32]; */ - /* Max string size in the SB spec is 31. */ - char manufacturer_ext[32]; /* SB_MANUFACTURER_NAME */ - char model_ext[32]; /* SB_DEVICE_NAME */ - char serial_ext[32]; /* SB_SERIAL_NUMBER */ - char type_ext[32]; /* SB_DEVICE_CHEMISTRY */ + char manufacturer_ext[SB_MAX_STR_SIZE + 1]; /* SB_MANUFACTURER_NAME */ + char model_ext[SB_MAX_STR_SIZE + 1]; /* SB_DEVICE_NAME */ + char serial_ext[SB_MAX_STR_SIZE + 1]; /* SB_SERIAL_NUMBER */ + char type_ext[SB_MAX_STR_SIZE + 1]; /* SB_DEVICE_CHEMISTRY */ #ifdef CONFIG_BATTERY_VENDOR_PARAM - uint8_t vendor_param[32]; + uint8_t vendor_param[SB_MAX_STR_SIZE + 1]; #endif }; @@ -111,18 +113,18 @@ extern struct ec_response_battery_dynamic_info battery_dynamic[]; /* Battery parameters */ struct batt_params { - int temperature; /* Temperature in 0.1 K */ - int state_of_charge; /* State of charge (percent, 0-100) */ - int voltage; /* Battery voltage (mV) */ - int current; /* Battery current (mA); negative=discharging */ - int desired_voltage; /* Charging voltage desired by battery (mV) */ - int desired_current; /* Charging current desired by battery (mA) */ - int remaining_capacity; /* Remaining capacity in mAh */ - int full_capacity; /* Capacity in mAh (might change occasionally) */ - int display_charge; /* Display charge in 10ths of a % (1000=100.0%) */ - int status; /* Battery status */ + int temperature; /* Temperature in 0.1 K */ + int state_of_charge; /* State of charge (percent, 0-100) */ + int voltage; /* Battery voltage (mV) */ + int current; /* Battery current (mA); negative=discharging */ + int desired_voltage; /* Charging voltage desired by battery (mV) */ + int desired_current; /* Charging current desired by battery (mA) */ + int remaining_capacity; /* Remaining capacity in mAh */ + int full_capacity; /* Capacity in mAh (might change occasionally) */ + int display_charge; /* Display charge in 10ths of a % (1000=100.0%) */ + int status; /* Battery status */ enum battery_present is_present; /* Is the battery physically present */ - int flags; /* Flags */ + int flags; /* Flags */ }; /* @@ -138,25 +140,25 @@ int battery_get_avg_voltage(void); /* in mV */ /* Flags for batt_params */ /* Battery wants to be charged */ -#define BATT_FLAG_WANT_CHARGE 0x00000001 +#define BATT_FLAG_WANT_CHARGE 0x00000001 /* Battery is responsive (talking to us via I2C) */ -#define BATT_FLAG_RESPONSIVE 0x00000002 +#define BATT_FLAG_RESPONSIVE 0x00000002 /* Bits to indicate which parameter(s) could not be read */ -#define BATT_FLAG_BAD_TEMPERATURE 0x00000004 -#define BATT_FLAG_BAD_STATE_OF_CHARGE 0x00000008 -#define BATT_FLAG_BAD_VOLTAGE 0x00000010 -#define BATT_FLAG_BAD_CURRENT 0x00000020 -#define BATT_FLAG_BAD_DESIRED_VOLTAGE 0x00000040 -#define BATT_FLAG_BAD_DESIRED_CURRENT 0x00000080 -#define BATT_FLAG_BAD_REMAINING_CAPACITY 0x00000100 -#define BATT_FLAG_BAD_FULL_CAPACITY 0x00000200 -#define BATT_FLAG_BAD_STATUS 0x00000400 -#define BATT_FLAG_IMBALANCED_CELL 0x00000800 -#define BATT_FLAG_BAD_AVERAGE_CURRENT 0x00001000 +#define BATT_FLAG_BAD_TEMPERATURE 0x00000004 +#define BATT_FLAG_BAD_STATE_OF_CHARGE 0x00000008 +#define BATT_FLAG_BAD_VOLTAGE 0x00000010 +#define BATT_FLAG_BAD_CURRENT 0x00000020 +#define BATT_FLAG_BAD_DESIRED_VOLTAGE 0x00000040 +#define BATT_FLAG_BAD_DESIRED_CURRENT 0x00000080 +#define BATT_FLAG_BAD_REMAINING_CAPACITY 0x00000100 +#define BATT_FLAG_BAD_FULL_CAPACITY 0x00000200 +#define BATT_FLAG_BAD_STATUS 0x00000400 +#define BATT_FLAG_IMBALANCED_CELL 0x00000800 +#define BATT_FLAG_BAD_AVERAGE_CURRENT 0x00001000 /* All of the above BATT_FLAG_BAD_* bits */ -#define BATT_FLAG_BAD_ANY 0x000017fc +#define BATT_FLAG_BAD_ANY 0x000017fc /* Battery constants */ struct battery_info { diff --git a/include/battery_bq27621_g1.h b/include/battery_bq27621_g1.h index ff7e546f3a..019a9d2fe4 100644 --- a/include/battery_bq27621_g1.h +++ b/include/battery_bq27621_g1.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/battery_fuel_gauge.h b/include/battery_fuel_gauge.h index 7589a68190..b3fbb035e7 100644 --- a/include/battery_fuel_gauge.h +++ b/include/battery_fuel_gauge.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -67,7 +67,6 @@ struct board_batt_params { extern const struct board_batt_params board_battery_info[]; extern const enum battery_type DEFAULT_BATTERY_TYPE; - #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE /** * Report the absolute difference between the highest and lowest cell voltage in diff --git a/include/battery_smart.h b/include/battery_smart.h index c37b7c692c..f07b967861 100644 --- a/include/battery_smart.h +++ b/include/battery_smart.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,167 +11,168 @@ #include "common.h" /* Smart battery and charger I2C address */ -#define BATTERY_ADDR_FLAGS 0x0B -#define CHARGER_ADDR_FLAGS 0x09 +#define BATTERY_ADDR_FLAGS 0x0B +#define CHARGER_ADDR_FLAGS 0x09 /* Charger functions */ -#define SB_CHARGER_SPEC_INFO 0x11 -#define SB_CHARGE_MODE 0x12 -#define SB_CHARGER_STATUS 0x13 -#define SB_CHARGING_CURRENT 0x14 -#define SB_CHARGING_VOLTAGE 0x15 -#define SB_ALARM_WARNING 0x16 +#define SB_CHARGER_SPEC_INFO 0x11 +#define SB_CHARGE_MODE 0x12 +#define SB_CHARGER_STATUS 0x13 +#define SB_CHARGING_CURRENT 0x14 +#define SB_CHARGING_VOLTAGE 0x15 +#define SB_ALARM_WARNING 0x16 /* Battery functions */ -#define SB_MANUFACTURER_ACCESS 0x00 -#define SB_REMAINING_CAPACITY_ALARM 0x01 -#define SB_REMAINING_TIME_ALARM 0x02 -#define SB_BATTERY_MODE 0x03 -#define SB_AT_RATE 0x04 -#define SB_AT_RATE_TIME_TO_FULL 0x05 -#define SB_AT_RATE_TIME_TO_EMPTY 0x06 -#define SB_AT_RATE_OK 0x07 -#define SB_TEMPERATURE 0x08 -#define SB_VOLTAGE 0x09 -#define SB_CURRENT 0x0a -#define SB_AVERAGE_CURRENT 0x0b -#define SB_MAX_ERROR 0x0c -#define SB_RELATIVE_STATE_OF_CHARGE 0x0d -#define SB_ABSOLUTE_STATE_OF_CHARGE 0x0e -#define SB_REMAINING_CAPACITY 0x0f -#define SB_FULL_CHARGE_CAPACITY 0x10 -#define SB_RUN_TIME_TO_EMPTY 0x11 -#define SB_AVERAGE_TIME_TO_EMPTY 0x12 -#define SB_AVERAGE_TIME_TO_FULL 0x13 -#define SB_CHARGING_CURRENT 0x14 -#define SB_CHARGING_VOLTAGE 0x15 -#define SB_BATTERY_STATUS 0x16 -#define SB_CYCLE_COUNT 0x17 -#define SB_DESIGN_CAPACITY 0x18 -#define SB_DESIGN_VOLTAGE 0x19 -#define SB_SPECIFICATION_INFO 0x1a -#define SB_MANUFACTURE_DATE 0x1b -#define SB_SERIAL_NUMBER 0x1c -#define SB_MANUFACTURER_NAME 0x20 -#define SB_DEVICE_NAME 0x21 -#define SB_DEVICE_CHEMISTRY 0x22 -#define SB_MANUFACTURER_DATA 0x23 -#define SB_OPTIONAL_MFG_FUNC1 0x3C -#define SB_OPTIONAL_MFG_FUNC2 0x3D -#define SB_OPTIONAL_MFG_FUNC3 0x3E -#define SB_OPTIONAL_MFG_FUNC4 0x3F +#define SB_MANUFACTURER_ACCESS 0x00 +#define SB_REMAINING_CAPACITY_ALARM 0x01 +#define SB_REMAINING_TIME_ALARM 0x02 +#define SB_BATTERY_MODE 0x03 +#define SB_AT_RATE 0x04 +#define SB_AT_RATE_TIME_TO_FULL 0x05 +#define SB_AT_RATE_TIME_TO_EMPTY 0x06 +#define SB_AT_RATE_OK 0x07 +#define SB_TEMPERATURE 0x08 +#define SB_VOLTAGE 0x09 +#define SB_CURRENT 0x0a +#define SB_AVERAGE_CURRENT 0x0b +#define SB_MAX_ERROR 0x0c +#define SB_RELATIVE_STATE_OF_CHARGE 0x0d +#define SB_ABSOLUTE_STATE_OF_CHARGE 0x0e +#define SB_REMAINING_CAPACITY 0x0f +#define SB_FULL_CHARGE_CAPACITY 0x10 +#define SB_RUN_TIME_TO_EMPTY 0x11 +#define SB_AVERAGE_TIME_TO_EMPTY 0x12 +#define SB_AVERAGE_TIME_TO_FULL 0x13 +#define SB_CHARGING_CURRENT 0x14 +#define SB_CHARGING_VOLTAGE 0x15 +#define SB_BATTERY_STATUS 0x16 +#define SB_CYCLE_COUNT 0x17 +#define SB_DESIGN_CAPACITY 0x18 +#define SB_DESIGN_VOLTAGE 0x19 +#define SB_SPECIFICATION_INFO 0x1a +#define SB_MANUFACTURE_DATE 0x1b +#define SB_SERIAL_NUMBER 0x1c +#define SB_MANUFACTURER_NAME 0x20 +#define SB_DEVICE_NAME 0x21 +#define SB_DEVICE_CHEMISTRY 0x22 +#define SB_MANUFACTURER_DATA 0x23 +#define SB_OPTIONAL_MFG_FUNC1 0x3C +#define SB_OPTIONAL_MFG_FUNC2 0x3D +#define SB_OPTIONAL_MFG_FUNC3 0x3E +#define SB_OPTIONAL_MFG_FUNC4 0x3F /* Extension of smart battery spec, may not be supported on all platforms */ -#define SB_PACK_STATUS 0x43 -#define SB_ALT_MANUFACTURER_ACCESS 0x44 -#define SB_MANUFACTURE_INFO 0x70 +#define SB_PACK_STATUS 0x43 +#define SB_ALT_MANUFACTURER_ACCESS 0x44 +#define SB_MANUFACTURE_INFO 0x70 /* Battery mode */ #define MODE_INTERNAL_CHARGE_CONTROLLER BIT(0) -#define MODE_PRIMARY_BATTERY_SUPPORT BIT(1) -#define MODE_CONDITION_CYCLE BIT(7) -#define MODE_CHARGE_CONTROLLER_ENABLED BIT(8) -#define MODE_PRIMARY_BATTERY BIT(9) -#define MODE_ALARM BIT(13) -#define MODE_CHARGER BIT(14) -#define MODE_CAPACITY BIT(15) +#define MODE_PRIMARY_BATTERY_SUPPORT BIT(1) +#define MODE_CONDITION_CYCLE BIT(7) +#define MODE_CHARGE_CONTROLLER_ENABLED BIT(8) +#define MODE_PRIMARY_BATTERY BIT(9) +#define MODE_ALARM BIT(13) +#define MODE_CHARGER BIT(14) +#define MODE_CAPACITY BIT(15) /* Battery status */ -#define STATUS_ERR_CODE_MASK 0xf -#define STATUS_CODE_OK 0 -#define STATUS_CODE_BUSY 1 -#define STATUS_CODE_RESERVED 2 -#define STATUS_CODE_UNSUPPORTED 3 -#define STATUS_CODE_ACCESS_DENIED 4 -#define STATUS_CODE_OVERUNDERFLOW 5 -#define STATUS_CODE_BADSIZE 6 -#define STATUS_CODE_UNKNOWN_ERROR 7 -#define STATUS_FULLY_DISCHARGED BIT(4) -#define STATUS_FULLY_CHARGED BIT(5) -#define STATUS_DISCHARGING BIT(6) -#define STATUS_INITIALIZED BIT(7) -#define STATUS_REMAINING_TIME_ALARM BIT(8) +#define STATUS_ERR_CODE_MASK 0xf +#define STATUS_CODE_OK 0 +#define STATUS_CODE_BUSY 1 +#define STATUS_CODE_RESERVED 2 +#define STATUS_CODE_UNSUPPORTED 3 +#define STATUS_CODE_ACCESS_DENIED 4 +#define STATUS_CODE_OVERUNDERFLOW 5 +#define STATUS_CODE_BADSIZE 6 +#define STATUS_CODE_UNKNOWN_ERROR 7 +#define STATUS_FULLY_DISCHARGED BIT(4) +#define STATUS_FULLY_CHARGED BIT(5) +#define STATUS_DISCHARGING BIT(6) +#define STATUS_INITIALIZED BIT(7) +#define STATUS_REMAINING_TIME_ALARM BIT(8) #define STATUS_REMAINING_CAPACITY_ALARM BIT(9) #define STATUS_TERMINATE_DISCHARGE_ALARM BIT(11) -#define STATUS_OVERTEMP_ALARM BIT(12) -#define STATUS_TERMINATE_CHARGE_ALARM BIT(14) -#define STATUS_OVERCHARGED_ALARM BIT(15) +#define STATUS_OVERTEMP_ALARM BIT(12) +#define STATUS_TERMINATE_CHARGE_ALARM BIT(14) +#define STATUS_OVERCHARGED_ALARM BIT(15) /* Battery Spec Info */ -#define BATTERY_SPEC_REVISION_MASK 0x000F -#define BATTERY_SPEC_REVISION_SHIFT 0 -#define BATTERY_SPEC_VERSION_MASK 0x00F0 -#define BATTERY_SPEC_VERSION_SHIFT 4 -#define BATTERY_SPEC_VSCALE_MASK 0x0F00 -#define BATTERY_SPEC_VSCALE_SHIFT 8 -#define BATTERY_SPEC_IPSCALE_MASK 0xF000 -#define BATTERY_SPEC_IPSCALE_SHIFT 12 - -#define BATTERY_SPEC_VERSION(INFO) ((INFO & BATTERY_SPEC_VERSION_MASK) >> \ - BATTERY_SPEC_VERSION_SHIFT) +#define BATTERY_SPEC_REVISION_MASK 0x000F +#define BATTERY_SPEC_REVISION_SHIFT 0 +#define BATTERY_SPEC_VERSION_MASK 0x00F0 +#define BATTERY_SPEC_VERSION_SHIFT 4 +#define BATTERY_SPEC_VSCALE_MASK 0x0F00 +#define BATTERY_SPEC_VSCALE_SHIFT 8 +#define BATTERY_SPEC_IPSCALE_MASK 0xF000 +#define BATTERY_SPEC_IPSCALE_SHIFT 12 + +#define BATTERY_SPEC_VERSION(INFO) \ + ((INFO & BATTERY_SPEC_VERSION_MASK) >> BATTERY_SPEC_VERSION_SHIFT) /* Smart battery version info */ -#define BATTERY_SPEC_VER_1_0 1 -#define BATTERY_SPEC_VER_1_1 2 -#define BATTERY_SPEC_VER_1_1_WITH_PEC 3 +#define BATTERY_SPEC_VER_1_0 1 +#define BATTERY_SPEC_VER_1_1 2 +#define BATTERY_SPEC_VER_1_1_WITH_PEC 3 /* Smart battery revision info */ -#define BATTERY_SPEC_REVISION_1 1 +#define BATTERY_SPEC_REVISION_1 1 /* Charger alarm warning */ -#define ALARM_OVER_CHARGED 0x8000 -#define ALARM_TERMINATE_CHARGE 0x4000 -#define ALARM_RESERVED_2000 0x2000 -#define ALARM_OVER_TEMP 0x1000 -#define ALARM_TERMINATE_DISCHARGE 0x0800 -#define ALARM_RESERVED_0400 0x0400 -#define ALARM_REMAINING_CAPACITY 0x0200 -#define ALARM_REMAINING_TIME 0x0100 -#define ALARM_STATUS_INITIALIZE 0x0080 -#define ALARM_STATUS_DISCHARGING 0x0040 -#define ALARM_STATUS_FULLY_CHARGED 0x0020 -#define ALARM_STATUS_FULLY_DISCHARGED 0x0010 +#define ALARM_OVER_CHARGED 0x8000 +#define ALARM_TERMINATE_CHARGE 0x4000 +#define ALARM_RESERVED_2000 0x2000 +#define ALARM_OVER_TEMP 0x1000 +#define ALARM_TERMINATE_DISCHARGE 0x0800 +#define ALARM_RESERVED_0400 0x0400 +#define ALARM_REMAINING_CAPACITY 0x0200 +#define ALARM_REMAINING_TIME 0x0100 +#define ALARM_STATUS_INITIALIZE 0x0080 +#define ALARM_STATUS_DISCHARGING 0x0040 +#define ALARM_STATUS_FULLY_CHARGED 0x0020 +#define ALARM_STATUS_FULLY_DISCHARGED 0x0010 /* Charge mode */ -#define CHARGE_FLAG_INHIBIT_CHARGE BIT(0) -#define CHARGE_FLAG_ENABLE_POLLING BIT(1) -#define CHARGE_FLAG_POR_RESET BIT(2) -#define CHARGE_FLAG_RESET_TO_ZERO BIT(3) +#define CHARGE_FLAG_INHIBIT_CHARGE BIT(0) +#define CHARGE_FLAG_ENABLE_POLLING BIT(1) +#define CHARGE_FLAG_POR_RESET BIT(2) +#define CHARGE_FLAG_RESET_TO_ZERO BIT(3) /* Charger status */ -#define CHARGER_CHARGE_INHIBITED BIT(0) -#define CHARGER_POLLING_ENABLED BIT(1) -#define CHARGER_VOLTAGE_NOTREG BIT(2) -#define CHARGER_CURRENT_NOTREG BIT(3) -#define CHARGER_LEVEL_2 BIT(4) -#define CHARGER_LEVEL_3 BIT(5) -#define CHARGER_CURRENT_OR BIT(6) -#define CHARGER_VOLTAGE_OR BIT(7) -#define CHARGER_RES_OR BIT(8) -#define CHARGER_RES_COLD BIT(9) -#define CHARGER_RES_HOT BIT(10) -#define CHARGER_RES_UR BIT(11) -#define CHARGER_ALARM_INHIBITED BIT(12) -#define CHARGER_POWER_FAIL BIT(13) -#define CHARGER_BATTERY_PRESENT BIT(14) -#define CHARGER_AC_PRESENT BIT(15) +#define CHARGER_CHARGE_INHIBITED BIT(0) +#define CHARGER_POLLING_ENABLED BIT(1) +#define CHARGER_VOLTAGE_NOTREG BIT(2) +#define CHARGER_CURRENT_NOTREG BIT(3) +#define CHARGER_LEVEL_2 BIT(4) +#define CHARGER_LEVEL_3 BIT(5) +#define CHARGER_CURRENT_OR BIT(6) +#define CHARGER_VOLTAGE_OR BIT(7) +#define CHARGER_RES_OR BIT(8) +#define CHARGER_RES_COLD BIT(9) +#define CHARGER_RES_HOT BIT(10) +#define CHARGER_RES_UR BIT(11) +#define CHARGER_ALARM_INHIBITED BIT(12) +#define CHARGER_POWER_FAIL BIT(13) +#define CHARGER_BATTERY_PRESENT BIT(14) +#define CHARGER_AC_PRESENT BIT(15) +#define CHARGER_BYPASS_MODE BIT(16) /* Charger specification info */ -#define INFO_CHARGER_SPEC(INFO) ((INFO) & 0xf) -#define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1) +#define INFO_CHARGER_SPEC(INFO) ((INFO)&0xf) +#define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1) /* Manufacturer Access parameters */ -#define PARAM_SAFETY_STATUS 0x51 -#define PARAM_OPERATION_STATUS 0x54 -#define PARAM_FIRMWARE_RUNTIME 0x62 +#define PARAM_SAFETY_STATUS 0x51 +#define PARAM_OPERATION_STATUS 0x54 +#define PARAM_FIRMWARE_RUNTIME 0x62 /* Operation status masks -- 6 byte reply */ /* reply[3] */ -#define BATTERY_DISCHARGING_DISABLED 0x20 -#define BATTERY_CHARGING_DISABLED 0x40 +#define BATTERY_DISCHARGING_DISABLED 0x20 +#define BATTERY_CHARGING_DISABLED 0x40 /* Battery manufacture date */ -#define MANUFACTURE_DATE_DAY_MASK 0x001F -#define MANUFACTURE_DATE_DAY_SHIFT 0 -#define MANUFACTURE_DATE_MONTH_MASK 0x01E0 -#define MANUFACTURE_DATE_MONTH_SHIFT 5 -#define MANUFACTURE_DATE_YEAR_MASK 0xFE00 -#define MANUFACTURE_DATE_YEAR_SHIFT 9 -#define MANUFACTURE_DATE_YEAR_OFFSET 1980 -#define MANUFACTURE_RUNTIME_SIZE 4 +#define MANUFACTURE_DATE_DAY_MASK 0x001F +#define MANUFACTURE_DATE_DAY_SHIFT 0 +#define MANUFACTURE_DATE_MONTH_MASK 0x01E0 +#define MANUFACTURE_DATE_MONTH_SHIFT 5 +#define MANUFACTURE_DATE_YEAR_MASK 0xFE00 +#define MANUFACTURE_DATE_YEAR_SHIFT 9 +#define MANUFACTURE_DATE_YEAR_OFFSET 1980 +#define MANUFACTURE_RUNTIME_SIZE 4 /* Read from battery */ int sb_read(int cmd, int *param); diff --git a/include/bluetooth_le.h b/include/bluetooth_le.h index 286653dda6..e65b3d448b 100644 --- a/include/bluetooth_le.h +++ b/include/bluetooth_le.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,69 +23,67 @@ #include "common.h" #include "util.h" -#define BLUETOOTH_ADDR_OCTETS 6 +#define BLUETOOTH_ADDR_OCTETS 6 /* * GAP assigned numbers * https://www.bluetooth.org/en-us/specification/ * assigned-numbers/generic-access-profile */ -#define GAP_FLAGS 0x01 -#define GAP_INCOMP_16_BIT_UUID 0x02 -#define GAP_COMP_16_BIT_UUID 0x03 -#define GAP_INCOMP_32_BIT_UUID 0x04 -#define GAP_COMP_32_BIT_UUID 0x05 -#define GAP_INCOMP_128_BIT_UUID 0x06 -#define GAP_COMP_128_BIT_UUID 0x07 -#define GAP_SHORT_NAME 0x08 -#define GAP_COMPLETE_NAME 0x09 -#define GAP_TX_POWER_LEVEL 0x0A -#define GAP_CLASS_OF_DEVICE 0x0D -#define GAP_SIMPLE_PAIRING_HASH 0x0E -#define GAP_SIMPLE_PAIRING_HASH_192 0x0E -#define GAP_SIMPLE_PAIRING_RAND 0x0F -#define GAP_SIMPLE_PAIRING_RAND_192 0x0F -#define GAP_DEVICE_ID 0x10 -#define GAP_SECURITY_MANAGER_TK 0x10 -#define GAP_SECURITY_MANAGER_OOB_FLAGS 0x11 -#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 -#define GAP_SERVICE_SOLICITATION_UUID_16 0x14 -#define GAP_SERVICE_SOLICITATION_UUID_32 0x1F -#define GAP_SERVICE_SOLICITATION_UUID_128 0x15 -#define GAP_SERVICE_DATA 0x16 -#define GAP_SERVICE_DATA_UUID_16 0x16 -#define GAP_SERVICE_DATA_UUID_32 0x20 -#define GAP_SERVICE_DATA_UUID_128 0x21 -#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION 0x22 -#define GAP_LE_SECURE_CONNECTIONS_RAND 0x23 -#define GAP_PUBLIC_TARGET_ADDRESS 0x17 -#define GAP_RANDOM_TARGET_ADDRESS 0x18 -#define GAP_APPEARANCE 0x19 -#define GAP_ADVERTISING_INTERVAL 0x1A -#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B -#define GAP_LE_ROLE 0x1C -#define GAP_SIMPLE_PAIRING_HASH_256 0x1D -#define GAP_SIMPLE_PAIRING_RAND_256 0x1E -#define GAP_3D_INFORMATION_DATA 0x3D -#define GAP_MANUFACTURER_SPECIFIC_DATA 0xFF - +#define GAP_FLAGS 0x01 +#define GAP_INCOMP_16_BIT_UUID 0x02 +#define GAP_COMP_16_BIT_UUID 0x03 +#define GAP_INCOMP_32_BIT_UUID 0x04 +#define GAP_COMP_32_BIT_UUID 0x05 +#define GAP_INCOMP_128_BIT_UUID 0x06 +#define GAP_COMP_128_BIT_UUID 0x07 +#define GAP_SHORT_NAME 0x08 +#define GAP_COMPLETE_NAME 0x09 +#define GAP_TX_POWER_LEVEL 0x0A +#define GAP_CLASS_OF_DEVICE 0x0D +#define GAP_SIMPLE_PAIRING_HASH 0x0E +#define GAP_SIMPLE_PAIRING_HASH_192 0x0E +#define GAP_SIMPLE_PAIRING_RAND 0x0F +#define GAP_SIMPLE_PAIRING_RAND_192 0x0F +#define GAP_DEVICE_ID 0x10 +#define GAP_SECURITY_MANAGER_TK 0x10 +#define GAP_SECURITY_MANAGER_OOB_FLAGS 0x11 +#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 +#define GAP_SERVICE_SOLICITATION_UUID_16 0x14 +#define GAP_SERVICE_SOLICITATION_UUID_32 0x1F +#define GAP_SERVICE_SOLICITATION_UUID_128 0x15 +#define GAP_SERVICE_DATA 0x16 +#define GAP_SERVICE_DATA_UUID_16 0x16 +#define GAP_SERVICE_DATA_UUID_32 0x20 +#define GAP_SERVICE_DATA_UUID_128 0x21 +#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION 0x22 +#define GAP_LE_SECURE_CONNECTIONS_RAND 0x23 +#define GAP_PUBLIC_TARGET_ADDRESS 0x17 +#define GAP_RANDOM_TARGET_ADDRESS 0x18 +#define GAP_APPEARANCE 0x19 +#define GAP_ADVERTISING_INTERVAL 0x1A +#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B +#define GAP_LE_ROLE 0x1C +#define GAP_SIMPLE_PAIRING_HASH_256 0x1D +#define GAP_SIMPLE_PAIRING_RAND_256 0x1E +#define GAP_3D_INFORMATION_DATA 0x3D +#define GAP_MANUFACTURER_SPECIFIC_DATA 0xFF /* org.bluetooth.characteristic.gap.appearance.xml */ -#define GAP_APPEARANCE_HID_KEYBOARD 961 +#define GAP_APPEARANCE_HID_KEYBOARD 961 /* org.bluetooth.service.human_interface_device.xml */ -#define GATT_SERVICE_HID_UUID 0x1812 +#define GATT_SERVICE_HID_UUID 0x1812 /* Bluetooth Core Supplement v5 */ /* Bluetooth Core Supplement v5 1.3 */ -#define GAP_FLAGS_LE_LIM_DISC 0x01 -#define GAP_FLAGS_LE_GEN_DISC 0x02 -#define GAP_FLAGS_LE_NO_BR_EDR 0x04 +#define GAP_FLAGS_LE_LIM_DISC 0x01 +#define GAP_FLAGS_LE_GEN_DISC 0x02 +#define GAP_FLAGS_LE_NO_BR_EDR 0x04 /* Bluetooth Core Supplement v5 1.3 */ - /* BLE 4.1 Vol 6 section 2.3 pg 38+ */ /* Advertising PDU Header @@ -103,49 +101,48 @@ struct ble_adv_header { uint8_t length; }; -#define BLE_ADV_HEADER_PDU_TYPE_SHIFT 0 -#define BLE_ADV_HEADER_TXADD_SHIFT 6 -#define BLE_ADV_HEADER_RXADD_SHIFT 7 -#define BLE_ADV_HEADER_LENGTH_SHIFT 8 +#define BLE_ADV_HEADER_PDU_TYPE_SHIFT 0 +#define BLE_ADV_HEADER_TXADD_SHIFT 6 +#define BLE_ADV_HEADER_RXADD_SHIFT 7 +#define BLE_ADV_HEADER_LENGTH_SHIFT 8 -#define BLE_ADV_HEADER(type, tx, rx, length) \ - ((uint16_t) \ - ((((length) & 0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \ - (((rx) & 0x1) << BLE_ADV_HEADER_RXADD_SHIFT) | \ - (((tx) & 0x1) << BLE_ADV_HEADER_TXADD_SHIFT) | \ - (((type) & 0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT))) +#define BLE_ADV_HEADER(type, tx, rx, length) \ + ((uint16_t)((((length)&0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \ + (((rx)&0x1) << BLE_ADV_HEADER_RXADD_SHIFT) | \ + (((tx)&0x1) << BLE_ADV_HEADER_TXADD_SHIFT) | \ + (((type)&0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT))) -#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND 0 -#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND 1 +#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND 0 +#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND 1 #define BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND 2 -#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ 3 -#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP 4 -#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ 5 -#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND 6 +#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ 3 +#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP 4 +#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ 5 +#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND 6 -#define BLE_ADV_HEADER_PUBLIC_ADDR 0 -#define BLE_ADV_HEADER_RANDOM_ADDR 1 +#define BLE_ADV_HEADER_PUBLIC_ADDR 0 +#define BLE_ADV_HEADER_RANDOM_ADDR 1 /* BLE 4.1 Vol 3 Part C 10.8 */ -#define BLE_RANDOM_ADDR_MSBS_PRIVATE 0x00 -#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE 0x40 -#define BLE_RANDOM_ADDR_MSBS_RFU 0x80 -#define BLE_RANDOM_ADDR_MSBS_STATIC 0xC0 +#define BLE_RANDOM_ADDR_MSBS_PRIVATE 0x00 +#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE 0x40 +#define BLE_RANDOM_ADDR_MSBS_RFU 0x80 +#define BLE_RANDOM_ADDR_MSBS_STATIC 0xC0 #define BLE_ADV_ACCESS_ADDRESS 0x8E89BED6 #define BLE_ADV_CRCINIT 0x555555 -#define BLE_MAX_ADV_PAYLOAD_OCTETS 37 +#define BLE_MAX_ADV_PAYLOAD_OCTETS 37 /* LL SCA Values. They are shifted left 5 bits for Hop values */ -#define BLE_LL_SCA_251_PPM_TO_500_PPM (0 << 5) -#define BLE_LL_SCA_151_PPM_TO_250_PPM BIT(5) -#define BLE_LL_SCA_101_PPM_TO_150_PPM (2 << 5) -#define BLE_LL_SCA_076_PPM_TO_100_PPM (3 << 5) -#define BLE_LL_SCA_051_PPM_TO_075_PPM (4 << 5) -#define BLE_LL_SCA_031_PPM_TO_050_PPM (5 << 5) -#define BLE_LL_SCA_021_PPM_TO_030_PPM (6 << 5) -#define BLE_LL_SCA_000_PPM_TO_020_PPM (7 << 5) +#define BLE_LL_SCA_251_PPM_TO_500_PPM (0 << 5) +#define BLE_LL_SCA_151_PPM_TO_250_PPM BIT(5) +#define BLE_LL_SCA_101_PPM_TO_150_PPM (2 << 5) +#define BLE_LL_SCA_076_PPM_TO_100_PPM (3 << 5) +#define BLE_LL_SCA_051_PPM_TO_075_PPM (4 << 5) +#define BLE_LL_SCA_031_PPM_TO_050_PPM (5 << 5) +#define BLE_LL_SCA_021_PPM_TO_030_PPM (6 << 5) +#define BLE_LL_SCA_000_PPM_TO_020_PPM (7 << 5) /* BLE 4.1 Vol 6 section 2.4 pg 45 */ @@ -169,26 +166,25 @@ struct ble_data_header { uint8_t length; }; -#define BLE_DATA_HEADER_LLID_SHIFT 0 -#define BLE_DATA_HEADER_NESN_SHIFT 2 -#define BLE_DATA_HEADER_SN_SHIFT 3 -#define BLE_DATA_HEADER_MD_SHIFT 4 -#define BLE_DATA_HEADER_LENGTH_SHIFT 8 +#define BLE_DATA_HEADER_LLID_SHIFT 0 +#define BLE_DATA_HEADER_NESN_SHIFT 2 +#define BLE_DATA_HEADER_SN_SHIFT 3 +#define BLE_DATA_HEADER_MD_SHIFT 4 +#define BLE_DATA_HEADER_LENGTH_SHIFT 8 #define BLE_DATA_HEADER_LLID_DATANOSTART 1 -#define BLE_DATA_HEADER_LLID_DATASTART 2 -#define BLE_DATA_HEADER_LLID_CONTROL 3 +#define BLE_DATA_HEADER_LLID_DATASTART 2 +#define BLE_DATA_HEADER_LLID_CONTROL 3 -#define BLE_DATA_HEADER(llid, nesn, sn, md, length) \ - ((uint16_t) \ - ((((length) & 0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \ - (((MD) & 0x1) << BLE_DATA_HEADER_MD_SHIFT) | \ - (((SN) & 0x1) << BLE_DATA_HEADER_SN_SHIFT) | \ - (((NESN) & 0x1) << BLE_DATA_HEADER_NESN_SHIFT) | \ - (((llid) & 0x3) << BLE_DATA_HEADER_LLID_SHIFT))) +#define BLE_DATA_HEADER(llid, nesn, sn, md, length) \ + ((uint16_t)((((length)&0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \ + (((MD)&0x1) << BLE_DATA_HEADER_MD_SHIFT) | \ + (((SN)&0x1) << BLE_DATA_HEADER_SN_SHIFT) | \ + (((NESN)&0x1) << BLE_DATA_HEADER_NESN_SHIFT) | \ + (((llid)&0x3) << BLE_DATA_HEADER_LLID_SHIFT))) -#define BLE_MAX_DATA_PAYLOAD_OCTETS 31 -#define BLE_MAX_PAYLOAD_OCTETS BLE_MAX_ADV_PAYLOAD_OCTETS +#define BLE_MAX_DATA_PAYLOAD_OCTETS 31 +#define BLE_MAX_PAYLOAD_OCTETS BLE_MAX_ADV_PAYLOAD_OCTETS union ble_header { struct ble_adv_header adv; @@ -210,34 +206,34 @@ struct ble_packet { }; /* LL Control PDU Opcodes BLE 4.1 Vol 6 2.4.2 */ -#define BLE_LL_CONNECTION_UPDATE_REQ 0x00 -#define BLE_LL_CHANNEL_MAP_REQ 0x01 -#define BLE_LL_TERMINATE_IND 0x02 -#define BLE_LL_ENC_REQ 0x03 -#define BLE_LL_ENC_RSP 0x04 -#define BLE_LL_START_ENC_REQ 0x05 -#define BLE_LL_START_ENC_RSP 0x06 -#define BLE_LL_UNKNOWN_RSP 0x07 -#define BLE_LL_FEATURE_REQ 0x08 -#define BLE_LL_FEATURE_RSP 0x09 -#define BLE_LL_PAUSE_ENC_REQ 0x0A -#define BLE_LL_PAUSE_ENC_RSP 0x0B -#define BLE_LL_VERSION_IND 0x0C -#define BLE_LL_REJECT_IND 0x0D -#define BLE_LL_SLAVE_FEATURE_REQ 0x0E -#define BLE_LL_CONNECTION_PARAM_REQ 0x0F -#define BLE_LL_CONNECTION_PARAM_RSP 0x10 -#define BLE_LL_REJECT_IND_EXT 0x11 -#define BLE_LL_PING_REQ 0x12 -#define BLE_LL_PING_RSP 0x13 -#define BLE_LL_RFU 0x14 +#define BLE_LL_CONNECTION_UPDATE_REQ 0x00 +#define BLE_LL_CHANNEL_MAP_REQ 0x01 +#define BLE_LL_TERMINATE_IND 0x02 +#define BLE_LL_ENC_REQ 0x03 +#define BLE_LL_ENC_RSP 0x04 +#define BLE_LL_START_ENC_REQ 0x05 +#define BLE_LL_START_ENC_RSP 0x06 +#define BLE_LL_UNKNOWN_RSP 0x07 +#define BLE_LL_FEATURE_REQ 0x08 +#define BLE_LL_FEATURE_RSP 0x09 +#define BLE_LL_PAUSE_ENC_REQ 0x0A +#define BLE_LL_PAUSE_ENC_RSP 0x0B +#define BLE_LL_VERSION_IND 0x0C +#define BLE_LL_REJECT_IND 0x0D +#define BLE_LL_SLAVE_FEATURE_REQ 0x0E +#define BLE_LL_CONNECTION_PARAM_REQ 0x0F +#define BLE_LL_CONNECTION_PARAM_RSP 0x10 +#define BLE_LL_REJECT_IND_EXT 0x11 +#define BLE_LL_PING_REQ 0x12 +#define BLE_LL_PING_RSP 0x13 +#define BLE_LL_RFU 0x14 /* BLE 4.1 Vol 6 4.6 Table 4.3 */ -#define BLE_LL_FEATURE_LE_ENCRYPTION 0x00 -#define BLE_LL_FEATURE_CONN_PARAMS_REQ 0x01 -#define BLE_LL_FEATURE_EXT_REJ_IND 0x02 -#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG 0x03 -#define BLE_LL_FEATURE_LE_PING 0x04 +#define BLE_LL_FEATURE_LE_ENCRYPTION 0x00 +#define BLE_LL_FEATURE_CONN_PARAMS_REQ 0x01 +#define BLE_LL_FEATURE_EXT_REJ_IND 0x02 +#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG 0x03 +#define BLE_LL_FEATURE_LE_PING 0x04 struct ble_ll_connection_update_req { uint8_t win_size; @@ -285,8 +281,8 @@ struct ble_ll_feature_rsp { /* ble_ll_pause_enc_rsp has no CtrData field */ -#define BLE_LL_VERS_NR_4_0 6 -#define BLE_LL_VERS_NR_4_1 7 +#define BLE_LL_VERS_NR_4_0 6 +#define BLE_LL_VERS_NR_4_1 7 struct ble_ll_version_ind { uint8_t vers_nr; /* Version Number */ @@ -348,7 +344,7 @@ int chan2freq(int channel); /* BLE 4.1 Vol 6 2.3.3.1 */ void fill_remapping_table(struct remapping_table *rt, uint8_t map[5], - int hop_increment); + int hop_increment); void ble_tx(struct ble_pdu *pdu); @@ -376,7 +372,7 @@ uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data); uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr); const uint8_t *unpack_adv(const uint8_t *src, int *length, int *type, - const uint8_t **data); + const uint8_t **data); void dump_ble_addr(uint8_t *mem, char *name); diff --git a/include/bluetooth_le_ll.h b/include/bluetooth_le_ll.h index 9f540102da..d17aec8a57 100644 --- a/include/bluetooth_le_ll.h +++ b/include/bluetooth_le_ll.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,33 +17,30 @@ enum ll_state_t { TEST_TX, }; -#define LL_ADV_INTERVAL_UNIT_US 625 -#define LL_ADV_TIMEOUT_UNIT_US 1000000 +#define LL_ADV_INTERVAL_UNIT_US 625 +#define LL_ADV_TIMEOUT_UNIT_US 1000000 -#define LL_ADV_DIRECT_INTERVAL_US 3750 /* 3.75 ms */ -#define LL_ADV_DIRECT_TIMEOUT_US 1280000 /* 1.28 s */ +#define LL_ADV_DIRECT_INTERVAL_US 3750 /* 3.75 ms */ +#define LL_ADV_DIRECT_TIMEOUT_US 1280000 /* 1.28 s */ -#define LL_MAX_DATA_PACKET_LENGTH 27 -#define LL_MAX_DATA_PACKETS 4 +#define LL_MAX_DATA_PACKET_LENGTH 27 +#define LL_MAX_DATA_PACKETS 4 /* BTLE Spec 4.0: Vol 6, Part B, Section 4.5.3 */ -#define TRANSMIT_WINDOW_OFFSET_CONSTANT 1250 +#define TRANSMIT_WINDOW_OFFSET_CONSTANT 1250 -#define LL_MAX_BUFFER_SIZE (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS) +#define LL_MAX_BUFFER_SIZE (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS) -#define LL_SUPPORTED_FEATURES (HCI_LE_FTR_ENCRYPTION | \ - HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \ - HCI_LE_FTR_EXTENDED_REJECT_INDICATION | \ - HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE) +#define LL_SUPPORTED_FEATURES \ + (HCI_LE_FTR_ENCRYPTION | HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \ + HCI_LE_FTR_EXTENDED_REJECT_INDICATION | \ + HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE) -#define LL_SUPPORTED_STATES (HCI_LE_STATE_NONCON_ADV | \ - HCI_LE_STATE_SCANNABLE_ADV | \ - HCI_LE_STATE_CONNECTABLE_ADV | \ - HCI_LE_STATE_DIRECT_ADV | \ - HCI_LE_STATE_PASSIVE_SCAN | \ - HCI_LE_STATE_ACTIVE_SCAN | \ - HCI_LE_STATE_INITIATE | \ - HCI_LE_STATE_SLAVE) +#define LL_SUPPORTED_STATES \ + (HCI_LE_STATE_NONCON_ADV | HCI_LE_STATE_SCANNABLE_ADV | \ + HCI_LE_STATE_CONNECTABLE_ADV | HCI_LE_STATE_DIRECT_ADV | \ + HCI_LE_STATE_PASSIVE_SCAN | HCI_LE_STATE_ACTIVE_SCAN | \ + HCI_LE_STATE_INITIATE | HCI_LE_STATE_SLAVE) /* * 4.6.1 LE Encryption @@ -60,64 +57,63 @@ enum ll_state_t { */ /*Link Layer Control PDU Opcodes */ -#define LL_CONNECTION_UPDATE_REQ 0x00 -#define LL_CHANNEL_MAP_REQ 0x01 -#define LL_TERMINATE_IND 0x02 -#define LL_ENC_REQ 0x03 -#define LL_ENC_RSP 0x04 -#define LL_START_ENC_REQ 0x05 -#define LL_START_ENC_RSP 0x06 -#define LL_UNKNOWN_RSP 0x07 -#define LL_FEATURE_REQ 0x08 -#define LL_FEATURE_RSP 0x09 -#define LL_PAUSE_ENC_REQ 0x0A -#define LL_PAUSE_ENC_RSP 0x0B -#define LL_VERSION_IND 0x0C -#define LL_REJECT_IND 0x0D -#define LL_SLAVE_FEATURE_REQ 0x0E -#define LL_CONNECTION_PARAM_REQ 0x0F -#define LL_CONNECTION_PARAM_RSP 0x10 -#define LL_REJECT_IND_EXT 0x11 -#define LL_PING_REQ 0x12 -#define LL_PING_RSP 0x13 +#define LL_CONNECTION_UPDATE_REQ 0x00 +#define LL_CHANNEL_MAP_REQ 0x01 +#define LL_TERMINATE_IND 0x02 +#define LL_ENC_REQ 0x03 +#define LL_ENC_RSP 0x04 +#define LL_START_ENC_REQ 0x05 +#define LL_START_ENC_RSP 0x06 +#define LL_UNKNOWN_RSP 0x07 +#define LL_FEATURE_REQ 0x08 +#define LL_FEATURE_RSP 0x09 +#define LL_PAUSE_ENC_REQ 0x0A +#define LL_PAUSE_ENC_RSP 0x0B +#define LL_VERSION_IND 0x0C +#define LL_REJECT_IND 0x0D +#define LL_SLAVE_FEATURE_REQ 0x0E +#define LL_CONNECTION_PARAM_REQ 0x0F +#define LL_CONNECTION_PARAM_RSP 0x10 +#define LL_REJECT_IND_EXT 0x11 +#define LL_PING_REQ 0x12 +#define LL_PING_RSP 0x13 /* BLE 4.1 Vol 6 2.3.3.1 Connection information */ -#define CONNECT_REQ_INITA_LEN 6 -#define CONNECT_REQ_ADVA_LEN 6 -#define CONNECT_REQ_ACCESS_ADDR_LEN 4 -#define CONNECT_REQ_CRC_INIT_VAL_LEN 3 -#define CONNECT_REQ_WIN_SIZE_LEN 1 -#define CONNECT_REQ_WIN_OFFSET_LEN 2 -#define CONNECT_REQ_INTERVAL_LEN 2 -#define CONNECT_REQ_LATENCY_LEN 2 -#define CONNECT_REQ_TIMEOUT_LEN 2 -#define CONNECT_REQ_CHANNEL_MAP_LEN 5 -#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN 1 +#define CONNECT_REQ_INITA_LEN 6 +#define CONNECT_REQ_ADVA_LEN 6 +#define CONNECT_REQ_ACCESS_ADDR_LEN 4 +#define CONNECT_REQ_CRC_INIT_VAL_LEN 3 +#define CONNECT_REQ_WIN_SIZE_LEN 1 +#define CONNECT_REQ_WIN_OFFSET_LEN 2 +#define CONNECT_REQ_INTERVAL_LEN 2 +#define CONNECT_REQ_LATENCY_LEN 2 +#define CONNECT_REQ_TIMEOUT_LEN 2 +#define CONNECT_REQ_CHANNEL_MAP_LEN 5 +#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN 1 struct ble_connection_params { - uint8_t init_a[CONNECT_REQ_INITA_LEN]; - uint8_t adv_a[CONNECT_REQ_ADVA_LEN]; - uint32_t access_addr; - uint32_t crc_init_val; - uint8_t win_size; - uint16_t win_offset; - uint16_t interval; - uint16_t latency; - uint16_t timeout; - uint64_t channel_map; - uint8_t hop_increment; - uint8_t sleep_clock_accuracy; - uint32_t transmitWindowOffset; - uint32_t transmitWindowSize; - uint32_t connInterval; - uint16_t connLatency; - uint32_t connSupervisionTimeout; + uint8_t init_a[CONNECT_REQ_INITA_LEN]; + uint8_t adv_a[CONNECT_REQ_ADVA_LEN]; + uint32_t access_addr; + uint32_t crc_init_val; + uint8_t win_size; + uint16_t win_offset; + uint16_t interval; + uint16_t latency; + uint16_t timeout; + uint64_t channel_map; + uint8_t hop_increment; + uint8_t sleep_clock_accuracy; + uint32_t transmitWindowOffset; + uint32_t transmitWindowSize; + uint32_t connInterval; + uint16_t connLatency; + uint32_t connSupervisionTimeout; }; uint8_t ll_reset(void); uint8_t ll_set_tx_power(uint8_t *params); - /* LE Information */ uint8_t ll_read_buffer_size(uint8_t *return_params); uint8_t ll_read_local_supported_features(uint8_t *return_params); diff --git a/include/board_config.h b/include/board_config.h index 5b21be8236..b20f1fe46c 100644 --- a/include/board_config.h +++ b/include/board_config.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/body_detection.h b/include/body_detection.h index 59af6580c6..8fea5d84e1 100644 --- a/include/body_detection.h +++ b/include/body_detection.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,10 +9,7 @@ #include <stdint.h> #include <stdbool.h> -enum body_detect_states { - BODY_DETECTION_OFF_BODY, - BODY_DETECTION_ON_BODY -}; +enum body_detect_states { BODY_DETECTION_OFF_BODY, BODY_DETECTION_ON_BODY }; /* get/set the state of body detection */ enum body_detect_states body_detect_get_state(void); diff --git a/include/btle_hci2.h b/include/btle_hci2.h index 193df3391b..dc59b72277 100644 --- a/include/btle_hci2.h +++ b/include/btle_hci2.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,40 +14,39 @@ struct hciCmdHdr { uint16_t opcode; uint8_t paramLen; } __packed; -#define CMD_MAKE_OPCODE(ogf, ocf) ((((uint16_t)((ogf) & 0x3f)) << 10) | ((ocf) & 0x03ff)) -#define CMD_GET_OGF(opcode) (((opcode) >> 10) & 0x3f) -#define CMD_GET_OCF(opcode) ((opcode) & 0x03ff) - +#define CMD_MAKE_OPCODE(ogf, ocf) \ + ((((uint16_t)((ogf)&0x3f)) << 10) | ((ocf)&0x03ff)) +#define CMD_GET_OGF(opcode) (((opcode) >> 10) & 0x3f) +#define CMD_GET_OCF(opcode) ((opcode)&0x03ff) struct hciAclHdr { uint16_t hdr; uint16_t len; } __packed; -#define ACL_HDR_MASK_CONN_ID 0x0FFF -#define ACL_HDR_MASK_PB 0x3000 -#define ACL_HDR_MASK_BC 0xC000 -#define ACL_HDR_PB_FIRST_NONAUTO 0x0000 -#define ACL_HDR_PB_CONTINUED 0x1000 -#define ACL_HDR_PB_FIRST_AUTO 0x2000 -#define ACL_HDR_PB_COMPLETE 0x3000 +#define ACL_HDR_MASK_CONN_ID 0x0FFF +#define ACL_HDR_MASK_PB 0x3000 +#define ACL_HDR_MASK_BC 0xC000 +#define ACL_HDR_PB_FIRST_NONAUTO 0x0000 +#define ACL_HDR_PB_CONTINUED 0x1000 +#define ACL_HDR_PB_FIRST_AUTO 0x2000 +#define ACL_HDR_PB_COMPLETE 0x3000 struct hciScoHdr { uint16_t hdr; uint8_t len; } __packed; -#define SCO_HDR_MASK_CONN_ID 0x0FFF -#define SCO_HDR_MASK_STATUS 0x3000 -#define SCO_STATUS_ALL_OK 0x0000 -#define SCO_STATUS_UNKNOWN 0x1000 -#define SCO_STATUS_NO_DATA 0x2000 -#define SCO_STATUS_SOME_DATA 0x3000 +#define SCO_HDR_MASK_CONN_ID 0x0FFF +#define SCO_HDR_MASK_STATUS 0x3000 +#define SCO_STATUS_ALL_OK 0x0000 +#define SCO_STATUS_UNKNOWN 0x1000 +#define SCO_STATUS_NO_DATA 0x2000 +#define SCO_STATUS_SOME_DATA 0x3000 struct hciEvtHdr { uint8_t code; uint8_t len; } __packed; - void hci_cmd(uint8_t *hciCmdbuf); void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len); void hci_acl_from_host(uint8_t *hciAclbuf); diff --git a/include/btle_hci_int.h b/include/btle_hci_int.h index 83fffee69f..ce3fd6ef41 100644 --- a/include/btle_hci_int.h +++ b/include/btle_hci_int.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,377 +8,479 @@ * original author. */ - #ifndef _HCI_INT_H_ #define _HCI_INT_H_ #include "util.h" -#define HCI_DEV_NAME_LEN 248 - -#define HCI_INQUIRY_LENGTH_UNIT 1280 /* msec */ -#define HCI_INQUIRY_LENGTH_MAX 48 /* units */ - -#define HCI_LAP_Unlimited_Inquiry 0x9E8B33 -#define HCI_LAP_Limited_Inquiry 0x9E8B00 - -#define HCI_CLOCK_OFST_VALID 0x8000 - -#define HCI_PKT_TYP_NO_2_DH1 0x0002 /* BT 2.1+ */ -#define HCI_PKT_TYP_NO_3_DH1 0x0004 /* BT 2.1+ */ -#define HCI_PKT_TYP_DM1 0x0008 /* BT 1.1+ */ -#define HCI_PKT_TYP_DH1 0x0010 /* BT 1.1+ */ -#define HCI_PKT_TYP_NO_2_DH3 0x0100 /* BT 2.1+ */ -#define HCI_PKT_TYP_NO_3_DH3 0x0200 /* BT 2.1+ */ -#define HCI_PKT_TYP_DM3 0x0400 /* BT 1.1+ */ -#define HCI_PKT_TYP_DH3 0x0800 /* BT 1.1+ */ -#define HCI_PKT_TYP_NO_2_DH5 0x1000 /* BT 2.1+ */ -#define HCI_PKT_TYP_NO_3_DH5 0x1000 /* BT 2.1+ */ -#define HCI_PKT_TYP_DM5 0x4000 /* BT 1.1+ */ -#define HCI_PKT_TYP_DH5 0x8000 /* BT 1.1+ */ -#define HCI_PKT_TYP_DEFAULT 0xCC18 - -#define HCI_PKT_TYP_SCO_HV1 0x0001 /* BT 1.1+ */ -#define HCI_PKT_TYP_SCO_HV2 0x0002 /* BT 1.1+ */ -#define HCI_PKT_TYP_SCO_HV3 0x0004 /* BT 1.1+ */ -#define HCI_PKT_TYP_SCO_EV3 0x0008 /* BT 1.2+ */ -#define HCI_PKT_TYP_SCO_EV4 0x0010 /* BT 1.2+ */ -#define HCI_PKT_TYP_SCO_EV5 0x0020 /* BT 1.2+ */ -#define HCI_PKT_TYP_SCO_NO_2_EV3 0x0040 /* BT 2.1+ */ -#define HCI_PKT_TYP_SCO_NO_3_EV3 0x0080 /* BT 2.1+ */ -#define HCI_PKT_TYP_SCO_NO_2_EV5 0x0100 /* BT 2.1+ */ -#define HCI_PKT_TYP_SCO_NO_3_EV5 0x0200 /* BT 2.1+ */ - -#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES 0x0000 -#define HCI_LINK_POLICY_ENABLE_ROLESWITCH 0x0001 -#define HCI_LINK_POLICY_ENABLE_HOLD_MODE 0x0002 -#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE 0x0004 -#define HCI_LINK_POLICY_ENABLE_PARK_MODE 0x0008 - -#define HCI_FILTER_TYPE_CLEAR_ALL 0x00 /* no subtypes, no data */ -#define HCI_FILTER_INQUIRY_RESULT 0x01 /* below subtypes */ -#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS 0x00 /* no data */ -#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class) */ -#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR 0x02 /* uint8_t mac[6] */ -#define HCI_FILTER_CONNECTION_SETUP 0x02 /* below subtypes */ -#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS 0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 - yes w/ roleswitch */ -#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class), auto_accept flag same as above */ -#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR 0x02 /* uint8_t mac[6], auto_accept flag same as above */ - -#define HCI_SCAN_ENABLE_INQUIRY 0x01 /* discoverable */ -#define HCI_SCAN_ENABLE_PAGE 0x02 /* connectable */ - -#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN 0x01 -#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN 0x02 -#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES 0x04 - -#define HCI_TO_HOST_FLOW_CTRL_ACL 0x01 -#define HCI_TO_HOST_FLOW_CTRL_SCO 0x02 - -#define HCI_INQ_MODE_STD 0 /* normal mode @ BT 1.1+ */ -#define HCI_INQ_MODE_RSSI 1 /* with RSSI @ BT 1.2+ */ -#define HCI_INQ_MODE_EIR 2 /* with EIR @ BT 2.1+ */ - -#define HCI_SSP_KEY_ENTRY_STARTED 0 -#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED 1 -#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED 2 -#define HCI_SSP_KEY_ENTRY_CLEARED 3 -#define HCI_SSP_KEY_ENTRY_COMPLETED 4 - -#define HCI_LOCATION_DOMAIN_OPTION_NONE 0x20 /* ' ' */ -#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY 0x4F /* 'O' */ -#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY 0x49 /* 'I' */ -#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY 0x58 /* 'X' */ - -#define HCI_PERIOD_TYPE_DOWNLINK 0x00 -#define HCI_PERIOD_TYPE_UPLINK 0x01 -#define HCI_PERIOD_TYPE_BIDIRECTIONAL 0x02 -#define HCI_PERIOD_TYPE_GUARD_PERIOD 0x03 - -#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX 0x00 -#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED 0x01 -#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED 0x02 -#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED 0x03 -#define HCI_MWS_INTERVAL_TYPE_FRAME 0x04 /* type defined by Set External Frame Configuration command */ - -#define HCI_CONNLESS_FRAG_TYPE_CONT 0x00 /* continuation fragment */ -#define HCI_CONNLESS_FRAG_TYPE_START 0x01 /* first fragment */ -#define HCI_CONNLESS_FRAG_TYPE_END 0x02 /* last fragment */ -#define HCI_CONNLESS_FRAG_TYPE_COMPLETE 0x03 /* complete fragment - no fragmentation */ - -#define HCI_CUR_MODE_ACTIVE 0x00 -#define HCI_CUR_MODE_HOLD 0x01 -#define HCI_CUR_MODE_SNIFF 0x02 -#define HCI_CUR_MODE_PARK 0x03 - -#define HCI_SCO_LINK_TYPE_SCO 0x00 -#define HCI_SCO_LINK_TYPE_ESCO 0x02 - -#define HCI_SCO_AIR_MODE_MULAW 0x00 -#define HCI_SCO_AIR_MODE_ALAW 0x01 -#define HCI_SCO_AIR_MODE_CVSD 0x02 -#define HCI_SCO_AIR_MODE_TRANSPARENT 0x03 - -#define HCI_MCA_500_PPM 0x00 -#define HCI_MCA_250_PPM 0x01 -#define HCI_MCA_150_PPM 0x02 -#define HCI_MCA_100_PPM 0x03 -#define HCI_MCA_75_PPM 0x04 -#define HCI_MCA_50_PPM 0x05 -#define HCI_MCA_30_PPM 0x06 -#define HCI_MCA_20_PPM 0x07 - -#define HCI_EDR_LINK_KEY_COMBO 0x00 -#define HCI_EDR_LINK_KEY_LOCAL 0x01 -#define HCI_EDR_LINK_KEY_REMOTE 0x02 -#define HCI_EDR_LINK_KEY_DEBUG 0x03 -#define HCI_EDR_LINK_KEY_UNAUTH_COMBO 0x04 -#define HCI_EDR_LINK_KEY_AUTH_COMBO 0x05 -#define HCI_EDR_LINK_KEY_CHANGED 0x06 - -#define HCI_VERSION_1_0_B 0 /* BT 1.0b */ -#define HCI_VERSION_1_1 1 /* BT 1.1 */ -#define HCI_VERSION_1_2 2 /* BT 1.2 */ -#define HCI_VERSION_2_0 4 /* BT 2.0 */ -#define HCI_VERSION_2_1 3 /* BT 2.1 */ -#define HCI_VERSION_3_0 4 /* BT 3.0 */ -#define HCI_VERSION_4_0 6 /* BT 4.0 */ -#define HCI_VERSION_4_1 7 /* BT 4.1 */ - -#define HCI_LE_STATE_NONCON_ADV 0x0000000000000001ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV 0x0000000000000002ULL /* BT 4.0+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV 0x0000000000000004ULL /* BT 4.0+ */ -#define HCI_LE_STATE_DIRECT_ADV 0x0000000000000008ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN 0x0000000000000010ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN 0x0000000000000020ULL /* BT 4.0+ */ -#define HCI_LE_STATE_INITIATE 0x0000000000000040ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SLAVE 0x0000000000000080ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN 0x0000000000000100ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN 0x0000000000000200ULL /* BT 4.0+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN 0x0000000000000400ULL /* BT 4.0+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN 0x0000000000000800ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN 0x0000000000001000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN 0x0000000000002000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN 0x0000000000004000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN 0x0000000000008000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_INITIATING 0x0000000000010000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING 0x0000000000020000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_MASTER 0x0000000000040000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER 0x0000000000080000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_SLAVE 0x0000000000100000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE 0x0000000000200000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING 0x0000000000400000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING 0x0000000000800000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER 0x0000000001000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER 0x0000000002000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE 0x0000000004000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE 0x0000000008000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_INTIATING_w_MASTER 0x0000000010000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV 0x0000000020000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV 0x0000000040000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV 0x0000000080000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING 0x0000000100000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING 0x0000000200000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING 0x0000000400000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER 0x0000000800000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_MASTER 0x0000001000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER 0x0000002000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE 0x0000004000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE 0x0000008000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE 0x0000010000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_INITIATING_w_SLAVE 0x0000020000000000ULL /* BT 4.1+ */ - -#define HCI_LMP_FTR_3_SLOT_PACKETS 0x0000000000000001ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_5_SLOT_PACKETS 0x0000000000000002ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_ENCRYPTION 0x0000000000000004ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SLOT_OFFSET 0x0000000000000008ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_TIMING_ACCURACY 0x0000000000000010ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SWITCH 0x0000000000000020ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_HOLD_MODE 0x0000000000000040ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SNIFF_MODE 0x0000000000000080ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_PARK_MODE 0x0000000000000100ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_RSSI 0x0000000000000200ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE 0x0000000000000400ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SCO_LINKS 0x0000000000000800ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_HV2_PACKETS 0x0000000000001000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_HV3_PACKETS 0x0000000000002000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_MU_LAW 0x0000000000004000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_A_LAW 0x0000000000008000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_CVSD 0x0000000000010000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_PAGING_SCHEME 0x0000000000020000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_POWER_CONTROL 0x0000000000040000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA 0x0000000000080000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0 0x0000000000100000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1 0x0000000000200000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2 0x0000000000400000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_BROADCAST_ENCRYPTION 0x0000000000800000ULL /* BT 1.2+ */ -#define HCI_LMP_FTR_ACL_2MBPS 0x0000000002000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ACL_3MBPS 0x0000000004000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN 0x0000000008000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN 0x0000000010000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN 0x0000000020000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS 0x0000000040000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EXTENDED_SCO_LINK 0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */ -#define HCI_LMP_FTR_EV4_PACKETS 0x0000000100000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EV5_PACKETS 0x0000000200000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE 0x0000000800000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE 0x0000001000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED 0x0000002000000000ULL /* BT 4.0+ */ -#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER 0x0000004000000000ULL /* BT 4.0+ */ -#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS 0x0000008000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS 0x0000010000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_SNIFF_SUBRATING 0x0000020000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_PAUSE_ENCRYPTION 0x0000040000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CAPABLE_MASTER 0x0000080000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER 0x0000100000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ESCO_2MBPS 0x0000200000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ESCO_3MBPS 0x0000400000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_3_SLOT_ESCO 0x0000800000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE 0x0001000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_SSP 0x0008000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ENCAPSULATED_PDU 0x0010000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING 0x0020000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG 0x0040000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT 0x0100000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL 0x0200000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EXTENDED_FEATURES 0x8000000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL 0x0400000000000000ULL /* BT 3.0+ */ -#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER 0x0002000000000000ULL /* BT 4.0+ */ - -#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT 0x0000000000000001ULL /* BT 2.1+ */ -#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT 0x0000000000000002ULL /* BT 4.0+ */ -#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT 0x0000000000000004ULL /* BT 4.0+ */ -#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT 0x0000000000000008ULL /* BT 4.1+ */ - -#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER 0x0000000000000001ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE 0x0000000000000002ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN 0x0000000000000004ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN 0x0000000000000008ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT 0x0000000000000010ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN 0x0000000000000020ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT 0x0000000000000040ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER 0x0000000000000100ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_PING 0x0000000000000200ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING 0x0000000000000800ULL /* BT 4.1+ */ - -#define HCI_EVENT_INQUIRY_COMPLETE 0x0000000000000001ULL /* BT 1.1+ */ -#define HCI_EVENT_INQUIRY_RESULT 0x0000000000000002ULL /* BT 1.1+ */ -#define HCI_EVENT_CONN_COMPLETE 0x0000000000000004ULL /* BT 1.1+ */ -#define HCI_EVENT_CONN_REQUEST 0x0000000000000008ULL /* BT 1.1+ */ -#define HCI_EVENT_DISCONNECTION_COMPLETE 0x0000000000000010ULL /* BT 1.1+ */ -#define HCI_EVENT_AUTH_COMPLETE 0x0000000000000020ULL /* BT 1.1+ */ -#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE 0x0000000000000040ULL /* BT 1.1+ */ -#define HCI_EVENT_ENCR_CHANGE 0x0000000000000080ULL /* BT 1.1+ */ -#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE 0x0000000000000100ULL /* BT 1.1+ */ -#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0000000000000200ULL /* BT 1.1+ */ -#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE 0x0000000000000400ULL /* BT 1.1+ */ -#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE 0x0000000000000800ULL /* BT 1.1+ */ -#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0000000000001000ULL /* BT 1.1+ */ -#define HCI_EVENT_HARDWARE_ERROR 0x0000000000008000ULL /* BT 1.1+ */ -#define HCI_EVENT_FLUSH_OCCURRED 0x0000000000010000ULL /* BT 1.1+ */ -#define HCI_EVENT_ROLE_CHANGE 0x0000000000020000ULL /* BT 1.1+ */ -#define HCI_EVENT_MODE_CHANGE 0x0000000000080000ULL /* BT 1.1+ */ -#define HCI_EVENT_RETURN_LINK_KEYS 0x0000000000100000ULL /* BT 1.1+ */ -#define HCI_EVENT_PIN_CODE_REQUEST 0x0000000000200000ULL /* BT 1.1+ */ -#define HCI_EVENT_LINK_KEY_REQUEST 0x0000000000400000ULL /* BT 1.1+ */ -#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x0000000000800000ULL /* BT 1.1+ */ -#define HCI_EVENT_LOOPBACK_COMMAND 0x0000000001000000ULL /* BT 1.1+ */ -#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x0000000002000000ULL /* BT 1.1+ */ -#define HCI_EVENT_MAX_SLOTS_CHANGE 0x0000000004000000ULL /* BT 1.1+ */ -#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE 0x0000000008000000ULL /* BT 1.1+ */ -#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED 0x0000000010000000ULL /* BT 1.1+ */ -#define HCI_EVENT_QOS_VIOLATION 0x0000000020000000ULL /* BT 1.1+ */ -#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE 0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */ -#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE 0x0000000080000000ULL /* BT 1.1+ */ -#define HCI_EVENT_ALL_BT_1_1 0x00000000FFFFFFFFULL /* also the default for BT 1.1 */ -#define HCI_EVENT_FLOW_SPEC_COMPLETE 0x0000000100000000ULL /* BT 1.2+ */ -#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x0000000200000000ULL /* BT 1.2+ */ -#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE 0x0000000400000000ULL /* BT 1.2+ */ -#define HCI_EVENT_SYNC_CONN_COMPLETE 0x0000080000000000ULL /* BT 1.2+ */ -#define HCI_EVENT_SYNC_CONN_CHANGED 0x0000100000000000ULL /* BT 1.2+ */ -#define HCI_EVENT_ALL_BT_1_2 0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */ -#define HCI_EVENT_SNIFF_SUBRATING 0x0000200000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x0000400000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE 0x0000800000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_IO_CAPABILITY_REQUEST 0x0001000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY 0x0002000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_CONFIRMATION_REQUEST 0x0004000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_PASSKEY_REQUEST 0x0008000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x0010000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x0020000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED 0x0080000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE 0x0100000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_PASSKEY_NOTIFICATION 0x0400000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_KEYPRESS_NOTIFICATION 0x0800000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES 0x1000000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_ALL_BT_2_1 0x1DBFFFFFFFFFFFFFULL -#define HCI_EVENT_ALL_BT_3_0 0x1DBFFFFFFFFFFFFFULL -#define HCI_EVENT_LE_META 0x2000000000000000ULL /* BT 4.0+ */ -#define HCI_EVENT_ALL_BT_4_0 0x3DBFFFFFFFFFFFFFULL -#define HCI_EVENT_ALL_BT_4_1 0x3DBFFFFFFFFFFFFFULL - -#define HCI_EVENT_P2_PHYS_LINK_COMPLETE 0x0000000000000001ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_CHANNEL_SELECTED 0x0000000000000002ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK 0x0000000000000004ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING 0x0000000000000008ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY 0x0000000000000010ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE 0x0000000000000020ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE 0x0000000000000040ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE 0x0000000000000080ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS 0x0000000000000100ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_START_TEST 0x0000000000000200ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_TEST_END 0x0000000000000400ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_RECEIVER_REPORT 0x0000000000000800ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE 0x0000000000001000ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_STATUS_CHANGE 0x0000000000002000ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_ALL_BT_3_0 0x0000000000003FFFULL -#define HCI_EVENT_P2_ALL_BT_4_0 0x0000000000003FFFULL -#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE 0x0000000000004000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE 0x0000000000008000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED 0x0000000000010000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED 0x0000000000020000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT 0x0000000000040000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE 0x0000000000080000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT 0x0000000000100000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE 0x0000000000200000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION 0x0000000000400000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED 0x0000000000800000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_ALL_BT_4_1 0x0000000000FFFFFFULL - -#define HCI_LE_EVENT_CONN_COMPLETE 0x0000000000000001ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_ADV_REPORT 0x0000000000000002ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE 0x0000000000000004ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE 0x0000000000000008ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_LTK_REQUEST 0x0000000000000010ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST 0x0000000000000020ULL /* BT 4.1+ */ - -#define HCI_LE_FTR_ENCRYPTION 0x0000000000000001ULL /* BT 4.0+ */ -#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST 0x0000000000000002ULL /* BT 4.1+ */ -#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION 0x0000000000000004ULL /* BT 4.1+ */ -#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE 0x0000000000000008ULL /* BT 4.1+ */ -#define HCI_LE_FTR_LE_PING 0x0000000000000010ULL /* BT 4.1+ */ - - - - - -#define HCI_OGF_Link_Control 1 - +#define HCI_DEV_NAME_LEN 248 + +#define HCI_INQUIRY_LENGTH_UNIT 1280 /* msec */ +#define HCI_INQUIRY_LENGTH_MAX 48 /* units */ + +#define HCI_LAP_Unlimited_Inquiry 0x9E8B33 +#define HCI_LAP_Limited_Inquiry 0x9E8B00 + +#define HCI_CLOCK_OFST_VALID 0x8000 + +#define HCI_PKT_TYP_NO_2_DH1 0x0002 /* BT 2.1+ */ +#define HCI_PKT_TYP_NO_3_DH1 0x0004 /* BT 2.1+ */ +#define HCI_PKT_TYP_DM1 0x0008 /* BT 1.1+ */ +#define HCI_PKT_TYP_DH1 0x0010 /* BT 1.1+ */ +#define HCI_PKT_TYP_NO_2_DH3 0x0100 /* BT 2.1+ */ +#define HCI_PKT_TYP_NO_3_DH3 0x0200 /* BT 2.1+ */ +#define HCI_PKT_TYP_DM3 0x0400 /* BT 1.1+ */ +#define HCI_PKT_TYP_DH3 0x0800 /* BT 1.1+ */ +#define HCI_PKT_TYP_NO_2_DH5 0x1000 /* BT 2.1+ */ +#define HCI_PKT_TYP_NO_3_DH5 0x1000 /* BT 2.1+ */ +#define HCI_PKT_TYP_DM5 0x4000 /* BT 1.1+ */ +#define HCI_PKT_TYP_DH5 0x8000 /* BT 1.1+ */ +#define HCI_PKT_TYP_DEFAULT 0xCC18 + +#define HCI_PKT_TYP_SCO_HV1 0x0001 /* BT 1.1+ */ +#define HCI_PKT_TYP_SCO_HV2 0x0002 /* BT 1.1+ */ +#define HCI_PKT_TYP_SCO_HV3 0x0004 /* BT 1.1+ */ +#define HCI_PKT_TYP_SCO_EV3 0x0008 /* BT 1.2+ */ +#define HCI_PKT_TYP_SCO_EV4 0x0010 /* BT 1.2+ */ +#define HCI_PKT_TYP_SCO_EV5 0x0020 /* BT 1.2+ */ +#define HCI_PKT_TYP_SCO_NO_2_EV3 0x0040 /* BT 2.1+ */ +#define HCI_PKT_TYP_SCO_NO_3_EV3 0x0080 /* BT 2.1+ */ +#define HCI_PKT_TYP_SCO_NO_2_EV5 0x0100 /* BT 2.1+ */ +#define HCI_PKT_TYP_SCO_NO_3_EV5 0x0200 /* BT 2.1+ */ + +#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES 0x0000 +#define HCI_LINK_POLICY_ENABLE_ROLESWITCH 0x0001 +#define HCI_LINK_POLICY_ENABLE_HOLD_MODE 0x0002 +#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE 0x0004 +#define HCI_LINK_POLICY_ENABLE_PARK_MODE 0x0008 + +#define HCI_FILTER_TYPE_CLEAR_ALL 0x00 /* no subtypes, no data */ +#define HCI_FILTER_INQUIRY_RESULT 0x01 /* below subtypes */ +#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS 0x00 /* no data */ +#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS \ + 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \ + compared to wanted_class) */ +#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR 0x02 /* uint8_t mac[6] */ +#define HCI_FILTER_CONNECTION_SETUP 0x02 /* below subtypes */ +#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS \ + 0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 \ + - yes w/ roleswitch */ +#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS \ + 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \ + compared to wanted_class), auto_accept flag same as above */ +#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR \ + 0x02 /* uint8_t mac[6], auto_accept flag same as above */ + +#define HCI_SCAN_ENABLE_INQUIRY 0x01 /* discoverable */ +#define HCI_SCAN_ENABLE_PAGE 0x02 /* connectable */ + +#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN 0x01 +#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN 0x02 +#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES 0x04 + +#define HCI_TO_HOST_FLOW_CTRL_ACL 0x01 +#define HCI_TO_HOST_FLOW_CTRL_SCO 0x02 + +#define HCI_INQ_MODE_STD 0 /* normal mode @ BT 1.1+ */ +#define HCI_INQ_MODE_RSSI 1 /* with RSSI @ BT 1.2+ */ +#define HCI_INQ_MODE_EIR 2 /* with EIR @ BT 2.1+ */ + +#define HCI_SSP_KEY_ENTRY_STARTED 0 +#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED 1 +#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED 2 +#define HCI_SSP_KEY_ENTRY_CLEARED 3 +#define HCI_SSP_KEY_ENTRY_COMPLETED 4 + +#define HCI_LOCATION_DOMAIN_OPTION_NONE 0x20 /* ' ' */ +#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY 0x4F /* 'O' */ +#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY 0x49 /* 'I' */ +#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY 0x58 /* 'X' */ + +#define HCI_PERIOD_TYPE_DOWNLINK 0x00 +#define HCI_PERIOD_TYPE_UPLINK 0x01 +#define HCI_PERIOD_TYPE_BIDIRECTIONAL 0x02 +#define HCI_PERIOD_TYPE_GUARD_PERIOD 0x03 + +#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX 0x00 +#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED 0x01 +#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED 0x02 +#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED 0x03 +#define HCI_MWS_INTERVAL_TYPE_FRAME \ + 0x04 /* type defined by Set External Frame Configuration command */ + +#define HCI_CONNLESS_FRAG_TYPE_CONT 0x00 /* continuation fragment */ +#define HCI_CONNLESS_FRAG_TYPE_START 0x01 /* first fragment */ +#define HCI_CONNLESS_FRAG_TYPE_END 0x02 /* last fragment */ +#define HCI_CONNLESS_FRAG_TYPE_COMPLETE \ + 0x03 /* complete fragment - no fragmentation */ + +#define HCI_CUR_MODE_ACTIVE 0x00 +#define HCI_CUR_MODE_HOLD 0x01 +#define HCI_CUR_MODE_SNIFF 0x02 +#define HCI_CUR_MODE_PARK 0x03 + +#define HCI_SCO_LINK_TYPE_SCO 0x00 +#define HCI_SCO_LINK_TYPE_ESCO 0x02 + +#define HCI_SCO_AIR_MODE_MULAW 0x00 +#define HCI_SCO_AIR_MODE_ALAW 0x01 +#define HCI_SCO_AIR_MODE_CVSD 0x02 +#define HCI_SCO_AIR_MODE_TRANSPARENT 0x03 + +#define HCI_MCA_500_PPM 0x00 +#define HCI_MCA_250_PPM 0x01 +#define HCI_MCA_150_PPM 0x02 +#define HCI_MCA_100_PPM 0x03 +#define HCI_MCA_75_PPM 0x04 +#define HCI_MCA_50_PPM 0x05 +#define HCI_MCA_30_PPM 0x06 +#define HCI_MCA_20_PPM 0x07 + +#define HCI_EDR_LINK_KEY_COMBO 0x00 +#define HCI_EDR_LINK_KEY_LOCAL 0x01 +#define HCI_EDR_LINK_KEY_REMOTE 0x02 +#define HCI_EDR_LINK_KEY_DEBUG 0x03 +#define HCI_EDR_LINK_KEY_UNAUTH_COMBO 0x04 +#define HCI_EDR_LINK_KEY_AUTH_COMBO 0x05 +#define HCI_EDR_LINK_KEY_CHANGED 0x06 + +#define HCI_VERSION_1_0_B 0 /* BT 1.0b */ +#define HCI_VERSION_1_1 1 /* BT 1.1 */ +#define HCI_VERSION_1_2 2 /* BT 1.2 */ +#define HCI_VERSION_2_0 4 /* BT 2.0 */ +#define HCI_VERSION_2_1 3 /* BT 2.1 */ +#define HCI_VERSION_3_0 4 /* BT 3.0 */ +#define HCI_VERSION_4_0 6 /* BT 4.0 */ +#define HCI_VERSION_4_1 7 /* BT 4.1 */ + +#define HCI_LE_STATE_NONCON_ADV 0x0000000000000001ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV 0x0000000000000002ULL /* BT 4.0+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV 0x0000000000000004ULL /* BT 4.0+ */ +#define HCI_LE_STATE_DIRECT_ADV 0x0000000000000008ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN 0x0000000000000010ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN 0x0000000000000020ULL /* BT 4.0+ */ +#define HCI_LE_STATE_INITIATE 0x0000000000000040ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SLAVE 0x0000000000000080ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN \ + 0x0000000000000100ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN \ + 0x0000000000000200ULL /* BT 4.0+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN \ + 0x0000000000000400ULL /* BT 4.0+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN \ + 0x0000000000000800ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN \ + 0x0000000000001000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN \ + 0x0000000000002000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN \ + 0x0000000000004000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN \ + 0x0000000000008000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_INITIATING \ + 0x0000000000010000ULL /* BT 4.0+ \ + */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING \ + 0x0000000000020000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_MASTER 0x0000000000040000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER \ + 0x0000000000080000ULL /* BT 4.0+ \ + */ +#define HCI_LE_STATE_NONCON_ADV_w_SLAVE 0x0000000000100000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE 0x0000000000200000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING \ + 0x0000000000400000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING \ + 0x0000000000800000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER 0x0000000001000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER 0x0000000002000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE 0x0000000004000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE 0x0000000008000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_INTIATING_w_MASTER 0x0000000010000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV \ + 0x0000000020000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \ + 0x0000000040000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \ + 0x0000000080000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING \ + 0x0000000100000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING \ + 0x0000000200000000ULL /* BT 4.1+ \ + */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING \ + 0x0000000400000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER \ + 0x0000000800000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_MASTER 0x0000001000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER \ + 0x0000002000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE \ + 0x0000004000000000ULL /* BT 4.1+ \ + */ +#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE 0x0000008000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE \ + 0x0000010000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_INITIATING_w_SLAVE 0x0000020000000000ULL /* BT 4.1+ */ + +#define HCI_LMP_FTR_3_SLOT_PACKETS 0x0000000000000001ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_5_SLOT_PACKETS 0x0000000000000002ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_ENCRYPTION 0x0000000000000004ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SLOT_OFFSET 0x0000000000000008ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_TIMING_ACCURACY 0x0000000000000010ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SWITCH 0x0000000000000020ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_HOLD_MODE 0x0000000000000040ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SNIFF_MODE 0x0000000000000080ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_PARK_MODE 0x0000000000000100ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_RSSI 0x0000000000000200ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE \ + 0x0000000000000400ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SCO_LINKS 0x0000000000000800ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_HV2_PACKETS 0x0000000000001000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_HV3_PACKETS 0x0000000000002000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_MU_LAW 0x0000000000004000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_A_LAW 0x0000000000008000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_CVSD 0x0000000000010000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_PAGING_SCHEME 0x0000000000020000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_POWER_CONTROL 0x0000000000040000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA 0x0000000000080000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0 0x0000000000100000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1 0x0000000000200000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2 0x0000000000400000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_BROADCAST_ENCRYPTION 0x0000000000800000ULL /* BT 1.2+ */ +#define HCI_LMP_FTR_ACL_2MBPS 0x0000000002000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ACL_3MBPS 0x0000000004000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN 0x0000000008000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN \ + 0x0000000010000000ULL /* BT 2.1+ \ + */ +#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN 0x0000000020000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS \ + 0x0000000040000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EXTENDED_SCO_LINK \ + 0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */ +#define HCI_LMP_FTR_EV4_PACKETS 0x0000000100000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EV5_PACKETS 0x0000000200000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE 0x0000000800000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE \ + 0x0000001000000000ULL /* BT 2.1+ \ + */ +#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED 0x0000002000000000ULL /* BT 4.0+ */ +#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER \ + 0x0000004000000000ULL /* BT 4.0+ \ + */ +#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS 0x0000008000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS 0x0000010000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_SNIFF_SUBRATING 0x0000020000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_PAUSE_ENCRYPTION 0x0000040000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CAPABLE_MASTER 0x0000080000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER \ + 0x0000100000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ESCO_2MBPS 0x0000200000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ESCO_3MBPS 0x0000400000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_3_SLOT_ESCO 0x0000800000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE \ + 0x0001000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_SSP 0x0008000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ENCAPSULATED_PDU 0x0010000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING \ + 0x0020000000000000ULL /* BT 2.1+ \ + */ +#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG \ + 0x0040000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT \ + 0x0100000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL \ + 0x0200000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EXTENDED_FEATURES 0x8000000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL 0x0400000000000000ULL /* BT 3.0+ */ +#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER \ + 0x0002000000000000ULL /* BT 4.0+ */ + +#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT \ + 0x0000000000000001ULL /* BT 2.1+ \ + */ +#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT 0x0000000000000002ULL /* BT 4.0+ */ +#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT \ + 0x0000000000000004ULL /* BT 4.0+ */ +#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT \ + 0x0000000000000008ULL /* BT 4.1+ */ + +#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER \ + 0x0000000000000001ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE \ + 0x0000000000000002ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN \ + 0x0000000000000004ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN \ + 0x0000000000000008ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT \ + 0x0000000000000010ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN \ + 0x0000000000000020ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT \ + 0x0000000000000040ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER \ + 0x0000000000000100ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_PING 0x0000000000000200ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING 0x0000000000000800ULL /* BT 4.1+ */ + +#define HCI_EVENT_INQUIRY_COMPLETE 0x0000000000000001ULL /* BT 1.1+ */ +#define HCI_EVENT_INQUIRY_RESULT 0x0000000000000002ULL /* BT 1.1+ */ +#define HCI_EVENT_CONN_COMPLETE 0x0000000000000004ULL /* BT 1.1+ */ +#define HCI_EVENT_CONN_REQUEST 0x0000000000000008ULL /* BT 1.1+ */ +#define HCI_EVENT_DISCONNECTION_COMPLETE 0x0000000000000010ULL /* BT 1.1+ */ +#define HCI_EVENT_AUTH_COMPLETE 0x0000000000000020ULL /* BT 1.1+ */ +#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE \ + 0x0000000000000040ULL /* BT 1.1+ */ +#define HCI_EVENT_ENCR_CHANGE 0x0000000000000080ULL /* BT 1.1+ */ +#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE \ + 0x0000000000000100ULL /* BT 1.1+ */ +#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0000000000000200ULL /* BT 1.1+ */ +#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE \ + 0x0000000000000400ULL /* BT 1.1+ */ +#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE \ + 0x0000000000000800ULL /* BT 1.1+ */ +#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0000000000001000ULL /* BT 1.1+ */ +#define HCI_EVENT_HARDWARE_ERROR 0x0000000000008000ULL /* BT 1.1+ */ +#define HCI_EVENT_FLUSH_OCCURRED 0x0000000000010000ULL /* BT 1.1+ */ +#define HCI_EVENT_ROLE_CHANGE 0x0000000000020000ULL /* BT 1.1+ */ +#define HCI_EVENT_MODE_CHANGE 0x0000000000080000ULL /* BT 1.1+ */ +#define HCI_EVENT_RETURN_LINK_KEYS 0x0000000000100000ULL /* BT 1.1+ */ +#define HCI_EVENT_PIN_CODE_REQUEST 0x0000000000200000ULL /* BT 1.1+ */ +#define HCI_EVENT_LINK_KEY_REQUEST 0x0000000000400000ULL /* BT 1.1+ */ +#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x0000000000800000ULL /* BT 1.1+ */ +#define HCI_EVENT_LOOPBACK_COMMAND 0x0000000001000000ULL /* BT 1.1+ */ +#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x0000000002000000ULL /* BT 1.1+ */ +#define HCI_EVENT_MAX_SLOTS_CHANGE 0x0000000004000000ULL /* BT 1.1+ */ +#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE \ + 0x0000000008000000ULL /* BT 1.1+ \ + */ +#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED 0x0000000010000000ULL /* BT 1.1+ */ +#define HCI_EVENT_QOS_VIOLATION 0x0000000020000000ULL /* BT 1.1+ */ +#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE \ + 0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */ +#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE \ + 0x0000000080000000ULL /* BT 1.1+ */ +#define HCI_EVENT_ALL_BT_1_1 \ + 0x00000000FFFFFFFFULL /* also the default for BT 1.1 */ +#define HCI_EVENT_FLOW_SPEC_COMPLETE 0x0000000100000000ULL /* BT 1.2+ */ +#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x0000000200000000ULL /* BT 1.2+ */ +#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE \ + 0x0000000400000000ULL /* BT 1.2+ */ +#define HCI_EVENT_SYNC_CONN_COMPLETE 0x0000080000000000ULL /* BT 1.2+ */ +#define HCI_EVENT_SYNC_CONN_CHANGED 0x0000100000000000ULL /* BT 1.2+ */ +#define HCI_EVENT_ALL_BT_1_2 \ + 0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */ +#define HCI_EVENT_SNIFF_SUBRATING 0x0000200000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x0000400000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE \ + 0x0000800000000000ULL /* BT 2.1+ \ + */ +#define HCI_EVENT_IO_CAPABILITY_REQUEST 0x0001000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY \ + 0x0002000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_USER_CONFIRMATION_REQUEST \ + 0x0004000000000000ULL /* BT 2.1+ \ + */ +#define HCI_EVENT_USER_PASSKEY_REQUEST 0x0008000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x0010000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x0020000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED \ + 0x0080000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE 0x0100000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_USER_PASSKEY_NOTIFICATION \ + 0x0400000000000000ULL /* BT 2.1+ \ + */ +#define HCI_EVENT_KEYPRESS_NOTIFICATION 0x0800000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES \ + 0x1000000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_ALL_BT_2_1 0x1DBFFFFFFFFFFFFFULL +#define HCI_EVENT_ALL_BT_3_0 0x1DBFFFFFFFFFFFFFULL +#define HCI_EVENT_LE_META 0x2000000000000000ULL /* BT 4.0+ */ +#define HCI_EVENT_ALL_BT_4_0 0x3DBFFFFFFFFFFFFFULL +#define HCI_EVENT_ALL_BT_4_1 0x3DBFFFFFFFFFFFFFULL + +#define HCI_EVENT_P2_PHYS_LINK_COMPLETE 0x0000000000000001ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_CHANNEL_SELECTED 0x0000000000000002ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK \ + 0x0000000000000004ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING \ + 0x0000000000000008ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY \ + 0x0000000000000010ULL /* BT 3.0+ \ + */ +#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE 0x0000000000000020ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE \ + 0x0000000000000040ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE \ + 0x0000000000000080ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS \ + 0x0000000000000100ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_START_TEST 0x0000000000000200ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_TEST_END 0x0000000000000400ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_RECEIVER_REPORT 0x0000000000000800ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE \ + 0x0000000000001000ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_STATUS_CHANGE 0x0000000000002000ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_ALL_BT_3_0 0x0000000000003FFFULL +#define HCI_EVENT_P2_ALL_BT_4_0 0x0000000000003FFFULL +#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE \ + 0x0000000000004000ULL /* BT 4.1+ \ + */ +#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE 0x0000000000008000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED 0x0000000000010000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED \ + 0x0000000000020000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT \ + 0x0000000000040000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE \ + 0x0000000000080000ULL /* BT 4.1+ \ + */ +#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT \ + 0x0000000000100000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE \ + 0x0000000000200000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION \ + 0x0000000000400000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED \ + 0x0000000000800000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_ALL_BT_4_1 0x0000000000FFFFFFULL + +#define HCI_LE_EVENT_CONN_COMPLETE 0x0000000000000001ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_ADV_REPORT 0x0000000000000002ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE 0x0000000000000004ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE \ + 0x0000000000000008ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_LTK_REQUEST 0x0000000000000010ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST \ + 0x0000000000000020ULL /* BT 4.1+ */ + +#define HCI_LE_FTR_ENCRYPTION 0x0000000000000001ULL /* BT 4.0+ */ +#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST \ + 0x0000000000000002ULL /* BT 4.1+ */ +#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION \ + 0x0000000000000004ULL /* BT 4.1+ */ +#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE \ + 0x0000000000000008ULL /* BT 4.1+ */ +#define HCI_LE_FTR_LE_PING 0x0000000000000010ULL /* BT 4.1+ */ + +#define HCI_OGF_Link_Control 1 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Inquiry 0x0001 /* status */ +#define HCI_CMD_Inquiry 0x0001 /* status */ struct hciInquiry { uint8_t lap[3]; uint8_t inqLen; uint8_t numResp; } __packed; -#define HCI_CMD_Inquiry_Cancel 0x0002 /* complete */ +#define HCI_CMD_Inquiry_Cancel 0x0002 /* complete */ struct hciCmplInquiryCancel { uint8_t status; } __packed; -#define HCI_CMD_Periodic_Inquiry_Mode 0x0003 /* complete */ +#define HCI_CMD_Periodic_Inquiry_Mode 0x0003 /* complete */ struct hciPeriodicInquiryMode { uint16_t maxPeriodLen; uint16_t minPeriodLen; @@ -390,10 +492,9 @@ struct hciCmplPeriodicInquiryMode { uint8_t status; } __packed; +#define HCI_CMD_Exit_Periodic_Inquiry_Mode 0x0004 /* complete */ -#define HCI_CMD_Exit_Periodic_Inquiry_Mode 0x0004 /* complete */ - -#define HCI_CMD_Create_Connection 0x0005 /* status */ +#define HCI_CMD_Create_Connection 0x0005 /* status */ struct hciCreateConnection { uint8_t mac[6]; uint16_t allowedPackets; /* HCI_PKT_TYP_* */ @@ -402,19 +503,20 @@ struct hciCreateConnection { uint8_t allowRoleSwitch; } __packed; -#define HCI_CMD_Disconnect 0x0006 /* status */ +#define HCI_CMD_Disconnect 0x0006 /* status */ struct hciDisconnect { uint16_t conn; uint8_t reason; } __packed; -#define HCI_CMD_Add_SCO_Connection 0x0007 /* status */ /* deprecated in BT 1.2+ */ +#define HCI_CMD_Add_SCO_Connection \ + 0x0007 /* status */ /* deprecated in BT 1.2+ */ struct hciAddScoConnection { uint16_t conn; uint16_t packetTypes; /* HCI_PKT_TYP_SCO_* */ } __packed; -#define HCI_CMD_Create_Connection_Cancel 0x0008 /* complete */ +#define HCI_CMD_Create_Connection_Cancel 0x0008 /* complete */ struct hciCreateConnectionCancel { uint8_t mac[6]; } __packed; @@ -423,19 +525,19 @@ struct hciCmplCreateConnectionCancel { uint8_t mac[6]; } __packed; -#define HCI_CMD_Accept_Connection_Request 0x0009 /* status */ +#define HCI_CMD_Accept_Connection_Request 0x0009 /* status */ struct hciAcceptConnection { uint8_t mac[6]; uint8_t remainSlave; } __packed; -#define HCI_CMD_Reject_Connection_Request 0x000A /* status */ +#define HCI_CMD_Reject_Connection_Request 0x000A /* status */ struct hciRejectConnection { uint8_t mac[6]; uint8_t reason; } __packed; -#define HCI_CMD_Link_Key_Request_Reply 0x000B /* complete */ +#define HCI_CMD_Link_Key_Request_Reply 0x000B /* complete */ struct hciLinkKeyRequestReply { uint8_t mac[6]; uint8_t key[16]; @@ -445,7 +547,7 @@ struct hciCmplLinkKeyRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Link_Key_Request_Negative_Reply 0x000C /* complete */ +#define HCI_CMD_Link_Key_Request_Negative_Reply 0x000C /* complete */ struct hciLinkKeyRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -454,7 +556,7 @@ struct hciCmplLinkKeyRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_PIN_Code_Request_Reply 0x000D /* complete */ +#define HCI_CMD_PIN_Code_Request_Reply 0x000D /* complete */ struct hciPinCodeRequestReply { uint8_t mac[6]; uint8_t pinCodeLen; @@ -465,7 +567,7 @@ struct hciCmplPinCodeRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_PIN_Code_Request_Negative_Reply 0x000E /* complete */ +#define HCI_CMD_PIN_Code_Request_Negative_Reply 0x000E /* complete */ struct hciPinCodeRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -474,34 +576,34 @@ struct hciCmplPinCodeRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Change_Connection_Packet_Type 0x000F /* status */ +#define HCI_CMD_Change_Connection_Packet_Type 0x000F /* status */ struct hciChangeConnectionPacketType { uint16_t conn; uint16_t allowedPackets; /* HCI_PKT_TYP_* */ } __packed; -#define HCI_CMD_Authentication_Requested 0x0011 /* status */ +#define HCI_CMD_Authentication_Requested 0x0011 /* status */ struct hciAuthRequested { uint16_t conn; } __packed; -#define HCI_CMD_Set_Connection_Encryption 0x0013 /* status */ +#define HCI_CMD_Set_Connection_Encryption 0x0013 /* status */ struct hciSetConnectionEncryption { uint16_t conn; uint8_t encrOn; } __packed; -#define HCI_CMD_Change_Connection_Link_Key 0x0015 /* status */ +#define HCI_CMD_Change_Connection_Link_Key 0x0015 /* status */ struct hciChangeConnLinkKey { uint16_t conn; } __packed; -#define HCI_CMD_Master_Link_Key 0x0017 /* status */ +#define HCI_CMD_Master_Link_Key 0x0017 /* status */ struct hciMasterLinkKey { uint8_t useTempKey; } __packed; -#define HCI_CMD_Remote_Name_Request 0x0019 /* status */ +#define HCI_CMD_Remote_Name_Request 0x0019 /* status */ struct hciRemoteNameRequest { uint8_t mac[6]; uint8_t PSRM; @@ -509,7 +611,7 @@ struct hciRemoteNameRequest { uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */ } __packed; -#define HCI_CMD_Remote_Name_Request_Cancel 0x001A /* complete */ +#define HCI_CMD_Remote_Name_Request_Cancel 0x001A /* complete */ struct hciRemoteNameRequestCancel { uint8_t mac[6]; } __packed; @@ -518,31 +620,30 @@ struct hciCmplRemoteNameRequestCancel { uint8_t mac[6]; } __packed; -#define HCI_CMD_Read_Remote_Supported_Features 0x001B /* status */ +#define HCI_CMD_Read_Remote_Supported_Features 0x001B /* status */ struct hciReadRemoteSupportedFeatures { uint16_t conn; } __packed; -#define HCI_CMD_Read_Remote_Version_Information 0x001D /* status */ +#define HCI_CMD_Read_Remote_Version_Information 0x001D /* status */ struct hciReadRemoteVersionInfo { uint16_t conn; } __packed; -#define HCI_CMD_Read_Clock_Offset 0x001F /* status */ +#define HCI_CMD_Read_Clock_Offset 0x001F /* status */ struct hciReadClockOffset { uint16_t conn; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Read_Remote_Extended_Features 0x001C /* status */ +#define HCI_CMD_Read_Remote_Extended_Features 0x001C /* status */ struct hciReadRemoteExtendedFeatures { uint16_t conn; uint8_t page; /* BT1.2 max: 0 */ } __packed; -#define HCI_CMD_Read_Lmp_Handle 0x0020 /* complete */ +#define HCI_CMD_Read_Lmp_Handle 0x0020 /* complete */ struct hciReadLmpHandle { uint16_t handle; } __packed; @@ -553,7 +654,7 @@ struct hciCmplReadLmpHandle { uint32_t reserved; } __packed; -#define HCI_CMD_Setup_Synchronous_Connection 0x0028 /* status */ +#define HCI_CMD_Setup_Synchronous_Connection 0x0028 /* status */ struct hciSetupSyncConn { uint16_t conn; uint32_t txBandwidth; @@ -564,7 +665,7 @@ struct hciSetupSyncConn { uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */ } __packed; -#define HCI_CMD_Accept_Synchronous_Connection_Request 0x0029 /* status */ +#define HCI_CMD_Accept_Synchronous_Connection_Request 0x0029 /* status */ struct hciAcceptSyncConn { uint8_t mac[6]; uint32_t txBandwidth; @@ -575,16 +676,15 @@ struct hciAcceptSyncConn { uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */ } __packed; -#define HCI_CMD_Reject_Synchronous_Connection_Request 0x002A /* status */ +#define HCI_CMD_Reject_Synchronous_Connection_Request 0x002A /* status */ struct hciRejectSyncConn { uint8_t mac[6]; uint8_t reason; } __packed; - /* ==== BR 2.1 ==== */ -#define HCI_CMD_IO_Capability_Request_Reply 0x002B /* complete */ +#define HCI_CMD_IO_Capability_Request_Reply 0x002B /* complete */ struct hciIoCapabilityRequestReply { uint8_t mac[6]; uint8_t cap; /* HCI_DISPLAY_CAP_* */ @@ -596,7 +696,7 @@ struct hciCmplIoCapabilityRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Confirmation_Request_Reply 0x002C /* complete */ +#define HCI_CMD_User_Confirmation_Request_Reply 0x002C /* complete */ struct hciUserConfRequestReply { uint8_t mac[6]; } __packed; @@ -605,7 +705,7 @@ struct hciCmplUserConfRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Confirmation_Request_Negative_Reply 0x002D /* complete */ +#define HCI_CMD_User_Confirmation_Request_Negative_Reply 0x002D /* complete */ struct hciUserConfRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -614,7 +714,7 @@ struct hciCmplUserConfRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Passkey_Request_Reply 0x002E /* complete */ +#define HCI_CMD_User_Passkey_Request_Reply 0x002E /* complete */ struct hciUserPasskeyRequestReply { uint8_t mac[6]; uint32_t num; @@ -624,7 +724,7 @@ struct hciCmplUserPasskeyRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Passkey_Request_Negative_Reply 0x002F /* complete */ +#define HCI_CMD_User_Passkey_Request_Negative_Reply 0x002F /* complete */ struct hciUserPasskeyRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -633,7 +733,7 @@ struct hciCmplUserPasskeyRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Remote_OOB_Data_Request_Reply 0x0030 /* complete */ +#define HCI_CMD_Remote_OOB_Data_Request_Reply 0x0030 /* complete */ struct hciRemoteOobDataRequestReply { uint8_t mac[6]; uint8_t C[16]; @@ -644,7 +744,7 @@ struct hciCmplRemoteOobDataRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply 0x0033 /* complete */ +#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply 0x0033 /* complete */ struct hciRemoteOobDataRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -653,7 +753,7 @@ struct hciCmplRemoteOobDataRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_IO_Capability_Request_Negative_Reply 0x0034 /* complete */ +#define HCI_CMD_IO_Capability_Request_Negative_Reply 0x0034 /* complete */ struct hciIoCapabilityRequestNegativeReply { uint8_t mac[6]; uint8_t reason; @@ -663,10 +763,9 @@ struct hciCmplIoCapabilityRequestNegativeReply { uint8_t mac[6]; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Create_Physical_link 0x0035 /* status */ +#define HCI_CMD_Create_Physical_link 0x0035 /* status */ struct hciCreatePhysicalLink { uint8_t physLinkHandle; uint8_t dedicatedAmpKeyLength; @@ -674,7 +773,7 @@ struct hciCreatePhysicalLink { uint8_t dedicatedAmpKey; } __packed; -#define HCI_CMD_Accept_Physical_link 0x0036 /* status */ +#define HCI_CMD_Accept_Physical_link 0x0036 /* status */ struct hciAcceptPhysicalLink { uint8_t physLinkHandle; uint8_t dedicatedAmpKeyLength; @@ -682,32 +781,32 @@ struct hciAcceptPhysicalLink { uint8_t dedicatedAmpKey; } __packed; -#define HCI_CMD_Disconnect_Physical_link 0x0037 /* status */ +#define HCI_CMD_Disconnect_Physical_link 0x0037 /* status */ struct hciDisconnectPhysicalLink { uint8_t physLinkHandle; uint8_t reason; } __packed; -#define HCI_CMD_Create_Logical_link 0x0038 /* status */ +#define HCI_CMD_Create_Logical_link 0x0038 /* status */ struct hciCreateLogicalLink { uint8_t physLinkHandle; uint8_t txFlowSpec[16]; uint8_t rxFlowSpec[16]; } __packed; -#define HCI_CMD_Accept_Logical_Link 0x0039 /* status */ +#define HCI_CMD_Accept_Logical_Link 0x0039 /* status */ struct hciAcceptLogicalLink { uint8_t physLinkHandle; uint8_t txFlowSpec[16]; uint8_t rxFlowSpec[16]; } __packed; -#define HCI_CMD_Disconnect_Logical_link 0x003A /* status */ +#define HCI_CMD_Disconnect_Logical_link 0x003A /* status */ struct hciDisconnectLogicalLink { uint8_t physLinkHandle; } __packed; -#define HCI_CMD_Logical_Link_Cancel 0x003B /* complete */ +#define HCI_CMD_Logical_Link_Cancel 0x003B /* complete */ struct hciLogicalLinkCancel { uint8_t physLinkHandle; uint8_t txFlowSpecID; @@ -718,17 +817,16 @@ struct hciCmplLogicalLinkCancel { uint8_t txFlowSpecID; } __packed; -#define HCI_CMD_Flow_Spec_Modify 0x003C /* status */ +#define HCI_CMD_Flow_Spec_Modify 0x003C /* status */ struct hciFlowSpecModify { uint16_t handle; uint8_t txFlowSpec[16]; uint8_t rxFlowSpec[16]; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_Enhanced_Setup_Synchronous_Connection 0x003D /* status */ +#define HCI_CMD_Enhanced_Setup_Synchronous_Connection 0x003D /* status */ struct hciEnhSetupSyncConn { uint16_t conn; uint32_t txBandwidth; @@ -756,7 +854,7 @@ struct hciEnhSetupSyncConn { uint8_t retransmissionEffort; } __packed; -#define HCI_CMD_Enhanced_Accept_Synchronous_Connection 0x003E /* status */ +#define HCI_CMD_Enhanced_Accept_Synchronous_Connection 0x003E /* status */ struct hciEnhAcceptSyncConn { uint8_t mac[6]; uint32_t txBandwidth; @@ -784,14 +882,14 @@ struct hciEnhAcceptSyncConn { uint8_t retransmissionEffort; } __packed; -#define HCI_CMD_Truncated_Page 0x003F /* status */ +#define HCI_CMD_Truncated_Page 0x003F /* status */ struct hciTruncatedPage { uint8_t mac[6]; uint8_t PSRM; uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */ } __packed; -#define HCI_CMD_Truncated_Page_Cancel 0x0040 /* complete */ +#define HCI_CMD_Truncated_Page_Cancel 0x0040 /* complete */ struct hciTruncatedPageCancel { uint8_t mac[6]; } __packed; @@ -800,7 +898,7 @@ struct hciCmplTruncatedPageCancel { uint8_t mac[6]; } __packed; -#define HCI_CMD_Set_Connectionless_Slave_Broadcast 0x0041 /* complete */ +#define HCI_CMD_Set_Connectionless_Slave_Broadcast 0x0041 /* complete */ struct hciSetConnectionlessSlaveBroadcast { uint8_t enabled; uint8_t ltAddr; /* 1..7 */ @@ -816,7 +914,9 @@ struct hciCmplSetConnectionlessSlaveBroadcast { uint16_t interval; } __packed; -#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive 0x0042 /* complete */ +#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive \ + 0x0042 /* complete \ + */ struct hciSetConnectionlessSlaveBroadcastReceive { uint8_t enabled; uint8_t mac[6]; /* add rof tranmitter */ @@ -836,9 +936,9 @@ struct hciCmplSetConnectionlessSlaveBroadcastReceive { uint8_t ltAddr; /* 1..7 */ } __packed; -#define HCI_CMD_Start_Synchronisation_Train 0x0043 /* status */ +#define HCI_CMD_Start_Synchronisation_Train 0x0043 /* status */ -#define HCI_CMD_Receive_Synchronisation_Train 0x0044 /* status */ +#define HCI_CMD_Receive_Synchronisation_Train 0x0044 /* status */ struct hciReceiveSyncTrain { uint8_t mac[6]; uint16_t syncScanTimeout; @@ -846,7 +946,7 @@ struct hciReceiveSyncTrain { uint16_t syncScanInterval; } __packed; -#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply 0x0045 /* complete */ +#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply 0x0045 /* complete */ struct hciRemoteOobExtendedDataRequestReply { uint8_t mac[6]; uint8_t C_192[16]; @@ -859,23 +959,18 @@ struct hciCmplRemoteOobExtendedDataRequestReply { uint8_t mac[6]; } __packed; - - - - -#define HCI_OGF_Link_Policy 2 - +#define HCI_OGF_Link_Policy 2 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Hold_Mode 0x0001 /* status */ +#define HCI_CMD_Hold_Mode 0x0001 /* status */ struct hciHoldMode { uint16_t conn; uint16_t holdModeMaxInt; uint16_t holdModeMinInt; } __packed; -#define HCI_CMD_Sniff_Mode 0x0003 /* status */ +#define HCI_CMD_Sniff_Mode 0x0003 /* status */ struct hciSniffMode { uint16_t conn; uint16_t sniffMaxInt; @@ -884,24 +979,24 @@ struct hciSniffMode { uint16_t sniffTimeout; } __packed; -#define HCI_CMD_Exit_Sniff_Mode 0x0004 /* status */ +#define HCI_CMD_Exit_Sniff_Mode 0x0004 /* status */ struct hciExitSniffMode { uint16_t conn; } __packed; -#define HCI_CMD_Park_State 0x0005 /* status */ +#define HCI_CMD_Park_State 0x0005 /* status */ struct hciParkState { uint16_t conn; uint16_t beaconMaxInt; uint16_t beaconMinInt; } __packed; -#define HCI_CMD_Exit_Park_State 0x0006 /* status */ +#define HCI_CMD_Exit_Park_State 0x0006 /* status */ struct hciExitParkState { uint16_t conn; } __packed; -#define HCI_CMD_QoS_Setup 0x0007 /* status */ +#define HCI_CMD_QoS_Setup 0x0007 /* status */ struct hisQosSetup { uint16_t conn; uint8_t flags; @@ -912,7 +1007,7 @@ struct hisQosSetup { uint32_t delayVariation; } __packed; -#define HCI_CMD_Role_Discovery 0x0009 /* complete */ +#define HCI_CMD_Role_Discovery 0x0009 /* complete */ struct hciRoleDiscovery { uint16_t conn; } __packed; @@ -920,13 +1015,13 @@ struct hciCmplRoleDiscovery { uint8_t status; } __packed; -#define HCI_CMD_Switch_Role 0x000B /* status */ +#define HCI_CMD_Switch_Role 0x000B /* status */ struct hciSwitchRole { uint8_t mac[6]; uint8_t becomeSlave; } __packed; -#define HCI_CMD_Read_Link_Policy_Settings 0x000C /* complete */ +#define HCI_CMD_Read_Link_Policy_Settings 0x000C /* complete */ struct hciReadLinkPolicySettings { uint16_t conn; } __packed; @@ -936,7 +1031,7 @@ struct hciCmplReadLinkPolicySettings { uint16_t policy; /* HCI_LINK_POLICY_* */ } __packed; -#define HCI_CMD_Write_Link_Policy_Settings 0x000D /* complete */ +#define HCI_CMD_Write_Link_Policy_Settings 0x000D /* complete */ struct hciWriteLinkPolicySettings { uint16_t conn; uint16_t policy; /* HCI_LINK_POLICY_* */ @@ -946,16 +1041,15 @@ struct hciCmplWriteLinkPolicySettings { uint16_t conn; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Read_Default_Link_Policy_Settings 0x000E /* complete */ +#define HCI_CMD_Read_Default_Link_Policy_Settings 0x000E /* complete */ struct hciCmplReadDefaultLinkPolicySettings { uint8_t status; uint16_t policy; /* HCI_LINK_POLICY_* */ } __packed; -#define HCI_CMD_Write_Default_Link_Policy_Settings 0x000F /* complete */ +#define HCI_CMD_Write_Default_Link_Policy_Settings 0x000F /* complete */ struct hciWriteDefaultLinkPolicySettings { uint16_t policy; /* HCI_LINK_POLICY_* */ } __packed; @@ -963,7 +1057,7 @@ struct hciCmplWriteDefaultLinkPolicySettings { uint8_t status; } __packed; -#define HCI_CMD_Flow_Specification 0x0010 /* status */ +#define HCI_CMD_Flow_Specification 0x0010 /* status */ struct hisFlowSpecification { uint16_t conn; uint8_t flags; @@ -975,10 +1069,9 @@ struct hisFlowSpecification { uint32_t accessLatency; } __packed; - /* ==== BT 2.1 ==== */ -#define HCI_CMD_Sniff_Subrating 0x0011 /* complete */ +#define HCI_CMD_Sniff_Subrating 0x0011 /* complete */ struct hciSniffSubrating { uint16_t conn; uint16_t maxLatency; @@ -990,16 +1083,11 @@ struct hciCmplSniffSubrating { uint16_t conn; } __packed; - - - - -#define HCI_OGF_Controller_and_Baseband 3 - +#define HCI_OGF_Controller_and_Baseband 3 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Set_Event_Mask 0x0001 /* complete */ +#define HCI_CMD_Set_Event_Mask 0x0001 /* complete */ struct hciSetEventMask { uint64_t mask; /* bitmask of HCI_EVENT_* */ } __packed; @@ -1007,12 +1095,12 @@ struct hciCmplSetEventMask { uint8_t status; } __packed; -#define HCI_CMD_Reset 0x0003 /* complete */ +#define HCI_CMD_Reset 0x0003 /* complete */ struct hciCmplReset { uint8_t status; } __packed; -#define HCI_CMD_Set_Event_Filter 0x0005 /* complete */ +#define HCI_CMD_Set_Event_Filter 0x0005 /* complete */ struct hciSetEventFilter { uint8_t filterType; /* HCI_FILTER_TYPE_* */ /* more things are optional here */ @@ -1021,7 +1109,7 @@ struct hciCmplSetEventFiler { uint8_t status; } __packed; -#define HCI_CMD_Flush 0x0008 /* complete */ +#define HCI_CMD_Flush 0x0008 /* complete */ struct hciFlush { uint16_t conn; } __packed; @@ -1030,13 +1118,13 @@ struct hciCmplFlush { uint16_t conn; } __packed; -#define HCI_CMD_Read_PIN_Type 0x0009 /* complete */ +#define HCI_CMD_Read_PIN_Type 0x0009 /* complete */ struct hciCmplReadPinType { uint8_t status; uint8_t isFixed; } __packed; -#define HCI_CMD_Write_PIN_Type 0x000A /* complete */ +#define HCI_CMD_Write_PIN_Type 0x000A /* complete */ struct hciWritePinType { uint8_t isFixed; } __packed; @@ -1044,12 +1132,12 @@ struct hciCmplWritePinType { uint8_t status; } __packed; -#define HCI_CMD_Create_New_Unit_Key 0x000B /* complete */ +#define HCI_CMD_Create_New_Unit_Key 0x000B /* complete */ struct hciCmplCreateNewUnitKey { uint8_t status; } __packed; -#define HCI_CMD_Read_Stored_Link_Key 0x000D /* complete */ +#define HCI_CMD_Read_Stored_Link_Key 0x000D /* complete */ struct hciReadStoredLinkKey { uint8_t mac[6]; uint8_t readAll; @@ -1060,7 +1148,7 @@ struct hciCmplReadStoredLinkKey { uint16_t numKeysRead; } __packed; -#define HCI_CMD_Write_Stored_Link_Key 0x0011 /* complete */ +#define HCI_CMD_Write_Stored_Link_Key 0x0011 /* complete */ struct hciWriteStoredLinkKeyItem { uint8_t mac[6]; uint8_t key[16]; @@ -1074,7 +1162,7 @@ struct hciCmplWriteStoredLinkKey { uint8_t numKeysWritten; } __packed; -#define HCI_CMD_Delete_Stored_Link_Key 0x0012 /* complete */ +#define HCI_CMD_Delete_Stored_Link_Key 0x0012 /* complete */ struct hciDeleteStoredLinkKey { uint8_t mac[6]; uint8_t deleteAll; @@ -1084,7 +1172,7 @@ struct hciCmplDeleteStoredLinkKey { uint8_t numKeysDeleted; } __packed; -#define HCI_CMD_Write_Local_Name 0x0013 /* complete */ +#define HCI_CMD_Write_Local_Name 0x0013 /* complete */ struct hciWriteLocalName { char name[HCI_DEV_NAME_LEN]; } __packed; @@ -1092,19 +1180,19 @@ struct hciCmplWriteLocalName { uint8_t status; } __packed; -#define HCI_CMD_Read_Local_Name 0x0014 /* complete */ +#define HCI_CMD_Read_Local_Name 0x0014 /* complete */ struct hciCmplReadLocalName { uint8_t status; char name[HCI_DEV_NAME_LEN]; } __packed; -#define HCI_CMD_Read_Connection_Accept_Timeout 0x0015 /* complete */ +#define HCI_CMD_Read_Connection_Accept_Timeout 0x0015 /* complete */ struct hciCmplReadConnAcceptTimeout { uint8_t status; uint16_t timeout; /* in units of 0.625ms 1..0xB540 */ } __packed; -#define HCI_CMD_Write_Connection_Accept_Timeout 0x0016 /* complete */ +#define HCI_CMD_Write_Connection_Accept_Timeout 0x0016 /* complete */ struct hciWriteConnAcceptTimeout { uint16_t timeout; /* in units of 0.625ms 1..0xB540 */ } __packed; @@ -1112,13 +1200,13 @@ struct hciCmplWriteConnAcceptTimeout { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Timeout 0x0017 /* complete */ +#define HCI_CMD_Read_Page_Timeout 0x0017 /* complete */ struct hciCmplReadPageTimeout { uint8_t status; uint16_t timeout; } __packed; -#define HCI_CMD_Write_Page_Timeout 0x0018 /* complete */ +#define HCI_CMD_Write_Page_Timeout 0x0018 /* complete */ struct hciWritePageTimeout { uint16_t timeout; } __packed; @@ -1126,13 +1214,13 @@ struct hciCmplWritePageTimeout { uint8_t status; } __packed; -#define HCI_CMD_Read_Scan_Enable 0x0019 /* complete */ +#define HCI_CMD_Read_Scan_Enable 0x0019 /* complete */ struct hciCmplReadScanEnable { uint8_t status; uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */ } __packed; -#define HCI_CMD_Write_Scan_Enable 0x001A /* complete */ +#define HCI_CMD_Write_Scan_Enable 0x001A /* complete */ struct hciWriteScanEnable { uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */ } __packed; @@ -1140,14 +1228,14 @@ struct hciCmplWriteScanEnable { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Activity 0x001B /* complete */ +#define HCI_CMD_Read_Page_Scan_Activity 0x001B /* complete */ struct hciCmplReadPageScanActivity { uint8_t status; uint16_t scanInterval; uint16_t scanWindow; } __packed; -#define HCI_CMD_Write_Page_Scan_Activity 0x001C /* complete */ +#define HCI_CMD_Write_Page_Scan_Activity 0x001C /* complete */ struct hciWritePageScanActivity { uint16_t scanInterval; uint16_t scanWindow; @@ -1156,14 +1244,14 @@ struct hciCmplWritePageScanActivity { uint8_t status; } __packed; -#define HCI_CMD_Read_Inquiry_Scan_Activity 0x001D /* complete */ +#define HCI_CMD_Read_Inquiry_Scan_Activity 0x001D /* complete */ struct hciCmplReadInquiryScanActivity { uint8_t status; uint16_t scanInterval; uint16_t scanWindow; } __packed; -#define HCI_CMD_Write_Inquiry_Scan_Activity 0x001E /* complete */ +#define HCI_CMD_Write_Inquiry_Scan_Activity 0x001E /* complete */ struct hciWriteInquiryScanActivity { uint16_t scanInterval; uint16_t scanWindow; @@ -1172,13 +1260,13 @@ struct hciCmplWriteInquiryScanActivity { uint8_t status; } __packed; -#define HCI_CMD_Read_Authentication_Enable 0x001F /* complete */ +#define HCI_CMD_Read_Authentication_Enable 0x001F /* complete */ struct hciCmplReadAuthEnable { uint8_t status; uint8_t authRequired; } __packed; -#define HCI_CMD_Write_Authentication_Enable 0x0020 /* complete */ +#define HCI_CMD_Write_Authentication_Enable 0x0020 /* complete */ struct hciWriteAuthEnable { uint8_t authRequired; } __packed; @@ -1186,13 +1274,15 @@ struct hciCmplWriteAuthEnable { uint8_t status; } __packed; -#define HCI_CMD_Read_Encryption_Mode 0x0021 /* complete *//* deprecated in BT 2.1+ */ +#define HCI_CMD_Read_Encryption_Mode \ + 0x0021 /* complete */ /* deprecated in BT 2.1+ */ struct hciCmplReadEncryptionMode { uint8_t status; uint8_t encrRequired; } __packed; -#define HCI_CMD_Write_Encryption_Mode 0x0022 /* complete *//* deprecated in BT 2.1+ */ +#define HCI_CMD_Write_Encryption_Mode \ + 0x0022 /* complete */ /* deprecated in BT 2.1+ */ struct hciWriteEncryptionMode { uint8_t encrRequired; } __packed; @@ -1200,13 +1290,13 @@ struct hciCmplWriteEncryptionMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Class_Of_Device 0x0023 /* complete */ +#define HCI_CMD_Read_Class_Of_Device 0x0023 /* complete */ struct hciCmplReadClassOfDevice { uint8_t status; uint8_t cls[3]; } __packed; -#define HCI_CMD_Write_Class_Of_Device 0x0024 /* complete */ +#define HCI_CMD_Write_Class_Of_Device 0x0024 /* complete */ struct hciWriteClassOfDevice { uint8_t cls[3]; } __packed; @@ -1214,13 +1304,13 @@ struct hciCmplWriteClassOfDevice { uint8_t status; } __packed; -#define HCI_CMD_Read_Voice_Setting 0x0025 /* complete */ +#define HCI_CMD_Read_Voice_Setting 0x0025 /* complete */ struct hciCmplReadVoiceSetting { uint8_t status; uint16_t voiceSetting; } __packed; -#define HCI_CMD_Write_Voice_Setting 0x0026 /* complete */ +#define HCI_CMD_Write_Voice_Setting 0x0026 /* complete */ struct hciWriteVoiceSetting { uint16_t voiceSetting; } __packed; @@ -1228,7 +1318,7 @@ struct hciCmplWriteVoiceSetting { uint8_t status; } __packed; -#define HCI_CMD_Read_Automatic_Flush_Timeout 0x0027 /* complete */ +#define HCI_CMD_Read_Automatic_Flush_Timeout 0x0027 /* complete */ struct hciReadAutoFlushTimeout { uint16_t conn; } __packed; @@ -1238,7 +1328,7 @@ struct hciCmplReadAutoFlushTimeout { uint16_t timeout; } __packed; -#define HCI_CMD_Write_Automatic_Flush_Timeout 0x0028 /* complete */ +#define HCI_CMD_Write_Automatic_Flush_Timeout 0x0028 /* complete */ struct hciWriteAutoFlushTimeout { uint16_t conn; uint16_t timeout; @@ -1248,13 +1338,13 @@ struct hciCmplWriteAutoFlushTimeout { uint16_t conn; } __packed; -#define HCI_CMD_Read_Num_Broadcast_Retransmissions 0x0029 /* complete */ +#define HCI_CMD_Read_Num_Broadcast_Retransmissions 0x0029 /* complete */ struct hciCmplReadNumBroadcastRetransmissions { uint8_t status; uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */ } __packed; -#define HCI_CMD_Write_Num_Broadcast_Retransmissions 0x002A /* complete */ +#define HCI_CMD_Write_Num_Broadcast_Retransmissions 0x002A /* complete */ struct hciWriteNumBroadcastRetransmissions { uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */ } __packed; @@ -1262,13 +1352,13 @@ struct hciCmplWriteNumBroadcastRetransmissions { uint8_t status; } __packed; -#define HCI_CMD_Read_Hold_Mode_Activity 0x002B /* complete */ +#define HCI_CMD_Read_Hold_Mode_Activity 0x002B /* complete */ struct hciCmplReadHoldModeActivity { uint8_t status; uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */ } __packed; -#define HCI_CMD_Write_Hold_Mode_Activity 0x002C /* complete */ +#define HCI_CMD_Write_Hold_Mode_Activity 0x002C /* complete */ struct hciWriteHoldModeActivity { uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */ } __packed; @@ -1276,7 +1366,7 @@ struct hciCmplWriteHoldModeActivity { uint8_t status; } __packed; -#define HCI_CMD_Read_Transmit_Power_Level 0x002D /* complete */ +#define HCI_CMD_Read_Transmit_Power_Level 0x002D /* complete */ struct hciReadTransmitPowerLevel { uint16_t conn; uint8_t max; /* else current */ @@ -1287,13 +1377,13 @@ struct hciCmplReadTransmitPowerLevel { uint8_t txPower; /* actually an int8_t */ } __packed; -#define HCI_CMD_Read_SCO_Flow_Control_Enable 0x002E /* complete */ +#define HCI_CMD_Read_SCO_Flow_Control_Enable 0x002E /* complete */ struct hciCmplReadSyncFlowCtrl { uint8_t status; uint8_t syncFlowCtrlOn; } __packed; -#define HCI_CMD_Write_SCO_Flow_Control_Enable 0x002F /* complete */ +#define HCI_CMD_Write_SCO_Flow_Control_Enable 0x002F /* complete */ struct hciWriteSyncFlowCtrlEnable { uint8_t syncFlowCtrlOn; } __packed; @@ -1301,7 +1391,7 @@ struct hciCmplWriteSyncFlowCtrlEnable { uint8_t status; } __packed; -#define HCI_CMD_Set_Controller_To_Host_Flow_Control 0x0031 /* complete */ +#define HCI_CMD_Set_Controller_To_Host_Flow_Control 0x0031 /* complete */ struct hciSetControllerToHostFlowControl { uint8_t chipToHostFlowCtrl; /* bitmask of HCI_TO_HOST_FLOW_CTRL_* */ } __packed; @@ -1309,7 +1399,7 @@ struct hciCmplSetControllerToHostFlowControl { uint8_t status; } __packed; -#define HCI_CMD_Host_Buffer_Size 0x0033 /* complete */ +#define HCI_CMD_Host_Buffer_Size 0x0033 /* complete */ struct hciHostBufferSize { uint16_t maxAclPacket; uint8_t maxScoPacket; @@ -1320,7 +1410,9 @@ struct hciCmplHostBufferSize { uint8_t status; } __packed; -#define HCI_CMD_Host_Number_Of_Completed_Packets 0x0035 /* special: can be sent anytime (not subj to cmd flow control), does not generate events unless error */ +#define HCI_CMD_Host_Number_Of_Completed_Packets \ + 0x0035 /* special: can be sent anytime (not subj to cmd flow control), \ + does not generate events unless error */ struct hciHostNumberOfCompletedPacketsItem { uint16_t conn; uint16_t numCompletedPackets; @@ -1330,33 +1422,35 @@ struct hciHostNumberOfCompletedPackets { struct hciHostNumberOfCompletedPacketsItem items[]; } __packed; -#define HCI_CMD_Read_Link_Supervision_Timeout 0x0036 /* complete */ +#define HCI_CMD_Read_Link_Supervision_Timeout 0x0036 /* complete */ struct hciReadLinkSupervisionTimeout { uint16_t conn; } __packed; struct hciCmplReadLinkSupervisionTimeout { uint8_t status; uint16_t conn; - uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */ + uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required + support 0x0190 - 0xffff */ } __packed; -#define HCI_CMD_Write_Link_Supervision_Timeout 0x0037 /* complete */ +#define HCI_CMD_Write_Link_Supervision_Timeout 0x0037 /* complete */ struct hciWriteLinkSupervisionTimeout { uint16_t conn; - uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */ + uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required + support 0x0190 - 0xffff */ } __packed; struct hciCmplWriteLinkSupervisionTimeout { uint8_t status; uint16_t conn; } __packed; -#define HCI_CMD_Read_Number_Of_Supported_IAC 0x0038 /* complete */ +#define HCI_CMD_Read_Number_Of_Supported_IAC 0x0038 /* complete */ struct hciCmplReadNumberOfSupportedIac { uint8_t status; uint8_t numSupportedIac; } __packed; -#define HCI_CMD_Read_Current_IAC_LAP 0x0039 /* complete */ +#define HCI_CMD_Read_Current_IAC_LAP 0x0039 /* complete */ struct hciCmplReadCurrentIacItem { uint8_t iac_lap[3]; } __packed; @@ -1366,7 +1460,7 @@ struct hciCmplReadCurrentIac { struct hciCmplReadCurrentIacItem items[]; } __packed; -#define HCI_CMD_Write_Current_IAC_LAP 0x003A /* complete */ +#define HCI_CMD_Write_Current_IAC_LAP 0x003A /* complete */ struct hciWriteCurrentIacLapItem { uint8_t iacLap[3]; } __packed; @@ -1378,13 +1472,13 @@ struct hciCmplWriteCurrentIacLap { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Period_Mode 0x003B /* complete */ +#define HCI_CMD_Read_Page_Scan_Period_Mode 0x003B /* complete */ struct hciCmplReadPageScanPeriodMode { uint8_t status; uint8_t mode; } __packed; -#define HCI_CMD_Write_Page_Scan_Period_Mode 0x003C /* complete */ +#define HCI_CMD_Write_Page_Scan_Period_Mode 0x003C /* complete */ struct hciWritePageScanPeriodMode { uint8_t mode; } __packed; @@ -1392,13 +1486,15 @@ struct hciCmplWritePageScanPeriodMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Mode 0x003D /* complete *//* deprecated in BT 1.2+ */ +#define HCI_CMD_Read_Page_Scan_Mode \ + 0x003D /* complete */ /* deprecated in BT 1.2+ */ struct hciCmplReadPageScanMode { uint8_t status; uint8_t pageScanMode; /* nonzero modes are optional */ } __packed; -#define HCI_CMD_Write_Page_Scan_Mode 0x003E /* complete *//* deprecated in BT 1.2+ */ +#define HCI_CMD_Write_Page_Scan_Mode \ + 0x003E /* complete */ /* deprecated in BT 1.2+ */ struct hciWritePageScanMode { uint8_t pageScanMode; /* nonzero modes are optional */ } __packed; @@ -1406,10 +1502,9 @@ struct hciCmplWritePageScanMode { uint8_t status; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Set_AFH_Host_Channel_Classification 0x003F /* complete */ +#define HCI_CMD_Set_AFH_Host_Channel_Classification 0x003F /* complete */ struct hciSetAfhHostChannelClassification { uint8_t channels[10]; } __packed; @@ -1417,13 +1512,13 @@ struct hciCmplSetAfhHostChannelClassification { uint8_t status; } __packed; -#define HCI_CMD_Read_Inquiry_Scan_Type 0x0042 /* complete */ +#define HCI_CMD_Read_Inquiry_Scan_Type 0x0042 /* complete */ struct hciCmplReadInquiryScanType { uint8_t status; uint8_t interlaced; /* optional */ } __packed; -#define HCI_CMD_Write_Inquiry_Scan_Type 0x0043 /* complete */ +#define HCI_CMD_Write_Inquiry_Scan_Type 0x0043 /* complete */ struct hciWriteInquiryScanType { uint8_t interlaced; /* optional */ } __packed; @@ -1431,13 +1526,13 @@ struct hciCmplWriteInquiryScanType { uint8_t status; } __packed; -#define HCI_CMD_Read_Inquiry_Mode 0x0044 /* complete */ +#define HCI_CMD_Read_Inquiry_Mode 0x0044 /* complete */ struct hciCmplReadInquryMode { uint8_t status; uint8_t inqMode; /* HCI_INQ_MODE_* */ } __packed; -#define HCI_CMD_Write_Inquiry_Mode 0x0045 /* complete */ +#define HCI_CMD_Write_Inquiry_Mode 0x0045 /* complete */ struct hciWriteInquiryMode { uint8_t inqMode; /* HCI_INQ_MODE_* */ } __packed; @@ -1445,13 +1540,13 @@ struct hciCmplWriteInquiryMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Type 0x0046 /* complete */ +#define HCI_CMD_Read_Page_Scan_Type 0x0046 /* complete */ struct hciCmplReadPageScanType { uint8_t status; uint8_t interlaced; /* optional */ } __packed; -#define HCI_CMD_Write_Page_Scan_Type 0x0047 /* complete */ +#define HCI_CMD_Write_Page_Scan_Type 0x0047 /* complete */ struct hciWritePageScanType { uint8_t interlaced; /* optional */ } __packed; @@ -1459,13 +1554,13 @@ struct hciCmplWritePageScanType { uint8_t status; } __packed; -#define HCI_CMD_Read_AFH_Channel_Assessment_Mode 0x0048 /* complete */ +#define HCI_CMD_Read_AFH_Channel_Assessment_Mode 0x0048 /* complete */ struct hciCmplReadAfhChannelAssessment { uint8_t status; uint8_t channelAssessmentEnabled; } __packed; -#define HCI_CMD_Write_AFH_Channel_Assessment_Mode 0x0049 /* complete */ +#define HCI_CMD_Write_AFH_Channel_Assessment_Mode 0x0049 /* complete */ struct hciWriteAfhChannelAssessment { uint8_t channelAssessmentEnabled; } __packed; @@ -1473,17 +1568,16 @@ struct hciCmplWriteAfhChannelAssessment { uint8_t status; } __packed; - /* ==== BT 2.1 ==== */ -#define HCI_CMD_Read_Extended_Inquiry_Response 0x0051 /* complete */ +#define HCI_CMD_Read_Extended_Inquiry_Response 0x0051 /* complete */ struct hciCmplReadEIR { uint8_t status; uint8_t useFec; uint8_t data[240]; } __packed; -#define HCI_CMD_Write_Extended_Inquiry_Response 0x0052 /* complete */ +#define HCI_CMD_Write_Extended_Inquiry_Response 0x0052 /* complete */ struct hciWriteEIR { uint8_t useFec; uint8_t data[240]; @@ -1492,18 +1586,18 @@ struct hciCmplWriteEIR { uint8_t status; } __packed; -#define HCI_CMD_Refresh_Encryption_Key 0x0052 /* status */ +#define HCI_CMD_Refresh_Encryption_Key 0x0052 /* status */ struct hciRefreshEncryptionKey { uint16_t conn; } __packed; -#define HCI_CMD_Read_Simple_Pairing_Mode 0x0055 /* complete */ +#define HCI_CMD_Read_Simple_Pairing_Mode 0x0055 /* complete */ struct hciCmplReadSimplePairingMore { uint8_t status; uint8_t useSsp; } __packed; -#define HCI_CMD_Write_Simple_Pairing_Mode 0x0056 /* complete */ +#define HCI_CMD_Write_Simple_Pairing_Mode 0x0056 /* complete */ struct hciWriteSimplePairingMode { uint8_t useSsp; } __packed; @@ -1511,20 +1605,22 @@ struct hciCmplWriteSimplePairingMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Local_OOB_Data 0x0057 /* complete */ +#define HCI_CMD_Read_Local_OOB_Data 0x0057 /* complete */ struct hciCmplReadLocalOobData { uint8_t status; uint8_t C[16]; uint8_t R[16]; } __packed; -#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level 0x0058 /* complete */ +#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level \ + 0x0058 /* complete \ + */ struct hciCmplReadInquiryTransmitPowerLevel { uint8_t status; uint8_t power; /* actually an int8_t */ } __packed; -#define HCI_CMD_Write_Inquiry_Transmit_Power_Level 0x0059 /* complete */ +#define HCI_CMD_Write_Inquiry_Transmit_Power_Level 0x0059 /* complete */ struct hciWriteInquiryTransmitPowerLevel { uint8_t power; /* actually an int8_t */ } __packed; @@ -1532,13 +1628,13 @@ struct hciCmplWriteInquiryTransmitPowerLevel { uint8_t status; } __packed; -#define HCI_CMD_Read_Default_Erroneous_Data_Reporting 0x005A /* complete */ +#define HCI_CMD_Read_Default_Erroneous_Data_Reporting 0x005A /* complete */ struct hciCmplReadErroneousDataReporting { uint8_t status; uint8_t reportingEnabled; } __packed; -#define HCI_CMD_Write_Default_Erroneous_Data_Reporting 0x005B /* complete */ +#define HCI_CMD_Write_Default_Erroneous_Data_Reporting 0x005B /* complete */ struct hciWriteErroneousDataReporting { uint8_t reportingEnabled; } __packed; @@ -1546,13 +1642,14 @@ struct hciCmplWriteErroneousDataReporting { uint8_t status; } __packed; -#define HCI_CMD_Enhanced_Flush 0x005F /* status */ +#define HCI_CMD_Enhanced_Flush 0x005F /* status */ struct hciEnhancedFlush { uint16_t conn; - uint8_t which; /* 0 is the only value - flush auto-flushable packets only */ + uint8_t which; /* 0 is the only value - flush auto-flushable packets + only */ } __packed; -#define HCI_CMD_Send_Keypress_Notification 0x0060 /* complete */ +#define HCI_CMD_Send_Keypress_Notification 0x0060 /* complete */ struct hciSendKeypressNotification { uint8_t mac[6]; uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */ @@ -1562,24 +1659,25 @@ struct hciCmplSendKeypressNotification { uint8_t mac[6]; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Read_Logical_Link_Accept_Timeout 0x0061 /* complete */ +#define HCI_CMD_Read_Logical_Link_Accept_Timeout 0x0061 /* complete */ struct hciCmplReadLogicalLinkTimeout { uint8_t status; - uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */ + uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support + 0x00A0..0xB540 */ } __packed; -#define HCI_CMD_Write_Logical_Link_Accept_Timeout 0x0062 /* complete */ +#define HCI_CMD_Write_Logical_Link_Accept_Timeout 0x0062 /* complete */ struct hciWriteLogicalLinkTimeout { - uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */ + uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support + 0x00A0..0xB540 */ } __packed; struct hciCmplWriteLogicalLinkTimeout { uint8_t status; } __packed; -#define HCI_CMD_Set_Event_Mask_Page_2 0x0063 /* complete */ +#define HCI_CMD_Set_Event_Mask_Page_2 0x0063 /* complete */ struct hciSetEventMaskPage2 { uint64_t mask; /* bitmask of HCI_EVENT_P2_* */ } __packed; @@ -1587,7 +1685,7 @@ struct hciCmplSetEventMaskPage2 { uint8_t status; } __packed; -#define HCI_CMD_Read_Location_Data 0x0064 /* complete */ +#define HCI_CMD_Read_Location_Data 0x0064 /* complete */ struct hciCmplReadLocationData { uint8_t status; uint8_t regulatoryDomainKnown; @@ -1596,7 +1694,7 @@ struct hciCmplReadLocationData { uint8_t mainsPowered; } __packed; -#define HCI_CMD_Write_Location_Data 0x0065 /* complete */ +#define HCI_CMD_Write_Location_Data 0x0065 /* complete */ struct hciWriteLocationData { uint8_t regulatoryDomainKnown; uint16_t domain; /* ISO3166-1 code if known, else 0x5858 'XX' */ @@ -1607,21 +1705,23 @@ struct hciCmplWriteLocationData { uint8_t status; } __packed; -#define HCI_CMD_Read_Flow_Control_Mode 0x0066 /* complete */ +#define HCI_CMD_Read_Flow_Control_Mode 0x0066 /* complete */ struct hciCmplReadFlowControlMode { uint8_t status; - uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */ + uint8_t blockBased; /* block based is for amp, packed-based is for + BR/EDR */ } __packed; -#define HCI_CMD_Write_Flow_Control_mode 0x0067 /* complete */ +#define HCI_CMD_Write_Flow_Control_mode 0x0067 /* complete */ struct hciWriteFlowControlMode { - uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */ + uint8_t blockBased; /* block based is for amp, packed-based is for + BR/EDR */ } __packed; struct hciCmplWriteFlowcontrolMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Enhanced_Transmit_Power_Level 0x0068 /* complete */ +#define HCI_CMD_Read_Enhanced_Transmit_Power_Level 0x0068 /* complete */ struct hciReadEnhancedTransmitPowerLevel { uint16_t conn; uint8_t max; /* else currurent is read */ @@ -1634,7 +1734,7 @@ struct hciCmplReadEnhancedTransmitPowerLevel { uint8_t txLevel8DPSK; /* actually an int8_t */ } __packed; -#define HCI_CMD_Read_Best_Effort_Flush_Timeout 0x0069 /* complete */ +#define HCI_CMD_Read_Best_Effort_Flush_Timeout 0x0069 /* complete */ struct hciReadBestEffortFlushTimeout { uint16_t logicalLinkHandle; } __packed; @@ -1643,7 +1743,7 @@ struct hciCmplReadBestEffortFlushTimeout { uint32_t bestEffortFlushTimeout; /* in microseconds */ } __packed; -#define HCI_CMD_Write_Best_Effort_Flush_Timeout 0x006A /* complete */ +#define HCI_CMD_Write_Best_Effort_Flush_Timeout 0x006A /* complete */ struct hciWriteBestEffortFlushTimeout { uint16_t logicalLinkHandle; uint32_t bestEffortFlushTimeout; /* in microseconds */ @@ -1652,23 +1752,22 @@ struct hciCmplWriteBestEffortFlushTimeout { uint8_t status; } __packed; -#define HCI_CMD_Short_Range_Mode 0x006B /* status */ +#define HCI_CMD_Short_Range_Mode 0x006B /* status */ struct hciShortRangeMode { uint8_t physicalLinkHandle; uint8_t shortRangeModeEnabled; } __packed; - /* ==== BT 4.0 ==== */ -#define HCI_CMD_Read_LE_Host_Supported 0x006C /* complete */ +#define HCI_CMD_Read_LE_Host_Supported 0x006C /* complete */ struct hciCmplReadLeHostSupported { uint8_t status; uint8_t leSupportedHost; uint8_t simultaneousLeHost; } __packed; -#define HCI_CMD_Write_LE_Host_Supported 0x006D /* complete */ +#define HCI_CMD_Write_LE_Host_Supported 0x006D /* complete */ struct hciWriteLeHostSupported { uint8_t leSupportedHost; uint8_t simultaneousLeHost; @@ -1677,10 +1776,9 @@ struct hciCmplWriteLeHostSupported { uint8_t status; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_Set_MWS_Channel_Parameters 0x006E /* complete */ +#define HCI_CMD_Set_MWS_Channel_Parameters 0x006E /* complete */ struct hciSetMwsChannelParams { uint8_t mwsEnabled; uint16_t mwsChannelRxCenterFreq; /* in MHz */ @@ -1693,7 +1791,7 @@ struct hciCmplSetMwsChannelParams { uint8_t status; } __packed; -#define HCI_CMD_Set_External_Frame_Configuration 0x006F /* complete */ +#define HCI_CMD_Set_External_Frame_Configuration 0x006F /* complete */ struct hciSetExternalFrameConfigItem { uint16_t periodDuration; /* in microseconds */ uint8_t periodType; /* HCI_PERIOD_TYPE_* */ @@ -1709,7 +1807,7 @@ struct hciCmplSetExternalFrameConfig { uint8_t status; } __packed; -#define HCI_CMD_Set_MWS_Signalling 0x0070 /* complete */ +#define HCI_CMD_Set_MWS_Signalling 0x0070 /* complete */ struct hciSetMwsSignalling { uint16_t mwsRxAssertOffset; /* all of these are in microseconds */ uint16_t mwsRxAssertJitter; @@ -1747,7 +1845,7 @@ struct hciCmplSetMwsSignalling { uint16_t _802TxOnDeassertJitter; } __packed; -#define HCI_CMD_Set_MWS_Transport_Layer 0x0071 /* complete */ +#define HCI_CMD_Set_MWS_Transport_Layer 0x0071 /* complete */ struct hciSetMwsTransportLayer { uint8_t transportLayer; uint32_t toMwsBaudRate; /* in byte/sec */ @@ -1757,7 +1855,7 @@ struct hciCmplSetMwsTransportLayer { uint8_t status; } __packed; -#define HCI_CMD_Set_MWS_Scan_Frequency_Table 0x0072 /* complete */ +#define HCI_CMD_Set_MWS_Scan_Frequency_Table 0x0072 /* complete */ struct hciSetMwsScanFrequencyTableItem { uint16_t scanFreqLow; /*in MHz */ uint16_t scanFreqHigh; /*in MHz */ @@ -1770,7 +1868,7 @@ struct hciCmplSetMwsScanFrequencyTable { uint8_t status; } __packed; -#define HCI_CMD_Set_MWS_PATTERN_Configuration 0x0073 /* complete */ +#define HCI_CMD_Set_MWS_PATTERN_Configuration 0x0073 /* complete */ struct hciSetMwsPatternConfigItem { uint16_t intervalDuration; /* in microseconds */ uint8_t intervalType; /* HCI_MWS_INTERVAL_TYPE_* */ @@ -1784,7 +1882,7 @@ struct hciCmplSetMwsPatternConfig { uint8_t status; } __packed; -#define HCI_CMD_Set_Reserved_LT_ADDR 0x0074 /* complete */ +#define HCI_CMD_Set_Reserved_LT_ADDR 0x0074 /* complete */ struct hciSetReservedLtAddr { uint8_t ltAddr; } __packed; @@ -1793,7 +1891,7 @@ struct hciCmplSetReservedLtAddr { uint8_t ltAddr; } __packed; -#define HCI_CMD_Delete_Reserved_LT_ADDR 0x0075 /* complete */ +#define HCI_CMD_Delete_Reserved_LT_ADDR 0x0075 /* complete */ struct hciDeleteReservedLtAddr { uint8_t ltAddr; } __packed; @@ -1802,7 +1900,7 @@ struct hciCmplDeleteReservedLtAddr { uint8_t ltAddr; } __packed; -#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data 0x0076 /* complete */ +#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data 0x0076 /* complete */ struct hciSetConnlessSlaveBroadcastData { uint8_t ltAddr; uint8_t fragment; /* HCI_CONNLESS_FRAG_TYPE_* */ @@ -1814,7 +1912,7 @@ struct hciCmplSetConnlessSlaveBroadcastData { uint8_t ltAddr; } __packed; -#define HCI_CMD_Read_Synchronisation_Train_Parameters 0x0077 /* complete */ +#define HCI_CMD_Read_Synchronisation_Train_Parameters 0x0077 /* complete */ struct hciCmplReadSyncTrainParams { uint8_t status; uint16_t interval; @@ -1822,7 +1920,7 @@ struct hciCmplReadSyncTrainParams { uint8_t serviceData; } __packed; -#define HCI_CMD_Write_Synchronisation_Train_Parameters 0x0078 /* complete */ +#define HCI_CMD_Write_Synchronisation_Train_Parameters 0x0078 /* complete */ struct hciWriteSyncTrainParams { uint16_t intMin; uint16_t intMax; @@ -1834,13 +1932,13 @@ struct hciCmplWriteSyncTrainParams { uint16_t interval; } __packed; -#define HCI_CMD_Read_Secure_Connections_Host_Support 0x0079 /* complete */ +#define HCI_CMD_Read_Secure_Connections_Host_Support 0x0079 /* complete */ struct hciCmplReadSecureConnectionsHostSupport { uint8_t status; uint8_t secureConnectionsSupported; } __packed; -#define HCI_CMD_Write_Secure_Connections_Host_Support 0x007A /* complete */ +#define HCI_CMD_Write_Secure_Connections_Host_Support 0x007A /* complete */ struct hciWriteSecureConnectionsHostSupport { uint8_t secureConnectionsSupported; } __packed; @@ -1848,7 +1946,7 @@ struct hciCmplWriteSecureConnectionsHostSupport { uint8_t status; } __packed; -#define HCI_CMD_Read_Authenticated_Payload_Timeout 0x007B /* complete */ +#define HCI_CMD_Read_Authenticated_Payload_Timeout 0x007B /* complete */ struct hciReadAuthedPayloadTimeout { uint16_t conn; } __packed; @@ -1858,7 +1956,7 @@ struct hciCmplReadAuthedPayloadTimeout { uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */ } __packed; -#define HCI_CMD_Write_Authenticated_Payload_Timeout 0x007C /* complete */ +#define HCI_CMD_Write_Authenticated_Payload_Timeout 0x007C /* complete */ struct hciWriteAuthedPayloadTimeout { uint16_t conn; uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */ @@ -1868,7 +1966,7 @@ struct hciCmplWriteAuthedPayloadTimeout { uint16_t conn; } __packed; -#define HCI_CMD_Read_Local_OOB_Extended_Data 0x007D /* complete */ +#define HCI_CMD_Read_Local_OOB_Extended_Data 0x007D /* complete */ struct hciCmplReadLocalOobExtendedData { uint8_t status; uint8_t C_192[16]; @@ -1877,13 +1975,13 @@ struct hciCmplReadLocalOobExtendedData { uint8_t R_256[16]; } __packed; -#define HCI_CMD_Read_Extended_Page_Timeout 0x007E /* complete */ +#define HCI_CMD_Read_Extended_Page_Timeout 0x007E /* complete */ struct hciCmplReadExtendedPageTimeout { uint8_t status; uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; -#define HCI_CMD_Write_Extended_Page_Timeout 0x007F /* complete */ +#define HCI_CMD_Write_Extended_Page_Timeout 0x007F /* complete */ struct hciWriteExtendedPageTimeout { uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; @@ -1891,13 +1989,13 @@ struct hciCmplWriteExtendedPageTimeout { uint8_t status; } __packed; -#define HCI_CMD_Read_Extended_Inquiry_Length 0x0080 /* complete */ +#define HCI_CMD_Read_Extended_Inquiry_Length 0x0080 /* complete */ struct hciCmplReadExtendedInquiryLength { uint8_t status; uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; -#define HCI_CMD_Write_Extended_Inquiry_Length 0x0081 /* complete */ +#define HCI_CMD_Write_Extended_Inquiry_Length 0x0081 /* complete */ struct hciWriteExtendedInquiryLength { uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; @@ -1905,16 +2003,11 @@ struct hciCmplWriteExtendedInquiryLength { uint8_t status; } __packed; - - - - -#define HCI_OGF_Informational 4 - +#define HCI_OGF_Informational 4 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Read_Local_Version_Information 0x0001 /* complete */ +#define HCI_CMD_Read_Local_Version_Information 0x0001 /* complete */ struct hciCmplReadLocalVersion { uint8_t status; uint8_t hciVersion; /* HCI_VERSION_* */ @@ -1924,19 +2017,19 @@ struct hciCmplReadLocalVersion { uint16_t lmpSubversion; } __packed; -#define HCI_CMD_Read_Local_Supported_Commands 0x0002 /* complete */ +#define HCI_CMD_Read_Local_Supported_Commands 0x0002 /* complete */ struct hciCmplReadLocalSupportedCommands { uint8_t status; uint64_t bitfield; } __packed; -#define HCI_CMD_Read_Local_Supported_Features 0x0003 /* complete */ +#define HCI_CMD_Read_Local_Supported_Features 0x0003 /* complete */ struct hciCmplReadLocalSupportedFeatures { uint8_t status; - uint64_t features; /* bitmask of HCI_LMP_FTR_* */ + uint64_t features; /* bitmask of HCI_LMP_FTR_* */ } __packed; -#define HCI_CMD_Read_Local_Extended_Features 0x0004 /* complete */ +#define HCI_CMD_Read_Local_Extended_Features 0x0004 /* complete */ struct hciReadLocalExtendedFeatures { uint8_t page; } __packed; @@ -1947,7 +2040,7 @@ struct hciCmplReadLocalExtendedFeatures { uint64_t features; /* bitmask of HCI_LMP_EXT_FTR_P* */ } __packed; -#define HCI_CMD_Read_Buffer_Size 0x0005 /* complete */ +#define HCI_CMD_Read_Buffer_Size 0x0005 /* complete */ struct hciCmplReadBufferSize { uint8_t status; uint16_t aclBufferLen; @@ -1956,16 +2049,15 @@ struct hciCmplReadBufferSize { uint16_t numScoBuffers; } __packed; -#define HCI_CMD_Read_BD_ADDR 0x0009 /* complete */ +#define HCI_CMD_Read_BD_ADDR 0x0009 /* complete */ struct hciCmplReadBdAddr { uint8_t status; uint8_t mac[6]; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Read_Data_Block_Size 0x000A /* complete */ +#define HCI_CMD_Read_Data_Block_Size 0x000A /* complete */ struct hciCmplReadDataBlockSize { uint8_t status; uint16_t maxAclDataPacketLen; @@ -1973,30 +2065,24 @@ struct hciCmplReadDataBlockSize { uint16_t totalNumDataBlocks; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_Read_Local_Supported_Codecs 0x000B /* complete */ +#define HCI_CMD_Read_Local_Supported_Codecs 0x000B /* complete */ struct hciCmplReadLocalSupportedCodecs { uint8_t status; uint8_t numSupportedCodecs; uint8_t codecs[]; -/* these follow, but due to var array cannot be declared here: - uint8_t numVendorCodecs; - uint32_t vendorCodecs[]; -*/ + /* these follow, but due to var array cannot be declared here: + uint8_t numVendorCodecs; + uint32_t vendorCodecs[]; + */ } __packed; - - - - -#define HCI_OGF_Status 5 - +#define HCI_OGF_Status 5 /* == BT 1.1 == */ -#define HCI_CMD_Read_Failed_Contact_Counter 0x0001 /* complete */ +#define HCI_CMD_Read_Failed_Contact_Counter 0x0001 /* complete */ struct hciReadFailedContactCounter { uint16_t conn; } __packed; @@ -2006,7 +2092,7 @@ struct hciCmplReadFailedContactCounter { uint16_t counter; } __packed; -#define HCI_CMD_Reset_Failed_Contact_Counter 0x0002 /* complete */ +#define HCI_CMD_Reset_Failed_Contact_Counter 0x0002 /* complete */ struct hciResetFailedContactCounter { uint16_t conn; } __packed; @@ -2015,7 +2101,7 @@ struct hciCmplResetFailedContactCounter { uint16_t conn; } __packed; -#define HCI_CMD_Read_Link_Quality 0x0003 /* complete */ +#define HCI_CMD_Read_Link_Quality 0x0003 /* complete */ struct hciReadLinkQuality { uint16_t conn; } __packed; @@ -2025,7 +2111,7 @@ struct hciCmplReadLinkQuality { uint8_t quality; } __packed; -#define HCI_CMD_Read_RSSI 0x0005 /* complete */ +#define HCI_CMD_Read_RSSI 0x0005 /* complete */ struct hciReadRssi { uint16_t conn; } __packed; @@ -2035,10 +2121,9 @@ struct hciCmplReadRssi { uint8_t RSSI; /* actually an int8_t */ } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Read_AFH_Channel_Map 0x0006 /* complete */ +#define HCI_CMD_Read_AFH_Channel_Map 0x0006 /* complete */ struct hciReadAfhChannelMap { uint16_t conn; } __packed; @@ -2048,7 +2133,7 @@ struct hciCmplReadAfhChannelMap { uint8_t map[10]; } __packed; -#define HCI_CMD_Read_Clock 0x0007 /* complete */ +#define HCI_CMD_Read_Clock 0x0007 /* complete */ struct hciReadClock { uint16_t conn; uint8_t readRemote; /* else reads local and ignores conn */ @@ -2060,10 +2145,9 @@ struct hciCmplReadClock { uint16_t accuracy; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Read_Encryption_Key_Size 0x0008 /* complete */ +#define HCI_CMD_Read_Encryption_Key_Size 0x0008 /* complete */ struct hciReadEncrKeySize { uint16_t conn; } __packed; @@ -2073,7 +2157,7 @@ struct hciCmplReadEncrKeySize { uint8_t keySize; } __packed; -#define HCI_CMD_Read_Local_AMP_Info 0x0009 /* complete */ +#define HCI_CMD_Read_Local_AMP_Info 0x0009 /* complete */ struct hciCmplReadLocalAmpInfo { uint8_t status; uint8_t ampStatus; @@ -2088,7 +2172,7 @@ struct hciCmplReadLocalAmpInfo { uint32_t bestEffortFlushTimeout; } __packed; -#define HCI_CMD_Read_Local_AMP_ASSOC 0x000A /* complete */ +#define HCI_CMD_Read_Local_AMP_ASSOC 0x000A /* complete */ struct hciReadLocalAmpAssoc { uint8_t physicalLinkHandle; uint16_t lengthSoFar; @@ -2101,7 +2185,7 @@ struct hciCmplReadLocalAmpAssoc { uint8_t ampAssocFragment[]; /* 1.. 248 byutes */ } __packed; -#define HCI_CMD_Write_Remote_AMP_ASSOC 0x000B /* complete */ +#define HCI_CMD_Write_Remote_AMP_ASSOC 0x000B /* complete */ struct hciWriteRemoteAmpAssoc { uint8_t physicalLinkHandle; uint16_t lengthSoFar; @@ -2115,7 +2199,7 @@ struct hciCmplWriteRemoteAmpAssoc { /* ==== BT 4.1 ==== */ -#define HCI_CMD_Get_MWS_Transport_Layer_Configuration 0x000C /* complete */ +#define HCI_CMD_Get_MWS_Transport_Layer_Configuration 0x000C /* complete */ struct hciCmplGetMwsTransportLayerConfigItem { uint8_t transportLayer; uint8_t numBaudRates; @@ -2127,13 +2211,15 @@ struct hciCmplGetMwsTransportLayerConfigBandwidthItem { struct hciCmplGetMwsTransportLayerConfig { uint8_t status; uint8_t numTransports; - struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports items */ -/* this follows: - struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] // sum(items[].numbaudRates) items -*/ + struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports + items */ + /* this follows: + struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] // + sum(items[].numbaudRates) items + */ } __packed; -#define HCI_CMD_Set_Triggered_Clock_Capture 0x000D /* complete */ +#define HCI_CMD_Set_Triggered_Clock_Capture 0x000D /* complete */ struct hciSetTriggeredClockCapture { uint16_t conn; uint8_t enable; @@ -2145,16 +2231,11 @@ struct hciCmplSetTriggeredClockCapture { uint8_t status; } __packed; - - - - -#define HCI_OGF_LE 8 - +#define HCI_OGF_LE 8 /* ==== BT 4.0 ==== */ -#define HCI_CMD_LE_Set_Event_Mask 0x0001 /* complete */ +#define HCI_CMD_LE_Set_Event_Mask 0x0001 /* complete */ struct hciLeSetEventMask { uint64_t events; /* bitmask of HCI_LE_EVENT_* */ } __packed; @@ -2162,28 +2243,28 @@ struct hciCmplLeSetEventMask { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Buffer_Size 0x0002 /* complete */ +#define HCI_CMD_LE_Read_Buffer_Size 0x0002 /* complete */ struct hciCmplLeReadBufferSize { uint8_t status; uint16_t leBufferSize; uint8_t leNumBuffers; } __packed; -#define HCI_CMD_LE_Read_Local_Supported_Features 0x0003 /* complete */ +#define HCI_CMD_LE_Read_Local_Supported_Features 0x0003 /* complete */ struct hciCmplLeReadLocalSupportedFeatures { uint8_t status; uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */ } __packed; -#define HCI_CMD_LE_Set_Random_Address 0x0005 /* complete */ -struct hciLeSetRandomAddress{ +#define HCI_CMD_LE_Set_Random_Address 0x0005 /* complete */ +struct hciLeSetRandomAddress { uint8_t mac[6]; } __packed; -struct hciCmplLeSetRandomAddress{ +struct hciCmplLeSetRandomAddress { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Adv_Params 0x0006 /* complete */ +#define HCI_CMD_LE_Set_Adv_Params 0x0006 /* complete */ struct hciLeSetAdvParams { uint16_t advIntervalMin; uint16_t advIntervalMax; @@ -2198,13 +2279,13 @@ struct hciCmplLeSetAdvParams { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Adv_Channel_TX_Power 0x0007 /* complete */ +#define HCI_CMD_LE_Read_Adv_Channel_TX_Power 0x0007 /* complete */ struct hciCmplLeReadAdvChannelTxPower { uint8_t status; uint8_t txPower; /* actually an int8_t */ } __packed; -#define HCI_CMD_LE_Set_Advertising_Data 0x0008 /* complete */ +#define HCI_CMD_LE_Set_Advertising_Data 0x0008 /* complete */ struct hciLeSetAdvData { uint8_t advDataLen; uint8_t advData[31]; @@ -2213,7 +2294,7 @@ struct hciCmplLeSetAdvData { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Scan_Response_Data 0x0009 /* complete */ +#define HCI_CMD_LE_Set_Scan_Response_Data 0x0009 /* complete */ struct hciSetScanResponseData { uint8_t scanRspDataLen; uint8_t scanRspData[31]; @@ -2222,7 +2303,7 @@ struct hciCmplSetScanResponseData { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Advertise_Enable 0x000A /* complete */ +#define HCI_CMD_LE_Set_Advertise_Enable 0x000A /* complete */ struct hciLeSetAdvEnable { uint8_t advOn; } __packed; @@ -2230,7 +2311,7 @@ struct hciCmplLeSetAdvEnable { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Scan_Parameters 0x000B /* complete */ +#define HCI_CMD_LE_Set_Scan_Parameters 0x000B /* complete */ struct hciLeSetScanParams { uint8_t activeScan; uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */ @@ -2242,7 +2323,7 @@ struct hciCmplLeSetScanParams { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Scan_Enable 0x000C /* complete */ +#define HCI_CMD_LE_Set_Scan_Enable 0x000C /* complete */ struct hciLeSetScanEnable { uint8_t scanOn; uint8_t filterDuplicates; @@ -2251,7 +2332,7 @@ struct hciCmplLeSetScanEnable { uint8_t status; } __packed; -#define HCI_CMD_LE_Create_Connection 0x000D /* status */ +#define HCI_CMD_LE_Create_Connection 0x000D /* status */ struct hciLeCreateConnection { uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */ uint16_t scanWindow; /* in units of 0.625ms, 4..0x4000 */ @@ -2263,27 +2344,29 @@ struct hciLeCreateConnection { uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connLatency; /* 0..0x1F4 */ uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */ - uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ - uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ + uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ + uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ } __packed; -#define HCI_CMD_LE_Create_Connection_Cancel 0x000E /* complete */ +#define HCI_CMD_LE_Create_Connection_Cancel 0x000E /* complete */ struct hciCmplLeCreateConnectionCancel { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Allow_List_Size 0x000F /* complete */ +#define HCI_CMD_LE_Read_Allow_List_Size 0x000F /* complete */ struct hciCmplLeReadAllowListSize { uint8_t status; uint8_t allowlistSize; } __packed; -#define HCI_CMD_LE_Clear_Allow_List 0x0010 /* complete */ +#define HCI_CMD_LE_Clear_Allow_List 0x0010 /* complete */ struct hciCmplLeClearAllowList { uint8_t status; } __packed; -#define HCI_CMD_LE_Add_Device_To_Allow_List 0x0011 /* complete */ +#define HCI_CMD_LE_Add_Device_To_Allow_List 0x0011 /* complete */ struct hciLeAddDeviceToAllowList { uint8_t randomAddr; uint8_t mac[6]; @@ -2292,7 +2375,7 @@ struct hciCmplLeAddDeviceToAllowList { uint8_t status; } __packed; -#define HCI_CMD_LE_Remove_Device_From_Allow_List 0x0012 /* complete */ +#define HCI_CMD_LE_Remove_Device_From_Allow_List 0x0012 /* complete */ struct hciLeRemoveDeviceFromAllowList { uint8_t randomAddr; uint8_t mac[6]; @@ -2301,18 +2384,20 @@ struct hciCmplLeRemoveDeviceFromAllowList { uint8_t status; } __packed; -#define HCI_CMD_LE_Connection_Update 0x0013 /* status */ +#define HCI_CMD_LE_Connection_Update 0x0013 /* status */ struct hciLeConnectionUpdate { uint16_t conn; uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connLatency; /* 0..0x1F4 */ uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */ - uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ - uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ + uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ + uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ } __packed; -#define HCI_CMD_LE_Set_Host_Channel_Classification 0x0014 /* complete */ +#define HCI_CMD_LE_Set_Host_Channel_Classification 0x0014 /* complete */ struct hciLeSetHostChannelClassification { uint8_t chMap[5]; } __packed; @@ -2320,7 +2405,7 @@ struct hciCmplLeSetHostChannelClassification { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Channel_Map 0x0015 /* complete */ +#define HCI_CMD_LE_Read_Channel_Map 0x0015 /* complete */ struct hciLeReadChannelMap { uint16_t conn; } __packed; @@ -2330,12 +2415,12 @@ struct hciCmplLeReadChannelMap { uint8_t chMap[5]; } __packed; -#define HCI_CMD_LE_Read_Remote_Used_Features 0x0016 /* status */ +#define HCI_CMD_LE_Read_Remote_Used_Features 0x0016 /* status */ struct hciLeReadRemoteUsedFeatures { uint16_t conn; } __packed; -#define HCI_CMD_LE_Encrypt 0x0017 /* complete */ +#define HCI_CMD_LE_Encrypt 0x0017 /* complete */ struct hciLeEncrypt { uint8_t key[16]; uint8_t plaintext[16]; @@ -2345,13 +2430,13 @@ struct hciCmplLeEncrypt { uint8_t encryptedData[16]; } __packed; -#define HCI_CMD_LE_Rand 0x0018 /* complete */ +#define HCI_CMD_LE_Rand 0x0018 /* complete */ struct hciCmplLeRand { uint8_t status; uint64_t rand; } __packed; -#define HCI_CMD_LE_Start_Encryption 0x0019 /* status */ +#define HCI_CMD_LE_Start_Encryption 0x0019 /* status */ struct hciLeStartEncryption { uint16_t conn; uint64_t rand; @@ -2359,7 +2444,7 @@ struct hciLeStartEncryption { uint8_t LTK[16]; } __packed; -#define HCI_CMD_LE_LTK_Request_Reply 0x001A /* complete */ +#define HCI_CMD_LE_LTK_Request_Reply 0x001A /* complete */ struct hciLeLtkRequestReply { uint16_t conn; uint8_t LTK[16]; @@ -2369,7 +2454,7 @@ struct hciCmplLeLtkRequestReply { uint16_t conn; } __packed; -#define HCI_CMD_LE_LTK_Request_Negative_Reply 0x001B /* complete */ +#define HCI_CMD_LE_LTK_Request_Negative_Reply 0x001B /* complete */ struct hciLeLtkRequestNegativeReply { uint16_t conn; } __packed; @@ -2378,13 +2463,13 @@ struct hciCmplLeLtkRequestNegativeReply { uint16_t conn; } __packed; -#define HCI_CMD_LE_Read_Supported_States 0x001C /* complete */ +#define HCI_CMD_LE_Read_Supported_States 0x001C /* complete */ struct hciCmplLeReadSupportedStates { uint8_t status; uint64_t states; /* bitmask of HCI_LE_STATE_* */ } __packed; -#define HCI_CMD_LE_Receiver_Test 0x001D /* complete */ +#define HCI_CMD_LE_Receiver_Test 0x001D /* complete */ struct hciLeReceiverTest { uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */ } __packed; @@ -2392,7 +2477,7 @@ struct hciCmplLeReceiverTest { uint8_t status; } __packed; -#define HCI_CMD_LE_Transmitter_Test 0x001E /* complete */ +#define HCI_CMD_LE_Transmitter_Test 0x001E /* complete */ struct hciLeTransmitterTest { uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */ uint8_t lengthOfTestData; @@ -2402,31 +2487,33 @@ struct hciCmplLeTransmitterTest { uint8_t status; } __packed; -#define HCI_CMD_LE_Test_End 0x001F /* complete */ +#define HCI_CMD_LE_Test_End 0x001F /* complete */ struct hciCmplLeTestEnd { uint8_t status; uint16_t numPackets; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply 0x0020 /* complete */ +#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply 0x0020 /* complete */ struct hciLeRemoteConnParamRequestReply { uint16_t conn; uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connLatency; /* 0..0x1F4 */ uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */ - uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ - uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ + uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ + uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ } __packed; struct hciCmplLeRemoteConnParamRequestReply { uint8_t status; uint16_t conn; } __packed; -#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply 0x0021 /* complete */ +#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply \ + 0x0021 /* complete */ struct hciRemoteConnParamRequestNegativeReply { uint16_t conn; uint8_t reason; @@ -2436,19 +2523,16 @@ struct hciCmplLeRemoteConnParamRequestNegativeReply { uint16_t conn; } __packed; - - /* EVENTS */ - /* ==== BT 1.1 ==== */ -#define HCI_EVT_Inquiry_Complete 0x01 +#define HCI_EVT_Inquiry_Complete 0x01 struct hciEvtInquiryComplete { uint8_t status; } __packed; -#define HCI_EVT_Inquiry_Result 0x02 +#define HCI_EVT_Inquiry_Result 0x02 struct hciEvtInquiryResultItem { uint8_t mac[6]; uint8_t PSRM; @@ -2462,7 +2546,7 @@ struct hciEvtInquiryResult { struct hciEvtInquiryResultItem items[]; } __packed; -#define HCI_EVT_Connection_Complete 0x03 +#define HCI_EVT_Connection_Complete 0x03 struct hciEvtConnComplete { uint8_t status; uint16_t conn; @@ -2471,61 +2555,61 @@ struct hciEvtConnComplete { uint8_t encrypted; } __packed; -#define HCI_EVT_Connection_Request 0x04 +#define HCI_EVT_Connection_Request 0x04 struct hciEvtConnRequest { uint8_t mac[6]; uint8_t deviceClass[3]; uint8_t isAclLink; } __packed; -#define HCI_EVT_Disconnection_Complete 0x05 +#define HCI_EVT_Disconnection_Complete 0x05 struct hciEvtDiscComplete { uint8_t status; uint16_t conn; uint8_t reason; } __packed; -#define HCI_EVT_Authentication_Complete 0x06 +#define HCI_EVT_Authentication_Complete 0x06 struct hciEvtAuthComplete { uint8_t status; uint16_t handle; } __packed; -#define HCI_EVT_Remote_Name_Request_Complete 0x07 +#define HCI_EVT_Remote_Name_Request_Complete 0x07 struct hciEvtRemoteNameReqComplete { uint8_t status; uint8_t mac[6]; char name[HCI_DEV_NAME_LEN]; } __packed; -#define HCI_EVT_Encryption_Change 0x08 +#define HCI_EVT_Encryption_Change 0x08 struct hciEvtEncrChange { uint8_t status; uint16_t conn; uint8_t encrOn; } __packed; -#define HCI_EVT_Change_Connection_Link_Key_Complete 0x09 +#define HCI_EVT_Change_Connection_Link_Key_Complete 0x09 struct hciEvtChangeConnLinkKeyComplete { uint8_t status; uint16_t handle; } __packed; -#define HCI_EVT_Master_Link_Key_Complete 0x0A +#define HCI_EVT_Master_Link_Key_Complete 0x0A struct hciEvtMasterLinkKeyComplete { uint8_t status; uint16_t conn; uint8_t usingTempKey; /* else using semi-permanent key */ } __packed; -#define HCI_EVT_Read_Remote_Supported_Features_Complete 0x0B +#define HCI_EVT_Read_Remote_Supported_Features_Complete 0x0B struct hciEvtReadRemoteSupportedFeaturesComplete { uint8_t status; uint16_t conn; uint64_t lmpFeatures; /* bitmask of HCI_LMP_FTR_* */ } __packed; -#define HCI_EVT_Read_Remote_Version_Complete 0x0C +#define HCI_EVT_Read_Remote_Version_Complete 0x0C struct hciEvtReadRemoteVersionComplete { uint8_t status; uint16_t conn; @@ -2534,7 +2618,7 @@ struct hciEvtReadRemoteVersionComplete { uint16_t lmpSubversion; } __packed; -#define HCI_EVT_QOS_Setup_Complete 0x0D +#define HCI_EVT_QOS_Setup_Complete 0x0D struct hciEvtQosSetupComplete { uint8_t status; uint16_t conn; @@ -2546,37 +2630,37 @@ struct hciEvtQosSetupComplete { uint32_t delayVariation; } __packed; -#define HCI_EVT_Command_Complete 0x0E +#define HCI_EVT_Command_Complete 0x0E struct hciEvtCmdComplete { uint8_t numCmdCredits; uint16_t opcode; } __packed; -#define HCI_EVT_Command_Status 0x0F +#define HCI_EVT_Command_Status 0x0F struct hciEvtCmdStatus { uint8_t status; uint8_t numCmdCredits; uint16_t opcode; } __packed; -#define HCI_EVT_Hardware_Error 0x10 +#define HCI_EVT_Hardware_Error 0x10 struct hciEvtHwError { uint8_t errCode; } __packed; -#define HCI_EVT_Flush_Occurred 0x11 +#define HCI_EVT_Flush_Occurred 0x11 struct hciEvtFlushOccurred { uint16_t conn; } __packed; -#define HCI_EVT_Role_Change 0x12 +#define HCI_EVT_Role_Change 0x12 struct hciEvtRoleChange { uint8_t status; uint8_t mac[6]; uint8_t amSlave; } __packed; -#define HCI_EVT_Number_Of_Completed_Packets 0x13 +#define HCI_EVT_Number_Of_Completed_Packets 0x13 struct hciEvtNumCompletedPacketsItem { uint16_t conn; uint16_t numPackets; @@ -2586,7 +2670,7 @@ struct hciEvtNumCompletedPackets { struct hciEvtNumCompletedPacketsItem items[]; } __packed; -#define HCI_EVT_Mode_Change 0x14 +#define HCI_EVT_Mode_Change 0x14 struct hciEvtModeChange { uint8_t status; uint16_t conn; @@ -2594,7 +2678,7 @@ struct hciEvtModeChange { uint16_t interval; /* in units of 0.625ms 0..0xffff */ } __packed; -#define HCI_EVT_Return_Link_Keys 0x15 +#define HCI_EVT_Return_Link_Keys 0x15 struct hciEvtReturnLinkKeysItem { uint8_t mac[6]; uint8_t key[16]; @@ -2604,72 +2688,71 @@ struct hciEvtReturnLinkKeys { struct hciEvtReturnLinkKeysItem items[]; } __packed; -#define HCI_EVT_PIN_Code_Request 0x16 +#define HCI_EVT_PIN_Code_Request 0x16 struct hciEvtPinCodeReq { uint8_t mac[6]; } __packed; -#define HCI_EVT_Link_Key_Request 0x17 +#define HCI_EVT_Link_Key_Request 0x17 struct hciEvtLinkKeyReq { uint8_t mac[6]; } __packed; -#define HCI_EVT_Link_Key_Notification 0x18 +#define HCI_EVT_Link_Key_Notification 0x18 struct hciEvtLinkKeyNotif { uint8_t mac[6]; uint8_t key[16]; uint8_t keyType; /* HCI_KEY_TYPE_ */ } __packed; -#define HCI_EVT_Loopback_Command 0x19 +#define HCI_EVT_Loopback_Command 0x19 /* data is the sent command, up to 252 bytes of it */ -#define HCI_EVT_Data_Buffer_Overflow 0x1A +#define HCI_EVT_Data_Buffer_Overflow 0x1A struct hciEvtDataBufferOverflow { uint8_t aclLink; } __packed; -#define HCI_EVT_Max_Slots_Change 0x1B +#define HCI_EVT_Max_Slots_Change 0x1B struct hciEvtMaxSlotsChange { uint16_t conn; uint8_t lmpMaxSlots; } __packed; -#define HCI_EVT_Read_Clock_Offset_Complete 0x1C +#define HCI_EVT_Read_Clock_Offset_Complete 0x1C struct hciEvtReadClockOffsetComplete { uint8_t status; uint16_t conn; uint16_t clockOffset; } __packed; -#define HCI_EVT_Connection_Packet_Type_Changed 0x1D +#define HCI_EVT_Connection_Packet_Type_Changed 0x1D struct hciEvtConnPacketTypeChanged { uint8_t status; uint16_t conn; uint16_t packetsAllowed; /* HCI_PKT_TYP_* */ } __packed; -#define HCI_EVT_QoS_Violation 0x1E +#define HCI_EVT_QoS_Violation 0x1E struct hciEvtQosViolation { uint16_t conn; } __packed; -#define HCI_EVT_Page_Scan_Mode_Change 0x1F /* deprecated in BT 1.2+ */ +#define HCI_EVT_Page_Scan_Mode_Change 0x1F /* deprecated in BT 1.2+ */ struct hciEvtPsmChange { uint8_t mac[6]; uint8_t PSM; } __packed; -#define HCI_EVT_Page_Scan_Repetition_Mode_Change 0x20 +#define HCI_EVT_Page_Scan_Repetition_Mode_Change 0x20 struct hciEvtPrsmChange { uint8_t mac[6]; uint8_t PSRM; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_EVT_Flow_Specification_Complete 0x21 +#define HCI_EVT_Flow_Specification_Complete 0x21 struct hciEvtFlowSpecComplete { uint8_t status; uint16_t conn; @@ -2681,7 +2764,7 @@ struct hciEvtFlowSpecComplete { uint32_t latency; } __packed; -#define HCI_EVT_Inquiry_Result_With_RSSI 0x22 +#define HCI_EVT_Inquiry_Result_With_RSSI 0x22 struct hciEvtInquiryResultWithRssiItem { uint8_t mac[6]; uint8_t PSRM; @@ -2695,7 +2778,7 @@ struct hciEvtInquiryResultWithRssi { struct hciEvtInquiryResultWithRssiItem items[]; } __packed; -#define HCI_EVT_Read_Remote_Extended_Features_Complete 0x23 +#define HCI_EVT_Read_Remote_Extended_Features_Complete 0x23 struct hciEvtReadRemoteExtFeturesComplete { uint8_t status; uint16_t conn; @@ -2704,7 +2787,7 @@ struct hciEvtReadRemoteExtFeturesComplete { uint64_t extLmpFeatures; /* HCI_LMP_EXT_FTR_P* & HCI_LMP_FTR_* */ } __packed; -#define HCI_EVT_Synchronous_Connection_Complete 0x2C +#define HCI_EVT_Synchronous_Connection_Complete 0x2C struct hciEvtSyncConnComplete { uint8_t status; uint16_t conn; @@ -2717,7 +2800,7 @@ struct hciEvtSyncConnComplete { uint8_t airMode; /* HCI_SCO_AIR_MODE_* */ } __packed; -#define HCI_EVT_Synchronous_Connection_Changed 0x2D +#define HCI_EVT_Synchronous_Connection_Changed 0x2D struct hciEvtSyncConnChanged { uint8_t status; uint16_t conn; @@ -2727,10 +2810,9 @@ struct hciEvtSyncConnChanged { uint16_t txPacketLen; } __packed; - /* ==== BT 2.1 ==== */ -#define HCI_EVT_Sniff_Subrating 0x2E +#define HCI_EVT_Sniff_Subrating 0x2E struct hciEvtSniffSubrating { uint8_t status; uint16_t conn; @@ -2740,7 +2822,7 @@ struct hciEvtSniffSubrating { uint16_t minLocalTimeout; } __packed; -#define HCI_EVT_Extended_Inquiry_Result 0x2F +#define HCI_EVT_Extended_Inquiry_Result 0x2F struct hciEvtExtendedInquiryResult { uint8_t numResponses; /* must be 1 */ uint8_t mac[6]; @@ -2752,18 +2834,18 @@ struct hciEvtExtendedInquiryResult { uint8_t EIR[240]; } __packed; -#define HCI_EVT_Encryption_Key_Refresh_Complete 0x30 +#define HCI_EVT_Encryption_Key_Refresh_Complete 0x30 struct hciEvtEncrKeyRefreshComplete { uint8_t status; uint16_t conn; } __packed; -#define HCI_EVT_IO_Capability_Request 0x31 +#define HCI_EVT_IO_Capability_Request 0x31 struct hciEvtIoCapRequest { uint8_t mac[6]; } __packed; -#define HCI_EVT_IO_Capability_Response 0x32 +#define HCI_EVT_IO_Capability_Response 0x32 struct hciEvtIoCapResponse { uint8_t mac[6]; uint8_t ioCapability; /* HCI_DISPLAY_CAP_* */ @@ -2771,90 +2853,89 @@ struct hciEvtIoCapResponse { uint8_t authReqments; /* HCI_AUTH_REQMENT_ */ } __packed; -#define HCI_EVT_User_Confirmation_Request 0x33 +#define HCI_EVT_User_Confirmation_Request 0x33 struct hciEvtUserConfRequest { uint8_t mac[6]; uint32_t numericValue; } __packed; -#define HCI_EVT_User_Passkey_Request 0x34 +#define HCI_EVT_User_Passkey_Request 0x34 struct hciEvtUserPasskeyRequest { uint8_t mac[6]; } __packed; -#define HCI_EVT_Remote_OOB_Data_Request 0x35 +#define HCI_EVT_Remote_OOB_Data_Request 0x35 struct hciEvtRemoteOobRequest { uint8_t mac[6]; } __packed; -#define HCI_EVT_Simple_Pairing_Complete 0x36 +#define HCI_EVT_Simple_Pairing_Complete 0x36 struct hciEvtSimplePairingComplete { uint8_t status; uint8_t mac[6]; } __packed; -#define HCI_EVT_Link_Supervision_Timeout_Changed 0x38 +#define HCI_EVT_Link_Supervision_Timeout_Changed 0x38 struct hciEvtLinkSupervisionTimeoutChanged { uint16_t conn; uint16_t timeout; /* in units of 0.625 ms 1..0xffff */ } __packed; -#define HCI_EVT_Enhanced_Flush_Complete 0x39 +#define HCI_EVT_Enhanced_Flush_Complete 0x39 struct hciEvtEnahncedFlushComplete { uint16_t conn; } __packed; -#define HCI_EVT_User_Passkey_Notification 0x3B +#define HCI_EVT_User_Passkey_Notification 0x3B struct hciEvtUserPasskeyNotif { uint8_t mac[6]; uint32_t passkey; } __packed; -#define HCI_EVT_Keypress_Notification 0x3C +#define HCI_EVT_Keypress_Notification 0x3C struct hciEvtKeypressNotification { uint8_t mac[6]; uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */ } __packed; -#define HCI_EVT_Remote_Host_Supported_Features_Notification 0x3D +#define HCI_EVT_Remote_Host_Supported_Features_Notification 0x3D struct hciEvtRemoteHostSupportedFeatures { uint8_t mac[6]; uint64_t hostSupportedFeatures; /* HCI_LMP_FTR_* */ } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_EVT_Physical_Link_Complete 0x40 +#define HCI_EVT_Physical_Link_Complete 0x40 struct hciEvtPhysLinkComplete { uint8_t status; uint8_t physLinkHandle; } __packed; -#define HIC_EVT_Channel_Selected 0x41 +#define HIC_EVT_Channel_Selected 0x41 struct hciEvtChannelSelected { uint8_t physLinkHandle; } __packed; -#define HCI_EVT_Disconnection_Physical_Link_Complete 0x42 +#define HCI_EVT_Disconnection_Physical_Link_Complete 0x42 struct hciEvtDiscPhysLinkComplete { uint8_t status; uint8_t physLinkHandle; uint8_t reason; } __packed; -#define HCI_EVT_Physical_Link_Loss_Early_Warning 0x43 +#define HCI_EVT_Physical_Link_Loss_Early_Warning 0x43 struct hciEvtDiscPhysLinkLossEralyWarning { uint8_t physLinkHandle; uint8_t lossReason; } __packed; -#define HCI_EVT_Physical_Link_Recovery 0x44 +#define HCI_EVT_Physical_Link_Recovery 0x44 struct hciEvtDiscPhysLinkRecovery { uint8_t physLinkHandle; } __packed; -#define HCI_EVT_Logical_Link_Complete 0x45 +#define HCI_EVT_Logical_Link_Complete 0x45 struct hciEvtLogicalLinkComplete { uint8_t status; uint16_t logicalLinkHandle; @@ -2862,20 +2943,20 @@ struct hciEvtLogicalLinkComplete { uint8_t txFlowSpecID; } __packed; -#define HCI_EVT_Disconnection_Logical_Link_Complete 0x46 +#define HCI_EVT_Disconnection_Logical_Link_Complete 0x46 struct hciEvtDiscLogicalLinkComplete { uint8_t status; uint16_t logicalLinkHandle; uint8_t reason; } __packed; -#define HCI_EVT_Flow_Spec_Modify_Complete 0x47 +#define HCI_EVT_Flow_Spec_Modify_Complete 0x47 struct hciEvtFlowSpecModifyComplete { uint8_t status; uint16_t conn; } __packed; -#define HCI_EVT_Number_Of_Completed_Data_Blocks 0x48 +#define HCI_EVT_Number_Of_Completed_Data_Blocks 0x48 struct hciEvtNumCompletedDataBlocksItem { uint16_t conn; uint16_t numPackets; @@ -2886,19 +2967,19 @@ struct hciEvtNumCompletedDataBlocks { struct hciEvtNumCompletedDataBlocksItem items[]; } __packed; -#define HCI_EVT_AMP_Start_Test 0x49 +#define HCI_EVT_AMP_Start_Test 0x49 struct hciEvtAmpStartTest { uint8_t status; uint8_t scenario; } __packed; -#define HCI_EVT_AMP_Test_End 0x4A +#define HCI_EVT_AMP_Test_End 0x4A struct hciEvtAmpTestEnd { uint8_t status; uint8_t scenario; } __packed; -#define HCI_EVT_AMP_Receiver_Report 0x4B +#define HCI_EVT_AMP_Receiver_Report 0x4B struct hciEvtampReceiverReport { uint8_t controllerType; uint8_t reason; @@ -2909,28 +2990,27 @@ struct hciEvtampReceiverReport { uint32_t numberOfErrorBits; } __packed; -#define HCI_EVT_Short_Range_Mode_Change_Complete 0x4C +#define HCI_EVT_Short_Range_Mode_Change_Complete 0x4C struct hciEvtshortRangeModeChangeComplete { uint8_t status; uint8_t physLinkHandle; uint8_t shortRangeModeOn; } __packed; -#define HCI_EVT_AMP_Status_Change 0x4D +#define HCI_EVT_AMP_Status_Change 0x4D struct hciEvtAmpStatusChange { uint8_t status; uint8_t ampStatus; } __packed; - /* ==== BT 4.0 ==== */ -#define HCI_EVT_LE_Meta 0x3E +#define HCI_EVT_LE_Meta 0x3E struct hciEvtLeMeta { uint8_t subevent; } __packed; -#define HCI_EVTLE_Connection_Complete 0x01 +#define HCI_EVTLE_Connection_Complete 0x01 struct hciEvtLeConnectionComplete { uint8_t status; uint16_t conn; @@ -2943,21 +3023,23 @@ struct hciEvtLeConnectionComplete { uint8_t masterClockAccuracy; /* HCI_MCA_* */ } __packed; -#define HCI_EVTLE_Advertising_Report 0x02 +#define HCI_EVTLE_Advertising_Report 0x02 struct hciEvtLeAdvReportItem { uint8_t advType; /* HCI_ADV_TYPE_* */ uint8_t randomAddr; uint8_t mac[6]; uint8_t dataLen; uint8_t data[]; -/* int8_t RSSI <-- this cannot be here due to variable data len, but in reality it is there */ + /* int8_t RSSI <-- this cannot be here due to variable data len, but in + * reality it is there */ } __packed; struct hciEvtLeAdvReport { uint8_t numReports; - /* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since data length is variable */ + /* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since + * data length is variable */ } __packed; -#define HCI_EVTLE_Connection_Update_Complete 0x03 +#define HCI_EVTLE_Connection_Update_Complete 0x03 struct hciEvtLeConnectionUpdateComplete { uint8_t status; uint16_t conn; @@ -2966,24 +3048,23 @@ struct hciEvtLeConnectionUpdateComplete { uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */ } __packed; -#define HCI_EVTLE_Read_Remote_Used_Features_Complete 0x04 +#define HCI_EVTLE_Read_Remote_Used_Features_Complete 0x04 struct hciEvtLeReadRemoteFeaturesComplete { uint8_t status; uint16_t conn; uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */ } __packed; -#define HCI_EVTLE_LTK_Request 0x05 +#define HCI_EVTLE_LTK_Request 0x05 struct hciEvtLeLtkRequest { uint16_t conn; uint64_t randomNum; uint16_t diversifier; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request 0x06 +#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request 0x06 struct hciEvtLeReadRemoteConnParamRequest { uint16_t conn; uint16_t connIntervalMin; /* in units of 1.25 ms 6..0x0C80 */ @@ -2992,7 +3073,7 @@ struct hciEvtLeReadRemoteConnParamRequest { uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */ } __packed; -#define HCI_EVT_Triggered_Clock_Capture 0x4E +#define HCI_EVT_Triggered_Clock_Capture 0x4E struct hciEvtTriggeredClockCapture { uint16_t conn; uint8_t piconetClock; @@ -3000,12 +3081,12 @@ struct hciEvtTriggeredClockCapture { uint16_t slotOffset; } __packed; -#define HCI_EVT_Synchronization_Train_Complete 0x4F +#define HCI_EVT_Synchronization_Train_Complete 0x4F struct hciEvtSyncTrainComplete { uint8_t status; } __packed; -#define HCI_EVT_Synchronization_Train_Received 0x50 +#define HCI_EVT_Synchronization_Train_Received 0x50 struct hciEvtSyncTrainReceived { uint8_t status; uint8_t mac[6]; @@ -3017,7 +3098,7 @@ struct hciEvtSyncTrainReceived { uint8_t serviceData; } __packed; -#define HCI_EVT_Connectionless_Slave_Broadcast_Receive 0x51 +#define HCI_EVT_Connectionless_Slave_Broadcast_Receive 0x51 struct hciEvtConnectionlessSlaveBroadcastReceive { uint8_t mac[6]; uint8_t ltAddr; @@ -3029,127 +3110,116 @@ struct hciEvtConnectionlessSlaveBroadcastReceive { /* data */ } __packed; -#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout 0x52 +#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout 0x52 struct hciEvtConnectionlessSlaveBroadcastTimeout { uint8_t mac[6]; uint8_t ltAddr; } __packed; -#define HCI_EVT_Truncated_Page_Complete 0x53 +#define HCI_EVT_Truncated_Page_Complete 0x53 struct hciEvtTruncatedPageComplete { uint8_t status; uint8_t mac[6]; } __packed; -#define HCI_EVT_Slave_Page_Response_Timeout 0x54 +#define HCI_EVT_Slave_Page_Response_Timeout 0x54 -#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change 0x55 +#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change 0x55 struct hciEvtConnlessSlaveBroadcastChannelMapChange { uint8_t map[10]; } __packed; -#define HCI_EVT_Inquiry_Response_Notification 0x56 +#define HCI_EVT_Inquiry_Response_Notification 0x56 struct hciEvtInquiryResponseNotif { uint8_t lap[3]; uint8_t RSSI; /* actually an int8_t */ } __packed; -#define HCI_EVT_Authenticated_Payload_Timeout_Expired 0x57 +#define HCI_EVT_Authenticated_Payload_Timeout_Expired 0x57 struct hciEvtAuthedPayloadTimeoutExpired { uint16_t conn; } __packed; - - - - /* ERROR CODES */ /* ==== BT 1.1 ==== */ -#define HCI_SUCCESS 0x00 -#define HCI_ERR_Unknown_HCI_Command 0x01 -#define HCI_ERR_No_Connection 0x02 -#define HCI_ERR_Hardware_Failure 0x03 -#define HCI_ERR_Page_Timeout 0x04 -#define HCI_ERR_Authentication_Failure 0x05 -#define HCI_ERR_Key_Missing 0x06 -#define HCI_ERR_Memory_Full 0x07 -#define HCI_ERR_Connection_Timeout 0x08 -#define HCI_ERR_Max_Number_Of_Connections 0x09 -#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device 0x0A -#define HCI_ERR_ACL_Connection_Already_Exists 0x0B -#define HCI_ERR_Command_Disallowed 0x0C -#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources 0x0D -#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons 0x0E -#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device 0x0F -#define HCI_ERR_Host_Timeout 0x10 -#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value 0x11 -#define HCI_ERR_Invalid_HCI_Command_Parameters 0x12 -#define HCI_ERR_Other_End_Terminated_Connection_User_Requested 0x13 -#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources 0x14 -#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off 0x15 -#define HCI_ERR_Connection_Terminated_By_Local_Host 0x16 -#define HCI_ERR_Repeated_Attempts 0x17 -#define HCI_ERR_Pairing_Not_Allowed 0x18 -#define HCI_ERR_Unknown_LMP_PDU 0x19 -#define HCI_ERR_Unsupported_Remote_Feature 0x1A -#define HCI_ERR_SCO_Offset_Rejected 0x1B -#define HCI_ERR_SCO_Interval_Rejected 0x1C -#define HCI_ERR_SCO_Air_Mode_Rejected 0x1D -#define HCI_ERR_Invalid_LMP_Parameters 0x1E -#define HCI_ERR_Unspecified_Error 0x1F -#define HCI_ERR_Unsupported_LMP_Parameter 0x20 -#define HCI_ERR_Role_Change_Not_Allowed 0x21 -#define HCI_ERR_LMP_Response_Timeout 0x22 -#define HCI_ERR_LMP_Error_Transaction_Collision 0x23 -#define HCI_ERR_LMP_PDU_Not_Allowed 0x24 -#define HCI_ERR_Encryption_Mode_Not_Acceptable 0x25 -#define HCI_ERR_Unit_Key_Used 0x26 -#define HCI_ERR_QoS_Not_Supported 0x27 -#define HCI_ERR_Instant_Passed 0x28 -#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported 0x29 - +#define HCI_SUCCESS 0x00 +#define HCI_ERR_Unknown_HCI_Command 0x01 +#define HCI_ERR_No_Connection 0x02 +#define HCI_ERR_Hardware_Failure 0x03 +#define HCI_ERR_Page_Timeout 0x04 +#define HCI_ERR_Authentication_Failure 0x05 +#define HCI_ERR_Key_Missing 0x06 +#define HCI_ERR_Memory_Full 0x07 +#define HCI_ERR_Connection_Timeout 0x08 +#define HCI_ERR_Max_Number_Of_Connections 0x09 +#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device 0x0A +#define HCI_ERR_ACL_Connection_Already_Exists 0x0B +#define HCI_ERR_Command_Disallowed 0x0C +#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources 0x0D +#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons 0x0E +#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device 0x0F +#define HCI_ERR_Host_Timeout 0x10 +#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value 0x11 +#define HCI_ERR_Invalid_HCI_Command_Parameters 0x12 +#define HCI_ERR_Other_End_Terminated_Connection_User_Requested 0x13 +#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources 0x14 +#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off 0x15 +#define HCI_ERR_Connection_Terminated_By_Local_Host 0x16 +#define HCI_ERR_Repeated_Attempts 0x17 +#define HCI_ERR_Pairing_Not_Allowed 0x18 +#define HCI_ERR_Unknown_LMP_PDU 0x19 +#define HCI_ERR_Unsupported_Remote_Feature 0x1A +#define HCI_ERR_SCO_Offset_Rejected 0x1B +#define HCI_ERR_SCO_Interval_Rejected 0x1C +#define HCI_ERR_SCO_Air_Mode_Rejected 0x1D +#define HCI_ERR_Invalid_LMP_Parameters 0x1E +#define HCI_ERR_Unspecified_Error 0x1F +#define HCI_ERR_Unsupported_LMP_Parameter 0x20 +#define HCI_ERR_Role_Change_Not_Allowed 0x21 +#define HCI_ERR_LMP_Response_Timeout 0x22 +#define HCI_ERR_LMP_Error_Transaction_Collision 0x23 +#define HCI_ERR_LMP_PDU_Not_Allowed 0x24 +#define HCI_ERR_Encryption_Mode_Not_Acceptable 0x25 +#define HCI_ERR_Unit_Key_Used 0x26 +#define HCI_ERR_QoS_Not_Supported 0x27 +#define HCI_ERR_Instant_Passed 0x28 +#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported 0x29 /* ==== BT 1.2 ==== */ -#define HCI_ERR_Different_Transaction_Collision 0x2A -#define HCI_ERR_QoS_Unacceptable_Parameter 0x2C -#define HCI_ERR_QoS_Rejected 0x2D -#define HCI_ERR_Channel_Classification_Not_Supported 0x2E -#define HCI_ERR_Insufficient_Security 0x2F -#define HCI_ERR_Parameter_Out_Of_Mandatory_Range 0x30 -#define HCI_ERR_Role_Switch_Pending 0x33 -#define HCI_ERR_Reserved_Slot_Violation 0x34 -#define HIC_ERR_Role_Switch_Failed 0x35 - +#define HCI_ERR_Different_Transaction_Collision 0x2A +#define HCI_ERR_QoS_Unacceptable_Parameter 0x2C +#define HCI_ERR_QoS_Rejected 0x2D +#define HCI_ERR_Channel_Classification_Not_Supported 0x2E +#define HCI_ERR_Insufficient_Security 0x2F +#define HCI_ERR_Parameter_Out_Of_Mandatory_Range 0x30 +#define HCI_ERR_Role_Switch_Pending 0x33 +#define HCI_ERR_Reserved_Slot_Violation 0x34 +#define HIC_ERR_Role_Switch_Failed 0x35 /* ==== BT 2.1 ==== */ -#define HCI_ERR_EIR_Too_Large 0x36 -#define HCI_ERR_SSP_Not_Supported_By_Host 0x37 -#define HCI_ERR_Host_Busy_Pairing 0x38 - +#define HCI_ERR_EIR_Too_Large 0x36 +#define HCI_ERR_SSP_Not_Supported_By_Host 0x37 +#define HCI_ERR_Host_Busy_Pairing 0x38 /* ==== BT 3.0 ==== */ -#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found 0x39 -#define HCI_ERR_Controller_Busy 0x3A - +#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found 0x39 +#define HCI_ERR_Controller_Busy 0x3A /* ==== BT 4.0 ==== */ -#define HCI_ERR_Unacceptable_Connection_Interval 0x3B -#define HCI_ERR_Directed_Advertising_Timeout 0x3C -#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure 0x3D -#define HCI_ERR_Connection_Failed_To_To_Established 0x3E -#define HCI_ERR_MAC_Connection_Failed 0x3F - +#define HCI_ERR_Unacceptable_Connection_Interval 0x3B +#define HCI_ERR_Directed_Advertising_Timeout 0x3C +#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure 0x3D +#define HCI_ERR_Connection_Failed_To_To_Established 0x3E +#define HCI_ERR_MAC_Connection_Failed 0x3F /* ==== BT 4.1 ==== */ -#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging 0x40 - - +#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging 0x40 #endif diff --git a/include/button.h b/include/button.h index 30d2969e8c..937b280876 100644 --- a/include/button.h +++ b/include/button.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,9 +13,8 @@ #include "gpio_signal.h" #include "ec_commands.h" -#define BUTTON_FLAG_ACTIVE_HIGH BIT(0) -#define BUTTON_FLAG_DISABLED BIT(1) /* Button disabled */ - +#define BUTTON_FLAG_ACTIVE_HIGH BIT(0) +#define BUTTON_FLAG_DISABLED BIT(1) /* Button disabled */ #define BUTTON_DEBOUNCE_US (30 * MSEC) @@ -103,4 +102,4 @@ int button_is_adc_detected(enum gpio_signal gpio); */ int adc_to_physical_value(enum gpio_signal gpio); -#endif /* __CROS_EC_BUTTON_H */ +#endif /* __CROS_EC_BUTTON_H */ diff --git a/include/byteorder.h b/include/byteorder.h index 8cfd810e54..7a47cbde65 100644 --- a/include/byteorder.h +++ b/include/byteorder.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,4 +8,4 @@ #include <endian.h> -#endif /* __EC_INCLUDE_BYTEORDER_H */ +#endif /* __EC_INCLUDE_BYTEORDER_H */ diff --git a/include/capsense.h b/include/capsense.h index 2c0734aa4d..cb967c595e 100644 --- a/include/capsense.h +++ b/include/capsense.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,4 +11,4 @@ void capsense_interrupt(enum gpio_signal signal); -#endif /* __CROS_EC_CAPSENSE_H */ +#endif /* __CROS_EC_CAPSENSE_H */ diff --git a/include/case_closed_debug.h b/include/case_closed_debug.h index 53c8b1ed17..ebca79fdc0 100644 --- a/include/case_closed_debug.h +++ b/include/case_closed_debug.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/cec.h b/include/cec.h index b1ac6dbbb0..006eeffe6a 100644 --- a/include/cec.h +++ b/include/cec.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/charge_manager.h b/include/charge_manager.h index b6d3c235bf..ccef9d8814 100644 --- a/include/charge_manager.h +++ b/include/charge_manager.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,7 +19,7 @@ /* Only track BC1.2 charge current if we support BC1.2 charging */ #if defined(HAS_TASK_USB_CHG) || defined(HAS_TASK_USB_CHG_P0) || \ - defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK) || \ + defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK) || \ defined(TEST_BUILD) #define CHARGE_MANAGER_BC12 #endif @@ -28,9 +28,12 @@ * Time to delay for detecting the charger type (must be long enough for BC1.2 * driver to get supplier information and notify charge manager). */ -#define CHARGE_DETECT_DELAY (2*SECOND) +#define CHARGE_DETECT_DELAY (2 * SECOND) -/* Commonly-used charge suppliers listed in no particular order */ +/* + * Commonly-used charge suppliers listed in no particular order. + * Don't forget to update CHARGE_SUPPLIER_NAME and supplier_priority. + */ enum charge_supplier { CHARGE_SUPPLIER_NONE = -1, CHARGE_SUPPLIER_PD, @@ -48,14 +51,34 @@ enum charge_supplier { #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 CHARGE_SUPPLIER_DEDICATED, #endif -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - CHARGE_SUPPLIER_WPC_BPP, - CHARGE_SUPPLIER_WPC_EPP, - CHARGE_SUPPLIER_WPC_GPP, -#endif CHARGE_SUPPLIER_COUNT }; +#ifdef CHARGE_MANAGER_BC12 +#define CHARGE_SUPPLIER_NAME_BC12 \ + [CHARGE_SUPPLIER_BC12_DCP] = "BC12_DCP", \ + [CHARGE_SUPPLIER_BC12_CDP] = "BC12_CDP", \ + [CHARGE_SUPPLIER_BC12_SDP] = "BC12_SDP", \ + [CHARGE_SUPPLIER_PROPRIETARY] = "BC12_PROP", \ + [CHARGE_SUPPLIER_TYPEC_UNDER_1_5A] = "USBC_U1_5A", \ + [CHARGE_SUPPLIER_OTHER] = "BC12_OTHER", [CHARGE_SUPPLIER_VBUS] = "VBUS", +#else +#define CHARGE_SUPPLIER_NAME_BC12 +#endif +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 +#define CHARGE_SUPPLIER_NAME_DEDICATED \ + [CHARGE_SUPPLIER_DEDICATED] = "DEDICATED", +#else +#define CHARGE_SUPPLIER_NAME_DEDICATED +#endif +#define CHARGE_SUPPLIER_NAME_QI + +#define CHARGE_SUPPLIER_NAME \ + [CHARGE_SUPPLIER_PD] = "PD", [CHARGE_SUPPLIER_TYPEC] = "USBC", \ + [CHARGE_SUPPLIER_TYPEC_DTS] = "USBC_DTS", \ + CHARGE_SUPPLIER_NAME_BC12 CHARGE_SUPPLIER_NAME_DEDICATED \ + CHARGE_SUPPLIER_NAME_QI + /* * Charge supplier priority: lower number indicates higher priority. * Default priority is in charge_manager.c. It can be overridden by boards. @@ -76,8 +99,7 @@ struct charge_port_info { * @param charge Charge port current / voltage. If NULL, current = 0 * voltage = 0 will be used. */ -void charge_manager_update_charge(int supplier, - int port, +void charge_manager_update_charge(int supplier, int port, const struct charge_port_info *charge); /* Partner port dualrole capabilities */ @@ -114,8 +136,8 @@ enum ceil_requestor { CEIL_REQUESTOR_COUNT, }; -#define CHARGE_PORT_COUNT (CONFIG_USB_PD_PORT_MAX_COUNT + \ - CONFIG_DEDICATED_CHARGE_PORT_COUNT) +#define CHARGE_PORT_COUNT \ + (CONFIG_USB_PD_PORT_MAX_COUNT + CONFIG_DEDICATED_CHARGE_PORT_COUNT) #if (CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0) /** @@ -201,7 +223,7 @@ int charge_manager_get_selected_charge_port(void); * * @return Power limit (uW). */ -int charge_manager_get_power_limit_uw(void); +test_mockable int charge_manager_get_power_limit_uw(void); /** * Get the charger current (mA) value. @@ -284,8 +306,8 @@ int board_set_active_charge_port(int charge_port); * @param max_ma Maximum charge current limit, >= charge_ma. * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv); +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv); /** * Get whether the port is sourcing power on VBUS. @@ -329,9 +351,8 @@ __override_proto int board_charge_port_is_connected(int port); * @param port Dedicated charge port. * @param r USB PD power info to be updated. */ -__override_proto -void board_fill_source_power_info(int port, - struct ec_response_usb_pd_power_info *r); +__override_proto void +board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r); /** * Board specific callback to get vbus voltage. @@ -339,4 +360,7 @@ void board_fill_source_power_info(int port, * @param port Dedicated charge port. */ __override_proto int board_get_vbus_voltage(int port); + +int is_pd_port(int port); + #endif /* __CROS_EC_CHARGE_MANAGER_H */ diff --git a/include/charge_ramp.h b/include/charge_ramp.h index 0745f5ef98..be456a64ec 100644 --- a/include/charge_ramp.h +++ b/include/charge_ramp.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,10 +11,7 @@ #include "timer.h" /* Charge ramp state used for checking VBUS */ -enum chg_ramp_vbus_state { - CHG_RAMP_VBUS_RAMPING, - CHG_RAMP_VBUS_STABLE -}; +enum chg_ramp_vbus_state { CHG_RAMP_VBUS_RAMPING, CHG_RAMP_VBUS_STABLE }; /** * Check if VBUS is too low @@ -81,11 +78,15 @@ int chg_ramp_is_detected(void); * @voltage Negotiated charge voltage. */ void chg_ramp_charge_supplier_change(int port, int supplier, int current, - timestamp_t registration_time, int voltage); + timestamp_t registration_time, + int voltage); #else -static inline void chg_ramp_charge_supplier_change( - int port, int supplier, timestamp_t registration_time) { } +static inline void +chg_ramp_charge_supplier_change(int port, int supplier, + timestamp_t registration_time) +{ +} #endif #endif /* __CROS_EC_CHARGE_RAMP_H */ diff --git a/include/charge_state.h b/include/charge_state.h index ed777c1a64..221947b9d1 100644 --- a/include/charge_state.h +++ b/include/charge_state.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,6 +7,7 @@ #include "common.h" #include "timer.h" +#include "stdbool.h" /* Stuff that's common to all charger implementations can go here. */ @@ -14,14 +15,14 @@ #define PRECHARGE_TIMEOUT CONFIG_BATTERY_PRECHARGE_TIMEOUT /* Power state task polling periods in usec */ -#define CHARGE_POLL_PERIOD_VERY_LONG MINUTE -#define CHARGE_POLL_PERIOD_LONG (MSEC * 500) -#define CHARGE_POLL_PERIOD_CHARGE (MSEC * 250) -#define CHARGE_POLL_PERIOD_SHORT (MSEC * 100) -#define CHARGE_MIN_SLEEP_USEC (MSEC * 50) +#define CHARGE_POLL_PERIOD_VERY_LONG MINUTE +#define CHARGE_POLL_PERIOD_LONG (MSEC * 500) +#define CHARGE_POLL_PERIOD_CHARGE (MSEC * 250) +#define CHARGE_POLL_PERIOD_SHORT (MSEC * 100) +#define CHARGE_MIN_SLEEP_USEC (MSEC * 50) /* If a board hasn't provided a max sleep, use 1 minute as default */ #ifndef CHARGE_MAX_SLEEP_USEC -#define CHARGE_MAX_SLEEP_USEC MINUTE +#define CHARGE_MAX_SLEEP_USEC MINUTE #endif /* Power states */ @@ -36,6 +37,8 @@ enum charge_state { PWR_STATE_IDLE0, /* Idle; AC present */ PWR_STATE_IDLE, + /* Forced Idle */ + PWR_STATE_FORCED_IDLE, /* Discharging */ PWR_STATE_DISCHARGE, /* Discharging and fully charged */ @@ -61,20 +64,13 @@ enum charge_state { /* Debugging constants, in the same order as enum charge_state. This string * table was moved here to sync with enum above. */ -#define CHARGE_STATE_NAME_TABLE { \ - "unchange", \ - "init", \ - "reinit", \ - "idle0", \ - "idle", \ - "discharge", \ - "discharge_full", \ - "charge", \ - "charge_near_full", \ - "error" \ +#define CHARGE_STATE_NAME_TABLE \ + { \ + "unchange", "init", "reinit", "idle0", "idle", "discharge", \ + "discharge_full", "charge", "charge_near_full", \ + "error" \ } - /* End of CHARGE_STATE_NAME_TABLE macro */ - +/* End of CHARGE_STATE_NAME_TABLE macro */ /** * Return current charge state. @@ -99,7 +95,14 @@ uint32_t charge_get_flags(void); /** * Return current battery charge percentage. */ +#if defined(CONFIG_BATTERY) || defined(TEST_BUILD) int charge_get_percent(void); +#else +static inline int charge_get_percent(void) +{ + return 0; +} +#endif /** * Return current battery charge if not using charge manager sub-system. @@ -124,7 +127,7 @@ __override_proto int charge_is_consuming_full_input_current(void); /** * Return non-zero if discharging and battery so low we should shut down. */ -#ifdef CONFIG_CHARGER +#if defined(CONFIG_CHARGER) && defined(CONFIG_BATTERY) int charge_want_shutdown(void); #else static inline int charge_want_shutdown(void) @@ -134,13 +137,41 @@ static inline int charge_want_shutdown(void) #endif /** + * Return true if battery level is below threshold, false otherwise, + * or if SoC can't be determined. + * + * @param transitioned True to check if SoC is previously above threshold + */ +enum batt_threshold_type { + BATT_THRESHOLD_TYPE_LOW = 0, + BATT_THRESHOLD_TYPE_SHUTDOWN +}; +#if defined(CONFIG_CHARGER) && defined(CONFIG_BATTERY) +int battery_is_below_threshold(enum batt_threshold_type type, + bool transitioned); +#else +static inline int battery_is_below_threshold(enum batt_threshold_type type, + bool transitioned) +{ + return 0; +} +#endif + +/** * Return non-zero if the battery level is too low to allow power on, even if * a charger is attached. * * @param power_button_pressed True if the power-up attempt is caused by a * power button press. */ +#ifdef CONFIG_BATTERY int charge_prevent_power_on(int power_button_pressed); +#else +static inline int charge_prevent_power_on(int power_button_pressed) +{ + return 0; +} +#endif /** * Get the last polled battery/charger temperature. @@ -159,8 +190,7 @@ int charge_get_battery_temp(int idx, int *temp_ptr); */ const struct batt_params *charger_current_battery_params(void); - /* Config Charger */ #include "charge_state_v2.h" -#endif /* __CROS_EC_CHARGE_STATE_H */ +#endif /* __CROS_EC_CHARGE_STATE_H */ diff --git a/include/charge_state_v1.h b/include/charge_state_v1.h index f5d464b655..302fc0acf8 100644 --- a/include/charge_state_v1.h +++ b/include/charge_state_v1.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,24 +13,22 @@ #define CHARGER_UPDATE_PERIOD (SECOND * 10) /* Power state error flags */ -#define F_CHARGER_INIT BIT(0) /* Charger initialization */ -#define F_CHARGER_VOLTAGE BIT(1) /* Charger maximum output voltage */ -#define F_CHARGER_CURRENT BIT(2) /* Charger maximum output current */ -#define F_BATTERY_VOLTAGE BIT(3) /* Battery voltage */ -#define F_BATTERY_MODE BIT(8) /* Battery mode */ -#define F_BATTERY_CAPACITY BIT(9) /* Battery capacity */ +#define F_CHARGER_INIT BIT(0) /* Charger initialization */ +#define F_CHARGER_VOLTAGE BIT(1) /* Charger maximum output voltage */ +#define F_CHARGER_CURRENT BIT(2) /* Charger maximum output current */ +#define F_BATTERY_VOLTAGE BIT(3) /* Battery voltage */ +#define F_BATTERY_MODE BIT(8) /* Battery mode */ +#define F_BATTERY_CAPACITY BIT(9) /* Battery capacity */ #define F_BATTERY_STATE_OF_CHARGE BIT(10) /* State of charge, percentage */ -#define F_BATTERY_UNRESPONSIVE BIT(11) /* Battery not responding */ -#define F_BATTERY_NOT_CONNECTED BIT(12) /* Battery not connected */ -#define F_BATTERY_GET_PARAMS BIT(13) /* Any battery parameter bad */ +#define F_BATTERY_UNRESPONSIVE BIT(11) /* Battery not responding */ +#define F_BATTERY_NOT_CONNECTED BIT(12) /* Battery not connected */ +#define F_BATTERY_GET_PARAMS BIT(13) /* Any battery parameter bad */ -#define F_BATTERY_MASK (F_BATTERY_VOLTAGE | \ - F_BATTERY_MODE | \ - F_BATTERY_CAPACITY | F_BATTERY_STATE_OF_CHARGE | \ - F_BATTERY_UNRESPONSIVE | F_BATTERY_NOT_CONNECTED | \ - F_BATTERY_GET_PARAMS) -#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | \ - F_CHARGER_INIT) +#define F_BATTERY_MASK \ + (F_BATTERY_VOLTAGE | F_BATTERY_MODE | F_BATTERY_CAPACITY | \ + F_BATTERY_STATE_OF_CHARGE | F_BATTERY_UNRESPONSIVE | \ + F_BATTERY_NOT_CONNECTED | F_BATTERY_GET_PARAMS) +#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | F_CHARGER_INIT) /* Power state data * Status collection of charging state machine. diff --git a/include/charge_state_v2.h b/include/charge_state_v2.h index 547dc6c63d..0817204774 100644 --- a/include/charge_state_v2.h +++ b/include/charge_state_v2.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -117,8 +117,8 @@ void board_base_reset(void); * @param curr Pointer to struct charge_state_data * @return Action to take. */ -enum critical_shutdown board_critical_shutdown_check( - struct charge_state_data *curr); +enum critical_shutdown +board_critical_shutdown_check(struct charge_state_data *curr); /** * Callback to set battery level for shutdown @@ -223,4 +223,11 @@ __test_only void reset_prev_disp_charge(void); */ __test_only bool charging_progress_displayed(void); +/** + * Callback for boards to request charger to enable bypass mode on/off. + * + * @return True for requesting bypass on. False for requesting bypass off. + */ +int board_should_charger_bypass(void); + #endif /* __CROS_EC_CHARGE_STATE_V2_H */ diff --git a/include/charger.h b/include/charger.h index 66130ce3a5..046ed3acc2 100644 --- a/include/charger.h +++ b/include/charger.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -50,7 +50,7 @@ struct charger_drv { enum ec_error_list (*post_init)(int chgnum); /* Get charger information */ - const struct charger_info * (*get_info)(int chgnum); + const struct charger_info *(*get_info)(int chgnum); /* Get smart battery charger status. Supported flags may vary. */ enum ec_error_list (*get_status)(int chgnum, int *status); @@ -85,12 +85,10 @@ struct charger_drv { enum ec_error_list (*get_voltage)(int chgnum, int *voltage); enum ec_error_list (*set_voltage)(int chgnum, int voltage); - /* Get the measured charge current and voltage in mA/mV */ enum ec_error_list (*get_actual_current)(int chgnum, int *current); enum ec_error_list (*get_actual_voltage)(int chgnum, int *voltage); - /* Discharge battery when on AC power. */ enum ec_error_list (*discharge_on_ac)(int chgnum, int enable); @@ -98,6 +96,10 @@ struct charger_drv { enum ec_error_list (*get_vbus_voltage)(int chgnum, int port, int *voltage); + /* Get the Vsys voltage (mV) from the charger */ + enum ec_error_list (*get_vsys_voltage)(int chgnum, int port, + int *voltage); + /* Set desired input current value */ enum ec_error_list (*set_input_current_limit)(int chgnum, int input_current); @@ -180,13 +182,13 @@ enum chg_id { void charger_get_params(struct charger_params *chg); /* Bits to indicate which fields of struct charger_params could not be read */ -#define CHG_FLAG_BAD_CURRENT 0x00000001 -#define CHG_FLAG_BAD_VOLTAGE 0x00000002 -#define CHG_FLAG_BAD_INPUT_CURRENT 0x00000004 -#define CHG_FLAG_BAD_STATUS 0x00000008 -#define CHG_FLAG_BAD_OPTION 0x00000010 +#define CHG_FLAG_BAD_CURRENT 0x00000001 +#define CHG_FLAG_BAD_VOLTAGE 0x00000002 +#define CHG_FLAG_BAD_INPUT_CURRENT 0x00000004 +#define CHG_FLAG_BAD_STATUS 0x00000008 +#define CHG_FLAG_BAD_OPTION 0x00000010 /* All of the above CHG_FLAG_BAD_* bits */ -#define CHG_FLAG_BAD_ANY 0x0000001f +#define CHG_FLAG_BAD_ANY 0x0000001f /** * Return the closest match the charger can supply to the requested current. @@ -277,6 +279,9 @@ enum ec_error_list charger_discharge_on_ac(int enable); /* Get the VBUS voltage (mV) from the charger */ enum ec_error_list charger_get_vbus_voltage(int port, int *voltage); +/* Get the Vsys voltage (mV) from the charger */ +enum ec_error_list charger_get_vsys_voltage(int port, int *voltage); + /* Custom board function to discharge battery when on AC power */ int board_discharge_on_ac(int enable); @@ -384,10 +389,15 @@ enum ec_error_list charger_enable_linear_charge(int chgnum, bool enable); */ enum ec_error_list charger_enable_bypass_mode(int chgnum, int enable); -/* +/** * Print all charger info for debugging purposes * @param chgnum: charger IC index. */ void print_charger_debug(int chgnum); +/** + * Get the value of CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON + */ +int charger_get_min_bat_pct_for_power_on(void); + #endif /* __CROS_EC_CHARGER_H */ diff --git a/include/charger_detect.h b/include/charger_detect.h index ae2001e418..7371583cd8 100644 --- a/include/charger_detect.h +++ b/include/charger_detect.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/charger_profile_override.h b/include/charger_profile_override.h index 091eb11946..24606d3c3d 100644 --- a/include/charger_profile_override.h +++ b/include/charger_profile_override.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,7 +10,7 @@ #include "charge_state_v2.h" -#define TEMPC_TENTHS_OF_DEG(c) ((c) * 10) +#define TEMPC_TENTHS_OF_DEG(c) ((c)*10) #define CHARGER_PROF_TEMP_C_LAST_RANGE 0xFFFF @@ -69,10 +69,11 @@ int charger_profile_override(struct charge_state_data *curr); * <0 An error occurred. The poll time will be shorter than usual. * Too many errors in a row may trigger some corrective action. */ -int charger_profile_override_common(struct charge_state_data *curr, - const struct fast_charge_params *fast_chg_params, - const struct fast_charge_profile **prev_chg_prof_info, - int batt_vtg_max); +int charger_profile_override_common( + struct charge_state_data *curr, + const struct fast_charge_params *fast_chg_params, + const struct fast_charge_profile **prev_chg_prof_info, + int batt_vtg_max); /* * Access to custom profile params through host commands. diff --git a/include/chipset.h b/include/chipset.h index 840db3aa60..1a5c5a0d2f 100644 --- a/include/chipset.h +++ b/include/chipset.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -29,17 +29,18 @@ * I'll compare it myself with the state(s) I want." */ enum chipset_state_mask { - CHIPSET_STATE_HARD_OFF = 0x01, /* Hard off (G3) */ - CHIPSET_STATE_SOFT_OFF = 0x02, /* Soft off (S5, S4) */ - CHIPSET_STATE_SUSPEND = 0x04, /* Suspend (S3) */ - CHIPSET_STATE_ON = 0x08, /* On (S0) */ - CHIPSET_STATE_STANDBY = 0x10, /* Standby (S0ix) */ + CHIPSET_STATE_HARD_OFF = 0x01, /* Hard off (G3) */ + CHIPSET_STATE_SOFT_OFF = 0x02, /* Soft off (S5, S4) */ + CHIPSET_STATE_SUSPEND = 0x04, /* Suspend (S3) */ + CHIPSET_STATE_ON = 0x08, /* On (S0) */ + CHIPSET_STATE_STANDBY = 0x10, /* Standby (S0ix) */ /* Common combinations */ - CHIPSET_STATE_ANY_OFF = (CHIPSET_STATE_HARD_OFF | - CHIPSET_STATE_SOFT_OFF), /* Any off state */ + CHIPSET_STATE_ANY_OFF = + (CHIPSET_STATE_HARD_OFF | CHIPSET_STATE_SOFT_OFF), /* Any off + state */ /* This combination covers any kind of suspend i.e. S3 or S0ix. */ - CHIPSET_STATE_ANY_SUSPEND = (CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY), + CHIPSET_STATE_ANY_SUSPEND = + (CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY), }; enum critical_shutdown { @@ -138,23 +139,47 @@ static inline int chipset_in_or_transitioning_to_state(int state_mask) return state_mask & CHIPSET_STATE_ANY_OFF; } -static inline void chipset_exit_hard_off(void) { } -static inline void chipset_throttle_cpu(int throttle) { } +static inline void chipset_exit_hard_off(void) +{ +} +static inline void chipset_throttle_cpu(int throttle) +{ +} static inline void chipset_force_shutdown(enum chipset_shutdown_reason reason) { } -static inline void chipset_reset(enum chipset_shutdown_reason reason) { } -static inline void power_interrupt(enum gpio_signal signal) { } -static inline void chipset_handle_espi_reset_assert(void) { } -static inline void chipset_handle_reboot(void) { } -static inline void chipset_reset_request_interrupt(enum gpio_signal signal) { } -static inline void chipset_warm_reset_interrupt(enum gpio_signal signal) { } -static inline void chipset_ap_rst_interrupt(enum gpio_signal signal) { } -static inline void chipset_power_good_interrupt(enum gpio_signal signal) { } -static inline void chipset_watchdog_interrupt(enum gpio_signal signal) { } +static inline void chipset_reset(enum chipset_shutdown_reason reason) +{ +} +static inline void power_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_handle_espi_reset_assert(void) +{ +} +static inline void chipset_handle_reboot(void) +{ +} +static inline void chipset_reset_request_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_warm_reset_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_ap_rst_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_power_good_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_watchdog_interrupt(enum gpio_signal signal) +{ +} -static inline void init_reset_log(void) { } +static inline void init_reset_log(void) +{ +} #endif /* !CONFIG_AP_POWER_CONTROL */ @@ -215,8 +240,9 @@ void chipset_watchdog_interrupt(enum gpio_signal signal); * @param now Current time * @return Action to take */ -__override_proto enum critical_shutdown board_system_is_idle( - uint64_t last_shutdown_time, uint64_t *target, uint64_t now); +__override_proto enum critical_shutdown +board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target, + uint64_t now); #ifdef CONFIG_CMD_AP_RESET_LOG @@ -237,9 +263,19 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, size_t num_reset_log_entries, uint32_t *resets_since_ec_boot); +/** + * Check the reason given in the last call to report_ap_reset() . + * + * @return Reason argument that was passed to the last call to + * report_ap_reset(). Zero if report_ap_reset() has not been called. + */ +enum chipset_shutdown_reason chipset_get_shutdown_reason(void); + #else -static inline void report_ap_reset(enum chipset_shutdown_reason reason) { } +static inline void report_ap_reset(enum chipset_shutdown_reason reason) +{ +} test_mockable_static_inline enum ec_error_list get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, @@ -248,6 +284,11 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, return EC_SUCCESS; } +static inline enum chipset_shutdown_reason chipset_get_shutdown_reason(void) +{ + return CHIPSET_RESET_UNKNOWN; +} + #endif /* !CONFIG_CMD_AP_RESET_LOG */ -#endif /* __CROS_EC_CHIPSET_H */ +#endif /* __CROS_EC_CHIPSET_H */ diff --git a/include/clock.h b/include/clock.h index c64cfe4db5..600649f891 100644 --- a/include/clock.h +++ b/include/clock.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -78,10 +78,10 @@ enum bus_type { void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles); /* Clock gate control modes for clock_enable_peripheral() */ -#define CGC_MODE_RUN BIT(0) -#define CGC_MODE_SLEEP BIT(1) +#define CGC_MODE_RUN BIT(0) +#define CGC_MODE_SLEEP BIT(1) #define CGC_MODE_DSLEEP BIT(2) -#define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP) +#define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP) /** * Enable clock to peripheral by setting the CGC register pertaining @@ -108,4 +108,4 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode); */ void clock_refresh_console_in_use(void); -#endif /* __CROS_EC_CLOCK_H */ +#endif /* __CROS_EC_CLOCK_H */ diff --git a/include/common.h b/include/common.h index 02989c692b..7334fe3aed 100644 --- a/include/common.h +++ b/include/common.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -46,7 +46,7 @@ * #define BAZ CONCAT2(BAR, FOO) * Will evaluate to BAR1, which then evaluates to 42. */ -#define CONCAT_STAGE_1(w, x, y, z) w ## x ## y ## z +#define CONCAT_STAGE_1(w, x, y, z) w##x##y##z #define CONCAT2(w, x) CONCAT_STAGE_1(w, x, , ) #define CONCAT3(w, x, y) CONCAT_STAGE_1(w, x, y, ) #define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z) @@ -58,20 +58,20 @@ * is safe with regards to using nested macros and defined arguments. */ #ifndef CONFIG_ZEPHYR -#define STRINGIFY0(name) #name -#define STRINGIFY(name) STRINGIFY0(name) -#endif /* CONFIG_ZEPHYR */ +#define STRINGIFY0(name) #name +#define STRINGIFY(name) STRINGIFY0(name) +#endif /* CONFIG_ZEPHYR */ /* Macros to access registers */ #define REG64_ADDR(addr) ((volatile uint64_t *)(addr)) #define REG32_ADDR(addr) ((volatile uint32_t *)(addr)) #define REG16_ADDR(addr) ((volatile uint16_t *)(addr)) -#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) +#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) #define REG64(addr) (*REG64_ADDR(addr)) #define REG32(addr) (*REG32_ADDR(addr)) #define REG16(addr) (*REG16_ADDR(addr)) -#define REG8(addr) (*REG8_ADDR(addr)) +#define REG8(addr) (*REG8_ADDR(addr)) /* * Define __aligned(n) and __packed if someone hasn't beat us to it. Linux @@ -184,7 +184,13 @@ */ #define __override_proto #define __override -#define __overridable __attribute__((weak)) +#define __overridable __attribute__((weak)) + +/* + * Attribute that will generate a compiler warning if the return value is not + * used. + */ +#define __warn_unused_result __attribute__((warn_unused_result)) /* * Macros for combining bytes into larger integers. _LE and _BE signify little @@ -198,30 +204,29 @@ #define UINT32_FROM_BYTES(lsb, byte1, byte2, msb) \ ((lsb) | (byte1) << 8 | (byte2) << 16 | (msb) << 24) -#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index) \ +#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index) \ UINT32_FROM_BYTES((data)[(lsb_index)], (data)[(lsb_index) + 1], \ (data)[(lsb_index) + 2], (data)[(lsb_index) + 3]) -#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index) \ +#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index) \ UINT32_FROM_BYTES((data)[(msb_index) + 3], (data)[(msb_index) + 2], \ (data)[(msb_index) + 1], (data)[(msb_index)]) /* There isn't really a better place for this */ #define C_TO_K(temp_c) ((temp_c) + 273) -#define K_TO_C(temp_c) ((temp_c) - 273) +#define K_TO_C(temp_c) ((temp_c)-273) /* * round_divide is part of math_utils, so you may need to import math_utils.h * and link math_utils.o if you use the following macros. */ #define CELSIUS_TO_DECI_KELVIN(temp_c) \ (round_divide(CELSIUS_TO_MILLI_KELVIN(temp_c), 100)) -#define DECI_KELVIN_TO_CELSIUS(temp_dk) \ - (MILLI_KELVIN_TO_CELSIUS((temp_dk) * 100)) -#define MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk) ((temp_mk) - 273150) +#define DECI_KELVIN_TO_CELSIUS(temp_dk) (MILLI_KELVIN_TO_CELSIUS((temp_dk)*100)) +#define MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk) ((temp_mk)-273150) #define MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc) ((temp_mc) + 273150) #define MILLI_KELVIN_TO_KELVIN(temp_mk) (round_divide((temp_mk), 1000)) -#define KELVIN_TO_MILLI_KELVIN(temp_k) ((temp_k) * 1000) +#define KELVIN_TO_MILLI_KELVIN(temp_k) ((temp_k)*1000) #define CELSIUS_TO_MILLI_KELVIN(temp_c) \ - (MILLI_CELSIUS_TO_MILLI_KELVIN((temp_c) * 1000)) + (MILLI_CELSIUS_TO_MILLI_KELVIN((temp_c)*1000)) #define MILLI_KELVIN_TO_CELSIUS(temp_mk) \ (round_divide(MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk), 1000)) @@ -229,14 +234,15 @@ * TARGET_WITH_MARGIN(X, 5) returns X' where X' * 100.5% is almost equal to * but does not exceed X. */ #define TARGET_WITH_MARGIN(target, tenths_percent) \ - (((target) * 1000) / (1000 + (tenths_percent))) + (((target)*1000) / (1000 + (tenths_percent))) /* Call a function, and return the error value unless it returns EC_SUCCESS. */ -#define RETURN_ERROR(fn) do { \ - int error = (fn); \ - if (error != EC_SUCCESS) \ - return error; \ -} while (0) +#define RETURN_ERROR(fn) \ + do { \ + int error = (fn); \ + if (error != EC_SUCCESS) \ + return error; \ + } while (0) /* * Define test_mockable and test_mockable_static for mocking @@ -246,11 +252,15 @@ #define test_mockable __attribute__((weak)) #define test_mockable_static __attribute__((weak)) #define test_mockable_static_inline __attribute__((weak)) +#define test_mockable_noreturn __attribute__((weak)) +#define test_mockable_static_noreturn __attribute__((weak)) #define test_export_static #else #define test_mockable #define test_mockable_static static #define test_mockable_static_inline static inline +#define test_mockable_noreturn noreturn +#define test_mockable_static_noreturn static noreturn #define test_export_static static #endif @@ -366,8 +376,7 @@ enum ec_error_list { /* * Mark functions that collide with stdlib so they can be hidden when linking - * against libraries that require stdlib. HIDE_EC_STDLIB should be defined - * before including common.h from code that links to cstdlib. + * against libraries that require stdlib. */ #ifdef TEST_FUZZ #define __stdlib_compat __attribute__((visibility("hidden"))) @@ -391,12 +400,12 @@ enum ec_error_list { * undefined, rather than defined to something else. This usually * involves tricks with __builtin_strcmp. */ -#define __cfg_select(cfg, empty, otherwise) \ +#define __cfg_select(cfg, empty, otherwise) \ __cfg_select_1(cfg, empty, otherwise) #define __cfg_select_placeholder_ _, -#define __cfg_select_1(value, empty, otherwise) \ +#define __cfg_select_1(value, empty, otherwise) \ __cfg_select_2(__cfg_select_placeholder_##value, empty, otherwise) -#define __cfg_select_2(arg1_or_junk, empty, otherwise) \ +#define __cfg_select_2(arg1_or_junk, empty, otherwise) \ __cfg_select_3(arg1_or_junk _, empty, otherwise) #define __cfg_select_3(_ignore1, _ignore2, select, ...) select @@ -405,13 +414,10 @@ enum ec_error_list { * handling the __builtin_strcmp trickery where a BUILD_ASSERT is * appropriate in the context. */ -#define __cfg_select_build_assert(cfg, value, empty, undef) \ - __cfg_select( \ - value, \ - empty, \ - BUILD_ASSERT( \ - __builtin_strcmp(cfg, #value) == 0); \ - undef) +#define __cfg_select_build_assert(cfg, value, empty, undef) \ + __cfg_select(value, empty, \ + BUILD_ASSERT(__builtin_strcmp(cfg, #value) == 0); \ + undef) /* * Attribute for generating an error if a function is used. @@ -436,16 +442,16 @@ enum ec_error_list { * technique requires that the optimizer be enabled so it can remove * the undefined function call. */ -#define __config_enabled(cfg, value) \ - __cfg_select( \ - value, 1, ({ \ - int __undefined = __builtin_strcmp(cfg, #value) == 0; \ - extern int IS_ENABLED_BAD_ARGS(void) __error( \ - cfg " must be <blank>, or not defined."); \ - if (!__undefined) \ - IS_ENABLED_BAD_ARGS(); \ - 0; \ - })) +#define __config_enabled(cfg, value) \ + __cfg_select(value, 1, ({ \ + int __undefined = \ + __builtin_strcmp(cfg, #value) == 0; \ + extern int IS_ENABLED_BAD_ARGS(void) __error( \ + cfg " must be <blank>, or not defined."); \ + if (!__undefined) \ + IS_ENABLED_BAD_ARGS(); \ + 0; \ + })) /** * Checks if a config option is enabled or disabled @@ -478,7 +484,7 @@ enum ec_error_list { * if the config option is enabled by Zephyr's definition. */ #define IS_ENABLED(option) __cfg_select(option, 1, Z_IS_ENABLED1(option)) -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ /** * Makes a global variable static when a config option is enabled, @@ -490,7 +496,7 @@ enum ec_error_list { * should be defined to nothing or undefined. */ #ifndef CONFIG_ZEPHYR -#define STATIC_IF(option) \ +#define STATIC_IF(option) \ __cfg_select_build_assert(#option, option, static, extern) #else /* @@ -511,7 +517,7 @@ enum ec_error_list { * config option. */ #ifndef CONFIG_ZEPHYR -#define STATIC_IF_NOT(option) \ +#define STATIC_IF_NOT(option) \ __cfg_select_build_assert(#option, option, extern, static) #else /* @@ -522,4 +528,4 @@ enum ec_error_list { __cfg_select(option, extern, COND_CODE_1(option, (extern), (static))) #endif /* CONFIG_ZEPHYR */ -#endif /* __CROS_EC_COMMON_H */ +#endif /* __CROS_EC_COMMON_H */ diff --git a/include/compile_time_macros.h b/include/compile_time_macros.h index 0151f1a391..8330ea5840 100644 --- a/include/compile_time_macros.h +++ b/include/compile_time_macros.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -69,7 +69,7 @@ /* Just in case - http://gcc.gnu.org/onlinedocs/gcc/Offsetof.html */ #ifndef offsetof -#define offsetof(type, member) __builtin_offsetof(type, member) +#define offsetof(type, member) __builtin_offsetof(type, member) #endif #define member_size(type, member) sizeof(((type *)0)->member) @@ -78,7 +78,7 @@ * Bit operation macros. */ #ifndef CONFIG_ZEPHYR -#define BIT(nr) (1U << (nr)) +#define BIT(nr) (1U << (nr)) /* * Set or clear <bit> of <var> depending on <set>. * It also supports setting and clearing (e.g. SET_BIT, CLR_BIT) macros. @@ -86,7 +86,7 @@ #define WRITE_BIT(var, bit, set) \ ((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit))) #endif -#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) /* * Create a bit mask from least significant bit |l| @@ -102,8 +102,8 @@ * warnings for BIT(31+1). */ #ifndef CONFIG_ZEPHYR -#define GENMASK(h, l) (((BIT(h)<<1) - 1) ^ (BIT(l) - 1)) -#define GENMASK_ULL(h, l) (((BIT_ULL(h)<<1) - 1) ^ (BIT_ULL(l) - 1)) +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) #endif #endif /* __CROS_EC_COMPILE_TIME_MACROS_H */ diff --git a/include/compiler.h b/include/compiler.h index b3d99e26af..d684308c95 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,7 +21,7 @@ * macro. */ #ifndef typeof -#define typeof(x) __typeof__(x) +#define typeof(x) __typeof__(x) #endif /** diff --git a/include/config.h b/include/config.h index 523d94a8a8..8ca7973093 100644 --- a/include/config.h +++ b/include/config.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -623,7 +623,7 @@ * are supplied and charging will be disabled after * CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT seconds. */ -#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (30*60*SECOND) +#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (30 * 60 * SECOND) /* * Specify the battery percentage at which the host is told it is full. @@ -695,7 +695,7 @@ * - If system fails to shutdown for some reason and battery further discharges * to 2%, EC will trigger shutdown. */ -#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 /* shutdown if soc <= 4% */ +#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 /* shutdown if soc <= 4% */ /* * Powerd's full_factor. The value comes from: @@ -703,7 +703,7 @@ * * This value is used by the host to calculate the ETA for full charge. */ -#define CONFIG_BATT_HOST_FULL_FACTOR 97 +#define CONFIG_BATT_HOST_FULL_FACTOR 97 /* * Smart battery pass-through host commands. @@ -943,7 +943,6 @@ #undef CONFIG_CHARGER_SM5803 #undef CONFIG_CHARGER_SY21612 - /* Allow run-time completion of the charger driver structure */ #undef CONFIG_CHARGER_RUNTIME_CONFIG @@ -1120,7 +1119,6 @@ */ #undef CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL - /* Enable if CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG should be applied */ #undef CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM @@ -1234,8 +1232,8 @@ * analog signaling. If the AP requires greater than 15W to boot, then see * CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW. */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 /* Don't boot if soc < 2% */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1 +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 /* Don't boot if soc < 2% */ +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1 /* Default: 15000 */ #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON /* Default: Disabled */ @@ -1335,7 +1333,6 @@ #undef CONFIG_TRICKLE_CHARGING /* Wireless chargers */ -#undef CONFIG_WIRELESS_CHARGER_P9221_R7 #undef CONFIG_CPS8100 /*****************************************************************************/ @@ -1395,39 +1392,38 @@ /* Chipset config */ /* AP chipset support; pick at most one */ -#undef CONFIG_CHIPSET_ALDERLAKE /* Intel Alderlake (x86) */ -#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 /* Intel Alderlake (x86) - * with power sequencer - * chip - */ -#undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */ -#undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */ -#undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */ -#undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */ -#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), - * discrete EC control - */ -#undef CONFIG_CHIPSET_ECDRIVEN /* Mock power module */ -#undef CONFIG_CHIPSET_FALCONLITE /* Falcon-lite*/ -#undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */ -#undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */ -#undef CONFIG_CHIPSET_JASPERLAKE /* Intel Jasperlake (x86) */ -#undef CONFIG_CHIPSET_METEORLAKE /* Intel Meteorlake (x86) */ -#undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */ -#undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */ -#undef CONFIG_CHIPSET_MT8192 /* MediaTek MT8192 */ -#undef CONFIG_CHIPSET_CEZANNE /* AMD Cezanne (x86) */ -#undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */ -#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */ -#undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ -#undef CONFIG_CHIPSET_SC7180 /* Qualcomm SC7180 */ -#undef CONFIG_CHIPSET_SC7280 /* Qualcomm SC7280 */ -#undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */ -#undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/ -#undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */ +#undef CONFIG_CHIPSET_ALDERLAKE /* Intel Alderlake (x86) */ +#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 /* Intel Alderlake (x86) \ + * with power sequencer \ + * chip \ + */ +#undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */ +#undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */ +#undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */ +#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), \ + * discrete EC control \ + */ +#undef CONFIG_CHIPSET_ECDRIVEN /* Mock power module */ +#undef CONFIG_CHIPSET_FALCONLITE /* Falcon-lite*/ +#undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */ +#undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */ +#undef CONFIG_CHIPSET_JASPERLAKE /* Intel Jasperlake (x86) */ +#undef CONFIG_CHIPSET_METEORLAKE /* Intel Meteorlake (x86) */ +#undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */ +#undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */ +#undef CONFIG_CHIPSET_MT8192 /* MediaTek MT8192 */ +#undef CONFIG_CHIPSET_CEZANNE /* AMD Cezanne (x86) */ +#undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */ +#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */ +#undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ +#undef CONFIG_CHIPSET_SC7180 /* Qualcomm SC7180 */ +#undef CONFIG_CHIPSET_SC7280 /* Qualcomm SC7280 */ +#undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */ +#undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/ +#undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */ /* Shared chipset support; automatically gets defined below. */ -#undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */ +#undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */ /* Support chipset throttling */ #undef CONFIG_CHIPSET_CAN_THROTTLE @@ -1539,8 +1535,8 @@ * Required Configuration: * - CONFIG_BLINK_LEDS --> List of LEDs (gpio enum names) to use as bits */ -#undef CONFIG_BLINK -#undef CONFIG_BLINK_LEDS /* Ex: GPIO_LED1, GPIO_LED2 */ +#undef CONFIG_BLINK +#undef CONFIG_BLINK_LEDS /* Ex: GPIO_LED1, GPIO_LED2 */ /*****************************************************************************/ /* @@ -1550,20 +1546,20 @@ * console. */ -#undef CONFIG_CMD_ACCELS -#undef CONFIG_CMD_ACCEL_FIFO -#undef CONFIG_CMD_ACCEL_INFO +#undef CONFIG_CMD_ACCELS +#undef CONFIG_CMD_ACCEL_FIFO +#undef CONFIG_CMD_ACCEL_INFO #define CONFIG_CMD_ACCELSPOOF #define CONFIG_CMD_ADC -#undef CONFIG_CMD_ALS +#undef CONFIG_CMD_ALS #define CONFIG_CMD_APTHROTTLE -#undef CONFIG_CMD_BATDEBUG +#undef CONFIG_CMD_BATDEBUG #define CONFIG_CMD_BATTFAKE -#undef CONFIG_CMD_BATT_MFG_ACCESS -#undef CONFIG_CMD_BUTTON +#undef CONFIG_CMD_BATT_MFG_ACCESS +#undef CONFIG_CMD_BUTTON #define CONFIG_CMD_CBI -#undef CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE -#undef CONFIG_CMD_VBUS +#undef CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE +#undef CONFIG_CMD_VBUS /* * HAS_TASK_CHIPSET implies the GSC presence. @@ -1576,97 +1572,97 @@ #undef CONFIG_CMD_CHARGEN #endif #define CONFIG_CMD_CHARGER -#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON -#undef CONFIG_CMD_CHARGER_DUMP -#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE -#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST +#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON +#undef CONFIG_CMD_CHARGER_DUMP +#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE +#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST #define CONFIG_CMD_CHARGE_SUPPLIER_INFO -#undef CONFIG_CMD_CHGRAMP -#undef CONFIG_CMD_CLOCKGATES -#undef CONFIG_CMD_COMXTEST +#undef CONFIG_CMD_CHGRAMP +#undef CONFIG_CMD_CLOCKGATES +#undef CONFIG_CMD_COMXTEST #define CONFIG_CMD_CRASH #define CONFIG_CMD_DEVICE_EVENT -#undef CONFIG_CMD_DLOG -#undef CONFIG_CMD_ECTEMP +#undef CONFIG_CMD_DLOG +#undef CONFIG_CMD_ECTEMP #define CONFIG_CMD_FASTCHARGE -#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_FLASH #define CONFIG_CMD_FLASHINFO -#undef CONFIG_CMD_FLASH_TRISTATE -#undef CONFIG_CMD_FORCETIME -#undef CONFIG_CMD_FPSENSOR_DEBUG +#undef CONFIG_CMD_FLASH_TRISTATE +#undef CONFIG_CMD_FORCETIME +#undef CONFIG_CMD_FPSENSOR_DEBUG #define CONFIG_CMD_GETTIME -#undef CONFIG_CMD_GL3590 -#undef CONFIG_CMD_GPIO_EXTENDED -#undef CONFIG_CMD_GT7288 +#undef CONFIG_CMD_GL3590 +#undef CONFIG_CMD_GPIO_EXTENDED +#undef CONFIG_CMD_GT7288 #define CONFIG_CMD_HASH #define CONFIG_CMD_HCDEBUG -#undef CONFIG_CMD_HOSTCMD -#undef CONFIG_CMD_I2CWEDGE -#undef CONFIG_CMD_I2C_PROTECT +#undef CONFIG_CMD_HOSTCMD +#undef CONFIG_CMD_I2CWEDGE +#undef CONFIG_CMD_I2C_PROTECT #define CONFIG_CMD_I2C_SCAN -#undef CONFIG_CMD_I2C_SPEED -#undef CONFIG_CMD_I2C_STRESS_TEST -#undef CONFIG_CMD_I2C_STRESS_TEST_ACCEL -#undef CONFIG_CMD_I2C_STRESS_TEST_ALS -#undef CONFIG_CMD_I2C_STRESS_TEST_BATTERY -#undef CONFIG_CMD_I2C_STRESS_TEST_CHARGER -#undef CONFIG_CMD_I2C_STRESS_TEST_TCPC +#undef CONFIG_CMD_I2C_SPEED +#undef CONFIG_CMD_I2C_STRESS_TEST +#undef CONFIG_CMD_I2C_STRESS_TEST_ACCEL +#undef CONFIG_CMD_I2C_STRESS_TEST_ALS +#undef CONFIG_CMD_I2C_STRESS_TEST_BATTERY +#undef CONFIG_CMD_I2C_STRESS_TEST_CHARGER +#undef CONFIG_CMD_I2C_STRESS_TEST_TCPC #define CONFIG_CMD_I2C_XFER -#undef CONFIG_CMD_I2C_XFER_RAW +#undef CONFIG_CMD_I2C_XFER_RAW #define CONFIG_CMD_IDLE_STATS #define CONFIG_CMD_INA -#undef CONFIG_CMD_JUMPTAGS +#undef CONFIG_CMD_JUMPTAGS #define CONFIG_CMD_KEYBOARD -#undef CONFIG_CMD_LEDTEST -#undef CONFIG_CMD_MCDP +#undef CONFIG_CMD_LEDTEST +#undef CONFIG_CMD_MCDP #define CONFIG_CMD_MD #define CONFIG_CMD_MEM #define CONFIG_CMD_MFALLOW #define CONFIG_CMD_MMAPINFO #define CONFIG_CMD_PD -#undef CONFIG_CMD_PD_DEV_DUMP_INFO -#undef CONFIG_CMD_PD_FLASH -#undef CONFIG_CMD_PD_TIMER +#undef CONFIG_CMD_PD_DEV_DUMP_INFO +#undef CONFIG_CMD_PD_FLASH +#undef CONFIG_CMD_PD_TIMER #define CONFIG_CMD_PECI -#undef CONFIG_CMD_PLL +#undef CONFIG_CMD_PLL #define CONFIG_CMD_POWERINDEBUG -#undef CONFIG_CMD_POWERLED +#undef CONFIG_CMD_POWERLED #define CONFIG_CMD_PWR_AVG #define CONFIG_CMD_POWER_AP -#undef CONFIG_CMD_PPC_DUMP -#undef CONFIG_CMD_PS2 -#undef CONFIG_CMD_RAND +#undef CONFIG_CMD_PPC_DUMP +#undef CONFIG_CMD_PS2 +#undef CONFIG_CMD_RAND #define CONFIG_CMD_REGULATOR -#undef CONFIG_CMD_RESET_FLAGS +#undef CONFIG_CMD_RESET_FLAGS #define CONFIG_CMD_RETIMER -#undef CONFIG_CMD_RTC -#undef CONFIG_CMD_RTC_ALARM +#undef CONFIG_CMD_RTC +#undef CONFIG_CMD_RTC_ALARM #define CONFIG_CMD_RW -#undef CONFIG_CMD_S5_TIMEOUT -#undef CONFIG_CMD_SCRATCHPAD -#undef CONFIG_CMD_SEVEN_SEG_DISPLAY +#undef CONFIG_CMD_S5_TIMEOUT +#undef CONFIG_CMD_SCRATCHPAD +#undef CONFIG_CMD_SEVEN_SEG_DISPLAY #define CONFIG_CMD_SHMEM -#undef CONFIG_CMD_SLEEP +#undef CONFIG_CMD_SLEEP #define CONFIG_CMD_SLEEPMASK #define CONFIG_CMD_SLEEPMASK_SET -#undef CONFIG_CMD_SPI_FLASH -#undef CONFIG_CMD_SPI_NOR -#undef CONFIG_CMD_SPI_XFER -#undef CONFIG_CMD_STACKOVERFLOW +#undef CONFIG_CMD_SPI_FLASH +#undef CONFIG_CMD_SPI_NOR +#undef CONFIG_CMD_SPI_XFER +#undef CONFIG_CMD_STACKOVERFLOW #define CONFIG_CMD_SYSINFO #define CONFIG_CMD_SYSJUMP #define CONFIG_CMD_SYSLOCK -#undef CONFIG_CMD_TASK_RESET -#undef CONFIG_CMD_TASKREADY -#undef CONFIG_CMD_TCPC_DUMP +#undef CONFIG_CMD_TASK_RESET +#undef CONFIG_CMD_TASKREADY +#undef CONFIG_CMD_TCPC_DUMP #define CONFIG_CMD_TEMP_SENSOR #define CONFIG_CMD_TIMERINFO #define CONFIG_CMD_TYPEC -#undef CONFIG_CMD_USART_INFO -#undef CONFIG_CMD_USB_PD_CABLE -#undef CONFIG_CMD_USB_PD_PE +#undef CONFIG_CMD_USART_INFO +#undef CONFIG_CMD_USB_PD_CABLE +#undef CONFIG_CMD_USB_PD_PE #define CONFIG_CMD_WAITMS -#undef CONFIG_CMD_AP_RESET_LOG +#undef CONFIG_CMD_AP_RESET_LOG /*****************************************************************************/ @@ -2003,6 +1999,15 @@ */ #undef CONFIG_FAN_UPDATE_PERIOD +/* + * Enable fan slow response control mechanism. + * A specific type of fan needs a longer time to output the TACH + * signal to EC after EC outputs the PWM signal to the fan. + * During this period, the driver will read two consecutive RPM = 0. + * In this case, don't step the PWM duty too aggressively + */ +#undef CONFIG_FAN_BYPASS_SLOW_RESPONSE + /*****************************************************************************/ /* Flash configuration */ @@ -2240,7 +2245,6 @@ /* If defined, protect rollback region readback using MPU. */ #undef CONFIG_ROLLBACK_MPU_PROTECT - /* * If defined, inject some locally generated entropy when secret is updated, * using board_get_entropy function. @@ -2342,6 +2346,11 @@ /* Support getting gpio flags. */ #undef CONFIG_GPIO_GET_EXTENDED +/* + * GPU Drivers + */ +#undef CONFIG_GPU_NVIDIA + /* Do we want to detect the lid angle? */ #undef CONFIG_LID_ANGLE @@ -2438,7 +2447,7 @@ #ifdef HAS_TASK_HOSTCMD #define CONFIG_HOSTCMD_EVENTS #else -#undef CONFIG_HOSTCMD_EVENTS +#undef CONFIG_HOSTCMD_EVENTS #endif /* @@ -2468,9 +2477,9 @@ * recess period of CONFIG_HOSTCMD_RATE_LIMITING_RECESS will be * enforced. */ -#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC) -#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC) -#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC) +#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC) +#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC) +#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC) /* PD MCU supports host commands */ #undef CONFIG_HOSTCMD_PD @@ -2515,10 +2524,8 @@ /* Set entry in PD MCU's device rw_hash table */ #define CONFIG_HOSTCMD_RWHASHPD -#if !defined(TEST_BUILD) && !defined(TEST_FUZZ) /* Enable EC_CMD_LOCATE_CHIP */ #define CONFIG_HOSTCMD_LOCATE_CHIP -#endif /* Command to get the EC uptime (and optionally AP reset stats) */ #define CONFIG_HOSTCMD_GET_UPTIME_INFO @@ -2530,11 +2537,11 @@ * List of host commands whose debug output will be suppressed * By default remove periodic commands and commands called often (SENSE). */ -#define CONFIG_SUPPRESSED_HOST_COMMANDS \ +#define CONFIG_SUPPRESSED_HOST_COMMANDS \ EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_USB_PD_DISCOVERY, \ - EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY, \ - EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT, EC_CMD_GET_UPTIME_INFO - + EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY, \ + EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT, \ + EC_CMD_GET_UPTIME_INFO /*****************************************************************************/ @@ -2776,7 +2783,6 @@ #undef CONFIG_INA231 #undef CONFIG_INA3221 - /*****************************************************************************/ /* Inductive charging */ @@ -3011,6 +3017,11 @@ #undef CONFIG_KEYBOARD_CUSTOMIZATION /* + * Allow support multiple keyboard matrix for speical key. + */ +#undef CONFIG_KEYBOARD_MULTIPLE + +/* * Allow board-specific 8042 keyboard callback when a key state is changed. */ #undef CONFIG_KEYBOARD_SCANCODE_CALLBACK @@ -3153,16 +3164,16 @@ #undef CONFIG_LED_POWER_ACTIVE_LOW /* Support for LED driver chip(s) */ -#undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */ -#undef CONFIG_LED_DRIVER_LM3509 /* LM3509, on I2C interface */ +#undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */ +#undef CONFIG_LED_DRIVER_LM3509 /* LM3509, on I2C interface */ #undef CONFIG_LED_DRIVER_LM3630A /* LM3630A, on I2C interface */ -#undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */ -#undef CONFIG_LED_DRIVER_MP3385 /* MPS MP3385, on I2C */ -#undef CONFIG_LED_DRIVER_OZ554 /* O2Micro OZ554, on I2C */ +#undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */ +#undef CONFIG_LED_DRIVER_MP3385 /* MPS MP3385, on I2C */ +#undef CONFIG_LED_DRIVER_OZ554 /* O2Micro OZ554, on I2C */ #undef CONFIG_LED_DRIVER_IS31FL3733B /* Lumissil IS31FL3733B on I2C */ #undef CONFIG_LED_DRIVER_IS31FL3743B /* Lumissil IS31FL3743B on SPI */ -#undef CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ -#undef CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ +#undef CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ +#undef CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ /* Enable late init for is31fl3743b. Work around b:232443638. */ #undef CONFIG_IS31FL3743B_LATE_INIT @@ -3266,15 +3277,15 @@ * SLP signals (SLP_S3, SLP_S4, and SLP_S5) use virtual wires instead of * physical pins with eSPI interface. */ -#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S5 +#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 +#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 +#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 /* MCHP next two items are EC eSPI slave configuration */ /* Maximum clock frequence eSPI EC slave advertises * Values in MHz are 20, 25, 33, 50, and 66 */ -#undef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ +#undef CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ /* EC eSPI slave advertises IO lanes * 0 = Single @@ -3282,7 +3293,7 @@ * 2 = Single and Quad * 3 = Single, Dual, and Quad */ -#undef CONFIG_HOSTCMD_ESPI_EC_MODE +#undef CONFIG_HOST_INTERFACE_ESPI_EC_MODE /* Bit map of eSPI channels EC advertises * bit[0] = 1 Peripheral channel @@ -3290,7 +3301,7 @@ * bit[2] = 1 OOB channel * bit[3] = 1 Flash channel */ -#undef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP +#undef CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP /* * Background information (from Intel eSPI Compatibility Specification): @@ -3321,7 +3332,7 @@ * Don't enable this config if the platform implements the Deep-Sx entry as EC * needs to maintain these pins' states per request. */ -#undef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST +#undef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST /* Base address of low power RAM. */ #undef CONFIG_LPRAM_BASE @@ -3403,9 +3414,6 @@ */ #undef CONFIG_MCDP28X0 -/* Define clock input to MFT module. */ -#undef CONFIG_MFT_INPUT_LFCLK - /* Minute-IA watchdog timer vector number. */ #define CONFIG_MIA_WDT_VEC 0xFF @@ -3577,7 +3585,7 @@ #undef CONFIG_POWER_BUTTON_INIT_IDLE /* Timeout before power button task gives up starting system */ -#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 1 +#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 1 /* * Enable delay between DSW_PWROK and PWRBTN assertion. @@ -3634,10 +3642,12 @@ #undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE /* - * Implement the '%li' printf format as a *32-bit* integer format, - * as it might be expected by non-EC code. + * Allow the use of the "long" printf length modifier ('l') to be in 32-bit + * systems along with any supported conversion specifiers. Note that this also + * reenables support for the 'i' printf format. This config will only take + * effect if sizeof(long) == sizeof(uint32_t). */ -#undef CONFIG_PRINTF_LEGACY_LI_FORMAT +#undef CONFIG_PRINTF_LONG_IS_32BITS /* * On x86 systems, define this option if the CPU_PROCHOT signal is active low. @@ -4147,28 +4157,28 @@ #undef CONFIG_TEMP_SENSOR /* Support particular temperature sensor chips */ -#undef CONFIG_TEMP_SENSOR_ADT7481 /* ADT 7481 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_EC_ADC /* Thermistors on EC's own ADC */ -#undef CONFIG_TEMP_SENSOR_G753 /* G753 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_G782 /* G782 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_OTI502 /* OTI502 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_PCT2075 /* PCT2075 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_SB_TSI /* SB_TSI sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP112 /* TI TMP112 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP411 /* TI TMP411 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP468 /* TI TMP468 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_F75303 /* Fintek F75303 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070 /* AMD_R19ME4070 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_ADT7481 /* ADT 7481 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_EC_ADC /* Thermistors on EC's own ADC */ +#undef CONFIG_TEMP_SENSOR_G753 /* G753 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_G782 /* G782 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_OTI502 /* OTI502 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_PCT2075 /* PCT2075 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_SB_TSI /* SB_TSI sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP112 /* TI TMP112 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP411 /* TI TMP411 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP468 /* TI TMP468 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_F75303 /* Fintek F75303 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070 /* AMD_R19ME4070 sensor, on I2C bus */ /* Compile common code for thermistor support */ #undef CONFIG_THERMISTOR /* Support particular thermistors */ -#undef CONFIG_THERMISTOR_NCP15WB /* NCP15WB thermistor */ +#undef CONFIG_THERMISTOR_NCP15WB /* NCP15WB thermistor */ /* * If defined, image includes lookup tables and helper functions that convert @@ -4680,7 +4690,7 @@ * Some TCPCs need additional time following a VBUS change to internally * debounce the CC line status and updating the CC_STATUS register. */ -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (25*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (25 * MSEC) /* Define EC and TCPC modules are in one integrated chip */ #undef CONFIG_USB_PD_TCPC_ON_CHIP @@ -4805,6 +4815,7 @@ * to provide the product id per port. */ #undef CONFIG_USB_PD_TCPM_MULTI_PS8XXX +#undef CONFIG_USB_PD_TCPM_PS8745 #undef CONFIG_USB_PD_TCPM_PS8751 #undef CONFIG_USB_PD_TCPM_PS8755 #undef CONFIG_USB_PD_TCPM_PS8705 @@ -4969,6 +4980,15 @@ #define CONFIG_USB_PD_TEMP_SENSOR 0 /* + * Time limit in ms for a USB PD power button press to be considered a short + * press + */ +#define CONFIG_USB_PD_SHORT_PRESS_MAX_MS 4000 + +/* Time limit in ms for a USB PD power button press to be considered valid. */ +#define CONFIG_USB_PD_LONG_PRESS_MAX_MS 8000 + +/* * Set the minimum battery percentage to allow a PD port to send resets as a * sink (and risk a hard reset, losing Vbus). Note this may cause a high-power * charger to appear as only a low-power 15W charger until a reset is sent to @@ -5044,6 +5064,12 @@ #undef CONFIG_USBC_PPC_SYV682X /* + * NX20P348x 5V SRC RCP trigger level at 10mV. Define to enable 5V SRC RCP + * mask for can't trigger interrupt signal. + */ +#undef CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE + +/* * SYV682x PPC high voltage power path current limit. Default limit is * 3.3A. See the syv682x header file for permissible values. */ @@ -5064,6 +5090,9 @@ /* PPC has level interrupts and has a dedicated interrupt pin to check */ #undef CONFIG_USBC_PPC_DEDICATED_INT +/* Enable logging related to the PPC. Undefine to reduce EC image size */ +#define CONFIG_USBC_PPC_LOGGING + /* Support for USB type-c superspeed mux */ #undef CONFIG_USBC_SS_MUX @@ -5116,6 +5145,9 @@ /* Common USB / BC1.2 charger detection routines */ #undef CONFIG_USB_CHARGER +/* Only allow PI3USB9201 to advertise itself as BC1.2 client */ +#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201 + /* * Used for bc1.2 chips that need to be triggered from data role swaps instead * of just VBUS changes. @@ -5141,7 +5173,6 @@ /* The delay in ms from power off to power on for MAX14637 */ #define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 1 - /* Enable USB serial console module. */ #undef CONFIG_USB_CONSOLE @@ -5416,7 +5447,6 @@ */ #undef CONFIG_STREAM_SIGNATURE - /*****************************************************************************/ /* @@ -5664,7 +5694,7 @@ * Used to include files for unit and other builds tests. */ - /* Define to enable Policy Engine State Machine. */ +/* Define to enable Policy Engine State Machine. */ #undef CONFIG_TEST_USB_PE_SM /* Define to enable USB State Machine framework. */ @@ -5691,13 +5721,13 @@ /* * The USB port used for CCD. Defaults to 0/C0. */ -#define CONFIG_CCD_USBC_PORT_NUMBER 0 +#define CONFIG_CCD_USBC_PORT_NUMBER 0 /* * The historical default SCI pulse width to the host is 65 microseconds, but * some chipsets may require different widths. */ -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 65 +#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 65 /*****************************************************************************/ /* @@ -5723,9 +5753,9 @@ * Define CONFIG_HOST_ESPI_VW_POWER_SIGNAL if any power signals from the host * are configured as virtual wires. */ -#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) || \ - defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S4) || \ - defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S5) +#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) || \ + defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4) || \ + defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5) #define CONFIG_HOST_ESPI_VW_POWER_SIGNAL #endif @@ -5737,7 +5767,7 @@ * with Key Locker support (TGL+). */ #if defined(CONFIG_POWER_S4_RESIDENCY) && \ - !defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S5) + !defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5) #error "S4_RESIDENCY needs eSPI support or SLP_S5 routed" #endif @@ -5746,7 +5776,7 @@ * without using eSPI for host commands. */ #if (!defined(CONFIG_ZEPHYR) && defined(CONFIG_HOST_ESPI_VW_POWER_SIGNAL) && \ - !defined(CONFIG_HOST_INTERFACE_ESPI)) + !defined(CONFIG_HOST_INTERFACE_ESPI)) #error Must enable eSPI to enable virtual wires. #endif @@ -5777,7 +5807,7 @@ #if !defined(CONFIG_USBC_SS_MUX) #error CONFIG_USBC_SS_MUX must be enabled for USB4 mode support #endif -# if !defined(CONFIG_USB_PD_ALT_MODE_DFP) +#if !defined(CONFIG_USB_PD_ALT_MODE_DFP) #error CONFIG_USB_PD_ALT_MODE_DFP must be enabled for USB4 mode support #endif #endif @@ -5824,9 +5854,9 @@ * Ensure that CONFIG_USB_PD_TCPMV2 is being used with exactly one device type */ #ifdef CONFIG_USB_PD_TCPMV2 -#if defined(CONFIG_USB_VPD) + \ - defined(CONFIG_USB_CTVPD) + \ - defined(CONFIG_USB_DRP_ACC_TRYSRC) != 1 +#if defined(CONFIG_USB_VPD) + defined(CONFIG_USB_CTVPD) + \ + defined(CONFIG_USB_DRP_ACC_TRYSRC) != \ + 1 #error Must define exactly one CONFIG_USB_ device type. #endif #endif @@ -5847,7 +5877,7 @@ #error Define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is limited to TCPMv1 #endif #ifndef CONFIG_USB_PD_3A_PORTS -#define CONFIG_USB_PD_3A_PORTS 1 +#define CONFIG_USB_PD_3A_PORTS 1 #endif /* USB4 support requires at least one port providing 3.0 A */ #if defined(CONFIG_USB_PD_USB4) && CONFIG_USB_PD_3A_PORTS == 0 @@ -5855,14 +5885,13 @@ #endif #endif - /******************************************************************************/ /* * Ensure CONFIG_USB_PD_TCPMV2 and CONFIG_USBC_SS_MUX both are defined. USBC * retimer firmware update feature requires both. */ #if (defined(CONFIG_USBC_RETIMER_FW_UPDATE) && \ - (!(defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USBC_SS_MUX)))) + (!(defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USBC_SS_MUX)))) #error Retimer firmware update requires TCPMv2 and USBC_SS_MUX #endif @@ -5879,8 +5908,7 @@ #error Must select only one type of host communication bus. #endif -#if defined(CONFIG_HOSTCMD_X86) && \ - !defined(CONFIG_HOST_INTERFACE_LPC) && \ +#if defined(CONFIG_HOSTCMD_X86) && !defined(CONFIG_HOST_INTERFACE_LPC) && \ !defined(CONFIG_HOST_INTERFACE_ESPI) #error Must select one type of host communication bus. #endif @@ -5904,11 +5932,11 @@ /* Automatic configuration of RAM banks **************************************/ /* Assume one RAM bank if not specified, auto-compute number of banks */ #ifndef CONFIG_RAM_BANK_SIZE -#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE +#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE #endif #ifndef CONFIG_RAM_BANKS -#define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE) +#define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE) #endif /******************************************************************************/ @@ -5919,13 +5947,12 @@ * the beginning of RAM. */ #ifndef CONFIG_PANIC_DATA_SIZE -#define CONFIG_PANIC_DATA_SIZE sizeof(struct panic_data) +#define CONFIG_PANIC_DATA_SIZE sizeof(struct panic_data) #endif #ifndef CONFIG_PANIC_DATA_BASE -#define CONFIG_PANIC_DATA_BASE (CONFIG_RAM_BASE \ - + CONFIG_RAM_SIZE \ - - CONFIG_PANIC_DATA_SIZE) +#define CONFIG_PANIC_DATA_BASE \ + (CONFIG_RAM_BASE + CONFIG_RAM_SIZE - CONFIG_PANIC_DATA_SIZE) #endif /******************************************************************************/ @@ -5957,7 +5984,6 @@ #endif #endif /* !CONFIG_SHAREDMEM_MINIMUM_SIZE */ - /******************************************************************************/ /* * Disable the built-in console history if using the experimental console. @@ -5970,7 +5996,6 @@ #define CONFIG_CRC8 #endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */ - /******************************************************************************/ /* * Thermal throttling AP must have temperature sensor enabled to get @@ -5989,7 +6014,6 @@ #define CONFIG_TEMP_SENSOR #endif - /******************************************************************************/ /* The Matrix Keyboard Protocol depends on MKBP input devices and events. */ #ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP @@ -6003,18 +6027,18 @@ /******************************************************************************/ /* MKBP events delivery methods. */ #ifdef CONFIG_MKBP_EVENT -#if !defined(CONFIG_MKBP_USE_CUSTOM) && \ - !defined(CONFIG_MKBP_USE_HOST_EVENT) && \ - !defined(CONFIG_MKBP_USE_GPIO) && \ +#if !defined(CONFIG_MKBP_USE_CUSTOM) && \ + !defined(CONFIG_MKBP_USE_HOST_EVENT) && \ + !defined(CONFIG_MKBP_USE_GPIO) && \ !defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT) && \ !defined(CONFIG_MKBP_USE_HECI) #error Please define one of CONFIG_MKBP_USE_* macro. #endif -#if defined(CONFIG_MKBP_USE_CUSTOM) + \ - defined(CONFIG_MKBP_USE_GPIO) + \ - defined(CONFIG_MKBP_USE_HOST_EVENT) + \ - defined(CONFIG_MKBP_USE_HOST_HECI) > 1 +#if defined(CONFIG_MKBP_USE_CUSTOM) + defined(CONFIG_MKBP_USE_GPIO) + \ + defined(CONFIG_MKBP_USE_HOST_EVENT) + \ + defined(CONFIG_MKBP_USE_HOST_HECI) > \ + 1 #error Must select only one type of MKBP event delivery method. #endif #endif /* CONFIG_MKBP_EVENT */ @@ -6031,27 +6055,22 @@ /*****************************************************************************/ /* Define CONFIG_BATTERY if board has a battery. */ -#if defined(CONFIG_BATTERY_BQ20Z453) || \ - defined(CONFIG_BATTERY_BQ27541) || \ - defined(CONFIG_BATTERY_BQ27621) || \ - defined(CONFIG_BATTERY_BQ4050) || \ - defined(CONFIG_BATTERY_MAX17055) || \ - defined(CONFIG_BATTERY_MM8013) || \ +#if defined(CONFIG_BATTERY_BQ20Z453) || defined(CONFIG_BATTERY_BQ27541) || \ + defined(CONFIG_BATTERY_BQ27621) || defined(CONFIG_BATTERY_BQ4050) || \ + defined(CONFIG_BATTERY_MAX17055) || defined(CONFIG_BATTERY_MM8013) || \ defined(CONFIG_BATTERY_SMART) #define CONFIG_BATTERY #endif /*****************************************************************************/ /* Define CONFIG_USBC_PPC if board has a USB Type-C Power Path Controller. */ -#if defined(CONFIG_USBC_PPC_AOZ1380) || \ - defined(CONFIG_USBC_PPC_NX20P3483) || \ +#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3483) || \ defined(CONFIG_USBC_PPC_SN5S330) #define CONFIG_USBC_PPC #endif /* "has a PPC" */ /* Following chips use Power Path Control information from TCPC chip */ -#if defined(CONFIG_USBC_PPC_AOZ1380) || \ - defined(CONFIG_USBC_PPC_NX20P3481) || \ +#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3481) || \ defined(CONFIG_USBC_PPC_NX20P3483) #define CONFIG_USB_PD_PPC #endif @@ -6063,7 +6082,6 @@ #define CONFIG_USBC_PPC_VCONN #endif - /*****************************************************************************/ /* PPC SYV682C is a subset of SYV682X. */ #if defined(CONFIG_USBC_PPC_SYV682C) @@ -6100,13 +6118,11 @@ /*****************************************************************************/ /* Define CONFIG_USBC_OCP if a component can detect overcurrent */ -#if defined(CONFIG_USBC_PPC_AOZ1380) || \ - defined(CONFIG_USBC_PPC_KTU1125) || \ - defined(CONFIG_USBC_PPC_NX20P3481) || \ - defined(CONFIG_USBC_PPC_NX20P3483) || \ - defined(CONFIG_USBC_PPC_SN5S330) || \ - defined(CONFIG_USBC_PPC_SYV682X) || \ - defined(CONFIG_CHARGER_SM5803) || \ +#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_KTU1125) || \ + defined(CONFIG_USBC_PPC_NX20P3481) || \ + defined(CONFIG_USBC_PPC_NX20P3483) || \ + defined(CONFIG_USBC_PPC_SN5S330) || \ + defined(CONFIG_USBC_PPC_SYV682X) || defined(CONFIG_CHARGER_SM5803) || \ defined(CONFIG_USB_PD_TCPM_TCPCI) #define CONFIG_USBC_OCP #endif @@ -6116,14 +6132,10 @@ * Define CONFIG_USB_PD_VBUS_MEASURE_CHARGER if the charger on the board * supports VBUS measurement. */ -#if defined(CONFIG_CHARGER_BD9995X) || \ - defined(CONFIG_CHARGER_RT9466) || \ - defined(CONFIG_CHARGER_RT9467) || \ - defined(CONFIG_CHARGER_RT9490) || \ - defined(CONFIG_CHARGER_MT6370) || \ - defined(CONFIG_CHARGER_BQ25710) || \ - defined(CONFIG_CHARGER_BQ25720) || \ - defined(CONFIG_CHARGER_ISL9241) +#if defined(CONFIG_CHARGER_BD9995X) || defined(CONFIG_CHARGER_RT9466) || \ + defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_RT9490) || \ + defined(CONFIG_CHARGER_MT6370) || defined(CONFIG_CHARGER_BQ25710) || \ + defined(CONFIG_CHARGER_BQ25720) || defined(CONFIG_CHARGER_ISL9241) #define CONFIG_USB_PD_VBUS_MEASURE_CHARGER #ifdef CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT @@ -6162,7 +6174,7 @@ * Define CONFIG_CHARGER_NARROW_VDC for chargers that use a Narrow VDC power * architecture. */ -#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) || \ +#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) || \ defined(CONFIG_CHARGER_ISL9238C) || defined(CONFIG_CHARGER_ISL9241) || \ defined(CONFIG_CHARGER_RAA489000) || defined(CONFIG_CHARGER_SM5803) || \ defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_BQ25720) @@ -6178,7 +6190,6 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */ - #ifdef CONFIG_LED_PWM_COUNT #define CONFIG_LED_PWM #endif /* defined(CONFIG_LED_PWM_COUNT) */ @@ -6213,7 +6224,7 @@ /*****************************************************************************/ /* Define derived USB PD Discharge common path */ -#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \ +#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \ defined(CONFIG_USB_PD_DISCHARGE_TCPC) || \ defined(CONFIG_USB_PD_DISCHARGE_PPC) #define CONFIG_USB_PD_DISCHARGE @@ -6235,6 +6246,7 @@ /* Define derived config options for BC1.2 detection */ #ifdef CONFIG_BC12_DETECT_PI3USB9201 #define CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER +#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201 #endif /*****************************************************************************/ @@ -6258,7 +6270,6 @@ #undef CONFIG_CHIPSET_ALDERLAKE #undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 #undef CONFIG_CHIPSET_APOLLOLAKE -#undef CONFIG_CHIPSET_BRASWELL #undef CONFIG_CHIPSET_CANNONLAKE #undef CONFIG_CHIPSET_COMETLAKE #undef CONFIG_CHIPSET_GEMINILAKE @@ -6286,7 +6297,7 @@ #ifndef CONFIG_AP_POWER_CONTROL #ifdef HAS_TASK_CHIPSET #define CONFIG_AP_POWER_CONTROL -#endif /* HAS_TASK_CHIPSET */ +#endif /* HAS_TASK_CHIPSET */ #endif /* CONFIG_AP_POWER_CONTROL */ /* @@ -6307,12 +6318,11 @@ #endif /* !defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) */ #endif /* defined(HAS_TASK_CHIPSET) */ - #ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW -# ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT -# define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \ +#ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT +#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \ (CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) -# endif +#endif #endif #ifndef CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON @@ -6381,13 +6391,11 @@ /*****************************************************************************/ /* Define derived Chipset configs */ -#if defined(CONFIG_CHIPSET_APOLLOLAKE) || \ - defined(CONFIG_CHIPSET_GEMINILAKE) +#if defined(CONFIG_CHIPSET_APOLLOLAKE) || defined(CONFIG_CHIPSET_GEMINILAKE) #define CONFIG_CHIPSET_APL_GLK #endif -#if defined(CONFIG_CHIPSET_JASPERLAKE) || \ - defined(CONFIG_CHIPSET_TIGERLAKE) || \ +#if defined(CONFIG_CHIPSET_JASPERLAKE) || defined(CONFIG_CHIPSET_TIGERLAKE) || \ defined(CONFIG_CHIPSET_ALDERLAKE) #define CONFIG_CHIPSET_ICELAKE #endif @@ -6397,28 +6405,25 @@ #define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 #endif -#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ - defined(CONFIG_CHIPSET_APOLLOLAKE) || \ - defined(CONFIG_CHIPSET_BRASWELL) || \ - defined(CONFIG_CHIPSET_CANNONLAKE) || \ - defined(CONFIG_CHIPSET_COMETLAKE) || \ +#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ + defined(CONFIG_CHIPSET_APOLLOLAKE) || \ + defined(CONFIG_CHIPSET_CANNONLAKE) || \ + defined(CONFIG_CHIPSET_COMETLAKE) || \ defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE) || \ - defined(CONFIG_CHIPSET_GEMINILAKE) || \ - defined(CONFIG_CHIPSET_ICELAKE) || \ - defined(CONFIG_CHIPSET_METEORLAKE) || \ - defined(CONFIG_CHIPSET_SKYLAKE) + defined(CONFIG_CHIPSET_GEMINILAKE) || \ + defined(CONFIG_CHIPSET_ICELAKE) || \ + defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE) #define CONFIG_POWER_COMMON #endif #if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ - defined(CONFIG_CHIPSET_CANNONLAKE) || \ - defined(CONFIG_CHIPSET_ICELAKE) || \ - defined(CONFIG_CHIPSET_METEORLAKE) || \ - defined(CONFIG_CHIPSET_SKYLAKE) + defined(CONFIG_CHIPSET_CANNONLAKE) || \ + defined(CONFIG_CHIPSET_ICELAKE) || \ + defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE) #define CONFIG_CHIPSET_X86_RSMRST_DELAY #endif -#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) && \ +#if defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3) && \ defined(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE) #error "Cannot use CONFIG_CHIPSET_SLP_S3_L_OVERRIDE if SLP_S3 is a virtual wire" #endif @@ -6443,8 +6448,7 @@ /* * Automatically define CONFIG_ACCEL_LIS2D_COMMON if a child option is defined. */ -#if defined(CONFIG_ACCEL_LIS2DH) || \ - defined(CONFIG_ACCEL_LIS2DE) || \ +#if defined(CONFIG_ACCEL_LIS2DH) || defined(CONFIG_ACCEL_LIS2DE) || \ defined(CONFIG_ACCEL_LNG2DM) #define CONFIG_ACCEL_LIS2D_COMMON #endif @@ -6452,8 +6456,7 @@ /* * Automatically define CONFIG_ACCEL_LIS2DW_COMMON if a child option is defined. */ -#if defined(CONFIG_ACCEL_LIS2DW12) || \ - defined(CONFIG_ACCEL_LIS2DWL) +#if defined(CONFIG_ACCEL_LIS2DW12) || defined(CONFIG_ACCEL_LIS2DWL) #define CONFIG_ACCEL_LIS2DW_COMMON #endif @@ -6461,8 +6464,7 @@ * CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL can't be defined at the same * time. */ -#if defined(CONFIG_ACCEL_LIS2DW12) && \ - defined(CONFIG_ACCEL_LIS2DWL) +#if defined(CONFIG_ACCEL_LIS2DW12) && defined(CONFIG_ACCEL_LIS2DWL) #error "Define only one of CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL" #endif @@ -6500,7 +6502,6 @@ #error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_RW_ROM_RESIDENT_SIZE #endif - #if (CONFIG_RO_ROM_RESIDENT_SIZE == 0) #error CONFIG_RO_ROM_RESIDENT_SIZE is 0 with CONFIG_CHIP_INIT_ROM_REGION defined #endif @@ -6520,11 +6521,13 @@ /* * By default, enable a request for an ACK from AP, on setting the mux, if the - * board supports Burnside Bridge retimer. + * board supports Intel retimer. */ -#if defined(CONFIG_USBC_RETIMER_INTEL_BB) && defined(CONFIG_USB_MUX_VIRTUAL) +#if (defined(CONFIG_USBC_RETIMER_INTEL_BB) || \ + defined(CONFIG_USBC_RETIMER_INTEL_HB)) && \ + defined(CONFIG_USB_MUX_VIRTUAL) #define CONFIG_USB_MUX_AP_ACK_REQUEST -#endif /* CONFIG_USBC_RETIMER_INTEL_BB */ +#endif /* CONFIG_USBC_RETIMER_INTEL_BB || CONFIG_USBC_RETIMER_INTEL_HB */ /*****************************************************************************/ @@ -6546,7 +6549,7 @@ * period. */ #ifdef CONFIG_WATCHDOG -#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS) * 2) +#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS)*2) #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS" #endif #endif @@ -6565,20 +6568,17 @@ #endif /* Enable BMI secondary port if needed. */ -#if defined(CONFIG_MAG_BMI_BMM150) || \ - defined(CONFIG_MAG_BMI_LIS2MDL) +#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_BMI_LIS2MDL) #define CONFIG_BMI_SEC_I2C #endif /* Enable LSM2MDL secondary port if needed. */ -#if defined(CONFIG_MAG_LSM6DSM_BMM150) || \ - defined(CONFIG_MAG_LSM6DSM_LIS2MDL) +#if defined(CONFIG_MAG_LSM6DSM_BMM150) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL) #define CONFIG_LSM6DSM_SEC_I2C #endif /* Load LIS2MDL driver if needed */ -#if defined(CONFIG_MAG_BMI_LIS2MDL) || \ - defined(CONFIG_MAG_LSM6DSM_LIS2MDL) +#if defined(CONFIG_MAG_BMI_LIS2MDL) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL) #define CONFIG_MAG_LIS2MDL #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS #error "The i2c address of the magnetometer is not set." @@ -6586,8 +6586,7 @@ #endif /* Load BMM150 driver if needed */ -#if defined(CONFIG_MAG_BMI_BMM150) || \ - defined(CONFIG_MAG_LSM6DSM_BMM150) +#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_LSM6DSM_BMM150) #define CONFIG_MAG_BMM150 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS #error "The i2c address of the magnetometer is not set." @@ -6620,7 +6619,7 @@ #endif #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ -#if defined(CONFIG_USB_PD_TCPM_ANX3429) || \ +#if defined(CONFIG_USB_PD_TCPM_ANX3429) || \ defined(CONFIG_USB_PD_TCPM_ANX740X) || \ defined(CONFIG_USB_PD_TCPM_ANX7471) /* Note: ANX7447 is handled by its own driver, not ANX74XX. */ @@ -6646,10 +6645,8 @@ /*****************************************************************************/ /* ISH power management related definitions */ -#if defined(CONFIG_ISH_PM_D0I2) || \ - defined(CONFIG_ISH_PM_D0I3) || \ - defined(CONFIG_ISH_PM_D3) || \ - defined(CONFIG_ISH_PM_RESET_PREP) +#if defined(CONFIG_ISH_PM_D0I2) || defined(CONFIG_ISH_PM_D0I3) || \ + defined(CONFIG_ISH_PM_D3) || defined(CONFIG_ISH_PM_RESET_PREP) #ifndef CONFIG_LOW_POWER_IDLE #error "Must define CONFIG_LOW_POWER_IDLE if enable ISH low power states" @@ -6682,7 +6679,6 @@ #endif /* CONFIG_ACCEL_FIFO */ - /* * If USB PD Discharge is enabled, verify that CONFIG_USB_PD_DISCHARGE_GPIO * and CONFIG_USB_PD_PORT_MAX_COUNT, CONFIG_USB_PD_DISCHARGE_TCPC, or @@ -6753,21 +6749,21 @@ #endif #if defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX) -#if defined(CONFIG_USB_PD_TCPM_PS8705) + \ - defined(CONFIG_USB_PD_TCPM_PS8751) + \ - defined(CONFIG_USB_PD_TCPM_PS8755) + \ - defined(CONFIG_USB_PD_TCPM_PS8805) + \ - defined(CONFIG_USB_PD_TCPM_PS8815) < 2 +#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \ + defined(CONFIG_USB_PD_TCPM_PS8755) + \ + defined(CONFIG_USB_PD_TCPM_PS8805) + \ + defined(CONFIG_USB_PD_TCPM_PS8815) < \ + 2 #error "Must select 2 CONFIG_USB_PD_TCPM_PS8* or above if " \ "CONFIG_USB_PD_TCPM_MULTI_PS8XXX is defined." #endif #endif /* CONFIG_USB_PD_TCPM_MULTI_PS8XXX */ -#if defined(CONFIG_USB_PD_TCPM_PS8705) + \ - defined(CONFIG_USB_PD_TCPM_PS8751) + \ - defined(CONFIG_USB_PD_TCPM_PS8755) + \ - defined(CONFIG_USB_PD_TCPM_PS8805) + \ - defined(CONFIG_USB_PD_TCPM_PS8815) > 1 +#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \ + defined(CONFIG_USB_PD_TCPM_PS8755) + \ + defined(CONFIG_USB_PD_TCPM_PS8805) + \ + defined(CONFIG_USB_PD_TCPM_PS8815) > \ + 1 #if !defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX) #error "CONFIG_USB_PD_TCPM_MULTI_PS8XXX MUST be defined if more than one " \ "CONFIG_USB_PD_TCPM_PS8* are intended to support in a board." @@ -6782,25 +6778,25 @@ #endif /* ifndef(CONFIG_BODY_DETECTION_SENSOR) */ #ifndef CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE -#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE 250 /* max sensor odr (Hz) */ +#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE 250 /* max sensor odr (Hz) */ #endif #ifndef CONFIG_BODY_DETECTION_VAR_THRESHOLD -#define CONFIG_BODY_DETECTION_VAR_THRESHOLD 550 /* (mm/s^2)^2 */ +#define CONFIG_BODY_DETECTION_VAR_THRESHOLD 550 /* (mm/s^2)^2 */ #endif #ifndef CONFIG_BODY_DETECTION_CONFIDENCE_DELTA -#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA 525 /* (mm/s^2)^2 */ +#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA 525 /* (mm/s^2)^2 */ #endif #ifndef CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR -#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 120 /* % */ +#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 120 /* % */ #endif #ifndef CONFIG_BODY_DETECTION_ON_BODY_CON -#define CONFIG_BODY_DETECTION_ON_BODY_CON 50 /* % */ +#define CONFIG_BODY_DETECTION_ON_BODY_CON 50 /* % */ #endif #ifndef CONFIG_BODY_DETECTION_OFF_BODY_CON -#define CONFIG_BODY_DETECTION_OFF_BODY_CON 10 /* % */ +#define CONFIG_BODY_DETECTION_OFF_BODY_CON 10 /* % */ #endif #ifndef CONFIG_BODY_DETECTION_STATIONARY_DURATION -#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15 /* second */ +#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15 /* second */ #endif #else /* CONFIG_BODY_DETECTION */ @@ -6844,7 +6840,6 @@ #define ALS_COUNT 0 #endif /* CONFIG_ALS */ - /* * If the EC has exclusive control over CBI EEPROM WP, don't consult the main * flash WP. @@ -6879,9 +6874,9 @@ #else #define CONFIG_ACCELGYRO_ICM_COMM_SPI #endif -#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_ICM_COMM_SPI && - * !CONFIG_ACCELGYRO_ICM_COMM_I2C - */ +#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_ICM_COMM_SPI && \ + * !CONFIG_ACCELGYRO_ICM_COMM_I2C \ + */ #if !defined(CONFIG_ZEPHYR) && !defined(CONFIG_ACCELGYRO_BMI_COMM_SPI) && \ !defined(CONFIG_ACCELGYRO_BMI_COMM_I2C) @@ -6890,9 +6885,9 @@ #else #define CONFIG_ACCELGYRO_BMI_COMM_SPI #endif -#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_BMI_SPI && \ - * !CONFIG_ACCELGYRO_BMI_I2C - */ +#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_BMI_SPI && \ + * !CONFIG_ACCELGYRO_BMI_I2C \ + */ /* AMD STT requires AMD SB-RMI to be enabled */ #if defined(CONFIG_AMD_STT) && !defined(CONFIG_AMD_SB_RMI) @@ -6907,4 +6902,9 @@ #define CONFIG_S5_EXIT_WAIT 4 #endif -#endif /* __CROS_EC_CONFIG_H */ +/* HAS_GPU_DRIVER enables D-Notify and throttling. */ +#if defined(CONFIG_GPU_NVIDIA) +#define HAS_GPU_DRIVER +#endif + +#endif /* __CROS_EC_CONFIG_H */ diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h index d272f5136c..5da01a4d16 100644 --- a/include/config_std_internal_flash.h +++ b/include/config_std_internal_flash.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -37,42 +37,38 @@ * This is NOT a globally defined config, and is only used in this file * for convenience. */ -#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_SHAREDLIB_SIZE) / 2) +#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE_BYTES - CONFIG_SHAREDLIB_SIZE) / 2) /* * The EC uses the one bank of flash to emulate a SPI-like write protect * register with persistent state. */ #define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) /* * By default, there is no shared objects library. However, if configured, the * shared objects library will be placed after the RO image. */ -#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + \ - _IMAGE_SIZE) -#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + \ - _IMAGE_SIZE) -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + _IMAGE_SIZE) +#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + _IMAGE_SIZE) +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + \ - CONFIG_SHAREDLIB_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE _IMAGE_SIZE +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + CONFIG_SHAREDLIB_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE _IMAGE_SIZE -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */ diff --git a/include/console.h b/include/console.h index 457d24cc95..4e40eddac8 100644 --- a/include/console.h +++ b/include/console.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,6 +16,10 @@ #include "zephyr_console_shim.h" #endif +#ifdef __cplusplus +extern "C" { +#endif + /* * Define uart_shell_stop() and uart_shell_start() functions to start/stop the * running shell. To avoid having a guard on the build type, non-Zephyr builds @@ -54,25 +58,9 @@ struct hex_buffer_params { uint16_t size; }; -#define HEX_BUF(_buffer, _size) (&(const struct hex_buffer_params){ \ - .buffer = (_buffer), \ - .size = (_size) \ -}) - -/* - * Define parameters to printing in binary: the value to print, and the number - * of digits to print. - */ - -struct binary_print_params { - unsigned int value; - uint8_t count; -}; - -#define BINARY_VALUE(_value, _count) (&(const struct binary_print_params){ \ - .value = (_value), \ - .count = (_count) \ -}) +#define HEX_BUF(_buffer, _size) \ + (&(const struct hex_buffer_params){ .buffer = (_buffer), \ + .size = (_size) }) #define PRINTF_TIMESTAMP_NOW NULL @@ -81,7 +69,7 @@ struct console_command { /* Command name. Case-insensitive. */ const char *name; /* Handler for the command. argv[0] will be the command name. */ - int (*handler)(int argc, char **argv); + int (*handler)(int argc, const char **argv); #ifdef CONFIG_CONSOLE_CMDHELP /* Description of args */ const char *argdesc; @@ -94,7 +82,7 @@ struct console_command { }; /* Flag bits for when CONFIG_CONSOLE_COMMAND_FLAGS is enabled */ -#define CMD_FLAG_RESTRICTED 0x00000001 +#define CMD_FLAG_RESTRICTED 0x00000001 /* The default .flags value can be overridden in board.h */ #ifndef CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT @@ -116,19 +104,19 @@ static inline int console_is_restricted(void) /* Console channels */ enum console_channel { - #define CONSOLE_CHANNEL(enumeration, string) enumeration, - #include "console_channel.inc" - #undef CONSOLE_CHANNEL +#define CONSOLE_CHANNEL(enumeration, string) enumeration, +#include "console_channel.inc" +#undef CONSOLE_CHANNEL /* Channel count; not itself a channel */ CC_CHANNEL_COUNT }; /* Mask in channel_mask for a particular channel */ -#define CC_MASK(channel) (1U << (channel)) +#define CC_MASK(channel) (1U << (channel)) /* Mask to use to enable all channels */ -#define CC_ALL 0xffffffffU +#define CC_ALL 0xffffffffU /** * Enable a console channel by name @@ -178,20 +166,20 @@ int cputs(enum console_channel channel, const char *outstr); * * @return non-zero if output was truncated. */ -__attribute__((__format__(__printf__, 2, 3))) -int cprintf(enum console_channel channel, const char *format, ...); +__attribute__((__format__(__printf__, 2, 3))) int +cprintf(enum console_channel channel, const char *format, ...); /** * Print formatted output with timestamp. This is like: - * cprintf(channel, "[%pT " + format + "]\n", PRINTF_TIMESTAMP_NOW, ...) + * cprintf(channel, "[<TIMESTAMP> " + format + "]\n", ...) * * @param channel Output channel * @param format Format string; see printf.h for valid formatting codes * * @return non-zero if output was truncated. */ -__attribute__((__format__(__printf__, 2, 3))) -int cprints(enum console_channel channel, const char *format, ...); +__attribute__((__format__(__printf__, 2, 3))) int +cprints(enum console_channel channel, const char *format, ...); /** * Flush the console output for all channels. @@ -205,8 +193,8 @@ void cflush(void); #define ccputs(outstr) cputs(CC_COMMAND, outstr) /* gcc allows variable arg lists in macros; see * http://gcc.gnu.org/onlinedocs/gcc/Variadic-Macros.html */ -#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ## args) -#define ccprints(format, args...) cprints(CC_COMMAND, format, ## args) +#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ##args) +#define ccprints(format, args...) cprints(CC_COMMAND, format, ##args) /** * Called by UART when a line of input is pending. @@ -221,51 +209,47 @@ void console_has_input(void); * long (excluding null terminator). Note this is NOT in * quotes so it can be concatenated to form a struct name. * @param routine Command handling routine, of the form - * int handler(int argc, char **argv) + * int handler(int argc, const char **argv) * @param argdesc String describing arguments to command; NULL if none. * @param help String with one-line description of command, or NULL. * @param flags Per-command flags, if needed. */ #if !defined(HAS_TASK_CONSOLE) && !defined(CONFIG_ZEPHYR) -#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - static int (ROUTINE)(int argc, char **argv) __attribute__((unused)) -#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - static int (ROUTINE)(int argc, char **argv) __attribute__((unused)) +#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + static int(ROUTINE)(int argc, const char **argv) __attribute__((unused)) +#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + static int(ROUTINE)(int argc, const char **argv) __attribute__((unused)) #define DECLARE_CONSOLE_COMMAND_FLAGS(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \ - static int (ROUTINE)(int argc, char **argv) __attribute__((unused)) + static int(ROUTINE)(int argc, const char **argv) __attribute__((unused)) #elif defined(HAS_TASK_CONSOLE) /* We always provde help args, but we may discard them to save space. */ #if defined(CONFIG_CONSOLE_CMDHELP) -#define _HELP_ARGS(A, H) \ - .argdesc = A, \ - .help = H, +#define _HELP_ARGS(A, H) .argdesc = A, .help = H, #else #define _HELP_ARGS(A, H) #endif /* We may or may not have a .flags field */ #ifdef CONFIG_CONSOLE_COMMAND_FLAGS -#define _FLAG_ARGS(F) \ - .flags = F, +#define _FLAG_ARGS(F) .flags = F, #else #define _FLAG_ARGS(F) #endif /* This macro takes all possible args and discards the ones we don't use */ -#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \ - static int (ROUTINE)(int argc, char **argv); \ - static const char __con_cmd_label_##NAME[] = #NAME; \ - _STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16, \ - "command name '" #NAME "' is too long"); \ - const struct console_command __keep __no_sanitize_address \ - __con_cmd_##NAME \ - __attribute__((section(".rodata.cmds." #NAME))) = \ - { .name = __con_cmd_label_##NAME, \ - .handler = ROUTINE, \ - _HELP_ARGS(ARGDESC, HELP) \ - _FLAG_ARGS(FLAGS) \ - } +#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \ + static int(ROUTINE)(int argc, const char **argv); \ + static const char __con_cmd_label_##NAME[] = #NAME; \ + _STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16, \ + "command name '" #NAME "' is too long"); \ + const struct console_command __keep __no_sanitize_address \ + __con_cmd_##NAME \ + __attribute__((section(".rodata.cmds." #NAME))) = { \ + .name = __con_cmd_label_##NAME, \ + .handler = ROUTINE, \ + _HELP_ARGS(ARGDESC, HELP) _FLAG_ARGS(FLAGS) \ + } /* * If the .flags field exists, we can use this to specify its value. If not, @@ -275,8 +259,8 @@ void console_has_input(void); _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS) /* This works as before, for the same reason. */ -#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ +#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT) /* @@ -284,11 +268,15 @@ void console_has_input(void); * the command is never restricted. BE CAREFUL! You should only use this for * commands that either do nothing or that do only safe things. */ -#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ - (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT & \ +#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ + (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT & \ ~CMD_FLAG_RESTRICTED)) -#endif /* HAS_TASK_CONSOLE */ +#endif /* HAS_TASK_CONSOLE */ + +#ifdef __cplusplus +} +#endif -#endif /* __CROS_EC_CONSOLE_H */ +#endif /* __CROS_EC_CONSOLE_H */ diff --git a/include/console_channel.inc b/include/console_channel.inc index 96691c21c3..47f065e268 100644 --- a/include/console_channel.inc +++ b/include/console_channel.inc @@ -1,6 +1,6 @@ /* -*- mode:c -*- * - * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -110,3 +110,6 @@ CONSOLE_CHANNEL(CC_USBPD, "usbpd") #endif CONSOLE_CHANNEL(CC_VBOOT, "vboot") CONSOLE_CHANNEL(CC_HOOK, "hook") +#ifdef HAS_GPU_DRIVER +CONSOLE_CHANNEL(CC_GPU, "gpu") +#endif diff --git a/include/consumer.h b/include/consumer.h index f6d164649e..a331e83a93 100644 --- a/include/consumer.h +++ b/include/consumer.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/crc.h b/include/crc.h index 04a82313d8..85d389e506 100644 --- a/include/crc.h +++ b/include/crc.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/crc8.h b/include/crc8.h index 45b2322b44..c20314311e 100644 --- a/include/crc8.h +++ b/include/crc8.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/cros_board_info.h b/include/cros_board_info.h index 9ed5e1777b..992192e910 100644 --- a/include/cros_board_info.h +++ b/include/cros_board_info.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,21 +10,22 @@ #include "common.h" #include "ec_commands.h" -#define CBI_VERSION_MAJOR 0 -#define CBI_VERSION_MINOR 0 +#define CBI_VERSION_MAJOR 0 +#define CBI_VERSION_MINOR 0 #ifdef CONFIG_CBI_GPIO /* * if CBI is sourced from GPIO, the CBI cache only needs to accomondate * BOARD_VERSION and SKU_ID */ -#define CBI_IMAGE_SIZE (sizeof(struct cbi_header) + (2 * \ - (sizeof(struct cbi_data) + sizeof(uint32_t)))) +#define CBI_IMAGE_SIZE \ + (sizeof(struct cbi_header) + \ + (2 * (sizeof(struct cbi_data) + sizeof(uint32_t)))) #else -#define CBI_IMAGE_SIZE 256 +#define CBI_IMAGE_SIZE 256 #endif -static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 }; /* 'C' 'B' 'I' */ +static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 }; /* 'C' 'B' 'I' */ struct cbi_header { uint8_t magic[3]; @@ -47,9 +48,9 @@ struct cbi_header { } __attribute__((packed)); struct cbi_data { - uint8_t tag; /* enum cbi_data_tag */ - uint8_t size; /* size of value[] */ - uint8_t value[]; /* data value */ + uint8_t tag; /* enum cbi_data_tag */ + uint8_t size; /* size of value[] */ + uint8_t value[]; /* data value */ } __attribute__((packed)); enum cbi_cache_status { @@ -98,6 +99,7 @@ int cbi_get_fw_config(uint32_t *fw_config); int cbi_get_pcb_supplier(uint32_t *pcb_supplier); int cbi_get_ssfc(uint32_t *ssfc); int cbi_get_rework_id(uint64_t *id); +int cbi_get_factory_calibration_data(uint32_t *calibration_data); /** * Get data from CBI store @@ -143,8 +145,8 @@ uint8_t cbi_crc8(const struct cbi_header *h); * @return Address of the byte following the stored data in the * destination buffer */ -uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, - const void *buf, int size); +uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, const void *buf, + int size); /** * Store string data in memory in CBI data format. diff --git a/include/cros_version.h b/include/cros_version.h index 47fa8d1774..8e3429773a 100644 --- a/include/cros_version.h +++ b/include/cros_version.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,8 +14,8 @@ #define CROS_EC_IMAGE_DATA_COOKIE1 0xce778899 #define CROS_EC_IMAGE_DATA_COOKIE2 0xceaabbdd #define CROS_EC_IMAGE_DATA_COOKIE3 0xceeeff00 -#define CROS_EC_IMAGE_DATA_COOKIE3_MASK GENMASK(31, 8) -#define CROS_EC_IMAGE_DATA_COOKIE3_VERSION GENMASK(7, 0) +#define CROS_EC_IMAGE_DATA_COOKIE3_MASK GENMASK(31, 8) +#define CROS_EC_IMAGE_DATA_COOKIE3_VERSION GENMASK(7, 0) #define CROS_FWID_MISSING_STR "CROS_FWID_MISSING" @@ -40,4 +40,4 @@ extern const void *__image_size; * @return Number of commits in integer or 0 on error */ int ver_get_num_commits(enum ec_image copy); -#endif /* __CROS_EC_VERSION_H */ +#endif /* __CROS_EC_VERSION_H */ diff --git a/include/crypto_api.h b/include/crypto_api.h index 8a8ccacf99..c6374ebee4 100644 --- a/include/crypto_api.h +++ b/include/crypto_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 The Chromium OS Authors. All rights reserved. + * Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,8 +26,8 @@ extern "C" { * value exceeds SHA1 size (20 bytes), the rest of the * hash is filled up with zeros. */ -void app_compute_hash(uint8_t *p_buf, size_t num_bytes, - uint8_t *p_hash, size_t hash_len); +void app_compute_hash(uint8_t *p_buf, size_t num_bytes, uint8_t *p_hash, + size_t hash_len); #define CIPHER_SALT_SIZE 16 diff --git a/include/device_event.h b/include/device_event.h index 7a6403e51d..7a9992b0df 100644 --- a/include/device_event.h +++ b/include/device_event.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -50,4 +50,4 @@ static inline void device_set_single_event(int event) */ void device_enable_event(enum ec_device_event event); -#endif /* __CROS_EC_DEVICE_EVENT_H */ +#endif /* __CROS_EC_DEVICE_EVENT_H */ diff --git a/include/device_state.h b/include/device_state.h index e7894ba998..7df80b374d 100644 --- a/include/device_state.h +++ b/include/device_state.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -84,4 +84,4 @@ int device_set_state(enum device_type device, enum device_state state); */ void board_update_device_state(enum device_type device); -#endif /* __CROS_DEVICE_STATE_H */ +#endif /* __CROS_DEVICE_STATE_H */ diff --git a/include/display_7seg.h b/include/display_7seg.h index 4369502672..976d496ccb 100644 --- a/include/display_7seg.h +++ b/include/display_7seg.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,9 +9,9 @@ #define __CROS_EC_DISPLAY_7SEG_H enum seven_seg_module_display { - SEVEN_SEG_CONSOLE_DISPLAY, /* Console data */ - SEVEN_SEG_EC_DISPLAY, /* power state */ - SEVEN_SEG_PORT80_DISPLAY, /* port80 data */ + SEVEN_SEG_CONSOLE_DISPLAY, /* Console data */ + SEVEN_SEG_EC_DISPLAY, /* power state */ + SEVEN_SEG_PORT80_DISPLAY, /* port80 data */ }; /** @@ -23,4 +23,4 @@ enum seven_seg_module_display { */ int display_7seg_write(enum seven_seg_module_display module, uint16_t data); -#endif /* __CROS_EC_DISPLAY_7SEG_H */ +#endif /* __CROS_EC_DISPLAY_7SEG_H */ diff --git a/include/dma.h b/include/dma.h index 1687b5f899..f35826a132 100644 --- a/include/dma.h +++ b/include/dma.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -17,14 +17,14 @@ /* DMA channel options */ struct dma_option { - enum dma_channel channel; /* DMA channel */ - void *periph; /* Pointer to peripheral data register */ - unsigned flags; /* DMA flags for the control register. Normally - used to select memory size. */ + enum dma_channel channel; /* DMA channel */ + void *periph; /* Pointer to peripheral data register */ + unsigned flags; /* DMA flags for the control register. Normally + used to select memory size. */ }; -#define DMA_POLLING_INTERVAL_US 100 /* us */ -#define DMA_TRANSFER_TIMEOUT_US (100 * MSEC) /* us */ +#define DMA_POLLING_INTERVAL_US 100 /* us */ +#define DMA_TRANSFER_TIMEOUT_US (100 * MSEC) /* us */ /** * Get a pointer to a DMA channel. @@ -117,7 +117,7 @@ void dma_dump(enum dma_channel channel); * Testing: Test that DMA works correctly for memory to memory transfers */ void dma_test(enum dma_channel channel); -#endif /* CONFIG_DMA_HELP */ +#endif /* CONFIG_DMA_HELP */ /** * Clear the DMA interrupt/event flags for a given channel diff --git a/include/dps.h b/include/dps.h index 151c6b3f09..0cb2a9455b 100644 --- a/include/dps.h +++ b/include/dps.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -68,4 +68,14 @@ bool dps_is_enabled(void); */ void dps_update_stabilized_time(int port); +#ifdef TEST_BUILD +__test_only void dps_enable(bool en); +__test_only int dps_init(void); +__test_only struct dps_config_t *dps_get_config(void); +__test_only bool dps_is_fake_enabled(void); +__test_only int dps_get_fake_mv(void); +__test_only int dps_get_fake_ma(void); +__test_only int *dps_get_debug_level(void); +#endif + #endif /* __CROS_EC_DPS__H */ diff --git a/include/dptf.h b/include/dptf.h index c34e8ea47a..b71b4cf5c0 100644 --- a/include/dptf.h +++ b/include/dptf.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -27,10 +27,10 @@ int dptf_get_fan_duty_target(void); /** * Set/enable the thresholds. */ -void dptf_set_temp_threshold(int sensor_id, /* zero-based sensor index */ - int temp, /* in degrees K */ - int idx, /* which threshold (0 or 1) */ - int enable); /* true = on, false = off */ +void dptf_set_temp_threshold(int sensor_id, /* zero-based sensor index */ + int temp, /* in degrees K */ + int idx, /* which threshold (0 or 1) */ + int enable); /* true = on, false = off */ /** * Return the ID of a temp sensor that has crossed its threshold since the last @@ -48,4 +48,4 @@ void dptf_set_charging_current_limit(int ma); */ int dptf_get_charging_current_limit(void); -#endif /* __CROS_EC_DPTF_H */ +#endif /* __CROS_EC_DPTF_H */ diff --git a/include/driver/accel_bma2x2.h b/include/driver/accel_bma2x2.h index 3a46c7c050..c6be3b0c87 100644 --- a/include/driver/accel_bma2x2.h +++ b/include/driver/accel_bma2x2.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,144 +12,143 @@ /*** Chip-specific registers ***/ /* REGISTER ADDRESS DEFINITIONS */ -#define BMA2x2_EEP_OFFSET 0x16 -#define BMA2x2_IMAGE_BASE 0x38 -#define BMA2x2_IMAGE_LEN 22 -#define BMA2x2_CHIP_ID_ADDR 0x00 -#define BMA255_CHIP_ID_MAJOR 0xfa +#define BMA2x2_EEP_OFFSET 0x16 +#define BMA2x2_IMAGE_BASE 0x38 +#define BMA2x2_IMAGE_LEN 22 +#define BMA2x2_CHIP_ID_ADDR 0x00 +#define BMA255_CHIP_ID_MAJOR 0xfa /* DATA ADDRESS DEFINITIONS */ -#define BMA2x2_X_AXIS_LSB_ADDR 0x02 -#define BMA2x2_X_AXIS_MSB_ADDR 0x03 -#define BMA2x2_Y_AXIS_LSB_ADDR 0x04 -#define BMA2x2_Y_AXIS_MSB_ADDR 0x05 -#define BMA2x2_Z_AXIS_LSB_ADDR 0x06 -#define BMA2x2_Z_AXIS_MSB_ADDR 0x07 -#define BMA2x2_TEMP_ADDR 0x08 +#define BMA2x2_X_AXIS_LSB_ADDR 0x02 +#define BMA2x2_X_AXIS_MSB_ADDR 0x03 +#define BMA2x2_Y_AXIS_LSB_ADDR 0x04 +#define BMA2x2_Y_AXIS_MSB_ADDR 0x05 +#define BMA2x2_Z_AXIS_LSB_ADDR 0x06 +#define BMA2x2_Z_AXIS_MSB_ADDR 0x07 +#define BMA2x2_TEMP_ADDR 0x08 -#define BMA2x2_AXIS_LSB_NEW_DATA 0x01 +#define BMA2x2_AXIS_LSB_NEW_DATA 0x01 /* STATUS ADDRESS DEFINITIONS */ -#define BMA2x2_STAT1_ADDR 0x09 -#define BMA2x2_STAT2_ADDR 0x0A -#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B -#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C -#define BMA2x2_STAT_FIFO_ADDR 0x0E -#define BMA2x2_RANGE_SELECT_ADDR 0x0F -#define BMA2x2_RANGE_SELECT_MSK 0x0F -#define BMA2x2_RANGE_2G 3 -#define BMA2x2_RANGE_4G 5 -#define BMA2x2_RANGE_8G 8 -#define BMA2x2_RANGE_16G 12 - -#define BMA2x2_RANGE_TO_REG(_range) \ +#define BMA2x2_STAT1_ADDR 0x09 +#define BMA2x2_STAT2_ADDR 0x0A +#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B +#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C +#define BMA2x2_STAT_FIFO_ADDR 0x0E +#define BMA2x2_RANGE_SELECT_ADDR 0x0F +#define BMA2x2_RANGE_SELECT_MSK 0x0F +#define BMA2x2_RANGE_2G 3 +#define BMA2x2_RANGE_4G 5 +#define BMA2x2_RANGE_8G 8 +#define BMA2x2_RANGE_16G 12 + +#define BMA2x2_RANGE_TO_REG(_range) \ ((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \ BMA2x2_RANGE_8G + ((_range) / 16) * 4) -#define BMA2x2_REG_TO_RANGE(_reg) \ - ((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg) - BMA2x2_RANGE_2G : \ - 8 + ((_reg) - BMA2x2_RANGE_8G) * 2) - -#define BMA2x2_BW_SELECT_ADDR 0x10 -#define BMA2x2_BW_MSK 0x1F -#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.8125HZ */ -#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.625HZ */ -#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */ -#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */ -#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */ -#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */ -#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */ -#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */ +#define BMA2x2_REG_TO_RANGE(_reg) \ + ((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg)-BMA2x2_RANGE_2G : \ + 8 + ((_reg)-BMA2x2_RANGE_8G) * 2) + +#define BMA2x2_BW_SELECT_ADDR 0x10 +#define BMA2x2_BW_MSK 0x1F +#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.8125HZ */ +#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.625HZ */ +#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */ +#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */ +#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */ +#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */ +#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */ +#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */ /* Do not use BW lower than 7813, because __fls cannot be call for 0 */ -#define BMA2x2_BW_TO_REG(_bw) \ - ((_bw) < 125000 ? \ - BMA2x2_BW_7_81HZ + __fls(((_bw) * 10) / 78125) : \ - BMA2x2_BW_125HZ + __fls((_bw) / 125000)) - -#define BMA2x2_REG_TO_BW(_reg) \ - ((_reg) < BMA2x2_BW_125HZ ? \ - (78125 << ((_reg) - BMA2x2_BW_7_81HZ)) / 10 : \ - 125000 << ((_reg) - BMA2x2_BW_125HZ)) - -#define BMA2x2_MODE_CTRL_ADDR 0x11 -#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12 -#define BMA2x2_DATA_CTRL_ADDR 0x13 -#define BMA2x2_DATA_HIGH_BW 0x80 -#define BMA2x2_DATA_SHADOW_DIS 0x40 -#define BMA2x2_RST_ADDR 0x14 -#define BMA2x2_CMD_SOFT_RESET 0xb6 +#define BMA2x2_BW_TO_REG(_bw) \ + ((_bw) < 125000 ? BMA2x2_BW_7_81HZ + __fls(((_bw)*10) / 78125) : \ + BMA2x2_BW_125HZ + __fls((_bw) / 125000)) + +#define BMA2x2_REG_TO_BW(_reg) \ + ((_reg) < BMA2x2_BW_125HZ ? \ + (78125 << ((_reg)-BMA2x2_BW_7_81HZ)) / 10 : \ + 125000 << ((_reg)-BMA2x2_BW_125HZ)) + +#define BMA2x2_MODE_CTRL_ADDR 0x11 +#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12 +#define BMA2x2_DATA_CTRL_ADDR 0x13 +#define BMA2x2_DATA_HIGH_BW 0x80 +#define BMA2x2_DATA_SHADOW_DIS 0x40 +#define BMA2x2_RST_ADDR 0x14 +#define BMA2x2_CMD_SOFT_RESET 0xb6 /* INTERRUPT ADDRESS DEFINITIONS */ -#define BMA2x2_INTR_ENABLE1_ADDR 0x16 -#define BMA2x2_INTR_ENABLE2_ADDR 0x17 -#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18 -#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19 -#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A -#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B -#define BMA2x2_INTR_SOURCE_ADDR 0x1E -#define BMA2x2_INTR_SET_ADDR 0x20 -#define BMA2x2_INTR_CTRL_ADDR 0x21 -#define BMA2x2_INTR_CTRL_RST_INT 0x80 +#define BMA2x2_INTR_ENABLE1_ADDR 0x16 +#define BMA2x2_INTR_ENABLE2_ADDR 0x17 +#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18 +#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19 +#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A +#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B +#define BMA2x2_INTR_SOURCE_ADDR 0x1E +#define BMA2x2_INTR_SET_ADDR 0x20 +#define BMA2x2_INTR_CTRL_ADDR 0x21 +#define BMA2x2_INTR_CTRL_RST_INT 0x80 /* FEATURE ADDRESS DEFINITIONS */ -#define BMA2x2_LOW_DURN_ADDR 0x22 -#define BMA2x2_LOW_THRES_ADDR 0x23 -#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24 -#define BMA2x2_HIGH_DURN_ADDR 0x25 -#define BMA2x2_HIGH_THRES_ADDR 0x26 -#define BMA2x2_SLOPE_DURN_ADDR 0x27 -#define BMA2x2_SLOPE_THRES_ADDR 0x28 -#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29 -#define BMA2x2_TAP_PARAM_ADDR 0x2A -#define BMA2x2_TAP_THRES_ADDR 0x2B -#define BMA2x2_ORIENT_PARAM_ADDR 0x2C -#define BMA2x2_THETA_BLOCK_ADDR 0x2D -#define BMA2x2_THETA_FLAT_ADDR 0x2E -#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F -#define BMA2x2_SELFTEST_ADDR 0x32 -#define BMA2x2_EEPROM_CTRL_ADDR 0x33 -#define BMA2x2_EEPROM_REMAIN_OFF 4 -#define BMA2x2_EEPROM_REMAIN_MSK 0xF0 -#define BMA2x2_EEPROM_LOAD 0x08 -#define BMA2x2_EEPROM_RDY 0x04 -#define BMA2x2_EEPROM_PROG 0x02 -#define BMA2x2_EEPROM_PROG_EN 0x01 -#define BMA2x2_SERIAL_CTRL_ADDR 0x34 +#define BMA2x2_LOW_DURN_ADDR 0x22 +#define BMA2x2_LOW_THRES_ADDR 0x23 +#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24 +#define BMA2x2_HIGH_DURN_ADDR 0x25 +#define BMA2x2_HIGH_THRES_ADDR 0x26 +#define BMA2x2_SLOPE_DURN_ADDR 0x27 +#define BMA2x2_SLOPE_THRES_ADDR 0x28 +#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29 +#define BMA2x2_TAP_PARAM_ADDR 0x2A +#define BMA2x2_TAP_THRES_ADDR 0x2B +#define BMA2x2_ORIENT_PARAM_ADDR 0x2C +#define BMA2x2_THETA_BLOCK_ADDR 0x2D +#define BMA2x2_THETA_FLAT_ADDR 0x2E +#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F +#define BMA2x2_SELFTEST_ADDR 0x32 +#define BMA2x2_EEPROM_CTRL_ADDR 0x33 +#define BMA2x2_EEPROM_REMAIN_OFF 4 +#define BMA2x2_EEPROM_REMAIN_MSK 0xF0 +#define BMA2x2_EEPROM_LOAD 0x08 +#define BMA2x2_EEPROM_RDY 0x04 +#define BMA2x2_EEPROM_PROG 0x02 +#define BMA2x2_EEPROM_PROG_EN 0x01 +#define BMA2x2_SERIAL_CTRL_ADDR 0x34 /* OFFSET ADDRESS DEFINITIONS */ -#define BMA2x2_OFFSET_CTRL_ADDR 0x36 -#define BMA2x2_OFFSET_RESET 0x80 -#define BMA2x2_OFFSET_TRIGGER_OFF 5 -#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF) -#define BMA2x2_OFFSET_CAL_READY 0x10 -#define BMA2x2_OFFSET_CAL_SLOW_X 0x04 -#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02 -#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01 - -#define BMA2x2_OFC_SETTING_ADDR 0x37 -#define BMA2x2_OFC_TARGET_AXIS_OFF 1 -#define BMA2x2_OFC_TARGET_AXIS_LEN 2 +#define BMA2x2_OFFSET_CTRL_ADDR 0x36 +#define BMA2x2_OFFSET_RESET 0x80 +#define BMA2x2_OFFSET_TRIGGER_OFF 5 +#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF) +#define BMA2x2_OFFSET_CAL_READY 0x10 +#define BMA2x2_OFFSET_CAL_SLOW_X 0x04 +#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02 +#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01 + +#define BMA2x2_OFC_SETTING_ADDR 0x37 +#define BMA2x2_OFC_TARGET_AXIS_OFF 1 +#define BMA2x2_OFC_TARGET_AXIS_LEN 2 #define BMA2x2_OFC_TARGET_AXIS(_axis) \ (BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF) -#define BMA2x2_OFC_TARGET_0G 0 -#define BMA2x2_OFC_TARGET_PLUS_1G 1 -#define BMA2x2_OFC_TARGET_MINUS_1G 2 +#define BMA2x2_OFC_TARGET_0G 0 +#define BMA2x2_OFC_TARGET_PLUS_1G 1 +#define BMA2x2_OFC_TARGET_MINUS_1G 2 -#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38 -#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39 -#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A +#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38 +#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39 +#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A /* GP ADDRESS DEFINITIONS */ -#define BMA2x2_GP0_ADDR 0x3B -#define BMA2x2_GP1_ADDR 0x3C +#define BMA2x2_GP0_ADDR 0x3B +#define BMA2x2_GP1_ADDR 0x3C /* FIFO ADDRESS DEFINITIONS */ -#define BMA2x2_FIFO_MODE_ADDR 0x3E -#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F -#define BMA2x2_FIFO_WML_TRIG 0x30 +#define BMA2x2_FIFO_MODE_ADDR 0x3E +#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F +#define BMA2x2_FIFO_WML_TRIG 0x30 /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define BMA2x2_RESOLUTION 12 +#define BMA2x2_RESOLUTION 12 #endif /* __CROS_EC_ACCEL_BMA2x2_H */ diff --git a/include/driver/accel_bma2x2_public.h b/include/driver/accel_bma2x2_public.h index 731fcebbc9..04d7a33e4c 100644 --- a/include/driver/accel_bma2x2_public.h +++ b/include/driver/accel_bma2x2_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,27 +14,27 @@ extern const struct accelgyro_drv bma2x2_accel_drv; /* I2C ADDRESS DEFINITIONS */ /* The following definition of I2C address is used for the following sensors -* BMA253 -* BMA255 -* BMA355 -* BMA280 -* BMA282 -* BMA223 -* BMA254 -* BMA284 -* BMA250E -* BMA222E -*/ -#define BMA2x2_I2C_ADDR1_FLAGS 0x18 -#define BMA2x2_I2C_ADDR2_FLAGS 0x19 + * BMA253 + * BMA255 + * BMA355 + * BMA280 + * BMA282 + * BMA223 + * BMA254 + * BMA284 + * BMA250E + * BMA222E + */ +#define BMA2x2_I2C_ADDR1_FLAGS 0x18 +#define BMA2x2_I2C_ADDR2_FLAGS 0x19 /* The following definition of I2C address is used for the following sensors -* BMC150 -* BMC056 -* BMC156 -*/ -#define BMA2x2_I2C_ADDR3_FLAGS 0x10 -#define BMA2x2_I2C_ADDR4_FLAGS 0x11 + * BMC150 + * BMC056 + * BMC156 + */ +#define BMA2x2_I2C_ADDR3_FLAGS 0x10 +#define BMA2x2_I2C_ADDR4_FLAGS 0x11 /* * Min and Max sampling frequency in mHz. @@ -43,8 +43,7 @@ extern const struct accelgyro_drv bma2x2_accel_drv; * (see CONFIG_MOTION_MIN_SENSE_WAIT_TIME), we may read too early when * other sensors are active. */ -#define BMA255_ACCEL_MIN_FREQ 7810 -#define BMA255_ACCEL_MAX_FREQ \ - MOTION_MAX_SENSOR_FREQUENCY(125000, 15625) +#define BMA255_ACCEL_MIN_FREQ 7810 +#define BMA255_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(125000, 15625) #endif /* CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H */ diff --git a/include/driver/accel_lis2dw12_public.h b/include/driver/accel_lis2dw12_public.h index 751df15f86..5596e6ba6a 100644 --- a/include/driver/accel_lis2dw12_public.h +++ b/include/driver/accel_lis2dw12_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,18 +17,18 @@ extern const struct accelgyro_drv lis2dw12_drv; * 7-bit address is 011000Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define LIS2DW12_ADDR0 0x18 -#define LIS2DW12_ADDR1 0x19 +#define LIS2DW12_ADDR0 0x18 +#define LIS2DW12_ADDR1 0x19 -#define LIS2DWL_ADDR0_FLAGS 0x18 -#define LIS2DWL_ADDR1_FLAGS 0x19 +#define LIS2DWL_ADDR0_FLAGS 0x18 +#define LIS2DWL_ADDR1_FLAGS 0x19 -#define LIS2DW12_EN_BIT 0x01 -#define LIS2DW12_DIS_BIT 0x00 +#define LIS2DW12_EN_BIT 0x01 +#define LIS2DW12_DIS_BIT 0x00 /* Absolute Acc rate. */ -#define LIS2DW12_ODR_MIN_VAL 12500 -#define LIS2DW12_ODR_MAX_VAL \ +#define LIS2DW12_ODR_MIN_VAL 12500 +#define LIS2DW12_ODR_MAX_VAL \ MOTION_MAX_SENSOR_FREQUENCY(1600000, LIS2DW12_ODR_MIN_VAL) void lis2dw12_interrupt(enum gpio_signal signal); diff --git a/include/driver/accelgyro_bmi160.h b/include/driver/accelgyro_bmi160.h index bd5637c2ba..8c6310e65b 100644 --- a/include/driver/accelgyro_bmi160.h +++ b/include/driver/accelgyro_bmi160.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,253 +12,251 @@ #include "driver/accelgyro_bmi160_public.h" #include "mag_bmm150.h" -#define BMI160_CHIP_ID 0x00 -#define BMI160_CHIP_ID_MAJOR 0xd1 -#define BMI168_CHIP_ID_MAJOR 0xd2 +#define BMI160_CHIP_ID 0x00 +#define BMI160_CHIP_ID_MAJOR 0xd1 +#define BMI168_CHIP_ID_MAJOR 0xd2 -#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10 -#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80 -#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60 +#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10 +#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80 +#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60 - -#define BMI160_ERR_REG 0x02 -#define BMI160_PMU_STATUS 0x03 -#define BMI160_PMU_MAG_OFFSET 0 -#define BMI160_PMU_GYR_OFFSET 2 -#define BMI160_PMU_ACC_OFFSET 4 +#define BMI160_ERR_REG 0x02 +#define BMI160_PMU_STATUS 0x03 +#define BMI160_PMU_MAG_OFFSET 0 +#define BMI160_PMU_GYR_OFFSET 2 +#define BMI160_PMU_ACC_OFFSET 4 #define BMI160_PMU_SENSOR_STATUS(_sensor_type, _val) \ (((_val) >> (4 - 2 * (_sensor_type))) & 0x3) -#define BMI160_PMU_SUSPEND 0 -#define BMI160_PMU_NORMAL 1 -#define BMI160_PMU_LOW_POWER 2 -#define BMI160_PMU_FAST_STARTUP 3 - -#define BMI160_MAG_X_L_G 0x04 -#define BMI160_MAG_X_H_G 0x05 -#define BMI160_MAG_Y_L_G 0x06 -#define BMI160_MAG_Y_H_G 0x07 -#define BMI160_MAG_Z_L_G 0x08 -#define BMI160_MAG_Z_H_G 0x09 -#define BMI160_RHALL_L_G 0x0a -#define BMI160_RHALL_H_G 0x0b -#define BMI160_GYR_X_L_G 0x0c -#define BMI160_GYR_X_H_G 0x0d -#define BMI160_GYR_Y_L_G 0x0e -#define BMI160_GYR_Y_H_G 0x0f -#define BMI160_GYR_Z_L_G 0x10 -#define BMI160_GYR_Z_H_G 0x11 -#define BMI160_ACC_X_L_G 0x12 -#define BMI160_ACC_X_H_G 0x13 -#define BMI160_ACC_Y_L_G 0x14 -#define BMI160_ACC_Y_H_G 0x15 -#define BMI160_ACC_Z_L_G 0x16 -#define BMI160_ACC_Z_H_G 0x17 - -#define BMI160_SENSORTIME_0 0x18 -#define BMI160_SENSORTIME_1 0x19 -#define BMI160_SENSORTIME_2 0x1a - -#define BMI160_STATUS 0x1b -#define BMI160_POR_DETECTED BIT(0) -#define BMI160_GYR_SLF_TST BIT(1) -#define BMI160_MAG_MAN_OP BIT(2) -#define BMI160_FOC_RDY BIT(3) -#define BMI160_NVM_RDY BIT(4) -#define BMI160_DRDY_MAG BIT(5) -#define BMI160_DRDY_GYR BIT(6) -#define BMI160_DRDY_ACC BIT(7) -#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) +#define BMI160_PMU_SUSPEND 0 +#define BMI160_PMU_NORMAL 1 +#define BMI160_PMU_LOW_POWER 2 +#define BMI160_PMU_FAST_STARTUP 3 + +#define BMI160_MAG_X_L_G 0x04 +#define BMI160_MAG_X_H_G 0x05 +#define BMI160_MAG_Y_L_G 0x06 +#define BMI160_MAG_Y_H_G 0x07 +#define BMI160_MAG_Z_L_G 0x08 +#define BMI160_MAG_Z_H_G 0x09 +#define BMI160_RHALL_L_G 0x0a +#define BMI160_RHALL_H_G 0x0b +#define BMI160_GYR_X_L_G 0x0c +#define BMI160_GYR_X_H_G 0x0d +#define BMI160_GYR_Y_L_G 0x0e +#define BMI160_GYR_Y_H_G 0x0f +#define BMI160_GYR_Z_L_G 0x10 +#define BMI160_GYR_Z_H_G 0x11 +#define BMI160_ACC_X_L_G 0x12 +#define BMI160_ACC_X_H_G 0x13 +#define BMI160_ACC_Y_L_G 0x14 +#define BMI160_ACC_Y_H_G 0x15 +#define BMI160_ACC_Z_L_G 0x16 +#define BMI160_ACC_Z_H_G 0x17 + +#define BMI160_SENSORTIME_0 0x18 +#define BMI160_SENSORTIME_1 0x19 +#define BMI160_SENSORTIME_2 0x1a + +#define BMI160_STATUS 0x1b +#define BMI160_POR_DETECTED BIT(0) +#define BMI160_GYR_SLF_TST BIT(1) +#define BMI160_MAG_MAN_OP BIT(2) +#define BMI160_FOC_RDY BIT(3) +#define BMI160_NVM_RDY BIT(4) +#define BMI160_DRDY_MAG BIT(5) +#define BMI160_DRDY_GYR BIT(6) +#define BMI160_DRDY_ACC BIT(7) +#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) /* first 2 bytes are the interrupt reasons, next 2 some qualifier */ -#define BMI160_INT_STATUS_0 0x1c -#define BMI160_STEP_INT BIT(0) -#define BMI160_SIGMOT_INT BIT(1) -#define BMI160_ANYM_INT BIT(2) -#define BMI160_PMU_TRIGGER_INT BIT(3) -#define BMI160_D_TAP_INT BIT(4) -#define BMI160_S_TAP_INT BIT(5) -#define BMI160_ORIENT_INT BIT(6) -#define BMI160_FLAT_INT BIT(7) -#define BMI160_ORIENT_XY_MASK 0x30 -#define BMI160_ORIENT_PORTRAIT (0 << 4) -#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) -#define BMI160_ORIENT_LANDSCAPE (2 << 4) -#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) - - -#define BMI160_INT_STATUS_1 0x1d -#define BMI160_HIGHG_INT (1 << (2 + 8)) -#define BMI160_LOWG_INT (1 << (3 + 8)) -#define BMI160_DRDY_INT (1 << (4 + 8)) -#define BMI160_FFULL_INT (1 << (5 + 8)) -#define BMI160_FWM_INT (1 << (6 + 8)) -#define BMI160_NOMO_INT (1 << (7 + 8)) - -#define BMI160_INT_MASK 0xFFFF - -#define BMI160_INT_STATUS_2 0x1e -#define BMI160_INT_STATUS_3 0x1f -#define BMI160_FIRST_X (1 << (0 + 16)) -#define BMI160_FIRST_Y (1 << (1 + 16)) -#define BMI160_FIRST_Z (1 << (2 + 16)) -#define BMI160_SIGN (1 << (3 + 16)) -#define BMI160_ANYM_OFFSET 0 -#define BMI160_TAP_OFFSET 4 -#define BMI160_HIGH_OFFSET 8 +#define BMI160_INT_STATUS_0 0x1c +#define BMI160_STEP_INT BIT(0) +#define BMI160_SIGMOT_INT BIT(1) +#define BMI160_ANYM_INT BIT(2) +#define BMI160_PMU_TRIGGER_INT BIT(3) +#define BMI160_D_TAP_INT BIT(4) +#define BMI160_S_TAP_INT BIT(5) +#define BMI160_ORIENT_INT BIT(6) +#define BMI160_FLAT_INT BIT(7) +#define BMI160_ORIENT_XY_MASK 0x30 +#define BMI160_ORIENT_PORTRAIT (0 << 4) +#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) +#define BMI160_ORIENT_LANDSCAPE (2 << 4) +#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) + +#define BMI160_INT_STATUS_1 0x1d +#define BMI160_HIGHG_INT (1 << (2 + 8)) +#define BMI160_LOWG_INT (1 << (3 + 8)) +#define BMI160_DRDY_INT (1 << (4 + 8)) +#define BMI160_FFULL_INT (1 << (5 + 8)) +#define BMI160_FWM_INT (1 << (6 + 8)) +#define BMI160_NOMO_INT (1 << (7 + 8)) + +#define BMI160_INT_MASK 0xFFFF + +#define BMI160_INT_STATUS_2 0x1e +#define BMI160_INT_STATUS_3 0x1f +#define BMI160_FIRST_X (1 << (0 + 16)) +#define BMI160_FIRST_Y (1 << (1 + 16)) +#define BMI160_FIRST_Z (1 << (2 + 16)) +#define BMI160_SIGN (1 << (3 + 16)) +#define BMI160_ANYM_OFFSET 0 +#define BMI160_TAP_OFFSET 4 +#define BMI160_HIGH_OFFSET 8 #define BMI160_INT_INFO(_type, _data) \ -(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET)) - -#define BMI160_ORIENT_Z (1 << (6 + 24)) -#define BMI160_FLAT (1 << (7 + 24)) - -#define BMI160_TEMPERATURE_0 0x20 -#define BMI160_TEMPERATURE_1 0x21 - - -#define BMI160_FIFO_LENGTH_0 0x22 -#define BMI160_FIFO_LENGTH_1 0x23 -#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) -#define BMI160_FIFO_DATA 0x24 - -#define BMI160_ACC_CONF 0x40 -#define BMI160_ACC_BW_OFFSET 4 -#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET) - -#define BMI160_ACC_RANGE 0x41 -#define BMI160_GSEL_2G 0x03 -#define BMI160_GSEL_4G 0x05 -#define BMI160_GSEL_8G 0x08 -#define BMI160_GSEL_16G 0x0c - -#define BMI160_GYR_CONF 0x42 -#define BMI160_GYR_BW_OFFSET 4 -#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET) - -#define BMI160_GYR_RANGE 0x43 -#define BMI160_DPS_SEL_2000 0x00 -#define BMI160_DPS_SEL_1000 0x01 -#define BMI160_DPS_SEL_500 0x02 -#define BMI160_DPS_SEL_250 0x03 -#define BMI160_DPS_SEL_125 0x04 - -#define BMI160_MAG_CONF 0x44 - -#define BMI160_FIFO_DOWNS 0x45 -#define BMI160_FIFO_CONFIG_0 0x46 -#define BMI160_FIFO_CONFIG_1 0x47 -#define BMI160_FIFO_TAG_TIME_EN BIT(1) -#define BMI160_FIFO_TAG_INT2_EN BIT(2) -#define BMI160_FIFO_TAG_INT1_EN BIT(3) -#define BMI160_FIFO_HEADER_EN BIT(4) -#define BMI160_FIFO_MAG_EN BIT(5) -#define BMI160_FIFO_ACC_EN BIT(6) -#define BMI160_FIFO_GYR_EN BIT(7) -#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) -#define BMI160_FIFO_SENSOR_EN(_sensor) \ - ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \ - ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \ - BMI160_FIFO_MAG_EN)) - -#define BMI160_MAG_IF_0 0x4b + (CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET)) + +#define BMI160_ORIENT_Z (1 << (6 + 24)) +#define BMI160_FLAT (1 << (7 + 24)) + +#define BMI160_TEMPERATURE_0 0x20 +#define BMI160_TEMPERATURE_1 0x21 + +#define BMI160_FIFO_LENGTH_0 0x22 +#define BMI160_FIFO_LENGTH_1 0x23 +#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) +#define BMI160_FIFO_DATA 0x24 + +#define BMI160_ACC_CONF 0x40 +#define BMI160_ACC_BW_OFFSET 4 +#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET) + +#define BMI160_ACC_RANGE 0x41 +#define BMI160_GSEL_2G 0x03 +#define BMI160_GSEL_4G 0x05 +#define BMI160_GSEL_8G 0x08 +#define BMI160_GSEL_16G 0x0c + +#define BMI160_GYR_CONF 0x42 +#define BMI160_GYR_BW_OFFSET 4 +#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET) + +#define BMI160_GYR_RANGE 0x43 +#define BMI160_DPS_SEL_2000 0x00 +#define BMI160_DPS_SEL_1000 0x01 +#define BMI160_DPS_SEL_500 0x02 +#define BMI160_DPS_SEL_250 0x03 +#define BMI160_DPS_SEL_125 0x04 + +#define BMI160_MAG_CONF 0x44 + +#define BMI160_FIFO_DOWNS 0x45 +#define BMI160_FIFO_CONFIG_0 0x46 +#define BMI160_FIFO_CONFIG_1 0x47 +#define BMI160_FIFO_TAG_TIME_EN BIT(1) +#define BMI160_FIFO_TAG_INT2_EN BIT(2) +#define BMI160_FIFO_TAG_INT1_EN BIT(3) +#define BMI160_FIFO_HEADER_EN BIT(4) +#define BMI160_FIFO_MAG_EN BIT(5) +#define BMI160_FIFO_ACC_EN BIT(6) +#define BMI160_FIFO_GYR_EN BIT(7) +#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) +#define BMI160_FIFO_SENSOR_EN(_sensor) \ + ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? \ + BMI160_FIFO_ACC_EN : \ + ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \ + BMI160_FIFO_MAG_EN)) + +#define BMI160_MAG_IF_0 0x4b #define BMI160_MAG_I2C_ADDRESS BMI160_MAG_IF_0 -#define BMI160_MAG_IF_1 0x4c +#define BMI160_MAG_IF_1 0x4c #define BMI160_MAG_I2C_CONTROL BMI160_MAG_IF_1 #define BMI160_MAG_READ_BURST_MASK 3 -#define BMI160_MAG_READ_BURST_1 0 -#define BMI160_MAG_READ_BURST_2 1 -#define BMI160_MAG_READ_BURST_6 2 -#define BMI160_MAG_READ_BURST_8 3 -#define BMI160_MAG_OFFSET_OFF 3 -#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) -#define BMI160_MAG_MANUAL_EN BIT(7) - -#define BMI160_MAG_IF_2 0x4d -#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 -#define BMI160_MAG_IF_3 0x4e -#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3 -#define BMI160_MAG_IF_4 0x4f -#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4 -#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G - -#define BMI160_INT_EN_0 0x50 -#define BMI160_INT_ANYMO_X_EN BIT(0) -#define BMI160_INT_ANYMO_Y_EN BIT(1) -#define BMI160_INT_ANYMO_Z_EN BIT(2) -#define BMI160_INT_D_TAP_EN BIT(4) -#define BMI160_INT_S_TAP_EN BIT(5) -#define BMI160_INT_ORIENT_EN BIT(6) -#define BMI160_INT_FLAT_EN BIT(7) -#define BMI160_INT_EN_1 0x51 -#define BMI160_INT_HIGHG_X_EN BIT(0) -#define BMI160_INT_HIGHG_Y_EN BIT(1) -#define BMI160_INT_HIGHG_Z_EN BIT(2) -#define BMI160_INT_LOW_EN BIT(3) -#define BMI160_INT_DRDY_EN BIT(4) -#define BMI160_INT_FFUL_EN BIT(5) -#define BMI160_INT_FWM_EN BIT(6) -#define BMI160_INT_EN_2 0x52 -#define BMI160_INT_NOMOX_EN BIT(0) -#define BMI160_INT_NOMOY_EN BIT(1) -#define BMI160_INT_NOMOZ_EN BIT(2) -#define BMI160_INT_STEP_DET_EN BIT(3) - -#define BMI160_INT_OUT_CTRL 0x53 -#define BMI160_INT_EDGE_CTRL BIT(0) -#define BMI160_INT_LVL_CTRL BIT(1) -#define BMI160_INT_OD BIT(2) -#define BMI160_INT_OUTPUT_EN BIT(3) -#define BMI160_INT1_CTRL_OFFSET 0 -#define BMI160_INT2_CTRL_OFFSET 4 +#define BMI160_MAG_READ_BURST_1 0 +#define BMI160_MAG_READ_BURST_2 1 +#define BMI160_MAG_READ_BURST_6 2 +#define BMI160_MAG_READ_BURST_8 3 +#define BMI160_MAG_OFFSET_OFF 3 +#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) +#define BMI160_MAG_MANUAL_EN BIT(7) + +#define BMI160_MAG_IF_2 0x4d +#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 +#define BMI160_MAG_IF_3 0x4e +#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3 +#define BMI160_MAG_IF_4 0x4f +#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4 +#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G + +#define BMI160_INT_EN_0 0x50 +#define BMI160_INT_ANYMO_X_EN BIT(0) +#define BMI160_INT_ANYMO_Y_EN BIT(1) +#define BMI160_INT_ANYMO_Z_EN BIT(2) +#define BMI160_INT_D_TAP_EN BIT(4) +#define BMI160_INT_S_TAP_EN BIT(5) +#define BMI160_INT_ORIENT_EN BIT(6) +#define BMI160_INT_FLAT_EN BIT(7) +#define BMI160_INT_EN_1 0x51 +#define BMI160_INT_HIGHG_X_EN BIT(0) +#define BMI160_INT_HIGHG_Y_EN BIT(1) +#define BMI160_INT_HIGHG_Z_EN BIT(2) +#define BMI160_INT_LOW_EN BIT(3) +#define BMI160_INT_DRDY_EN BIT(4) +#define BMI160_INT_FFUL_EN BIT(5) +#define BMI160_INT_FWM_EN BIT(6) +#define BMI160_INT_EN_2 0x52 +#define BMI160_INT_NOMOX_EN BIT(0) +#define BMI160_INT_NOMOY_EN BIT(1) +#define BMI160_INT_NOMOZ_EN BIT(2) +#define BMI160_INT_STEP_DET_EN BIT(3) + +#define BMI160_INT_OUT_CTRL 0x53 +#define BMI160_INT_EDGE_CTRL BIT(0) +#define BMI160_INT_LVL_CTRL BIT(1) +#define BMI160_INT_OD BIT(2) +#define BMI160_INT_OUTPUT_EN BIT(3) +#define BMI160_INT1_CTRL_OFFSET 0 +#define BMI160_INT2_CTRL_OFFSET 4 #define BMI160_INT_CTRL(_i, _bit) \ -(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) - -#define BMI160_INT_LATCH 0x54 -#define BMI160_INT1_INPUT_EN BIT(4) -#define BMI160_INT2_INPUT_EN BIT(5) -#define BMI160_LATCH_MASK 0xf -#define BMI160_LATCH_NONE 0 -#define BMI160_LATCH_5MS 5 -#define BMI160_LATCH_FOREVER 0xf - -#define BMI160_INT_MAP_0 0x55 -#define BMI160_INT_LOWG_STEP BIT(0) -#define BMI160_INT_HIGHG BIT(1) -#define BMI160_INT_ANYMOTION BIT(2) -#define BMI160_INT_NOMOTION BIT(3) -#define BMI160_INT_D_TAP BIT(4) -#define BMI160_INT_S_TAP BIT(5) -#define BMI160_INT_ORIENT BIT(6) -#define BMI160_INT_FLAT BIT(7) - -#define BMI160_INT_MAP_1 0x56 -#define BMI160_INT_PMU_TRIG BIT(0) -#define BMI160_INT_FFULL BIT(1) -#define BMI160_INT_FWM BIT(2) -#define BMI160_INT_DRDY BIT(3) -#define BMI160_INT1_MAP_OFFSET 4 -#define BMI160_INT2_MAP_OFFSET 0 + (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) + +#define BMI160_INT_LATCH 0x54 +#define BMI160_INT1_INPUT_EN BIT(4) +#define BMI160_INT2_INPUT_EN BIT(5) +#define BMI160_LATCH_MASK 0xf +#define BMI160_LATCH_NONE 0 +#define BMI160_LATCH_5MS 5 +#define BMI160_LATCH_FOREVER 0xf + +#define BMI160_INT_MAP_0 0x55 +#define BMI160_INT_LOWG_STEP BIT(0) +#define BMI160_INT_HIGHG BIT(1) +#define BMI160_INT_ANYMOTION BIT(2) +#define BMI160_INT_NOMOTION BIT(3) +#define BMI160_INT_D_TAP BIT(4) +#define BMI160_INT_S_TAP BIT(5) +#define BMI160_INT_ORIENT BIT(6) +#define BMI160_INT_FLAT BIT(7) + +#define BMI160_INT_MAP_1 0x56 +#define BMI160_INT_PMU_TRIG BIT(0) +#define BMI160_INT_FFULL BIT(1) +#define BMI160_INT_FWM BIT(2) +#define BMI160_INT_DRDY BIT(3) +#define BMI160_INT1_MAP_OFFSET 4 +#define BMI160_INT2_MAP_OFFSET 0 #define BMI160_INT_MAP(_i, _bit) \ -(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET)) -#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1 + (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET)) +#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1 -#define BMI160_INT_MAP_2 0x57 +#define BMI160_INT_MAP_2 0x57 -#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0 -#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2 -#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i) +#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0 +#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2 +#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i) -#define BMI160_INT_DATA_0 0x58 -#define BMI160_INT_DATA_1 0x59 +#define BMI160_INT_DATA_0 0x58 +#define BMI160_INT_DATA_1 0x59 -#define BMI160_INT_LOW_HIGH_0 0x5a -#define BMI160_INT_LOW_HIGH_1 0x5b -#define BMI160_INT_LOW_HIGH_2 0x5c -#define BMI160_INT_LOW_HIGH_3 0x5d -#define BMI160_INT_LOW_HIGH_4 0x5e +#define BMI160_INT_LOW_HIGH_0 0x5a +#define BMI160_INT_LOW_HIGH_1 0x5b +#define BMI160_INT_LOW_HIGH_2 0x5c +#define BMI160_INT_LOW_HIGH_3 0x5d +#define BMI160_INT_LOW_HIGH_4 0x5e -#define BMI160_INT_MOTION_0 0x5f -#define BMI160_INT_MOTION_1 0x60 +#define BMI160_INT_MOTION_0 0x5f +#define BMI160_INT_MOTION_1 0x60 /* * The formula is defined in 2.11.25 (any motion interrupt [1]). * @@ -268,11 +266,11 @@ * x = a * 1000 / range * 1953 */ #define BMI160_MOTION_TH(_s, _mg) \ - (MIN(((_mg) * 1000) / ((_s)->current_range * 1953), 0xff)) -#define BMI160_INT_MOTION_2 0x61 -#define BMI160_INT_MOTION_3 0x62 -#define BMI160_MOTION_NO_MOT_SEL BIT(0) -#define BMI160_MOTION_SIG_MOT_SEL BIT(1) + (MIN(((_mg)*1000) / ((_s)->current_range * 1953), 0xff)) +#define BMI160_INT_MOTION_2 0x61 +#define BMI160_INT_MOTION_3 0x62 +#define BMI160_MOTION_NO_MOT_SEL BIT(0) +#define BMI160_MOTION_SIG_MOT_SEL BIT(1) #define BMI160_MOTION_SKIP_OFF 2 #define BMI160_MOTION_SKIP_MASK 0x3 #define BMI160_MOTION_SKIP_TIME(_ms) \ @@ -282,74 +280,75 @@ #define BMI160_MOTION_PROOF_TIME(_ms) \ (MIN(__fls((_ms) / 250), BMI160_MOTION_PROOF_MASK)) -#define BMI160_INT_TAP_0 0x63 -#define BMI160_TAP_DUR(_s, _ms) \ +#define BMI160_INT_TAP_0 0x63 +#define BMI160_TAP_DUR(_s, _ms) \ ((_ms) <= 250 ? MAX((_ms), 50) / 50 - 1 : \ - (_ms) <= 500 ? 4 + ((_ms) - 250) / 125 : \ - (_ms) < 700 ? 6 : 7) + (_ms) <= 500 ? 4 + ((_ms)-250) / 125 : \ + (_ms) < 700 ? 6 : \ + 7) -#define BMI160_INT_TAP_1 0x64 +#define BMI160_INT_TAP_1 0x64 #define BMI160_TAP_TH(_s, _mg) \ - (MIN(((_mg) * 1000) / ((_s)->current_range * 31250), 0x1f)) + (MIN(((_mg)*1000) / ((_s)->current_range * 31250), 0x1f)) -#define BMI160_INT_ORIENT_0 0x65 +#define BMI160_INT_ORIENT_0 0x65 /* No hysterisis, theta block, int on slope > 0.2 or axis > 1.5, symmetrical */ -#define BMI160_INT_ORIENT_0_INIT_VAL 0x48 +#define BMI160_INT_ORIENT_0_INIT_VAL 0x48 -#define BMI160_INT_ORIENT_1 0x66 +#define BMI160_INT_ORIENT_1 0x66 /* no axes remap, no int on up/down, no blocking angle */ -#define BMI160_INT_ORIENT_1_INIT_VAL 0x00 - -#define BMI160_INT_FLAT_0 0x67 -#define BMI160_INT_FLAT_1 0x68 - -#define BMI160_FOC_CONF 0x69 -#define BMI160_FOC_GYRO_EN BIT(6) -#define BMI160_FOC_ACC_PLUS_1G 1 -#define BMI160_FOC_ACC_MINUS_1G 2 -#define BMI160_FOC_ACC_0G 3 -#define BMI160_FOC_ACC_Z_OFFSET 0 -#define BMI160_FOC_ACC_Y_OFFSET 2 -#define BMI160_FOC_ACC_X_OFFSET 4 - -#define BMI160_CONF 0x6a -#define BMI160_IF_CONF 0x6b -#define BMI160_IF_MODE_OFF 4 -#define BMI160_IF_MODE_MASK 3 +#define BMI160_INT_ORIENT_1_INIT_VAL 0x00 + +#define BMI160_INT_FLAT_0 0x67 +#define BMI160_INT_FLAT_1 0x68 + +#define BMI160_FOC_CONF 0x69 +#define BMI160_FOC_GYRO_EN BIT(6) +#define BMI160_FOC_ACC_PLUS_1G 1 +#define BMI160_FOC_ACC_MINUS_1G 2 +#define BMI160_FOC_ACC_0G 3 +#define BMI160_FOC_ACC_Z_OFFSET 0 +#define BMI160_FOC_ACC_Y_OFFSET 2 +#define BMI160_FOC_ACC_X_OFFSET 4 + +#define BMI160_CONF 0x6a +#define BMI160_IF_CONF 0x6b +#define BMI160_IF_MODE_OFF 4 +#define BMI160_IF_MODE_MASK 3 #define BMI160_IF_MODE_AUTO_OFF 0 -#define BMI160_IF_MODE_I2C_IOS 1 +#define BMI160_IF_MODE_I2C_IOS 1 #define BMI160_IF_MODE_AUTO_I2C 2 -#define BMI160_PMU_TRIGGER 0x6c -#define BMI160_SELF_TEST 0x6d +#define BMI160_PMU_TRIGGER 0x6c +#define BMI160_SELF_TEST 0x6d -#define BMI160_NV_CONF 0x70 +#define BMI160_NV_CONF 0x70 -#define BMI160_OFFSET_ACC70 0x71 -#define BMI160_OFFSET_GYR70 0x74 -#define BMI160_OFFSET_EN_GYR98 0x77 -#define BMI160_OFFSET_ACC_EN BIT(6) -#define BMI160_OFFSET_GYRO_EN BIT(7) +#define BMI160_OFFSET_ACC70 0x71 +#define BMI160_OFFSET_GYR70 0x74 +#define BMI160_OFFSET_EN_GYR98 0x77 +#define BMI160_OFFSET_ACC_EN BIT(6) +#define BMI160_OFFSET_GYRO_EN BIT(7) -#define BMI160_STEP_CNT_0 0x78 -#define BMI160_STEP_CNT_1 0x79 -#define BMI160_STEP_CONF_0 0x7a -#define BMI160_STEP_CONF_1 0x7b +#define BMI160_STEP_CNT_0 0x78 +#define BMI160_STEP_CNT_1 0x79 +#define BMI160_STEP_CONF_0 0x7a +#define BMI160_STEP_CONF_1 0x7b -#define BMI160_CMD_REG 0x7e -#define BMI160_CMD_SOFT_RESET 0xb6 -#define BMI160_CMD_NOOP 0x00 -#define BMI160_CMD_START_FOC 0x03 +#define BMI160_CMD_REG 0x7e +#define BMI160_CMD_SOFT_RESET 0xb6 +#define BMI160_CMD_NOOP 0x00 +#define BMI160_CMD_START_FOC 0x03 #define BMI160_CMD_ACC_MODE_OFFSET 0x10 -#define BMI160_CMD_ACC_MODE_SUSP 0x10 +#define BMI160_CMD_ACC_MODE_SUSP 0x10 #define BMI160_CMD_ACC_MODE_NORMAL 0x11 #define BMI160_CMD_ACC_MODE_LOWPOWER 0x12 -#define BMI160_CMD_GYR_MODE_SUSP 0x14 +#define BMI160_CMD_GYR_MODE_SUSP 0x14 #define BMI160_CMD_GYR_MODE_NORMAL 0x15 #define BMI160_CMD_GYR_MODE_FAST_STARTUP 0x17 -#define BMI160_CMD_MAG_MODE_SUSP 0x18 +#define BMI160_CMD_MAG_MODE_SUSP 0x18 #define BMI160_CMD_MAG_MODE_NORMAL 0x19 #define BMI160_CMD_MAG_MODE_LOWPOWER 0x1a #define BMI160_CMD_MODE_SUSPEND(_sensor_type) \ @@ -357,31 +356,31 @@ #define BMI160_CMD_MODE_NORMAL(_sensor_type) \ (BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_NORMAL) -#define BMI160_CMD_FIFO_FLUSH 0xb0 -#define BMI160_CMD_INT_RESET 0xb1 -#define BMI160_CMD_SOFT_RESET 0xb6 -#define BMI160_CMD_EXT_MODE_EN_B0 0x37 -#define BMI160_CMD_EXT_MODE_EN_B1 0x9a -#define BMI160_CMD_EXT_MODE_EN_B2 0xc0 +#define BMI160_CMD_FIFO_FLUSH 0xb0 +#define BMI160_CMD_INT_RESET 0xb1 +#define BMI160_CMD_SOFT_RESET 0xb6 +#define BMI160_CMD_EXT_MODE_EN_B0 0x37 +#define BMI160_CMD_EXT_MODE_EN_B1 0x9a +#define BMI160_CMD_EXT_MODE_EN_B2 0xc0 -#define BMI160_CMD_EXT_MODE_ADDR 0x7f -#define BMI160_CMD_PAGING_EN BIT(7) -#define BMI160_CMD_TARGET_PAGE BIT(4) +#define BMI160_CMD_EXT_MODE_ADDR 0x7f +#define BMI160_CMD_PAGING_EN BIT(7) +#define BMI160_CMD_TARGET_PAGE BIT(4) #define BMI160_COM_C_TRIM_ADDR 0x85 -#define BMI160_COM_C_TRIM (3 << 4) +#define BMI160_COM_C_TRIM (3 << 4) -#define BMI160_CMD_TGT_PAGE 0 -#define BMI160_CMD_TGT_PAGE_COM 1 -#define BMI160_CMD_TGT_PAGE_ACC 2 -#define BMI160_CMD_TGT_PAGE_GYR 3 +#define BMI160_CMD_TGT_PAGE 0 +#define BMI160_CMD_TGT_PAGE_COM 1 +#define BMI160_CMD_TGT_PAGE_ACC 2 +#define BMI160_CMD_TGT_PAGE_GYR 3 -#define BMI160_FF_FRAME_LEN_TS 4 -#define BMI160_FF_DATA_LEN_ACC 6 -#define BMI160_FF_DATA_LEN_GYR 6 -#define BMI160_FF_DATA_LEN_MAG 8 +#define BMI160_FF_FRAME_LEN_TS 4 +#define BMI160_FF_DATA_LEN_ACC 6 +#define BMI160_FF_DATA_LEN_GYR 6 +#define BMI160_FF_DATA_LEN_MAG 8 /* Root mean square noise of 100 Hz accelerometer, units: ug */ -#define BMI160_ACCEL_RMS_NOISE_100HZ 1300 +#define BMI160_ACCEL_RMS_NOISE_100HZ 1300 /* Functions to access the secondary device through the accel/gyro. */ int bmi160_sec_raw_read8(const int port, const uint16_t addr_flags, @@ -404,6 +403,6 @@ int bmi160_sec_raw_write8(const int port, const uint16_t addr_flags, #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_BMI160_H */ diff --git a/include/driver/accelgyro_bmi160_public.h b/include/driver/accelgyro_bmi160_public.h index 6a6890eb84..551e351fea 100644 --- a/include/driver/accelgyro_bmi160_public.h +++ b/include/driver/accelgyro_bmi160_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,7 +18,7 @@ */ /* I2C addresses */ -#define BMI160_ADDR0_FLAGS 0x68 +#define BMI160_ADDR0_FLAGS 0x68 extern const struct accelgyro_drv bmi160_drv; diff --git a/include/driver/accelgyro_bmi260.h b/include/driver/accelgyro_bmi260.h index fb5db82afb..5d55a85acc 100644 --- a/include/driver/accelgyro_bmi260.h +++ b/include/driver/accelgyro_bmi260.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,320 +13,320 @@ #include "mag_bmm150.h" #include "driver/accelgyro_bmi260_public.h" -#define BMI260_CHIP_ID 0x00 +#define BMI260_CHIP_ID 0x00 /* BMI260 chip identifier */ -#define BMI260_CHIP_ID_MAJOR 0x27 +#define BMI260_CHIP_ID_MAJOR 0x27 /* BMI220 chip identifier */ -#define BMI220_CHIP_ID_MAJOR 0x26 - -#define BMI260_ERR_REG 0x02 - -#define BMI260_STATUS 0x03 -#define BMI260_AUX_BUSY BIT(2) -#define BMI260_CMD_RDY BIT(4) -#define BMI260_DRDY_AUX BIT(5) -#define BMI260_DRDY_GYR BIT(6) -#define BMI260_DRDY_ACC BIT(7) -#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor)) - -#define BMI260_AUX_X_L_G 0x04 -#define BMI260_AUX_X_H_G 0x05 -#define BMI260_AUX_Y_L_G 0x06 -#define BMI260_AUX_Y_H_G 0x07 -#define BMI260_AUX_Z_L_G 0x08 -#define BMI260_AUX_Z_H_G 0x09 -#define BMI260_AUX_R_L_G 0x0a -#define BMI260_AUX_R_H_G 0x0b -#define BMI260_ACC_X_L_G 0x0c -#define BMI260_ACC_X_H_G 0x0d -#define BMI260_ACC_Y_L_G 0x0e -#define BMI260_ACC_Y_H_G 0x0f -#define BMI260_ACC_Z_L_G 0x10 -#define BMI260_ACC_Z_H_G 0x11 -#define BMI260_GYR_X_L_G 0x12 -#define BMI260_GYR_X_H_G 0x13 -#define BMI260_GYR_Y_L_G 0x14 -#define BMI260_GYR_Y_H_G 0x15 -#define BMI260_GYR_Z_L_G 0x16 -#define BMI260_GYR_Z_H_G 0x17 - -#define BMI260_SENSORTIME_0 0x18 -#define BMI260_SENSORTIME_1 0x19 -#define BMI260_SENSORTIME_2 0x1a - -#define BMI260_EVENT 0x1b +#define BMI220_CHIP_ID_MAJOR 0x26 + +#define BMI260_ERR_REG 0x02 + +#define BMI260_STATUS 0x03 +#define BMI260_AUX_BUSY BIT(2) +#define BMI260_CMD_RDY BIT(4) +#define BMI260_DRDY_AUX BIT(5) +#define BMI260_DRDY_GYR BIT(6) +#define BMI260_DRDY_ACC BIT(7) +#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor)) + +#define BMI260_AUX_X_L_G 0x04 +#define BMI260_AUX_X_H_G 0x05 +#define BMI260_AUX_Y_L_G 0x06 +#define BMI260_AUX_Y_H_G 0x07 +#define BMI260_AUX_Z_L_G 0x08 +#define BMI260_AUX_Z_H_G 0x09 +#define BMI260_AUX_R_L_G 0x0a +#define BMI260_AUX_R_H_G 0x0b +#define BMI260_ACC_X_L_G 0x0c +#define BMI260_ACC_X_H_G 0x0d +#define BMI260_ACC_Y_L_G 0x0e +#define BMI260_ACC_Y_H_G 0x0f +#define BMI260_ACC_Z_L_G 0x10 +#define BMI260_ACC_Z_H_G 0x11 +#define BMI260_GYR_X_L_G 0x12 +#define BMI260_GYR_X_H_G 0x13 +#define BMI260_GYR_Y_L_G 0x14 +#define BMI260_GYR_Y_H_G 0x15 +#define BMI260_GYR_Z_L_G 0x16 +#define BMI260_GYR_Z_H_G 0x17 + +#define BMI260_SENSORTIME_0 0x18 +#define BMI260_SENSORTIME_1 0x19 +#define BMI260_SENSORTIME_2 0x1a + +#define BMI260_EVENT 0x1b /* 2 bytes interrupt reasons*/ -#define BMI260_INT_STATUS_0 0x1c -#define BMI260_SIG_MOTION_OUT BIT(0) -#define BMI260_STEP_COUNTER_OUT BIT(1) -#define BMI260_HIGH_LOW_G_OUT BIT(2) -#define BMI260_TAP_OUT BIT(3) -#define BMI260_FLAT_OUT BIT(4) -#define BMI260_NO_MOTION_OUT BIT(5) -#define BMI260_ANY_MOTION_OUT BIT(6) -#define BMI260_ORIENTATION_OUT BIT(7) - -#define BMI260_INT_STATUS_1 0x1d -#define BMI260_FFULL_INT BIT(0 + 8) -#define BMI260_FWM_INT BIT(1 + 8) -#define BMI260_ERR_INT BIT(2 + 8) -#define BMI260_AUX_DRDY_INT BIT(5 + 8) -#define BMI260_GYR_DRDY_INT BIT(6 + 8) -#define BMI260_ACC_DRDY_INT BIT(7 + 8) - -#define BMI260_INT_MASK 0xFFFF - -#define BMI260_SC_OUT_0 0x1e -#define BMI260_SC_OUT_1 0x1f - -#define BMI260_ORIENT_ACT 0x20 - -#define BMI260_INTERNAL_STATUS 0X21 -#define BMI260_MESSAGE_MASK 0xf -#define BMI260_NOT_INIT 0x00 -#define BMI260_INIT_OK 0x01 -#define BMI260_INIT_ERR 0x02 -#define BMI260_DRV_ERR 0x03 -#define BMI260_SNS_STOP 0x04 -#define BMI260_NVM_ERROR 0x05 -#define BMI260_START_UP_ERROR 0x06 -#define BMI260_COMPAT_ERROR 0x07 - -#define BMI260_TEMPERATURE_0 0x22 -#define BMI260_TEMPERATURE_1 0x23 - -#define BMI260_FIFO_LENGTH_0 0x24 -#define BMI260_FIFO_LENGTH_1 0x25 -#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1) -#define BMI260_FIFO_DATA 0x26 - -#define BMI260_FEAT_PAGE 0x2f +#define BMI260_INT_STATUS_0 0x1c +#define BMI260_SIG_MOTION_OUT BIT(0) +#define BMI260_STEP_COUNTER_OUT BIT(1) +#define BMI260_HIGH_LOW_G_OUT BIT(2) +#define BMI260_TAP_OUT BIT(3) +#define BMI260_FLAT_OUT BIT(4) +#define BMI260_NO_MOTION_OUT BIT(5) +#define BMI260_ANY_MOTION_OUT BIT(6) +#define BMI260_ORIENTATION_OUT BIT(7) + +#define BMI260_INT_STATUS_1 0x1d +#define BMI260_FFULL_INT BIT(0 + 8) +#define BMI260_FWM_INT BIT(1 + 8) +#define BMI260_ERR_INT BIT(2 + 8) +#define BMI260_AUX_DRDY_INT BIT(5 + 8) +#define BMI260_GYR_DRDY_INT BIT(6 + 8) +#define BMI260_ACC_DRDY_INT BIT(7 + 8) + +#define BMI260_INT_MASK 0xFFFF + +#define BMI260_SC_OUT_0 0x1e +#define BMI260_SC_OUT_1 0x1f + +#define BMI260_ORIENT_ACT 0x20 + +#define BMI260_INTERNAL_STATUS 0X21 +#define BMI260_MESSAGE_MASK 0xf +#define BMI260_NOT_INIT 0x00 +#define BMI260_INIT_OK 0x01 +#define BMI260_INIT_ERR 0x02 +#define BMI260_DRV_ERR 0x03 +#define BMI260_SNS_STOP 0x04 +#define BMI260_NVM_ERROR 0x05 +#define BMI260_START_UP_ERROR 0x06 +#define BMI260_COMPAT_ERROR 0x07 + +#define BMI260_TEMPERATURE_0 0x22 +#define BMI260_TEMPERATURE_1 0x23 + +#define BMI260_FIFO_LENGTH_0 0x24 +#define BMI260_FIFO_LENGTH_1 0x25 +#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1) +#define BMI260_FIFO_DATA 0x26 + +#define BMI260_FEAT_PAGE 0x2f /* * The register of feature page should be read/write as 16-bit register * Otherwise, there can be invalid data */ /* Features page 0 */ -#define BMI260_ORIENT_OUT 0x36 -#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3 -#define BMI260_ORIENT_PORTRAIT 0x0 -#define BMI260_ORIENT_LANDSCAPE 0x1 -#define BMI260_ORIENT_PORTRAIT_INVERT 0x2 -#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3 +#define BMI260_ORIENT_OUT 0x36 +#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3 +#define BMI260_ORIENT_PORTRAIT 0x0 +#define BMI260_ORIENT_LANDSCAPE 0x1 +#define BMI260_ORIENT_PORTRAIT_INVERT 0x2 +#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3 /* Features page 1 */ -#define BMI260_GEN_SET_1 0x34 -#define BMI260_GYR_SELF_OFF BIT(9) +#define BMI260_GEN_SET_1 0x34 +#define BMI260_GYR_SELF_OFF BIT(9) -#define BMI260_TAP_1 0x3e -#define BMI260_TAP_1_EN BIT(0) -#define BMI260_TAP_1_SENSITIVITY_OFFSET 1 -#define BMI260_TAP_1_SENSITIVITY_MASK \ - (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET) +#define BMI260_TAP_1 0x3e +#define BMI260_TAP_1_EN BIT(0) +#define BMI260_TAP_1_SENSITIVITY_OFFSET 1 +#define BMI260_TAP_1_SENSITIVITY_MASK (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET) /* Features page 2 */ -#define BMI260_ORIENT_1 0x30 -#define BMI260_ORIENT_1_EN BIT(0) -#define BMI260_ORIENT_1_UD_EN BIT(1) +#define BMI260_ORIENT_1 0x30 +#define BMI260_ORIENT_1_EN BIT(0) +#define BMI260_ORIENT_1_UD_EN BIT(1) #define BMI260_ORIENT_1_MODE_OFFSET 2 -#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET) -#define BMI260_ORIENT_1_BLOCK_OFFSET 4 -#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET) -#define BMI260_ORIENT_1_THETA_OFFSET 6 -#define BMI260_ORIENT_1_THETA_MASK \ +#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET) +#define BMI260_ORIENT_1_BLOCK_OFFSET 4 +#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET) +#define BMI260_ORIENT_1_THETA_OFFSET 6 +#define BMI260_ORIENT_1_THETA_MASK \ ((BIT(6) - 1) << BMI260_ORIENT_1_THETA_OFFSET) -#define BMI260_ORIENT_2 0x32 +#define BMI260_ORIENT_2 0x32 /* hysteresis(10...0) range is 0~1g, default is 128 (0.0625g) */ -#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1) +#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1) -#define BMI260_ACC_CONF 0x40 -#define BMI260_ACC_BW_OFFSET 4 -#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET) -#define BMI260_FILTER_PERF BIT(7) -#define BMI260_ULP 0x0 -#define BMI260_HP 0x1 +#define BMI260_ACC_CONF 0x40 +#define BMI260_ACC_BW_OFFSET 4 +#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET) +#define BMI260_FILTER_PERF BIT(7) +#define BMI260_ULP 0x0 +#define BMI260_HP 0x1 -#define BMI260_ACC_RANGE 0x41 -#define BMI260_GSEL_2G 0x00 -#define BMI260_GSEL_4G 0x01 -#define BMI260_GSEL_8G 0x02 -#define BMI260_GSEL_16G 0x03 +#define BMI260_ACC_RANGE 0x41 +#define BMI260_GSEL_2G 0x00 +#define BMI260_GSEL_4G 0x01 +#define BMI260_GSEL_8G 0x02 +#define BMI260_GSEL_16G 0x03 /* The max positvie value of accel data is 0x7FFF, equal to range(g) */ /* So, in order to get +1g, divide the 0x7FFF by range */ #define BMI260_ACC_DATA_PLUS_1G(range) (0x7FFF / (range)) #define BMI260_ACC_DATA_MINUS_1G(range) (-BMI260_ACC_DATA_PLUS_1G(range)) -#define BMI260_GYR_CONF 0x42 -#define BMI260_GYR_BW_OFFSET 4 -#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET) -#define BMI260_GYR_NOISE_PERF BIT(6) - -#define BMI260_GYR_RANGE 0x43 -#define BMI260_DPS_SEL_2000 0x00 -#define BMI260_DPS_SEL_1000 0x01 -#define BMI260_DPS_SEL_500 0x02 -#define BMI260_DPS_SEL_250 0x03 -#define BMI260_DPS_SEL_125 0x04 - -#define BMI260_AUX_CONF 0x44 - -#define BMI260_FIFO_DOWNS 0x45 - -#define BMI260_FIFO_WTM_0 0x46 -#define BMI260_FIFO_WTM_1 0x47 - -#define BMI260_FIFO_CONFIG_0 0x48 -#define BMI260_FIFO_STOP_ON_FULL BIT(0) -#define BMI260_FIFO_TIME_EN BIT(1) - -#define BMI260_FIFO_CONFIG_1 0x49 -#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0 -#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET) -#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2 -#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET) -#define BMI260_FIFO_TAG_INT_EDGE 0x0 -#define BMI260_FIFO_TAG_INT_LEVEL 0x1 -#define BMI260_FIFO_TAG_ACC_SAT 0x2 -#define BMI260_FIFO_TAG_GYR_SAT 0x3 -#define BMI260_FIFO_HEADER_EN BIT(4) -#define BMI260_FIFO_AUX_EN BIT(5) -#define BMI260_FIFO_ACC_EN BIT(6) -#define BMI260_FIFO_GYR_EN BIT(7) -#define BMI260_FIFO_SENSOR_EN(_sensor) \ - ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI260_FIFO_ACC_EN : \ - ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \ - BMI260_FIFO_AUX_EN)) - -#define BMI260_SATURATION 0x4a - -#define BMI260_AUX_DEV_ID 0x4b -#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID - -#define BMI260_AUX_IF_CONF 0x4c -#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF -#define BMI260_AUX_READ_BURST_MASK 3 -#define BMI260_AUX_MAN_READ_BURST_OFF 2 -#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF) -#define BMI260_AUX_READ_BURST_1 0 -#define BMI260_AUX_READ_BURST_2 1 -#define BMI260_AUX_READ_BURST_6 2 -#define BMI260_AUX_READ_BURST_8 3 -#define BMI260_AUX_FCU_WRITE_EN BIT(6) -#define BMI260_AUX_MANUAL_EN BIT(7) - -#define BMI260_AUX_RD_ADDR 0x4d -#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR -#define BMI260_AUX_WR_ADDR 0x4e -#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR -#define BMI260_AUX_WR_DATA 0x4f -#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA -#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G - -#define BMI260_ERR_REG_MSK 0x52 -#define BMI260_FATAL_ERR BIT(0) -#define BMI260_INTERNAL_ERR_OFF 1 -#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF) -#define BMI260_FIFO_ERR BIT(6) -#define BMI260_AUX_ERR BIT(7) - -#define BMI260_INT1_IO_CTRL 0x53 -#define BMI260_INT1_LVL BIT(1) -#define BMI260_INT1_OD BIT(2) -#define BMI260_INT1_OUTPUT_EN BIT(3) -#define BMI260_INT1_INPUT_EN BIT(4) - -#define BMI260_INT2_IO_CTRL 0x54 -#define BMI260_INT2_LVL BIT(1) -#define BMI260_INT2_OD BIT(2) -#define BMI260_INT2_OUTPUT_EN BIT(3) -#define BMI260_INT2_INPUT_EN BIT(4) - -#define BMI260_INT_LATCH 0x55 -#define BMI260_INT_LATCH_EN BIT(0) - -#define BMI260_INT1_MAP_FEAT 0x56 -#define BMI260_INT2_MAP_FEAT 0x57 -#define BMI260_MAP_SIG_MOTION_OUT BIT(0) +#define BMI260_GYR_CONF 0x42 +#define BMI260_GYR_BW_OFFSET 4 +#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET) +#define BMI260_GYR_NOISE_PERF BIT(6) + +#define BMI260_GYR_RANGE 0x43 +#define BMI260_DPS_SEL_2000 0x00 +#define BMI260_DPS_SEL_1000 0x01 +#define BMI260_DPS_SEL_500 0x02 +#define BMI260_DPS_SEL_250 0x03 +#define BMI260_DPS_SEL_125 0x04 + +#define BMI260_AUX_CONF 0x44 + +#define BMI260_FIFO_DOWNS 0x45 + +#define BMI260_FIFO_WTM_0 0x46 +#define BMI260_FIFO_WTM_1 0x47 + +#define BMI260_FIFO_CONFIG_0 0x48 +#define BMI260_FIFO_STOP_ON_FULL BIT(0) +#define BMI260_FIFO_TIME_EN BIT(1) + +#define BMI260_FIFO_CONFIG_1 0x49 +#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0 +#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET) +#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2 +#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET) +#define BMI260_FIFO_TAG_INT_EDGE 0x0 +#define BMI260_FIFO_TAG_INT_LEVEL 0x1 +#define BMI260_FIFO_TAG_ACC_SAT 0x2 +#define BMI260_FIFO_TAG_GYR_SAT 0x3 +#define BMI260_FIFO_HEADER_EN BIT(4) +#define BMI260_FIFO_AUX_EN BIT(5) +#define BMI260_FIFO_ACC_EN BIT(6) +#define BMI260_FIFO_GYR_EN BIT(7) +#define BMI260_FIFO_SENSOR_EN(_sensor) \ + ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? \ + BMI260_FIFO_ACC_EN : \ + ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \ + BMI260_FIFO_AUX_EN)) + +#define BMI260_SATURATION 0x4a + +#define BMI260_AUX_DEV_ID 0x4b +#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID + +#define BMI260_AUX_IF_CONF 0x4c +#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF +#define BMI260_AUX_READ_BURST_MASK 3 +#define BMI260_AUX_MAN_READ_BURST_OFF 2 +#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF) +#define BMI260_AUX_READ_BURST_1 0 +#define BMI260_AUX_READ_BURST_2 1 +#define BMI260_AUX_READ_BURST_6 2 +#define BMI260_AUX_READ_BURST_8 3 +#define BMI260_AUX_FCU_WRITE_EN BIT(6) +#define BMI260_AUX_MANUAL_EN BIT(7) + +#define BMI260_AUX_RD_ADDR 0x4d +#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR +#define BMI260_AUX_WR_ADDR 0x4e +#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR +#define BMI260_AUX_WR_DATA 0x4f +#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA +#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G + +#define BMI260_ERR_REG_MSK 0x52 +#define BMI260_FATAL_ERR BIT(0) +#define BMI260_INTERNAL_ERR_OFF 1 +#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF) +#define BMI260_FIFO_ERR BIT(6) +#define BMI260_AUX_ERR BIT(7) + +#define BMI260_INT1_IO_CTRL 0x53 +#define BMI260_INT1_LVL BIT(1) +#define BMI260_INT1_OD BIT(2) +#define BMI260_INT1_OUTPUT_EN BIT(3) +#define BMI260_INT1_INPUT_EN BIT(4) + +#define BMI260_INT2_IO_CTRL 0x54 +#define BMI260_INT2_LVL BIT(1) +#define BMI260_INT2_OD BIT(2) +#define BMI260_INT2_OUTPUT_EN BIT(3) +#define BMI260_INT2_INPUT_EN BIT(4) + +#define BMI260_INT_LATCH 0x55 +#define BMI260_INT_LATCH_EN BIT(0) + +#define BMI260_INT1_MAP_FEAT 0x56 +#define BMI260_INT2_MAP_FEAT 0x57 +#define BMI260_MAP_SIG_MOTION_OUT BIT(0) #define BMI260_MAP_STEP_COUNTER_OUT BIT(1) -#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2) -#define BMI260_MAP_TAP_OUT BIT(3) -#define BMI260_MAP_FLAT_OUT BIT(4) -#define BMI260_MAP_NO_MOTION_OUT BIT(5) -#define BMI260_MAP_ANY_MOTION_OUT BIT(6) -#define BMI260_MAP_ORIENTAION_OUT BIT(7) - -#define BMI260_INT_MAP_DATA 0x58 -#define BMI260_MAP_FFULL_INT BIT(0) -#define BMI260_MAP_FWM_INT BIT(1) -#define BMI260_MAP_DRDY_INT BIT(2) -#define BMI260_MAP_ERR_INT BIT(3) -#define BMI260_INT_MAP_DATA_INT1_OFFSET 0 -#define BMI260_INT_MAP_DATA_INT2_OFFSET 4 +#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2) +#define BMI260_MAP_TAP_OUT BIT(3) +#define BMI260_MAP_FLAT_OUT BIT(4) +#define BMI260_MAP_NO_MOTION_OUT BIT(5) +#define BMI260_MAP_ANY_MOTION_OUT BIT(6) +#define BMI260_MAP_ORIENTAION_OUT BIT(7) + +#define BMI260_INT_MAP_DATA 0x58 +#define BMI260_MAP_FFULL_INT BIT(0) +#define BMI260_MAP_FWM_INT BIT(1) +#define BMI260_MAP_DRDY_INT BIT(2) +#define BMI260_MAP_ERR_INT BIT(3) +#define BMI260_INT_MAP_DATA_INT1_OFFSET 0 +#define BMI260_INT_MAP_DATA_INT2_OFFSET 4 #define BMI260_INT_MAP_DATA_REG(_i, _bit) \ - (CONCAT3(BMI260_MAP_, _bit, _INT) << \ - CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET)) + (CONCAT3(BMI260_MAP_, _bit, _INT) \ + << CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET)) -#define BMI260_INIT_CTRL 0x59 -#define BMI260_INIT_ADDR_0 0x5b -#define BMI260_INIT_ADDR_1 0x5c -#define BMI260_INIT_DATA 0x5e -#define BMI260_INTERNAL_ERROR 0x5f -#define BMI260_INT_ERR_1 BIT(1) -#define BMI260_INT_ERR_2 BIT(2) -#define BMI260_FEAT_ENG_DISABLED BIT(4) +#define BMI260_INIT_CTRL 0x59 +#define BMI260_INIT_ADDR_0 0x5b +#define BMI260_INIT_ADDR_1 0x5c +#define BMI260_INIT_DATA 0x5e +#define BMI260_INTERNAL_ERROR 0x5f +#define BMI260_INT_ERR_1 BIT(1) +#define BMI260_INT_ERR_2 BIT(2) +#define BMI260_FEAT_ENG_DISABLED BIT(4) -#define BMI260_AUX_IF_TRIM 0x68 -#define BMI260_GYR_CRT_CONF 0x69 +#define BMI260_AUX_IF_TRIM 0x68 +#define BMI260_GYR_CRT_CONF 0x69 -#define BMI260_NVM_CONF 0x6a -#define BMI260_NVM_PROG_EN BIT(1) +#define BMI260_NVM_CONF 0x6a +#define BMI260_NVM_PROG_EN BIT(1) -#define BMI260_IF_CONF 0x6b -#define BMI260_IF_SPI3 BIT(0) -#define BMI260_IF_SPI3_OIS BIT(1) -#define BMI260_IF_OIS_EN BIT(4) -#define BMI260_IF_AUX_EN BIT(5) +#define BMI260_IF_CONF 0x6b +#define BMI260_IF_SPI3 BIT(0) +#define BMI260_IF_SPI3_OIS BIT(1) +#define BMI260_IF_OIS_EN BIT(4) +#define BMI260_IF_AUX_EN BIT(5) -#define BMI260_DRV 0x6c -#define BMI260_ACC_SELF_TEST 0x6d +#define BMI260_DRV 0x6c +#define BMI260_ACC_SELF_TEST 0x6d #define BMI260_GYR_SELF_TEST_AXES 0x6e -#define BMI260_NV_CONF 0x70 -#define BMI260_ACC_OFFSET_EN BIT(3) +#define BMI260_NV_CONF 0x70 +#define BMI260_ACC_OFFSET_EN BIT(3) -#define BMI260_OFFSET_ACC70 0x71 -#define BMI260_OFFSET_GYR70 0x74 -#define BMI260_OFFSET_EN_GYR98 0x77 -#define BMI260_OFFSET_GYRO_EN BIT(6) -#define BMI260_GYR_GAIN_EN BIT(7) +#define BMI260_OFFSET_ACC70 0x71 +#define BMI260_OFFSET_GYR70 0x74 +#define BMI260_OFFSET_EN_GYR98 0x77 +#define BMI260_OFFSET_GYRO_EN BIT(6) +#define BMI260_GYR_GAIN_EN BIT(7) -#define BMI260_PWR_CONF 0x7c -#define BMI260_ADV_POWER_SAVE BIT(0) -#define BMI260_FIFO_SELF_WAKE_UP BIT(1) -#define BMI260_FUP_EN BIT(2) +#define BMI260_PWR_CONF 0x7c +#define BMI260_ADV_POWER_SAVE BIT(0) +#define BMI260_FIFO_SELF_WAKE_UP BIT(1) +#define BMI260_FUP_EN BIT(2) -#define BMI260_PWR_CTRL 0x7d -#define BMI260_AUX_EN BIT(0) -#define BMI260_GYR_EN BIT(1) -#define BMI260_ACC_EN BIT(2) +#define BMI260_PWR_CTRL 0x7d +#define BMI260_AUX_EN BIT(0) +#define BMI260_GYR_EN BIT(1) +#define BMI260_ACC_EN BIT(2) #define BMI260_PWR_EN(_sensor_type) BIT(2 - _sensor_type) -#define BMI260_TEMP_EN BIT(3) +#define BMI260_TEMP_EN BIT(3) -#define BMI260_CMD_REG 0x7e -#define BMI260_CMD_FIFO_FLUSH 0xb0 -#define BMI260_CMD_SOFT_RESET 0xb6 +#define BMI260_CMD_REG 0x7e +#define BMI260_CMD_FIFO_FLUSH 0xb0 +#define BMI260_CMD_SOFT_RESET 0xb6 -#define BMI260_FF_FRAME_LEN_TS 4 -#define BMI260_FF_DATA_LEN_ACC 6 -#define BMI260_FF_DATA_LEN_GYR 6 -#define BMI260_FF_DATA_LEN_MAG 8 +#define BMI260_FF_FRAME_LEN_TS 4 +#define BMI260_FF_DATA_LEN_ACC 6 +#define BMI260_FF_DATA_LEN_GYR 6 +#define BMI260_FF_DATA_LEN_MAG 8 /* Root mean square noise of 100Hz accelerometer, units: ug */ -#define BMI260_ACCEL_RMS_NOISE_100HZ 1060 +#define BMI260_ACCEL_RMS_NOISE_100HZ 1060 #if defined(CONFIG_ZEPHYR) #if DT_NODE_EXISTS(DT_ALIAS(bmi260_int)) @@ -343,9 +343,9 @@ * bmi260-int = &base_accel; * }; */ -#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \ +#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_BMI260_H */ diff --git a/include/driver/accelgyro_bmi260_public.h b/include/driver/accelgyro_bmi260_public.h index 9b93ef65ae..33fc55300d 100644 --- a/include/driver/accelgyro_bmi260_public.h +++ b/include/driver/accelgyro_bmi260_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,7 +18,7 @@ */ /* I2C addresses */ -#define BMI260_ADDR0_FLAGS 0x68 +#define BMI260_ADDR0_FLAGS 0x68 extern const struct accelgyro_drv bmi260_drv; diff --git a/include/driver/accelgyro_bmi_common.h b/include/driver/accelgyro_bmi_common.h index 6e1ed122b3..371d3d97ce 100644 --- a/include/driver/accelgyro_bmi_common.h +++ b/include/driver/accelgyro_bmi_common.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,18 +18,18 @@ #error "BMI must use either SPI or I2C communication" #endif -#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor)) -#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor)) +#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor)) +#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor)) -#define BMI_ODR_MASK 0x0F +#define BMI_ODR_MASK 0x0F /* odr = 100 / (1 << (8 - reg)) , within limit */ -#define BMI_ODR_0_78HZ 0x01 -#define BMI_ODR_100HZ 0x08 +#define BMI_ODR_0_78HZ 0x01 +#define BMI_ODR_100HZ 0x08 -#define BMI_REG_TO_ODR(_regval) \ +#define BMI_REG_TO_ODR(_regval) \ ((_regval) < BMI_ODR_100HZ ? 100000 / (1 << (8 - (_regval))) : \ - 100000 * (1 << ((_regval) - 8))) -#define BMI_ODR_TO_REG(_odr) \ + 100000 * (1 << ((_regval)-8))) +#define BMI_ODR_TO_REG(_odr) \ ((_odr) < 100000 ? (__builtin_clz(100000 / ((_odr) + 1)) - 24) : \ (39 - __builtin_clz((_odr) / 100000))) @@ -40,92 +40,97 @@ enum fifo_header { BMI_FH_CONFIG = 0x48 }; -#define BMI_FH_MODE_MASK 0xc0 -#define BMI_FH_PARM_OFFSET 2 -#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET) -#define BMI_FH_EXT_MASK 0x03 +#define BMI_FH_MODE_MASK 0xc0 +#define BMI_FH_PARM_OFFSET 2 +#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET) +#define BMI_FH_EXT_MASK 0x03 /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define BMI_RESOLUTION 16 +#define BMI_RESOLUTION 16 /* Min and Max sampling frequency in mHz */ #define BMI_ACCEL_MIN_FREQ 12500 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) -#define BMI_GYRO_MIN_FREQ 25000 +#define BMI_GYRO_MIN_FREQ 25000 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000) enum bmi_running_mode { - STANDARD_UI_9DOF_FIFO = 0, - STANDARD_UI_IMU_FIFO = 1, - STANDARD_UI_IMU = 2, - STANDARD_UI_ADVANCEPOWERSAVE = 3, - ACCEL_PEDOMETER = 4, - APPLICATION_HEAD_TRACKING = 5, - APPLICATION_NAVIGATION = 6, - APPLICATION_REMOTE_CONTROL = 7, - APPLICATION_INDOOR_NAVIGATION = 8, + STANDARD_UI_9DOF_FIFO = 0, + STANDARD_UI_IMU_FIFO = 1, + STANDARD_UI_IMU = 2, + STANDARD_UI_ADVANCEPOWERSAVE = 3, + ACCEL_PEDOMETER = 4, + APPLICATION_HEAD_TRACKING = 5, + APPLICATION_NAVIGATION = 6, + APPLICATION_REMOTE_CONTROL = 7, + APPLICATION_INDOOR_NAVIGATION = 8, }; -#define BMI_FLAG_SEC_I2C_ENABLED BIT(0) -#define BMI_FIFO_FLAG_OFFSET 4 -#define BMI_FIFO_ALL_MASK 7 - -#define BMI_GET_DATA(_s) \ - ((struct bmi_drv_data_t *)(_s)->drv_data) -#define BMI_GET_SAVED_DATA(_s) \ - (&BMI_GET_DATA(_s)->saved_data[(_s)->type]) - -#define BMI_ACC_DATA(v) (BMI160_ACC_X_L_G + \ - (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G)) -#define BMI_GYR_DATA(v) (BMI160_GYR_X_L_G + \ - (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G)) -#define BMI_AUX_DATA(v) (BMI160_MAG_X_L_G + \ - (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G)) - -#define BMI_FIFO_CONFIG_0(v) (BMI160_FIFO_CONFIG_0 + \ - (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0)) -#define BMI_FIFO_CONFIG_1(v) (BMI160_FIFO_CONFIG_1 + \ - (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1)) -#define BMI_FIFO_SENSOR_EN(v, _sensor) (BMI160_FIFO_SENSOR_EN(_sensor) + \ - (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - BMI160_FIFO_SENSOR_EN(_sensor))) - -#define BMI_TEMPERATURE_0(v) (BMI160_TEMPERATURE_0 + \ - (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0)) -#define BMI_INVALID_TEMP 0x8000 - -#define BMI_STATUS(v) (BMI160_STATUS + \ - (v) * (BMI260_STATUS - BMI160_STATUS)) -#define BMI_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) - -#define BMI_OFFSET_ACC70(v) (BMI160_OFFSET_ACC70 + \ - (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70)) -#define BMI_OFFSET_GYR70(v) (BMI160_OFFSET_GYR70 + \ - (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70)) +#define BMI_FLAG_SEC_I2C_ENABLED BIT(0) +#define BMI_FIFO_FLAG_OFFSET 4 +#define BMI_FIFO_ALL_MASK 7 + +#define BMI_GET_DATA(_s) ((struct bmi_drv_data_t *)(_s)->drv_data) +#define BMI_GET_SAVED_DATA(_s) (&BMI_GET_DATA(_s)->saved_data[(_s)->type]) + +#define BMI_ACC_DATA(v) \ + (BMI160_ACC_X_L_G + (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G)) +#define BMI_GYR_DATA(v) \ + (BMI160_GYR_X_L_G + (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G)) +#define BMI_AUX_DATA(v) \ + (BMI160_MAG_X_L_G + (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G)) + +#define BMI_FIFO_CONFIG_0(v) \ + (BMI160_FIFO_CONFIG_0 + \ + (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0)) +#define BMI_FIFO_CONFIG_1(v) \ + (BMI160_FIFO_CONFIG_1 + \ + (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1)) +#define BMI_FIFO_SENSOR_EN(v, _sensor) \ + (BMI160_FIFO_SENSOR_EN(_sensor) + \ + (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - \ + BMI160_FIFO_SENSOR_EN(_sensor))) + +#define BMI_TEMPERATURE_0(v) \ + (BMI160_TEMPERATURE_0 + \ + (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0)) +#define BMI_INVALID_TEMP 0x8000 + +#define BMI_STATUS(v) (BMI160_STATUS + (v) * (BMI260_STATUS - BMI160_STATUS)) +#define BMI_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) + +#define BMI_OFFSET_ACC70(v) \ + (BMI160_OFFSET_ACC70 + \ + (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70)) +#define BMI_OFFSET_GYR70(v) \ + (BMI160_OFFSET_GYR70 + \ + (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70)) /* * There is some bits in this register that differ between BMI160 and BMI260 * Only use this macro for gyro offset 9:8 (BMI_OFFSET_EN_GYR98 5:0). */ -#define BMI_OFFSET_EN_GYR98(v) (BMI160_OFFSET_EN_GYR98 + \ - (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98)) -#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1) -#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024) -#define BMI_OFFSET_ACC_DIV_MG 1000000 +#define BMI_OFFSET_EN_GYR98(v) \ + (BMI160_OFFSET_EN_GYR98 + \ + (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98)) +#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1) +#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024) +#define BMI_OFFSET_ACC_DIV_MG 1000000 #define BMI_OFFSET_GYRO_MULTI_MDS (61 * 1024) -#define BMI_OFFSET_GYRO_DIV_MDS 1000 - -#define BMI_FIFO_LENGTH_0(v) (BMI160_FIFO_LENGTH_0 + \ - (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0)) -#define BMI_FIFO_LENGTH_MASK(v) (BMI160_FIFO_LENGTH_MASK + \ - (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK)) -#define BMI_FIFO_DATA(v) (BMI160_FIFO_DATA + \ - (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA)) - -#define BMI_CMD_REG(v) (BMI160_CMD_REG + \ - (v) * (BMI260_CMD_REG - BMI160_CMD_REG)) +#define BMI_OFFSET_GYRO_DIV_MDS 1000 + +#define BMI_FIFO_LENGTH_0(v) \ + (BMI160_FIFO_LENGTH_0 + \ + (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0)) +#define BMI_FIFO_LENGTH_MASK(v) \ + (BMI160_FIFO_LENGTH_MASK + \ + (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK)) +#define BMI_FIFO_DATA(v) \ + (BMI160_FIFO_DATA + (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA)) + +#define BMI_CMD_REG(v) \ + (BMI160_CMD_REG + (v) * (BMI260_CMD_REG - BMI160_CMD_REG)) #define BMI_CMD_FIFO_FLUSH 0xb0 -#define BMI_ACCEL_RMS_NOISE_100HZ(v) (BMI160_ACCEL_RMS_NOISE_100HZ + \ - (v) * (BMI260_ACCEL_RMS_NOISE_100HZ - BMI160_ACCEL_RMS_NOISE_100HZ)) #define BMI_ACCEL_100HZ 100 /* @@ -145,8 +150,8 @@ int bmi_get_xyz_reg(const struct motion_sensor_t *s); * * @return Range table of the type. */ -const struct bmi_accel_param_pair *bmi_get_range_table( - const struct motion_sensor_t *s, int *psize); +const struct bmi_accel_param_pair * +bmi_get_range_table(const struct motion_sensor_t *s, int *psize); /** * @return reg value that matches the given engineering value passed in. @@ -155,8 +160,7 @@ const struct bmi_accel_param_pair *bmi_get_range_table( * outside the range of values, it returns the closest valid reg value. */ int bmi_get_reg_val(const int eng_val, const int round_up, - const struct bmi_accel_param_pair *pairs, - const int size); + const struct bmi_accel_param_pair *pairs, const int size); /** * @return engineering value that matches the given reg val @@ -168,14 +172,14 @@ int bmi_get_engineering_val(const int reg_val, /** * Read 8bit register from accelerometer. */ -int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int *data_ptr); +int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int *data_ptr); /** * Write 8bit register from accelerometer. */ -int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int data); +int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int data); /** * Read 16bit register from accelerometer. @@ -210,14 +214,14 @@ int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags, /* * Enable/Disable specific bit set of a 8-bit reg. */ -int bmi_enable_reg8(const struct motion_sensor_t *s, - int reg, uint8_t bits, int enable); +int bmi_enable_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits, + int enable); /* * Set specific bit set to certain value of a 8-bit reg. */ -int bmi_set_reg8(const struct motion_sensor_t *s, int reg, - uint8_t bits, int mask); +int bmi_set_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits, + int mask); /* * @s: base sensor. @@ -237,9 +241,8 @@ void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input); * @bp: current pointer in the buffer, updated when processing the header. * @ep: pointer to the end of the valid data in the buffer. */ -int bmi_decode_header(struct motion_sensor_t *accel, - enum fifo_header hdr, uint32_t last_ts, - uint8_t **bp, uint8_t *ep); +int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr, + uint32_t last_ts, uint8_t **bp, uint8_t *ep); /** * Retrieve hardware FIFO from sensor, * - put data in Sensor Hub fifo. @@ -261,21 +264,19 @@ int bmi_set_range(struct motion_sensor_t *s, int range, int rnd); int bmi_get_data_rate(const struct motion_sensor_t *s); - -int bmi_get_offset(const struct motion_sensor_t *s, - int16_t *offset, int16_t *temp); +int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp); int bmi_get_resolution(const struct motion_sensor_t *s); -#ifdef CONFIG_BODY_DETECTION -int bmi_get_rms_noise(const struct motion_sensor_t *s); -#endif +int bmi_get_rms_noise(const struct motion_sensor_t *accel, + int rms_noise_100hz_mg); -int bmi_set_scale(const struct motion_sensor_t *s, - const uint16_t *scale, int16_t temp); +int bmi_set_scale(const struct motion_sensor_t *s, const uint16_t *scale, + int16_t temp); -int bmi_get_scale(const struct motion_sensor_t *s, - uint16_t *scale, int16_t *temp); +int bmi_get_scale(const struct motion_sensor_t *s, uint16_t *scale, + int16_t *temp); /* Start/Stop the FIFO collecting events */ int bmi_enable_fifo(const struct motion_sensor_t *s, int enable); @@ -311,9 +312,8 @@ int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v); /* Set the gyroscope offset */ int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v, - int *val98_ptr); + int *val98_ptr); -int bmi_list_activities(const struct motion_sensor_t *s, - uint32_t *enabled, +int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled, uint32_t *disabled); #endif /* __CROS_EC_ACCELGYRO_BMI_COMMON_H */ diff --git a/include/driver/accelgyro_bmi_common_public.h b/include/driver/accelgyro_bmi_common_public.h index 52814c71bf..b3965d4dc5 100644 --- a/include/driver/accelgyro_bmi_common_public.h +++ b/include/driver/accelgyro_bmi_common_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,14 +10,14 @@ /* Min and Max sampling frequency in mHz */ #define BMI_ACCEL_MIN_FREQ 12500 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) -#define BMI_GYRO_MIN_FREQ 25000 +#define BMI_GYRO_MIN_FREQ 25000 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000) struct bmi_drv_data_t { struct accelgyro_saved_data_t saved_data[3]; - uint8_t flags; - uint8_t enabled_activities; - uint8_t disabled_activities; + uint8_t flags; + uint8_t enabled_activities; + uint8_t disabled_activities; #ifdef CONFIG_MAG_BMI_BMM150 struct bmm150_private_data compass; #endif @@ -26,7 +26,6 @@ struct bmi_drv_data_t { enum motionsensor_orientation orientation; enum motionsensor_orientation last_orientation; #endif - }; #endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H */ diff --git a/include/driver/accelgyro_lsm6dso_public.h b/include/driver/accelgyro_lsm6dso_public.h index 65e98bccec..f2c1b2bc4e 100644 --- a/include/driver/accelgyro_lsm6dso_public.h +++ b/include/driver/accelgyro_lsm6dso_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,12 +14,11 @@ * 7-bit address is 110101xb. Where 'x' is determined * by the voltage on the ADDR pin */ -#define LSM6DSO_ADDR0_FLAGS 0x6a -#define LSM6DSO_ADDR1_FLAGS 0x6b +#define LSM6DSO_ADDR0_FLAGS 0x6a +#define LSM6DSO_ADDR1_FLAGS 0x6b /* Absolute maximum rate for Acc and Gyro sensors */ -#define LSM6DSO_ODR_MIN_VAL 13000 -#define LSM6DSO_ODR_MAX_VAL \ - MOTION_MAX_SENSOR_FREQUENCY(416000, 13000) +#define LSM6DSO_ODR_MIN_VAL 13000 +#define LSM6DSO_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(416000, 13000) #endif /* __CROS_EC_ACCELGYRO_LSM6DSO_PUBLIC_H */ diff --git a/include/driver/als_tcs3400.h b/include/driver/als_tcs3400.h index 0748befa71..ab28d7e7d5 100644 --- a/include/driver/als_tcs3400.h +++ b/include/driver/als_tcs3400.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,70 +11,69 @@ #include "driver/als_tcs3400_public.h" /* ID for TCS34001 and TCS34005 */ -#define TCS340015_DEVICE_ID 0x90 +#define TCS340015_DEVICE_ID 0x90 /* ID for TCS34003 and TCS34007 */ -#define TCS340037_DEVICE_ID 0x93 +#define TCS340037_DEVICE_ID 0x93 /* Register Map */ -#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */ -#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */ -#define TCS_I2C_WTIME 0x83 /* R/W Wait time */ -#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */ -#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */ -#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */ -#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */ -#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */ -#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */ -#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */ -#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */ -#define TCS_I2C_REVID 0x91 /* R Revision ID */ -#define TCS_I2C_ID 0x92 /* R Device ID */ -#define TCS_I2C_STATUS 0x93 /* R Device status */ -#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */ -#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */ -#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */ -#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */ -#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */ -#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */ -#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */ -#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */ -#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */ -#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */ -#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */ -#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */ - -#define TCS_I2C_ENABLE_POWER_ON BIT(0) -#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1) -#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3) -#define TCS_I2C_ENABLE_INT_ENABLE BIT(4) -#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6) -#define TCS_I2C_ENABLE_MASK (TCS_I2C_ENABLE_POWER_ON | \ - TCS_I2C_ENABLE_ADC_ENABLE | \ - TCS_I2C_ENABLE_WAIT_ENABLE | \ - TCS_I2C_ENABLE_INT_ENABLE | \ - TCS_I2C_ENABLE_SLEEP_AFTER_INT) +#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */ +#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */ +#define TCS_I2C_WTIME 0x83 /* R/W Wait time */ +#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */ +#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */ +#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */ +#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */ +#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */ +#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */ +#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */ +#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */ +#define TCS_I2C_REVID 0x91 /* R Revision ID */ +#define TCS_I2C_ID 0x92 /* R Device ID */ +#define TCS_I2C_STATUS 0x93 /* R Device status */ +#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */ +#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */ +#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */ +#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */ +#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */ +#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */ +#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */ +#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */ +#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */ +#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */ +#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */ +#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */ + +#define TCS_I2C_ENABLE_POWER_ON BIT(0) +#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1) +#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3) +#define TCS_I2C_ENABLE_INT_ENABLE BIT(4) +#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6) +#define TCS_I2C_ENABLE_MASK \ + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE | \ + TCS_I2C_ENABLE_WAIT_ENABLE | TCS_I2C_ENABLE_INT_ENABLE | \ + TCS_I2C_ENABLE_SLEEP_AFTER_INT) enum tcs3400_mode { TCS3400_MODE_SUSPEND = 0, - TCS3400_MODE_IDLE = (TCS_I2C_ENABLE_POWER_ON | - TCS_I2C_ENABLE_ADC_ENABLE), - TCS3400_MODE_COLLECTING = (TCS_I2C_ENABLE_POWER_ON | - TCS_I2C_ENABLE_ADC_ENABLE | - TCS_I2C_ENABLE_INT_ENABLE), + TCS3400_MODE_IDLE = + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE), + TCS3400_MODE_COLLECTING = + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE | + TCS_I2C_ENABLE_INT_ENABLE), }; -#define TCS_I2C_CONTROL_MASK 0x03 -#define TCS_I2C_STATUS_RGBC_VALID BIT(0) -#define TCS_I2C_STATUS_ALS_IRQ BIT(4) -#define TCS_I2C_STATUS_ALS_SATURATED BIT(7) +#define TCS_I2C_CONTROL_MASK 0x03 +#define TCS_I2C_STATUS_RGBC_VALID BIT(0) +#define TCS_I2C_STATUS_ALS_IRQ BIT(4) +#define TCS_I2C_STATUS_ALS_SATURATED BIT(7) -#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5) +#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5) /* Light data resides at 0x94 thru 0x98 */ -#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL -#define TCS_CLEAR_DATA_SIZE 2 -#define TCS_RGBC_DATA_SIZE 8 +#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL +#define TCS_CLEAR_DATA_SIZE 2 +#define TCS_RGBC_DATA_SIZE 8 #define TCS3400_DRV_DATA(_s) ((struct als_drv_data_t *)(_s)->drv_data) #define TCS3400_RGB_DRV_DATA(_s) \ @@ -96,20 +95,20 @@ enum tcs3400_mode { * To avoid this, we require value to be <= 20% of saturation level * (TCS_GAIN_SAT_LEVEL) before allowing gain to be increased. */ -#define TCS_GAIN_ADJUST_FACTOR 5 -#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR) -#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */ -#define TCS_UPSHIFT_FACTOR_D 10 -#define TCS_GAIN_UPSHIFT_LEVEL (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D \ - / TCS_UPSHIFT_FACTOR_N) +#define TCS_GAIN_ADJUST_FACTOR 5 +#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR) +#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */ +#define TCS_UPSHIFT_FACTOR_D 10 +#define TCS_GAIN_UPSHIFT_LEVEL \ + (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D / TCS_UPSHIFT_FACTOR_N) /* * Percentage of saturation level that the auto-adjusting anti-saturation * method will drive towards. */ #define TSC_SATURATION_LOW_BAND_PERCENT 90 -#define TSC_SATURATION_LOW_BAND_LEVEL (TCS_SATURATION_LEVEL * \ - TSC_SATURATION_LOW_BAND_PERCENT / 100) +#define TSC_SATURATION_LOW_BAND_LEVEL \ + (TCS_SATURATION_LEVEL * TSC_SATURATION_LOW_BAND_PERCENT / 100) enum crbg_index { CLEAR_CRGB_IDX = 0, @@ -134,9 +133,9 @@ enum crbg_index { * tcs3400-int = &als_clear; * }; */ -#define CONFIG_ALS_TCS3400_INT_EVENT \ +#define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ALS_TCS3400_H */ diff --git a/include/driver/als_tcs3400_public.h b/include/driver/als_tcs3400_public.h index 812aeda8d3..2cf9aed45f 100644 --- a/include/driver/als_tcs3400_public.h +++ b/include/driver/als_tcs3400_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,34 +11,34 @@ #include "accelgyro.h" /* I2C Interface */ -#define TCS3400_I2C_ADDR_FLAGS 0x39 +#define TCS3400_I2C_ADDR_FLAGS 0x39 /* NOTE: The higher the ATIME value in reg, the shorter the accumulation time */ -#define TCS_MIN_ATIME 0x00 /* 712 ms */ -#define TCS_MAX_ATIME 0x70 /* 400 ms */ -#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */ -#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */ -#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */ -#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME -#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME +#define TCS_MIN_ATIME 0x00 /* 712 ms */ +#define TCS_MAX_ATIME 0x70 /* 400 ms */ +#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */ +#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */ +#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */ +#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME +#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME /* Number of different ranges supported for atime adjustment support */ -#define TCS_MAX_ATIME_RANGES 13 -#define TCS_GAIN_TABLE_MAX_LUX 12999 -#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */ +#define TCS_MAX_ATIME_RANGES 13 +#define TCS_GAIN_TABLE_MAX_LUX 12999 +#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */ -#define TCS_MIN_AGAIN 0x00 /* 1x gain */ -#define TCS_MAX_AGAIN 0x03 /* 64x gain */ -#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */ -#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN +#define TCS_MIN_AGAIN 0x00 /* 1x gain */ +#define TCS_MAX_AGAIN 0x03 /* 64x gain */ +#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */ +#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN #define TCS_MAX_INTEGRATION_TIME 2780 /* 2780us */ -#define TCS_ATIME_DEC_STEP 5 -#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME +#define TCS_ATIME_DEC_STEP 5 +#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME /* Min and Max sampling frequency in mHz */ -#define TCS3400_LIGHT_MIN_FREQ 149 -#define TCS3400_LIGHT_MAX_FREQ 1000 +#define TCS3400_LIGHT_MIN_FREQ 149 +#define TCS3400_LIGHT_MAX_FREQ 1000 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= TCS3400_LIGHT_MAX_FREQ) #error "EC too slow for light sensor" #endif @@ -55,15 +55,16 @@ struct tcs_saturation_t { uint8_t again; /* Acquisition Time, controlled by the ATIME register */ - uint8_t atime; /* ATIME register setting */ + uint8_t atime; /* ATIME register setting */ }; /* tcs3400 rgb als driver data */ struct tcs3400_rgb_drv_data_t { - uint8_t calibration_mode;/* 0 = normal run mode, 1 = calibration mode */ + uint8_t calibration_mode; /* 0 = normal run mode, 1 = calibration mode + */ struct rgb_calibration_t calibration; - struct tcs_saturation_t saturation; /* saturation adjustment */ + struct tcs_saturation_t saturation; /* saturation adjustment */ }; extern const struct accelgyro_drv tcs3400_drv; diff --git a/include/driver/amd_stt.h b/include/driver/amd_stt.h index 3d382a6c0a..124b13fb00 100644 --- a/include/driver/amd_stt.h +++ b/include/driver/amd_stt.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/bc12/mt6360_public.h b/include/driver/bc12/mt6360_public.h index d2b8499e1f..fbceb74dd6 100644 --- a/include/driver/bc12/mt6360_public.h +++ b/include/driver/bc12/mt6360_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/bc12/pi3usb9201_public.h b/include/driver/bc12/pi3usb9201_public.h index 643952ab4a..20788aa5e3 100644 --- a/include/driver/bc12/pi3usb9201_public.h +++ b/include/driver/bc12/pi3usb9201_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/charger/isl923x_public.h b/include/driver/charger/isl923x_public.h index 2ee5f62cdb..c5d38f75c7 100644 --- a/include/driver/charger/isl923x_public.h +++ b/include/driver/charger/isl923x_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,7 +11,7 @@ #include "common.h" #include "stdbool.h" -#define ISL923X_ADDR_FLAGS (0x09) +#define ISL923X_ADDR_FLAGS (0x09) extern const struct charger_drv isl923x_drv; diff --git a/include/driver/charger/isl9241_public.h b/include/driver/charger/isl9241_public.h index 342f627bd3..be586f39c3 100644 --- a/include/driver/charger/isl9241_public.h +++ b/include/driver/charger/isl9241_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -8,10 +8,10 @@ #ifndef __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H #define __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H -#define ISL9241_ADDR_FLAGS 0x09 +#define ISL9241_ADDR_FLAGS 0x09 /* Default minimum VIN voltage controlled by ISL9241_REG_VIN_VOLTAGE */ -#define ISL9241_BC12_MIN_VOLTAGE 4096 +#define ISL9241_BC12_MIN_VOLTAGE 4096 extern const struct charger_drv isl9241_drv; @@ -33,9 +33,9 @@ int isl9241_set_ac_prochot(int chgnum, int ma); */ int isl9241_set_dc_prochot(int chgnum, int ma); -#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */ -#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ -#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */ -#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ +#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */ +#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ +#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */ +#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ #endif /* __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H */ diff --git a/include/driver/ln9310.h b/include/driver/ln9310.h index a5d3cf8922..dacdf95a91 100644 --- a/include/driver/ln9310.h +++ b/include/driver/ln9310.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,192 +12,192 @@ #include "gpio_signal.h" /* I2C address */ -#define LN9310_I2C_ADDR_0_FLAGS 0x72 -#define LN9310_I2C_ADDR_1_FLAGS 0x73 -#define LN9310_I2C_ADDR_2_FLAGS 0x53 -#define LN9310_I2C_ADDR_3_FLAGS 0x54 +#define LN9310_I2C_ADDR_0_FLAGS 0x72 +#define LN9310_I2C_ADDR_1_FLAGS 0x73 +#define LN9310_I2C_ADDR_2_FLAGS 0x53 +#define LN9310_I2C_ADDR_3_FLAGS 0x54 /* Registers */ -#define LN9310_REG_CHIP_ID 0x00 -#define LN9310_CHIP_ID 0x44 -#define LN9310_REG_INT1 0x01 -#define LN9310_REG_INT1_MSK 0x02 -#define LN9310_INT1_TIMER BIT(0) -#define LN9310_INT1_INFET BIT(1) -#define LN9310_INT1_TEMP BIT(2) -#define LN9310_INT1_REV_CURR BIT(3) -#define LN9310_INT1_MODE BIT(4) -#define LN9310_INT1_ALARM BIT(5) -#define LN9310_INT1_OK BIT(6) -#define LN9310_INT1_FAULT BIT(7) - -#define LN9310_REG_SYSGPIO_MSK 0x03 - -#define LN9310_REG_SYS_STS 0x04 -#define LN9310_SYS_STANDBY BIT(0) -#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1) -#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2) -#define LN9310_SYS_BYPASS_ACTIVE BIT(3) -#define LN9310_SYS_INFET_OK BIT(4) -#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5) -#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6) - -#define LN9310_REG_SAFETY_STS 0x05 -#define LN9310_REG_FAULT1_STS 0x06 -#define LN9310_REG_FAULT2_STS 0x07 - -#define LN9310_REG_PWR_CTRL 0x1d -#define LN9310_PWR_OP_MODE0 BIT(0) -#define LN9310_PWR_OP_MODE1 BIT(1) -#define LN9310_PWR_INFET_EN BIT(2) -#define LN9310_PWR_INFET_AUTO_MODE BIT(3) -#define LN9310_PWR_REVERSE_MODE BIT(4) -#define LN9310_PWR_VIN_OV_IGNORE BIT(5) -#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6) -#define LN9310_PWR_FORCE_INSNS_EN BIT(7) -#define LN9310_PWR_OP_MODE_MASK 0x03 -#define LN9310_PWR_OP_MODE_DISABLED 0x00 -#define LN9310_PWR_OP_MODE_BYPASS 0x01 -#define LN9310_PWR_OP_MODE_SWITCH21 0x02 -#define LN9310_PWR_OP_MODE_SWITCH31 0x03 -#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40 -#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00 -#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08 -#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08 -#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00 - -#define LN9310_REG_SYS_CTRL 0x1e - -#define LN9310_REG_STARTUP_CTRL 0x1f -#define LN9310_STARTUP_STANDBY_EN BIT(0) -#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3) - -#define LN9310_REG_IIN_CTRL 0x20 -#define LN9310_REG_VIN_CTRL 0x21 - -#define LN9310_REG_TRACK_CTRL 0x22 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10 - -#define LN9310_REG_OCP_CTRL 0x23 - -#define LN9310_REG_TIMER_CTRL 0x24 -#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3) -#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08 -#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08 - -#define LN9310_REG_RECOVERY_CTRL 0x25 - -#define LN9310_REG_LB_CTRL 0x26 -#define LN9310_LB_MIN_FREQ_EN BIT(2) -#define LN9310_LB_DELTA_MASK 0x38 -#define LN9310_LB_DELTA_2S 0x20 -#define LN9310_LB_DELTA_3S 0x20 - -#define LN9310_REG_SC_OUT_OV_CTRL 0x29 -#define LN9310_REG_STS_CTRL 0x2d - -#define LN9310_REG_MODE_CHANGE_CFG 0x2e -#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0) -#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1) -#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2) -#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3) -#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4) -#define LN9310_MODE_TM_TRACK_CFG0 BIT(5) -#define LN9310_MODE_TM_TRACK_CFG1 BIT(6) -#define LN9310_MODE_FORCE_MODE_CFG BIT(7) -#define LN9310_MODE_TM_TRACK_MASK 0x60 -#define LN9310_MODE_TM_TRACK_BYPASS 0x00 -#define LN9310_MODE_TM_TRACK_SWITCH21 0x20 -#define LN9310_MODE_TM_TRACK_SWITCH31 0x60 -#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18 -#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0 -#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08 -#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18 -#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07 -#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */ -#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */ - -#define LN9310_REG_SPARE_0 0x2A -#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40 -#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40 -#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10 -#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10 - -#define LN9310_REG_SC_DITHER_CTRL 0x2f - -#define LN9310_REG_LION_CTRL 0x30 -#define LN9310_LION_CTRL_MASK 0xFF -#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA -#define LN9310_LION_CTRL_UNLOCK 0x5B +#define LN9310_REG_CHIP_ID 0x00 +#define LN9310_CHIP_ID 0x44 +#define LN9310_REG_INT1 0x01 +#define LN9310_REG_INT1_MSK 0x02 +#define LN9310_INT1_TIMER BIT(0) +#define LN9310_INT1_INFET BIT(1) +#define LN9310_INT1_TEMP BIT(2) +#define LN9310_INT1_REV_CURR BIT(3) +#define LN9310_INT1_MODE BIT(4) +#define LN9310_INT1_ALARM BIT(5) +#define LN9310_INT1_OK BIT(6) +#define LN9310_INT1_FAULT BIT(7) + +#define LN9310_REG_SYSGPIO_MSK 0x03 + +#define LN9310_REG_SYS_STS 0x04 +#define LN9310_SYS_STANDBY BIT(0) +#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1) +#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2) +#define LN9310_SYS_BYPASS_ACTIVE BIT(3) +#define LN9310_SYS_INFET_OK BIT(4) +#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5) +#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6) + +#define LN9310_REG_SAFETY_STS 0x05 +#define LN9310_REG_FAULT1_STS 0x06 +#define LN9310_REG_FAULT2_STS 0x07 + +#define LN9310_REG_PWR_CTRL 0x1d +#define LN9310_PWR_OP_MODE0 BIT(0) +#define LN9310_PWR_OP_MODE1 BIT(1) +#define LN9310_PWR_INFET_EN BIT(2) +#define LN9310_PWR_INFET_AUTO_MODE BIT(3) +#define LN9310_PWR_REVERSE_MODE BIT(4) +#define LN9310_PWR_VIN_OV_IGNORE BIT(5) +#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6) +#define LN9310_PWR_FORCE_INSNS_EN BIT(7) +#define LN9310_PWR_OP_MODE_MASK 0x03 +#define LN9310_PWR_OP_MODE_DISABLED 0x00 +#define LN9310_PWR_OP_MODE_BYPASS 0x01 +#define LN9310_PWR_OP_MODE_SWITCH21 0x02 +#define LN9310_PWR_OP_MODE_SWITCH31 0x03 +#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40 +#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00 +#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08 +#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08 +#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00 + +#define LN9310_REG_SYS_CTRL 0x1e + +#define LN9310_REG_STARTUP_CTRL 0x1f +#define LN9310_STARTUP_STANDBY_EN BIT(0) +#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3) + +#define LN9310_REG_IIN_CTRL 0x20 +#define LN9310_REG_VIN_CTRL 0x21 + +#define LN9310_REG_TRACK_CTRL 0x22 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10 + +#define LN9310_REG_OCP_CTRL 0x23 + +#define LN9310_REG_TIMER_CTRL 0x24 +#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3) +#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08 +#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08 + +#define LN9310_REG_RECOVERY_CTRL 0x25 + +#define LN9310_REG_LB_CTRL 0x26 +#define LN9310_LB_MIN_FREQ_EN BIT(2) +#define LN9310_LB_DELTA_MASK 0x38 +#define LN9310_LB_DELTA_2S 0x20 +#define LN9310_LB_DELTA_3S 0x20 + +#define LN9310_REG_SC_OUT_OV_CTRL 0x29 +#define LN9310_REG_STS_CTRL 0x2d + +#define LN9310_REG_MODE_CHANGE_CFG 0x2e +#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0) +#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1) +#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2) +#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3) +#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4) +#define LN9310_MODE_TM_TRACK_CFG0 BIT(5) +#define LN9310_MODE_TM_TRACK_CFG1 BIT(6) +#define LN9310_MODE_FORCE_MODE_CFG BIT(7) +#define LN9310_MODE_TM_TRACK_MASK 0x60 +#define LN9310_MODE_TM_TRACK_BYPASS 0x00 +#define LN9310_MODE_TM_TRACK_SWITCH21 0x20 +#define LN9310_MODE_TM_TRACK_SWITCH31 0x60 +#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18 +#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0 +#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08 +#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18 +#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07 +#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */ +#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */ + +#define LN9310_REG_SPARE_0 0x2A +#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40 +#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40 +#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10 +#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10 + +#define LN9310_REG_SC_DITHER_CTRL 0x2f + +#define LN9310_REG_LION_CTRL 0x30 +#define LN9310_LION_CTRL_MASK 0xFF +#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA +#define LN9310_LION_CTRL_UNLOCK 0x5B /* * value changed to 0x22 to distinguish from reset value of 0x00 * 0x22 and 0x00 are functionally equivalent within LN9310 */ -#define LN9310_LION_CTRL_LOCK 0x22 - -#define LN9310_REG_CFG_0 0x3C -#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20 -#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20 - -#define LN9310_REG_CFG_4 0x40 -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2) -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3) -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04 -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08 -#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0 -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04 -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00 -#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00 - -#define LN9310_REG_CFG_5 0x41 -#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0 -#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00 -#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30 -#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00 - -#define LN9310_REG_TEST_MODE_CTRL 0x46 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00 - -#define LN9310_REG_FORCE_SC21_CTRL_1 0x49 -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59 -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40 - -#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80 -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80 -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00 - -#define LN9310_REG_SWAP_CTRL_0 0x58 -#define LN9310_REG_SWAP_CTRL_1 0x59 -#define LN9310_REG_SWAP_CTRL_2 0x5A -#define LN9310_REG_SWAP_CTRL_3 0x5B - -#define LN9310_REG_BC_STS_B 0x51 -#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5) -#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20 - -#define LN9310_REG_BC_STS_C 0x52 -#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0 -#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40 +#define LN9310_LION_CTRL_LOCK 0x22 + +#define LN9310_REG_CFG_0 0x3C +#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20 +#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20 + +#define LN9310_REG_CFG_4 0x40 +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2) +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3) +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04 +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08 +#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0 +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04 +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00 +#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00 + +#define LN9310_REG_CFG_5 0x41 +#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0 +#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00 +#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30 +#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00 + +#define LN9310_REG_TEST_MODE_CTRL 0x46 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00 + +#define LN9310_REG_FORCE_SC21_CTRL_1 0x49 +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59 +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40 + +#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80 +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80 +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00 + +#define LN9310_REG_SWAP_CTRL_0 0x58 +#define LN9310_REG_SWAP_CTRL_1 0x59 +#define LN9310_REG_SWAP_CTRL_2 0x5A +#define LN9310_REG_SWAP_CTRL_3 0x5B + +#define LN9310_REG_BC_STS_B 0x51 +#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5) +#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20 + +#define LN9310_REG_BC_STS_C 0x52 +#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0 +#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40 /* LN9310 Timing definition */ -#define LN9310_CDC_DELAY 120 /* 120us */ -#define LN9310_CFLY_PRECHARGE_DELAY (12*MSEC) -#define LN9310_CFLY_PRECHARGE_TIMEOUT (100*MSEC) +#define LN9310_CDC_DELAY 120 /* 120us */ +#define LN9310_CFLY_PRECHARGE_DELAY (12 * MSEC) +#define LN9310_CFLY_PRECHARGE_TIMEOUT (100 * MSEC) /* LN9310 Driver Configuration */ #define LN9310_INIT_RETRY_COUNT 3 diff --git a/include/driver/mag_bmm150.h b/include/driver/mag_bmm150.h index 9f517f8097..0325e6c5fc 100644 --- a/include/driver/mag_bmm150.h +++ b/include/driver/mag_bmm150.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,68 +11,68 @@ #include "accelgyro.h" #include "mag_cal.h" -#define BMM150_ADDR0_FLAGS 0x10 -#define BMM150_ADDR1_FLAGS 0x11 -#define BMM150_ADDR2_FLAGS 0x12 -#define BMM150_ADDR3_FLAGS 0x13 - -#define BMM150_CHIP_ID 0x40 -#define BMM150_CHIP_ID_MAJOR 0x32 - -#define BMM150_BASE_DATA 0x42 - -#define BMM150_INT_STATUS 0x4a -#define BMM150_PWR_CTRL 0x4b -#define BMM150_SRST (BIT(7) | BIT(1)) -#define BMM150_PWR_ON BIT(0) - -#define BMM150_OP_CTRL 0x4c -#define BMM150_OP_MODE_OFFSET 1 -#define BMM150_OP_MODE_MASK 3 -#define BMM150_OP_MODE_NORMAL 0x00 -#define BMM150_OP_MODE_FORCED 0x01 -#define BMM150_OP_MODE_SLEEP 0x03 - -#define BMM150_INT_CTRL 0x4d - -#define BMM150_REPXY 0x51 -#define BMM150_LOW_POWER_nXY 3 -#define BMM150_REGULAR_nXY 9 -#define BMM150_ENHANCED_nXY 15 -#define BMM150_HIGH_ACCURACY_nXY 47 -#define BMM150_SPECIAL_nXY 75 -#define BMM150_REPZ 0x52 -#define BMM150_LOW_POWER_nZ 3 -#define BMM150_REGULAR_nZ 15 -#define BMM150_ENHANCED_nZ 27 -#define BMM150_HIGH_ACCURACY_nZ 83 -#define BMM150_SPECIAL_nZ 27 +#define BMM150_ADDR0_FLAGS 0x10 +#define BMM150_ADDR1_FLAGS 0x11 +#define BMM150_ADDR2_FLAGS 0x12 +#define BMM150_ADDR3_FLAGS 0x13 + +#define BMM150_CHIP_ID 0x40 +#define BMM150_CHIP_ID_MAJOR 0x32 + +#define BMM150_BASE_DATA 0x42 + +#define BMM150_INT_STATUS 0x4a +#define BMM150_PWR_CTRL 0x4b +#define BMM150_SRST (BIT(7) | BIT(1)) +#define BMM150_PWR_ON BIT(0) + +#define BMM150_OP_CTRL 0x4c +#define BMM150_OP_MODE_OFFSET 1 +#define BMM150_OP_MODE_MASK 3 +#define BMM150_OP_MODE_NORMAL 0x00 +#define BMM150_OP_MODE_FORCED 0x01 +#define BMM150_OP_MODE_SLEEP 0x03 + +#define BMM150_INT_CTRL 0x4d + +#define BMM150_REPXY 0x51 +#define BMM150_LOW_POWER_nXY 3 +#define BMM150_REGULAR_nXY 9 +#define BMM150_ENHANCED_nXY 15 +#define BMM150_HIGH_ACCURACY_nXY 47 +#define BMM150_SPECIAL_nXY 75 +#define BMM150_REPZ 0x52 +#define BMM150_LOW_POWER_nZ 3 +#define BMM150_REGULAR_nZ 15 +#define BMM150_ENHANCED_nZ 27 +#define BMM150_HIGH_ACCURACY_nZ 83 +#define BMM150_SPECIAL_nZ 27 #define BMM150_REP(_preset, _axis) CONCAT4(BMM150_, _preset, _n, _axis) /* Hidden registers for RHALL calculation */ -#define BMM150_REGA_DIG_X1 0x5d -#define BMM150_REGA_DIG_Y1 0x5e -#define BMM150_REGA_DIG_Z4_LSB 0x62 -#define BMM150_REGA_DIG_Z4_MSB 0x63 -#define BMM150_REGA_DIG_X2 0x64 -#define BMM150_REGA_DIG_Y2 0x65 -#define BMM150_REGA_DIG_Z2_LSB 0x68 -#define BMM150_REGA_DIG_Z2_MSB 0x69 -#define BMM150_REGA_DIG_Z1_LSB 0x6a -#define BMM150_REGA_DIG_Z1_MSB 0x6b +#define BMM150_REGA_DIG_X1 0x5d +#define BMM150_REGA_DIG_Y1 0x5e +#define BMM150_REGA_DIG_Z4_LSB 0x62 +#define BMM150_REGA_DIG_Z4_MSB 0x63 +#define BMM150_REGA_DIG_X2 0x64 +#define BMM150_REGA_DIG_Y2 0x65 +#define BMM150_REGA_DIG_Z2_LSB 0x68 +#define BMM150_REGA_DIG_Z2_MSB 0x69 +#define BMM150_REGA_DIG_Z1_LSB 0x6a +#define BMM150_REGA_DIG_Z1_MSB 0x6b #define BMM150_REGA_DIG_XYZ1_LSB 0x6c #define BMM150_REGA_DIG_XYZ1_MSB 0x6d -#define BMM150_REGA_DIG_Z3_LSB 0x6e -#define BMM150_REGA_DIG_Z3_MSB 0x6f -#define BMM150_REGA_DIG_XY2 0x70 -#define BMM150_REGA_DIG_XY1 0x71 +#define BMM150_REGA_DIG_Z3_LSB 0x6e +#define BMM150_REGA_DIG_Z3_MSB 0x6f +#define BMM150_REGA_DIG_XY2 0x70 +#define BMM150_REGA_DIG_XY1 0x71 /* Overflow */ -#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096) -#define BMM150_HALL_OVERFLOW_ADCVAL (-16384) -#define BMM150_OVERFLOW_OUTPUT (0x8000) +#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096) +#define BMM150_HALL_OVERFLOW_ADCVAL (-16384) +#define BMM150_OVERFLOW_OUTPUT (0x8000) /* Min and Max sampling frequency in mHz */ #define BMM150_MAG_MIN_FREQ 781 @@ -84,8 +84,9 @@ * * To be safe, declare only 75% of the value. */ -#define __BMM150_MAG_MAX_FREQ(_preset) (750000000 / \ - (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980)) +#define __BMM150_MAG_MAX_FREQ(_preset) \ + (750000000 / \ + (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980)) #if (__BMM150_MAG_MAX_FREQ(SPECIAL) > CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ) #error "EC too slow for magnetometer" @@ -93,34 +94,32 @@ struct bmm150_comp_registers { /* Local copy of the compensation registers. */ - int8_t dig1[2]; - int8_t dig2[2]; + int8_t dig1[2]; + int8_t dig2[2]; - uint16_t dig_z1; - int16_t dig_z2; - int16_t dig_z3; - int16_t dig_z4; + uint16_t dig_z1; + int16_t dig_z2; + int16_t dig_z3; + int16_t dig_z4; - uint8_t dig_xy1; - int8_t dig_xy2; + uint8_t dig_xy1; + int8_t dig_xy2; - uint16_t dig_xyz1; + uint16_t dig_xyz1; }; struct bmm150_private_data { /* lsm6dsm_data union requires cal be first element */ - struct mag_cal_t cal; + struct mag_cal_t cal; struct bmm150_comp_registers comp; }; #ifdef CONFIG_MAG_BMI_BMM150 #include "accelgyro_bmi_common.h" -#define BMM150_COMP_REG(_s) \ - (&BMI_GET_DATA(_s)->compass.comp) +#define BMM150_COMP_REG(_s) (&BMI_GET_DATA(_s)->compass.comp) -#define BMM150_CAL(_s) \ - (&BMI_GET_DATA(_s)->compass.cal) +#define BMM150_CAL(_s) (&BMI_GET_DATA(_s)->compass.cal) /* * Behind a BMI, the BMM150 is in forced mode. Be sure to choose a frequency * compatible with BMI. @@ -137,14 +136,11 @@ struct bmm150_private_data { int bmm150_init(struct motion_sensor_t *s); /* Command to normalize and apply temperature compensation */ -void bmm150_normalize(const struct motion_sensor_t *s, - intv3_t v, +void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data); -int bmm150_set_offset(const struct motion_sensor_t *s, - const intv3_t offset); +int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset); -int bmm150_get_offset(const struct motion_sensor_t *s, - intv3_t offset); +int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset); #endif /* __CROS_EC_MAG_BMM150_H */ diff --git a/include/driver/ppc/aoz1380_public.h b/include/driver/ppc/aoz1380_public.h new file mode 100644 index 0000000000..aa617054fe --- /dev/null +++ b/include/driver/ppc/aoz1380_public.h @@ -0,0 +1,43 @@ +/* Copyright 2019 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * AOZ1380 USB-C Power Path Controller + * + * This is a basic TCPM controlled PPC driver. It could easily be + * renamed and repurposed to be generic, if there are other TCPM + * controlled PPC chips that are similar to the AOZ1380 + */ + +#ifndef __CROS_EC_AOZ1380_PUBLIC_H +#define __CROS_EC_AOZ1380_PUBLIC_H + +#include "usb_pd_tcpm.h" + +struct ppc_drv; +extern const struct ppc_drv aoz1380_drv; + +/** + * AOZ1380 Set VBus Source Current Limit. + * + * Using this driver requires a board_aoz1380_set_vbus_source_limit + * function due to the lack of programability of this device and + * requirement for hardware specific code to handle setting this limit. + * + * @param port The Type-C port + * @param rp The Type-C RP value + * @return EC_SUCCESS for success, otherwise error + */ +int board_aoz1380_set_vbus_source_current_limit(int port, + enum tcpc_rp_value rp); + +/** + * Interrupt Handler for the AOZ1380. + * + * @param port: The Type-C port which triggered the interrupt. + */ +void aoz1380_interrupt(int port); + +#endif /* defined(__CROS_EC_AOZ1380_H) */ diff --git a/include/driver/ppc/ktu1125_public.h b/include/driver/ppc/ktu1125_public.h index 276f8c9a99..28ecfc7c23 100644 --- a/include/driver/ppc/ktu1125_public.h +++ b/include/driver/ppc/ktu1125_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/ppc/nx20p348x_public.h b/include/driver/ppc/nx20p348x_public.h new file mode 100644 index 0000000000..145896aca1 --- /dev/null +++ b/include/driver/ppc/nx20p348x_public.h @@ -0,0 +1,32 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TI NX20P348X USB-C Power Path Controller */ + +#ifndef __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H +#define __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H + +#include "usbc_ppc.h" + +#define NX20P3483_ADDR0_FLAGS 0x70 +#define NX20P3483_ADDR1_FLAGS 0x71 +#define NX20P3483_ADDR2_FLAGS 0x72 +#define NX20P3483_ADDR3_FLAGS 0x73 + +#define NX20P3481_ADDR0_FLAGS 0x74 +#define NX20P3481_ADDR1_FLAGS 0x75 +#define NX20P3481_ADDR2_FLAGS 0x76 +#define NX20P3481_ADDR3_FLAGS 0x77 + +extern const struct ppc_drv nx20p348x_drv; + +/** + * Interrupt Handler for the NX20P348x. + * + * @param port: The Type-C port which triggered the interrupt. + */ +void nx20p348x_interrupt(int port); + +#endif /* __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H */ diff --git a/include/driver/ppc/sn5s330_public.h b/include/driver/ppc/sn5s330_public.h index fdd60e54cb..62652d99b2 100644 --- a/include/driver/ppc/sn5s330_public.h +++ b/include/driver/ppc/sn5s330_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/ppc/syv682x_public.h b/include/driver/ppc/syv682x_public.h index 92c841f811..a97d412478 100644 --- a/include/driver/ppc/syv682x_public.h +++ b/include/driver/ppc/syv682x_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,10 +9,10 @@ #define __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H /* I2C addresses */ -#define SYV682X_ADDR0_FLAGS 0x40 -#define SYV682X_ADDR1_FLAGS 0x41 -#define SYV682X_ADDR2_FLAGS 0x42 -#define SYV682X_ADDR3_FLAGS 0x43 +#define SYV682X_ADDR0_FLAGS 0x40 +#define SYV682X_ADDR1_FLAGS 0x41 +#define SYV682X_ADDR2_FLAGS 0x42 +#define SYV682X_ADDR3_FLAGS 0x43 extern const struct ppc_drv syv682x_drv; diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index 8c3b9eaf60..83ad32508e 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -13,10 +13,10 @@ #include "usb_mux.h" /* I2C interface addresses */ -#define ANX7483_I2C_ADDR0_FLAGS 0x3E -#define ANX7483_I2C_ADDR1_FLAGS 0x38 -#define ANX7483_I2C_ADDR2_FLAGS 0x40 -#define ANX7483_I2C_ADDR3_FLAGS 0x44 +#define ANX7483_I2C_ADDR0_FLAGS 0x3E +#define ANX7483_I2C_ADDR1_FLAGS 0x38 +#define ANX7483_I2C_ADDR2_FLAGS 0x40 +#define ANX7483_I2C_ADDR3_FLAGS 0x44 /* Equalization tuning */ enum anx7483_eq_setting { @@ -52,9 +52,11 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, enum anx7483_tune_pin pin, enum anx7483_eq_setting eq); -/* Configure datasheet defaults for tuning registers at this mux setting */ -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state); +/* + * Configure datasheet defaults for tuning registers at this mux setting. + * Return int so function can be used directly for board_set. + */ +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state); extern const struct usb_mux_driver anx7483_usb_retimer_driver; #endif /* __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H */ diff --git a/include/driver/retimer/bb_retimer.h b/include/driver/retimer/bb_retimer.h index 6a311bd2ca..460156803e 100644 --- a/include/driver/retimer/bb_retimer.h +++ b/include/driver/retimer/bb_retimer.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,44 +12,44 @@ #include "driver/retimer/bb_retimer_public.h" /* Burnside Bridge I2C Configuration Space */ -#define BB_RETIMER_REG_VENDOR_ID 0 -#define BB_RETIMER_VENDOR_ID_1 0x8086 -#define BB_RETIMER_VENDOR_ID_2 0x8087 +#define BB_RETIMER_REG_VENDOR_ID 0 +#define BB_RETIMER_VENDOR_ID_1 0x8086 +#define BB_RETIMER_VENDOR_ID_2 0x8087 -#define BB_RETIMER_REG_DEVICE_ID 1 -#ifdef CONFIG_USBC_RETIMER_INTEL_HB +#define BB_RETIMER_REG_DEVICE_ID 1 +#ifdef CONFIG_USBC_RETIMER_INTEL_HB /* HB has no Device ID field instead it is combined with Vendor ID */ -#define BB_RETIMER_DEVICE_ID 0x0D9C8087 +#define BB_RETIMER_DEVICE_ID 0x0D9C8087 #else -#define BB_RETIMER_DEVICE_ID 0x15EE +#define BB_RETIMER_DEVICE_ID 0x15EE #endif /* Connection State Register Attributes */ -#define BB_RETIMER_REG_CONNECTION_STATE 4 -#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) -#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) -#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) -#define BB_RETIMER_USB_2_CONNECTION BIT(4) -#define BB_RETIMER_USB_3_CONNECTION BIT(5) -#define BB_RETIMER_USB_3_SPEED BIT(6) -#define BB_RETIMER_USB_DATA_ROLE BIT(7) -#define BB_RETIMER_DP_CONNECTION BIT(8) -#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) -#define BB_RETIMER_IRQ_HPD BIT(14) -#define BB_RETIMER_HPD_LVL BIT(15) -#define BB_RETIMER_TBT_CONNECTION BIT(16) -#define BB_RETIMER_TBT_TYPE BIT(17) -#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) -#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) -#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) -#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) -#define BB_RETIMER_USB4_ENABLED BIT(23) -#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x) & 0x7) << 25) -#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x) & 0x3) << 28) - -#define BB_RETIMER_REG_TBT_CONTROL 5 -#define BB_RETIMER_REG_EXT_CONNECTION_MODE 6 - -#define BB_RETIMER_REG_COUNT 7 +#define BB_RETIMER_REG_CONNECTION_STATE 4 +#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) +#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) +#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) +#define BB_RETIMER_USB_2_CONNECTION BIT(4) +#define BB_RETIMER_USB_3_CONNECTION BIT(5) +#define BB_RETIMER_USB_3_SPEED BIT(6) +#define BB_RETIMER_USB_DATA_ROLE BIT(7) +#define BB_RETIMER_DP_CONNECTION BIT(8) +#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) +#define BB_RETIMER_IRQ_HPD BIT(14) +#define BB_RETIMER_HPD_LVL BIT(15) +#define BB_RETIMER_TBT_CONNECTION BIT(16) +#define BB_RETIMER_TBT_TYPE BIT(17) +#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) +#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) +#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) +#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) +#define BB_RETIMER_USB4_ENABLED BIT(23) +#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x)&0x7) << 25) +#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x)&0x3) << 28) + +#define BB_RETIMER_REG_TBT_CONTROL 5 +#define BB_RETIMER_REG_EXT_CONNECTION_MODE 7 + +#define BB_RETIMER_REG_COUNT 8 #endif /* __CROS_EC_BB_RETIMER_H */ diff --git a/include/driver/retimer/bb_retimer_public.h b/include/driver/retimer/bb_retimer_public.h index d79b051504..2d2893fb49 100644 --- a/include/driver/retimer/bb_retimer_public.h +++ b/include/driver/retimer/bb_retimer_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -56,4 +56,12 @@ __override_proto int bb_retimer_power_enable(const struct usb_mux *me, void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required); +/** + * Enable/disable the USB3 state of BB retimer + * + * @param me Pointer to USB mux + * @param enable BB retimer USB3 state to be changed + */ +void bb_retimer_set_usb3(const struct usb_mux *me, bool enable); + #endif /* __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H */ diff --git a/include/driver/retimer/ps8818_public.h b/include/driver/retimer/ps8818_public.h new file mode 100644 index 0000000000..3f0aba963b --- /dev/null +++ b/include/driver/retimer/ps8818_public.h @@ -0,0 +1,96 @@ +/* Copyright 2019 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * PS8818 retimer. + */ +#include "usb_mux.h" + +#ifndef __CROS_EC_USB_RETIMER_PS8818_H +#define __CROS_EC_USB_RETIMER_PS8818_H + +#define PS8818_I2C_ADDR_FLAGS 0x28 + +/* + * PAGE 0 Register Definitions + */ +#define PS8818_REG_PAGE0 0x00 + +#define PS8818_REG0_FLIP 0x00 +#define PS8818_FLIP_CONFIG BIT(7) +#define PS8818_FLIP_NON_RESERVED_MASK 0xE0 + +#define PS8818_REG0_MODE 0x01 +#define PS8818_MODE_DP_ENABLE BIT(7) +#define PS8818_MODE_USB_ENABLE BIT(6) +#define PS8818_MODE_NON_RESERVED_MASK 0xC0 + +#define PS8818_REG0_DPHPD_CONFIG 0x02 +#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7) +#define PS8818_DPHPD_PLUGGED BIT(6) +#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC + +/* + * PAGE 1 Register Definitions + */ +#define PS8818_REG_PAGE1 0x01 + +#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00 +#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02 +#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08 +#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A +#define PS8818_REG1_APRX1_DE_LEVEL 0x0C +#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70 +#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72 +#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78 +#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A +#define PS8818_EQ_LEVEL_UP_9DB (0) +#define PS8818_EQ_LEVEL_UP_10DB (1) +#define PS8818_EQ_LEVEL_UP_12DB (2) +#define PS8818_EQ_LEVEL_UP_13DB (3) +#define PS8818_EQ_LEVEL_UP_16DB (4) +#define PS8818_EQ_LEVEL_UP_17DB (5) +#define PS8818_EQ_LEVEL_UP_18DB (6) +#define PS8818_EQ_LEVEL_UP_19DB (7) +#define PS8818_EQ_LEVEL_UP_20DB (8) +#define PS8818_EQ_LEVEL_UP_21DB (9) +#define PS8818_EQ_LEVEL_UP_MASK (0x0F) + +#define PS8818_REG1_RX_PHY 0x6D +#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6) +#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6) +#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6) +#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6) +#define PS8818_RX_INPUT_TERM_MASK (3 << 6) + +#define PS8818_REG1_DPEQ_LEVEL 0xB6 +#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3) +#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3) +#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3) +#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3) +#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3) +#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3) +#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3) +#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3) +#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3) +#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3) +#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3) + +/* + * PAGE 2 Register Definitions + */ +#define PS8818_REG_PAGE2 0x02 + +#define PS8818_REG2_TX_STATUS 0x42 +#define PS8818_REG2_RX_STATUS 0x46 +#define PS8818_STATUS_NORMAL_OPERATION BIT(7) +#define PS8818_STATUS_10_GBPS BIT(5) + +extern const struct usb_mux_driver ps8818_usb_retimer_driver; + +int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data); +int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data); +int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset, + uint8_t field_mask, uint8_t set_value); + +#endif /* __CROS_EC_USB_RETIMER_PS8818_H */ diff --git a/include/driver/tcpm/anx7447_public.h b/include/driver/tcpm/anx7447_public.h new file mode 100644 index 0000000000..5ea1eebd35 --- /dev/null +++ b/include/driver/tcpm/anx7447_public.h @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Analogix Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H + +#include "usb_mux.h" + +#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C +#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B +#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A +#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 + +#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F +#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 +#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 +#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 + +extern const struct tcpm_drv anx7447_tcpm_drv; +extern const struct usb_mux_driver anx7447_usb_mux_driver; + +void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, + mux_state_t mux_state, bool *ack_required); +#endif /* __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H */ diff --git a/include/driver/tcpm/it8xxx2_pd_public.h b/include/driver/tcpm/it8xxx2_pd_public.h index 6ad11a9555..0c28127cdb 100644 --- a/include/driver/tcpm/it8xxx2_pd_public.h +++ b/include/driver/tcpm/it8xxx2_pd_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h index ad84f93ced..d327dee2a3 100644 --- a/include/driver/tcpm/ps8xxx_public.h +++ b/include/driver/tcpm/ps8xxx_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,12 +15,12 @@ struct usb_mux; /* I2C interface */ #define PS8XXX_I2C_ADDR1_P1_FLAGS 0x09 #define PS8XXX_I2C_ADDR1_P2_FLAGS 0x0A -#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ -#define PS8XXX_I2C_ADDR2_FLAGS 0x1B -#define PS8XXX_I2C_ADDR3_FLAGS 0x2B -#define PS8XXX_I2C_ADDR4_FLAGS 0x4B +#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ +#define PS8XXX_I2C_ADDR2_FLAGS 0x1B +#define PS8XXX_I2C_ADDR3_FLAGS 0x2B +#define PS8XXX_I2C_ADDR4_FLAGS 0x4B -#define PS8XXX_VENDOR_ID 0x1DA0 +#define PS8XXX_VENDOR_ID 0x1DA0 /* Minimum Delay for reset assertion */ #define PS8XXX_RESET_DELAY_MS 1 @@ -56,6 +56,7 @@ struct usb_mux; * 8705, 8755 and 8805. */ #define PS8705_PRODUCT_ID 0x8705 +#define PS8745_PRODUCT_ID 0x8745 #define PS8751_PRODUCT_ID 0x8751 #define PS8755_PRODUCT_ID 0x8755 #define PS8805_PRODUCT_ID 0x8805 @@ -75,12 +76,10 @@ extern const struct tcpm_drv ps8xxx_tcpm_drv; * * @param port TCPC port number. */ -__override_proto -uint16_t board_get_ps8xxx_product_id(int port); +__override_proto uint16_t board_get_ps8xxx_product_id(int port); void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required); + mux_state_t mux_state, bool *ack_required); #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev; diff --git a/include/driver/tcpm/rt1715_public.h b/include/driver/tcpm/rt1715_public.h index 14fa9495e8..2f3af95443 100644 --- a/include/driver/tcpm/rt1715_public.h +++ b/include/driver/tcpm/rt1715_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/tcpm/rt1718s_public.h b/include/driver/tcpm/rt1718s_public.h new file mode 100644 index 0000000000..62bade6ab9 --- /dev/null +++ b/include/driver/tcpm/rt1718s_public.h @@ -0,0 +1,24 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Richtek Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H + +#define RT1718S_I2C_ADDR1_FLAGS 0x43 +#define RT1718S_I2C_ADDR2_FLAGS 0x40 + +#define RT1718S_VID 0x29CF +#define RT1718S_PID 0x1718 + +#define RT1718S_DEVICE_ID 0x04 +#define RT1718S_DEVICE_ID_ES1 0x4511 +#define RT1718S_DEVICE_ID_ES2 0x4513 + +extern const struct tcpm_drv rt1718s_tcpm_drv; +extern const struct bc12_drv rt1718s_bc12_drv; + +#endif /* __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H */ diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h index 559b75a14f..4879f7dad1 100644 --- a/include/driver/tcpm/tcpci.h +++ b/include/driver/tcpm/tcpci.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,259 +14,250 @@ #include "usb_mux.h" #include "usb_pd_tcpm.h" -#define TCPC_REG_VENDOR_ID 0x0 -#define TCPC_REG_PRODUCT_ID 0x2 -#define TCPC_REG_BCD_DEV 0x4 -#define TCPC_REG_TC_REV 0x6 -#define TCPC_REG_PD_REV 0x8 -#define TCPC_REG_PD_INT_REV 0xa - -#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 -#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 -#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 -#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff -#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 -#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 -#define TCPC_REG_PD_INT_REV_REV(reg) \ - ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) -#define TCPC_REG_PD_INT_REV_VER(reg) \ - (reg & TCOC_REG_PD_INT_REV_VER_MASK) - -#define TCPC_REG_ALERT 0x10 -#define TCPC_REG_ALERT_NONE 0x0000 -#define TCPC_REG_ALERT_MASK_ALL 0xffff -#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) -#define TCPC_REG_ALERT_ALERT_EXT BIT(14) -#define TCPC_REG_ALERT_EXT_STATUS BIT(13) +#define TCPC_REG_VENDOR_ID 0x0 +#define TCPC_REG_PRODUCT_ID 0x2 +#define TCPC_REG_BCD_DEV 0x4 +#define TCPC_REG_TC_REV 0x6 +#define TCPC_REG_PD_REV 0x8 +#define TCPC_REG_PD_INT_REV 0xa + +#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 +#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 +#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 +#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff +#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 +#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 +#define TCPC_REG_PD_INT_REV_REV(reg) ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) +#define TCPC_REG_PD_INT_REV_VER(reg) (reg & TCOC_REG_PD_INT_REV_VER_MASK) + +#define TCPC_REG_ALERT 0x10 +#define TCPC_REG_ALERT_NONE 0x0000 +#define TCPC_REG_ALERT_MASK_ALL 0xffff +#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_ALERT_EXT BIT(14) +#define TCPC_REG_ALERT_EXT_STATUS BIT(13) #define TCPC_REG_ALERT_RX_BEGINNING BIT(12) #define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11) -#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) -#define TCPC_REG_ALERT_FAULT BIT(9) -#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) -#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) -#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) +#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) +#define TCPC_REG_ALERT_FAULT BIT(9) +#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) +#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) +#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) #define TCPC_REG_ALERT_TX_DISCARDED BIT(5) -#define TCPC_REG_ALERT_TX_FAILED BIT(4) -#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) -#define TCPC_REG_ALERT_RX_STATUS BIT(2) +#define TCPC_REG_ALERT_TX_FAILED BIT(4) +#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) +#define TCPC_REG_ALERT_RX_STATUS BIT(2) #define TCPC_REG_ALERT_POWER_STATUS BIT(1) -#define TCPC_REG_ALERT_CC_STATUS BIT(0) -#define TCPC_REG_ALERT_TX_COMPLETE (TCPC_REG_ALERT_TX_SUCCESS | \ - TCPC_REG_ALERT_TX_DISCARDED | \ - TCPC_REG_ALERT_TX_FAILED) +#define TCPC_REG_ALERT_CC_STATUS BIT(0) +#define TCPC_REG_ALERT_TX_COMPLETE \ + (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | \ + TCPC_REG_ALERT_TX_FAILED) -#define TCPC_REG_ALERT_MASK 0x12 -#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_MASK 0x12 +#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) #define TCPC_REG_POWER_STATUS_MASK 0x14 #define TCPC_REG_FAULT_STATUS_MASK 0x15 -#define TCPC_REG_EXT_STATUS_MASK 0x16 +#define TCPC_REG_EXT_STATUS_MASK 0x16 #define TCPC_REG_ALERT_EXTENDED_MASK 0x17 #define TCPC_REG_CONFIG_STD_OUTPUT 0x18 -#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) -#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) +#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0) -#define TCPC_REG_TCPC_CTRL 0x19 +#define TCPC_REG_TCPC_CTRL 0x19 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity) -#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1) +#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg)&0x1) /* * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when * a connection is found. */ -#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) -#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) -#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) - -#define TCPC_REG_ROLE_CTRL 0x1a -#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) -#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5)|BIT(4)) -#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1)|BIT(0)) -#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ - ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ - (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ - (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ - ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK)) -#define TCPC_REG_ROLE_CTRL_DRP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) -#define TCPC_REG_ROLE_CTRL_RP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) -#define TCPC_REG_ROLE_CTRL_CC2(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) -#define TCPC_REG_ROLE_CTRL_CC1(reg) \ - ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK) - -#define TCPC_REG_FAULT_CTRL 0x1b -#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) -#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) - -#define TCPC_REG_POWER_CTRL 0x1c -#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) -#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) -#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) -#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) -#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) +#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) +#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) +#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) + +#define TCPC_REG_ROLE_CTRL 0x1a +#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) +#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5) | BIT(4)) +#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1) | BIT(0)) +#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ + ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ + (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ + (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ + ((cc1)&TCPC_REG_ROLE_CTRL_CC1_MASK)) +#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg)&TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) +#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg)&TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) +#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg)&TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) +#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg)&TCPC_REG_ROLE_CTRL_CC1_MASK) + +#define TCPC_REG_FAULT_CTRL 0x1b +#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) +#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) + +#define TCPC_REG_POWER_CTRL 0x1c +#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) +#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) +#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) +#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) +#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn) -#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1) +#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg)&0x1) -#define TCPC_REG_CC_STATUS 0x1d -#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) -#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) -#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1)|BIT(0)) +#define TCPC_REG_CC_STATUS 0x1d +#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) +#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) +#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1) | BIT(0)) #define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \ - ((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3)) + ((term) << 4 | ((cc2)&0x3) << 2 | ((cc1)&0x3)) #define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \ - ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) + ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) #define TCPC_REG_CC_STATUS_TERM(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) + (((reg)&TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) #define TCPC_REG_CC_STATUS_CC2(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) -#define TCPC_REG_CC_STATUS_CC1(reg) \ - ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK) + (((reg)&TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) +#define TCPC_REG_CC_STATUS_CC1(reg) ((reg)&TCPC_REG_CC_STATUS_CC1_STATE_MASK) -#define TCPC_REG_POWER_STATUS 0x1e -#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff +#define TCPC_REG_POWER_STATUS 0x1e +#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff #define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7) -#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) +#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) #define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4) -#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) +#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) #define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2) #define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0) -#define TCPC_REG_FAULT_STATUS 0x1f -#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) -#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) -#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) -#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) -#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) -#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) - -#define TCPC_REG_EXT_STATUS 0x20 -#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) - -#define TCPC_REG_ALERT_EXT 0x21 -#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) -#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) -#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) - -#define TCPC_REG_COMMAND 0x23 -#define TCPC_REG_COMMAND_WAKE_I2C 0x11 -#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 -#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 -#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 -#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 -#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 -#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 -#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD -#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE -#define TCPC_REG_COMMAND_I2CIDLE 0xFF - -#define TCPC_REG_DEV_CAP_1 0x24 -#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) -#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) -#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) -#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) -#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) -#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8)|BIT(9)) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) -#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) -#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) -#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) -#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) -#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) -#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) - -#define TCPC_REG_DEV_CAP_2 0x26 -#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) -#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) - -#define TCPC_REG_STD_INPUT_CAP 0x28 -#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4)|BIT(3)) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) -#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) - -#define TCPC_REG_STD_OUTPUT_CAP 0x29 -#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) -#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) -#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) -#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) -#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) -#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) - -#define TCPC_REG_CONFIG_EXT_1 0x2A -#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) - -#define TCPC_REG_GENERIC_TIMER 0x2c - -#define TCPC_REG_MSG_HDR_INFO 0x2e +#define TCPC_REG_FAULT_STATUS 0x1f +#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) +#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) +#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) +#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) +#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) +#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) + +#define TCPC_REG_EXT_STATUS 0x20 +#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) + +#define TCPC_REG_ALERT_EXT 0x21 +#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) +#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) +#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) + +#define TCPC_REG_COMMAND 0x23 +#define TCPC_REG_COMMAND_WAKE_I2C 0x11 +#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 +#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 +#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 +#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 +#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 +#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 +#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD +#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE +#define TCPC_REG_COMMAND_I2CIDLE 0xFF + +#define TCPC_REG_DEV_CAP_1 0x24 +#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) +#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) +#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) +#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) +#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) +#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8) | BIT(9)) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) +#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) +#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) +#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) +#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) +#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) +#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) + +#define TCPC_REG_DEV_CAP_2 0x26 +#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) +#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) + +#define TCPC_REG_STD_INPUT_CAP 0x28 +#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4) | BIT(3)) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) +#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) + +#define TCPC_REG_STD_OUTPUT_CAP 0x29 +#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) +#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) +#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) +#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) +#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) +#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) + +#define TCPC_REG_CONFIG_EXT_1 0x2A +#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) + +#define TCPC_REG_GENERIC_TIMER 0x2c + +#define TCPC_REG_MSG_HDR_INFO 0x2e #define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \ - ((drole) << 3 | (PD_REV20 << 1) | (prole)) -#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3) -#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1) - -#define TCPC_REG_RX_DETECT 0x2f -#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) -#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) -#define TCPC_REG_RX_DETECT_HRST BIT(5) -#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) -#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) -#define TCPC_REG_RX_DETECT_SOPPP BIT(2) -#define TCPC_REG_RX_DETECT_SOPP BIT(1) -#define TCPC_REG_RX_DETECT_SOP BIT(0) -#define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_HRST) -#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ - (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_SOPP | \ - TCPC_REG_RX_DETECT_SOPPP | \ - TCPC_REG_RX_DETECT_HRST) + ((drole) << 3 | (PD_REV20 << 1) | (prole)) +#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg)&0x8) >> 3) +#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg)&0x1) + +#define TCPC_REG_RX_DETECT 0x2f +#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) +#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) +#define TCPC_REG_RX_DETECT_HRST BIT(5) +#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) +#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) +#define TCPC_REG_RX_DETECT_SOPPP BIT(2) +#define TCPC_REG_RX_DETECT_SOPP BIT(1) +#define TCPC_REG_RX_DETECT_SOP BIT(0) +#define TCPC_REG_RX_DETECT_SOP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST) +#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | \ + TCPC_REG_RX_DETECT_SOPPP | TCPC_REG_RX_DETECT_HRST) /* TCPCI Rev 1.0 receive registers */ -#define TCPC_REG_RX_BYTE_CNT 0x30 +#define TCPC_REG_RX_BYTE_CNT 0x30 #define TCPC_REG_RX_BUF_FRAME_TYPE 0x31 -#define TCPC_REG_RX_HDR 0x32 -#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ +#define TCPC_REG_RX_HDR 0x32 +#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ /* * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers: * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can * only be accessed by reading at a common register address 30h. */ -#define TCPC_REG_RX_BUFFER 0x30 +#define TCPC_REG_RX_BUFFER 0x30 -#define TCPC_REG_TRANSMIT 0x50 +#define TCPC_REG_TRANSMIT 0x50 #define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) \ - ((retries) << 4 | (type)) + ((retries) << 4 | (type)) #define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type) -#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4) -#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg) & 0x7) +#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg)&0x30) >> 4) +#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg)&0x7) /* TCPCI Rev 1.0 transmit registers */ -#define TCPC_REG_TX_BYTE_CNT 0x51 -#define TCPC_REG_TX_HDR 0x52 -#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ +#define TCPC_REG_TX_BYTE_CNT 0x51 +#define TCPC_REG_TX_HDR 0x52 +#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ /* * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the @@ -274,12 +265,12 @@ * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x * is “hidden” and can only be accessed by writing to register address 51h */ -#define TCPC_REG_TX_BUFFER 0x51 +#define TCPC_REG_TX_BUFFER 0x51 -#define TCPC_REG_VBUS_VOLTAGE 0x70 -#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) -#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) -#define TCPC_REG_VBUS_VOLTAGE_LSB 25 +#define TCPC_REG_VBUS_VOLTAGE 0x70 +#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) +#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) +#define TCPC_REG_VBUS_VOLTAGE_LSB 25 /* * 00: the measurement is not scaled @@ -287,22 +278,21 @@ * 10: the measurement is divided by 4 * 11: reserved */ -#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ - (1 << (((x) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) -#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) \ - ((x) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) -#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ - (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ +#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ + (1 << (((x)&TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) +#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) ((x)&TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) +#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ + (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ TCPC_REG_VBUS_VOLTAGE_LSB) #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72 #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */ -#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 -#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a +#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a extern const struct tcpm_drv tcpci_tcpm_drv; extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver; @@ -315,7 +305,7 @@ enum tcpc_cc_pull tcpci_get_cached_pull(int port); void tcpci_tcpc_alert(int port); int tcpci_tcpm_init(int port); int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level); int tcpci_tcpm_select_rp_value(int port, int rp); int tcpci_tcpm_set_cc(int port, int pull); @@ -325,20 +315,22 @@ int tcpci_tcpm_set_vconn(int port, int enable); int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role); int tcpci_tcpm_set_rx_enable(int port, int enable); int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head); -int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data); +int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header, + const uint32_t *data); int tcpci_tcpm_release(int port); #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp, - enum tcpc_cc_pull pull); + enum tcpc_cc_pull pull); int tcpci_tcpc_drp_toggle(int port); #endif #ifdef CONFIG_USB_PD_TCPC_LOW_POWER int tcpci_enter_low_power_mode(int port); void tcpci_wake_low_power_mode(int port); #endif -enum ec_error_list tcpci_set_bist_test_mode(const int port, - const bool enable); +int tcpci_hard_reset_reinit(int port); + +enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable); +enum ec_error_list tcpci_get_bist_test_mode(const int port, bool *enable); void tcpci_tcpc_discharge_vbus(int port, int enable); void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable); int tcpci_tcpc_debug_accessory(int port, bool enable); diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h index ef47a3b1e2..8352423d9d 100644 --- a/include/driver/tcpm/tcpm.h +++ b/include/driver/tcpm/tcpm.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,26 +26,22 @@ #ifndef CONFIG_USB_PD_TCPC_LOW_POWER static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val) { - return i2c_write8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val) { - return i2c_write16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val) { - return i2c_read8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) { - return i2c_read16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } /* @@ -65,8 +61,8 @@ static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) * need an explicit by the caller. */ -static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, - int reg, int *val) +static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, + int *val) { return tcpc_addr_read16(port, i2c_addr, reg, val); } @@ -75,49 +71,47 @@ static inline int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, int in_size) { return i2c_xfer(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size); + tcpc_config[port].i2c_info.addr_flags, out, out_size, + in, in_size); } static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) + uint8_t *in, int in_size, int flags) { return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size, flags); + tcpc_config[port].i2c_info.addr_flags, out, + out_size, in, in_size, flags); } static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size) { return i2c_read_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, in, size); + tcpc_config[port].i2c_info.addr_flags, reg, in, + size); } -static inline int tcpc_write_block(int port, int reg, - const uint8_t *out, int size) +static inline int tcpc_write_block(int port, int reg, const uint8_t *out, + int size) { return i2c_write_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, out, size); + tcpc_config[port].i2c_info.addr_flags, reg, out, + size); } -static inline int tcpc_update8(int port, int reg, - uint8_t mask, +static inline int tcpc_update8(int port, int reg, uint8_t mask, enum mask_update_action action) { return i2c_update8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } -static inline int tcpc_update16(int port, int reg, - uint16_t mask, +static inline int tcpc_update16(int port, int reg, uint16_t mask, enum mask_update_action action) { return i2c_update16(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } #else /* !CONFIG_USB_PD_TCPC_LOW_POWER */ @@ -128,40 +122,40 @@ int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val); int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val); int tcpc_read_block(int port, int reg, uint8_t *in, int size); int tcpc_write_block(int port, int reg, const uint8_t *out, int size); -int tcpc_xfer(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size); -int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size); +int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); -int tcpc_update8(int port, int reg, - uint8_t mask, enum mask_update_action action); -int tcpc_update16(int port, int reg, - uint16_t mask, enum mask_update_action action); +int tcpc_update8(int port, int reg, uint8_t mask, + enum mask_update_action action); +int tcpc_update16(int port, int reg, uint16_t mask, + enum mask_update_action action); #endif /* CONFIG_USB_PD_TCPC_LOW_POWER */ static inline int tcpc_write(int port, int reg, int val) { - return tcpc_addr_write(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_write16(int port, int reg, int val) { - return tcpc_addr_write16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline int tcpc_read(int port, int reg, int *val) { - return tcpc_addr_read(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_read16(int port, int reg, int *val) { - return tcpc_addr_read16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline void tcpc_lock(int port, int lock) @@ -191,7 +185,7 @@ static inline int tcpm_release(int port) } static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { return tcpc_config[port].drv->get_cc(port, cc1, cc2); } @@ -281,7 +275,8 @@ static inline int tcpm_transmit(int port, enum tcpci_msg_type type, static inline bool tcpm_get_snk_ctrl(int port) { return tcpc_config[port].drv->get_snk_ctrl ? - tcpc_config[port].drv->get_snk_ctrl(port) : false; + tcpc_config[port].drv->get_snk_ctrl(port) : + false; } static inline int tcpm_set_snk_ctrl(int port, int enable) { @@ -293,9 +288,9 @@ static inline int tcpm_set_snk_ctrl(int port, int enable) static inline bool tcpm_get_src_ctrl(int port) { - return tcpc_config[port].drv->get_src_ctrl ? - tcpc_config[port].drv->get_src_ctrl(port) : false; + tcpc_config[port].drv->get_src_ctrl(port) : + false; } static inline int tcpm_set_src_ctrl(int port, int enable) { @@ -387,6 +382,13 @@ static inline int tcpm_get_chip_info(int port, int live, return EC_ERROR_UNIMPLEMENTED; } +static inline int tcpm_hard_reset_reinit(int port) +{ + if (tcpc_config[port].drv->hard_reset_reinit) + return tcpc_config[port].drv->hard_reset_reinit(port); + return EC_ERROR_UNIMPLEMENTED; +} + static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable) { const struct tcpm_drv *tcpc; @@ -398,6 +400,19 @@ static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable) return rv; } +static inline enum ec_error_list tcpc_get_bist_test_mode(int port, bool *enable) +{ + const struct tcpm_drv *tcpc; + + tcpc = tcpc_config[port].drv; + if (tcpc->get_bist_test_mode) + return tcpc->get_bist_test_mode(port, enable); + + *enable = false; + + return EC_ERROR_UNIMPLEMENTED; +} + /* * Returns true if the port controls FRS using the TCPC. */ @@ -444,8 +459,8 @@ static inline int tcpm_set_frs_enable(int port, int enable) static inline int tcpc_set_sbu(int port, bool enable) { return tcpc_config[port].drv->set_sbu ? - tcpc_config[port].drv->set_sbu(port, enable) : - EC_SUCCESS; + tcpc_config[port].drv->set_sbu(port, enable) : + EC_SUCCESS; } #endif /* CONFIG_USB_PD_TCPM_SBU */ @@ -470,7 +485,7 @@ int tcpm_init(int port); * @return EC_SUCCESS or error */ int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); /** * Check VBUS level diff --git a/include/driver/tcpm/tusb422_public.h b/include/driver/tcpm/tusb422_public.h index 8756d9b362..004abdd5c9 100644 --- a/include/driver/tcpm/tusb422_public.h +++ b/include/driver/tcpm/tusb422_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/driver/temp_sensor/pct2075.h b/include/driver/temp_sensor/pct2075.h index c09d0e383c..e79ac0e97a 100644 --- a/include/driver/temp_sensor/pct2075.h +++ b/include/driver/temp_sensor/pct2075.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,10 +17,10 @@ #define PCT2075_I2C_ADDR_FLAGS6 (0x4E | I2C_FLAG_BIG_ENDIAN) #define PCT2075_I2C_ADDR_FLAGS7 (0x4F | I2C_FLAG_BIG_ENDIAN) -#define PCT2075_REG_TEMP 0x00 -#define PCT2075_REG_CONF 0x01 -#define PCT2075_REG_THYST 0x02 -#define PCT2075_REG_TOS 0x03 +#define PCT2075_REG_TEMP 0x00 +#define PCT2075_REG_CONF 0x01 +#define PCT2075_REG_THYST 0x02 +#define PCT2075_REG_TOS 0x03 /* * I2C port and address information for all the board PCT2075 sensors should be diff --git a/include/driver/temp_sensor/sb_tsi.h b/include/driver/temp_sensor/sb_tsi.h index b7113dbc70..d8b015d200 100644 --- a/include/driver/temp_sensor/sb_tsi.h +++ b/include/driver/temp_sensor/sb_tsi.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,27 +11,27 @@ #ifndef __CROS_EC_SB_TSI_H #define __CROS_EC_SB_TSI_H -#define SB_TSI_I2C_ADDR_FLAGS 0x4C +#define SB_TSI_I2C_ADDR_FLAGS 0x4C /* G781 register */ -#define SB_TSI_TEMP_H 0x01 -#define SB_TSI_STATUS 0x02 -#define SB_TSI_CONFIG_1 0x03 -#define SB_TSI_UPDATE_RATE 0x04 -#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07 -#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08 -#define SB_TSI_CONFIG_2 0x09 -#define SB_TSI_TEMP_L 0x10 -#define SB_TSI_TEMP_OFFSET_H 0x11 -#define SB_TSI_TEMP_OFFSET_L 0x12 -#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13 -#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14 -#define SB_TSI_TIMEOUT_CONFIG 0x22 -#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F -#define SB_TSI_ALERT_THRESHOLD 0x32 -#define SB_TSI_ALERT_CONFIG 0xBF -#define SB_TSI_MANUFACTURE_ID 0xFE -#define SB_TSI_REVISION 0xFF +#define SB_TSI_TEMP_H 0x01 +#define SB_TSI_STATUS 0x02 +#define SB_TSI_CONFIG_1 0x03 +#define SB_TSI_UPDATE_RATE 0x04 +#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07 +#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08 +#define SB_TSI_CONFIG_2 0x09 +#define SB_TSI_TEMP_L 0x10 +#define SB_TSI_TEMP_OFFSET_H 0x11 +#define SB_TSI_TEMP_OFFSET_L 0x12 +#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13 +#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14 +#define SB_TSI_TIMEOUT_CONFIG 0x22 +#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F +#define SB_TSI_ALERT_THRESHOLD 0x32 +#define SB_TSI_ALERT_CONFIG 0xBF +#define SB_TSI_MANUFACTURE_ID 0xFE +#define SB_TSI_REVISION 0xFF /** * Get the value of a sensor in K. @@ -43,4 +43,4 @@ */ int sb_tsi_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_SB_TSI_H */ +#endif /* __CROS_EC_SB_TSI_H */ diff --git a/include/driver/temp_sensor/thermistor.h b/include/driver/temp_sensor/thermistor.h index adcd5c5be4..46b7763747 100644 --- a/include/driver/temp_sensor/thermistor.h +++ b/include/driver/temp_sensor/thermistor.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,13 +9,13 @@ #define __CROS_EC_TEMP_SENSOR_THERMISTOR_H struct thermistor_data_pair { - uint8_t mv; /* Scaled voltage level at ADC (in mV) */ - uint8_t temp; /* Temperature in Celsius */ + uint8_t mv; /* Scaled voltage level at ADC (in mV) */ + uint8_t temp; /* Temperature in Celsius */ }; struct thermistor_info { - uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */ - uint8_t num_pairs; /* Number of data pairs. */ + uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */ + uint8_t num_pairs; /* Number of data pairs. */ /* * Values between given data pairs will be calculated as points on diff --git a/include/driver/temp_sensor/tmp112.h b/include/driver/temp_sensor/tmp112.h index d1b97b138c..56d55d9133 100644 --- a/include/driver/temp_sensor/tmp112.h +++ b/include/driver/temp_sensor/tmp112.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,10 +13,10 @@ #define TMP112_I2C_ADDR_FLAGS2 (0x4A | I2C_FLAG_BIG_ENDIAN) #define TMP112_I2C_ADDR_FLAGS3 (0x4B | I2C_FLAG_BIG_ENDIAN) -#define TMP112_REG_TEMP 0x00 -#define TMP112_REG_CONF 0x01 -#define TMP112_REG_HYST 0x02 -#define TMP112_REG_MAX 0x03 +#define TMP112_REG_TEMP 0x00 +#define TMP112_REG_CONF 0x01 +#define TMP112_REG_HYST 0x02 +#define TMP112_REG_MAX 0x03 /* * I2C port and address information for all the board TMP112 sensors should be diff --git a/include/driver/usb_mux/it5205_public.h b/include/driver/usb_mux/it5205_public.h index 81dc326049..40590194c4 100644 --- a/include/driver/usb_mux/it5205_public.h +++ b/include/driver/usb_mux/it5205_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/driver/usb_mux/ps8743_public.h b/include/driver/usb_mux/ps8743_public.h index c20b948d07..64ba2d0cd7 100644 --- a/include/driver/usb_mux/ps8743_public.h +++ b/include/driver/usb_mux/ps8743_public.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,69 +10,69 @@ #include <inttypes.h> -#define PS8743_I2C_ADDR0_FLAG 0x10 -#define PS8743_I2C_ADDR1_FLAG 0x11 -#define PS8743_I2C_ADDR2_FLAG 0x19 -#define PS8743_I2C_ADDR3_FLAG 0x1a +#define PS8743_I2C_ADDR0_FLAG 0x10 +#define PS8743_I2C_ADDR1_FLAG 0x11 +#define PS8743_I2C_ADDR2_FLAG 0x19 +#define PS8743_I2C_ADDR3_FLAG 0x1a /* Mode register for setting mux */ #define PS8743_REG_MODE 0x00 -#define PS8743_MODE_IN_HPD_ASSERT BIT(0) -#define PS8743_MODE_IN_HPD_CONTROL BIT(1) -#define PS8743_MODE_FLIP_ENABLE BIT(2) +#define PS8743_MODE_IN_HPD_ASSERT BIT(0) +#define PS8743_MODE_IN_HPD_CONTROL BIT(1) +#define PS8743_MODE_FLIP_ENABLE BIT(2) #define PS8743_MODE_FLIP_REG_CONTROL BIT(3) -#define PS8743_MODE_USB_ENABLE BIT(4) -#define PS8743_MODE_USB_REG_CONTROL BIT(5) -#define PS8743_MODE_DP_ENABLE BIT(6) -#define PS8743_MODE_DP_REG_CONTROL BIT(7) +#define PS8743_MODE_USB_ENABLE BIT(4) +#define PS8743_MODE_USB_REG_CONTROL BIT(5) +#define PS8743_MODE_DP_ENABLE BIT(6) +#define PS8743_MODE_DP_REG_CONTROL BIT(7) /* To reset the state machine to default */ -#define PS8743_MODE_POWER_DOWN (PS8743_MODE_USB_REG_CONTROL | \ - PS8743_MODE_DP_REG_CONTROL) +#define PS8743_MODE_POWER_DOWN \ + (PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_DP_REG_CONTROL) /* DP output setting */ -#define PS8743_REG_DP_SETTING 0x07 -#define PS8743_DP_SWG_ADJ_DFLT 0x00 -#define PS8743_DP_SWG_ADJ_N20P 0x40 -#define PS8743_DP_SWG_ADJ_N15P 0x80 -#define PS8743_DP_SWG_ADJ_P15P 0xc0 -#define PS8743_DP_OUT_SWG_400 0x00 -#define PS8743_DP_OUT_SWG_600 0x10 -#define PS8743_DP_OUT_SWG_800 0x20 -#define PS8743_DP_OUT_SWG_1000 0x30 -#define PS8743_DP_OUT_PRE_EM_0_DB 0x00 +#define PS8743_REG_DP_SETTING 0x07 +#define PS8743_DP_SWG_ADJ_DFLT 0x00 +#define PS8743_DP_SWG_ADJ_N20P 0x40 +#define PS8743_DP_SWG_ADJ_N15P 0x80 +#define PS8743_DP_SWG_ADJ_P15P 0xc0 +#define PS8743_DP_OUT_SWG_400 0x00 +#define PS8743_DP_OUT_SWG_600 0x10 +#define PS8743_DP_OUT_SWG_800 0x20 +#define PS8743_DP_OUT_SWG_1000 0x30 +#define PS8743_DP_OUT_PRE_EM_0_DB 0x00 #define PS8743_DP_OUT_PRE_EM_3_5_DB 0x04 #define PS8743_DP_OUT_PRE_EM_6_0_DB 0x08 #define PS8743_DP_OUT_PRE_EM_9_5_DB 0x0c -#define PS8743_DP_POST_CUR2_0_DB 0x00 +#define PS8743_DP_POST_CUR2_0_DB 0x00 #define PS8743_DP_POST_CUR2_NEG_0_9_DB 0x01 #define PS8743_DP_POST_CUR2_NEG_1_9_DB 0x02 #define PS8743_DP_POST_CUR2_NEG_3_1_DB 0x03 /* USB equalization settings for Host to Mux */ -#define PS8743_REG_USB_EQ_TX 0x32 +#define PS8743_REG_USB_EQ_TX 0x32 #define PS8743_USB_EQ_TX_12_8_DB 0x00 -#define PS8743_USB_EQ_TX_17_DB 0x20 -#define PS8743_USB_EQ_TX_7_7_DB 0x40 -#define PS8743_USB_EQ_TX_3_6_DB 0x60 -#define PS8743_USB_EQ_TX_15_DB 0x80 +#define PS8743_USB_EQ_TX_17_DB 0x20 +#define PS8743_USB_EQ_TX_7_7_DB 0x40 +#define PS8743_USB_EQ_TX_3_6_DB 0x60 +#define PS8743_USB_EQ_TX_15_DB 0x80 #define PS8743_USB_EQ_TX_10_9_DB 0xc0 -#define PS8743_USB_EQ_TX_4_5_DB 0xe0 +#define PS8743_USB_EQ_TX_4_5_DB 0xe0 /* USB swing adjust for Mux to Type-C connector */ -#define PS8743_REG_USB_SWING 0x36 -#define PS8743_OUT_SWG_DEFAULT 0x00 -#define PS8743_OUT_SWG_NEG_20 0x40 -#define PS8743_OUT_SWG_NEG_15 0x80 -#define PS8743_OUT_SWG_POS_15 0xc0 -#define PS8743_LFPS_SWG_DEFAULT 0x00 -#define PS8743_LFPS_SWG_TD 0x08 +#define PS8743_REG_USB_SWING 0x36 +#define PS8743_OUT_SWG_DEFAULT 0x00 +#define PS8743_OUT_SWG_NEG_20 0x40 +#define PS8743_OUT_SWG_NEG_15 0x80 +#define PS8743_OUT_SWG_POS_15 0xc0 +#define PS8743_LFPS_SWG_DEFAULT 0x00 +#define PS8743_LFPS_SWG_TD 0x08 /* USB equalization settings for Connector to Mux */ -#define PS8743_REG_USB_EQ_RX 0x3b -#define PS8743_USB_EQ_RX_2_4_DB 0x00 -#define PS8743_USB_EQ_RX_5_DB 0x10 -#define PS8743_USB_EQ_RX_6_5_DB 0x20 -#define PS8743_USB_EQ_RX_7_4_DB 0x30 -#define PS8743_USB_EQ_RX_8_7_DB 0x40 +#define PS8743_REG_USB_EQ_RX 0x3b +#define PS8743_USB_EQ_RX_2_4_DB 0x00 +#define PS8743_USB_EQ_RX_5_DB 0x10 +#define PS8743_USB_EQ_RX_6_5_DB 0x20 +#define PS8743_USB_EQ_RX_7_4_DB 0x30 +#define PS8743_USB_EQ_RX_8_7_DB 0x40 #define PS8743_USB_EQ_RX_10_9_DB 0x50 #define PS8743_USB_EQ_RX_12_8_DB 0x60 #define PS8743_USB_EQ_RX_13_8_DB 0x70 @@ -85,21 +85,21 @@ #define PS8743_USB_EQ_RX_22_2_DB 0xe0 /* USB High Speed Signal Detector thershold adjustment */ -#define PS8743_REG_HS_DET_THRESHOLD 0x3c +#define PS8743_REG_HS_DET_THRESHOLD 0x3c #define PS8743_USB_HS_THRESH_DEFAULT 0x00 -#define PS8743_USB_HS_THRESH_POS_10 0x20 -#define PS8743_USB_HS_THRESH_POS_33 0x40 -#define PS8743_USB_HS_THRESH_NEG_10 0x60 -#define PS8743_USB_HS_THRESH_NEG_25 0x80 -#define PS8743_USB_HS_THRESH_POS_25 0xa0 -#define PS8743_USB_HS_THRESH_NEG_45 0xc0 -#define PS8743_USB_HS_THRESH_NEG_35 0xe0 +#define PS8743_USB_HS_THRESH_POS_10 0x20 +#define PS8743_USB_HS_THRESH_POS_33 0x40 +#define PS8743_USB_HS_THRESH_NEG_10 0x60 +#define PS8743_USB_HS_THRESH_NEG_25 0x80 +#define PS8743_USB_HS_THRESH_POS_25 0xa0 +#define PS8743_USB_HS_THRESH_NEG_45 0xc0 +#define PS8743_USB_HS_THRESH_NEG_35 0xe0 /* DCI config: 0x45~0x4D */ -#define PS8743_REG_DCI_CONFIG_2 0x47 -#define PS8743_AUTO_DCI_MODE_SHIFT 6 -#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT) -#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT) +#define PS8743_REG_DCI_CONFIG_2 0x47 +#define PS8743_AUTO_DCI_MODE_SHIFT 6 +#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT) +#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT) #define PS8743_AUTO_DCI_MODE_FORCE_USB (2 << PS8743_AUTO_DCI_MODE_SHIFT) #define PS8743_AUTO_DCI_MODE_FORCE_DCI (3 << PS8743_AUTO_DCI_MODE_SHIFT) diff --git a/include/ec_commands.h b/include/ec_commands.h index b11b34b5fd..a4ec6a00ed 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -32,7 +32,7 @@ #ifndef BUILD_ASSERT #define BUILD_ASSERT(_cond) #endif /* !BUILD_ASSERT */ -#endif /* CHROMIUM_EC */ +#endif /* CHROMIUM_EC */ #ifdef __KERNEL__ #include <linux/limits.h> @@ -45,11 +45,11 @@ */ #ifndef BIT -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) #endif #ifndef BIT_ULL -#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) #endif /* @@ -67,12 +67,26 @@ #endif #endif -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ #ifdef __cplusplus extern "C" { #endif +/** + * Constant for creation of flexible array members that work in both C and + * C++. Flexible array members were added in C99 and are not part of the C++ + * standard. However, clang++ supports them for C++. + * When compiling with gcc, flexible array members are not allowed to appear + * in an otherwise empty struct, so we use the GCC zero-length array + * extension that works with both clang/gcc/g++. + */ +#if defined(__cplusplus) && defined(__clang__) +#define FLEXIBLE_ARRAY_MEMBER_SIZE +#else +#define FLEXIBLE_ARRAY_MEMBER_SIZE 0 +#endif + /* * Current version of this protocol * @@ -80,28 +94,28 @@ extern "C" { * determined in other ways. Remove this once the kernel code no longer * depends on it. */ -#define EC_PROTO_VERSION 0x00000002 +#define EC_PROTO_VERSION 0x00000002 /* Command version mask */ #define EC_VER_MASK(version) BIT(version) /* I/O addresses for ACPI commands */ -#define EC_LPC_ADDR_ACPI_DATA 0x62 -#define EC_LPC_ADDR_ACPI_CMD 0x66 +#define EC_LPC_ADDR_ACPI_DATA 0x62 +#define EC_LPC_ADDR_ACPI_CMD 0x66 /* I/O addresses for host command */ -#define EC_LPC_ADDR_HOST_DATA 0x200 -#define EC_LPC_ADDR_HOST_CMD 0x204 +#define EC_LPC_ADDR_HOST_DATA 0x200 +#define EC_LPC_ADDR_HOST_CMD 0x204 /* I/O addresses for host command args and params */ /* Protocol version 2 */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ -#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is - * EC_PROTO2_MAX_PARAM_SIZE - */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +/* For version 2 params; size is EC_PROTO2_MAX_PARAM_SIZE */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 + /* Protocol version 3 */ -#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ -#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ /* * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff @@ -110,66 +124,79 @@ extern "C" { * Other BIOSes report only the I/O port region spanned by the Microchip * MEC series EC; an attempt to address a larger region may fail. */ -#define EC_HOST_CMD_REGION0 0x800 -#define EC_HOST_CMD_REGION1 0x880 -#define EC_HOST_CMD_REGION_SIZE 0x80 +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 +#define EC_HOST_CMD_REGION_SIZE 0x80 #define EC_HOST_CMD_MEC_REGION_SIZE 0x8 /* EC command register bit functions */ -#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ - -#define EC_LPC_ADDR_MEMMAP 0x900 -#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ -#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ + +#define EC_LPC_ADDR_MEMMAP 0x900 +#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ +#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ /* The offset address of each type of data in mapped memory. */ -#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ -#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ -#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ -#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ -#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ -#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ -#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ +#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ +#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ +#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ +#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ -#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ -#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ +#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ +#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ /* Unused 0x28 - 0x2f */ -#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ +#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ /* Unused 0x31 - 0x33 */ -#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ +#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ /* Battery values are all 32 bits, unless otherwise noted. */ -#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ -#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ -#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ -#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ -#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ -#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ +#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ +#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ +#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ +#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ +#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ +#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ /* Unused 0x4f */ -#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ -#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ -#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ -#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ +#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ +#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ +#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ /* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ -#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ -#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ -#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ -#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ -#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ +#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ +#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ +#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ +#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ /* Unused 0x84 - 0x8f */ -#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ +#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ /* Unused 0x91 */ -#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ /* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ /* 0x94 - 0x99: 1st Accelerometer */ /* 0x9a - 0x9f: 2nd Accelerometer */ -#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ -/* Unused 0xa6 - 0xdf */ + +#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ +#define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */ + +/* + * Bit fields for EC_MEMMAP_GPU + * 0:2: D-Notify level (0:D1, ... 4:D5) + * 3: Over temperature + */ +#define EC_MEMMAP_GPU_D_NOTIFY_MASK GENMASK(2, 0) +#define EC_MEMMAP_GPU_OVERT_BIT BIT(3) + +/* Power Participant related components */ +#define EC_MEMMAP_PWR_SRC 0xa7 /* Power source (8-bit) */ +/* Unused 0xa8 - 0xdf */ /* * ACPI is unable to access memory mapped data at or above this offset due to @@ -179,82 +206,83 @@ extern "C" { #define EC_MEMMAP_NO_ACPI 0xe0 /* Define the format of the accelerometer mapped memory status byte. */ -#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f -#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) -#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) +#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ -#define EC_TEMP_SENSOR_ENTRIES 16 +#define EC_TEMP_SENSOR_ENTRIES 16 /* * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. * * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. */ -#define EC_TEMP_SENSOR_B_ENTRIES 8 +#define EC_TEMP_SENSOR_B_ENTRIES 8 /* Max temp sensor entries for host commands */ -#define EC_MAX_TEMP_SENSOR_ENTRIES (EC_TEMP_SENSOR_ENTRIES + \ - EC_TEMP_SENSOR_B_ENTRIES) +#define EC_MAX_TEMP_SENSOR_ENTRIES \ + (EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES) /* Special values for mapped temperature sensors */ -#define EC_TEMP_SENSOR_NOT_PRESENT 0xff -#define EC_TEMP_SENSOR_ERROR 0xfe -#define EC_TEMP_SENSOR_NOT_POWERED 0xfd +#define EC_TEMP_SENSOR_NOT_PRESENT 0xff +#define EC_TEMP_SENSOR_ERROR 0xfe +#define EC_TEMP_SENSOR_NOT_POWERED 0xfd #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc /* * The offset of temperature value stored in mapped memory. This allows * reporting a temperature range of 200K to 454K = -73C to 181C. */ -#define EC_TEMP_SENSOR_OFFSET 200 +#define EC_TEMP_SENSOR_OFFSET 200 /* * Number of ALS readings at EC_MEMMAP_ALS */ -#define EC_ALS_ENTRIES 2 +#define EC_ALS_ENTRIES 2 /* * The default value a temperature sensor will return when it is present but * has not been read this boot. This is a reasonable number to avoid * triggering alarms on the host. */ -#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) +#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) -#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ -#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ -#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ +#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ +#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ +#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ /* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ -#define EC_BATT_FLAG_AC_PRESENT 0x01 +#define EC_BATT_FLAG_AC_PRESENT 0x01 #define EC_BATT_FLAG_BATT_PRESENT 0x02 -#define EC_BATT_FLAG_DISCHARGING 0x04 -#define EC_BATT_FLAG_CHARGING 0x08 +#define EC_BATT_FLAG_DISCHARGING 0x04 +#define EC_BATT_FLAG_CHARGING 0x08 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10 /* Set if some of the static/dynamic data is invalid (or outdated). */ #define EC_BATT_FLAG_INVALID_DATA 0x20 +#define EC_BATT_FLAG_CUT_OFF 0x40 /* Switch flags at EC_MEMMAP_SWITCHES */ -#define EC_SWITCH_LID_OPEN 0x01 -#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 +#define EC_SWITCH_LID_OPEN 0x01 +#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 /* Was recovery requested via keyboard; now unused. */ -#define EC_SWITCH_IGNORE1 0x08 +#define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ -#define EC_SWITCH_DEDICATED_RECOVERY 0x10 +#define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ -#define EC_SWITCH_IGNORE0 0x20 +#define EC_SWITCH_IGNORE0 0x20 /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ -#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 /* Host command interface supports version 3 protocol */ -#define EC_HOST_CMD_FLAG_VERSION_3 0x02 +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 /* Wireless switch flags */ -#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ -#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ -#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ -#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ -#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ +#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ +#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ +#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ +#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ /*****************************************************************************/ /* @@ -322,19 +350,19 @@ extern "C" { /* Valid addresses in ACPI memory space, for read/write commands */ /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ -#define EC_ACPI_MEM_VERSION 0x00 +#define EC_ACPI_MEM_VERSION 0x00 /* * Test location; writing value here updates test compliment byte to (0xff - * value). */ -#define EC_ACPI_MEM_TEST 0x01 +#define EC_ACPI_MEM_TEST 0x01 /* Test compliment; writes here are ignored. */ -#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 +#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 /* Keyboard backlight brightness percent (0 - 100) */ #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 /* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ -#define EC_ACPI_MEM_FAN_DUTY 0x04 +#define EC_ACPI_MEM_FAN_DUTY 0x04 /* * DPTF temp thresholds. Any of the EC's temp sensors can have up to two @@ -351,9 +379,9 @@ extern "C" { * have tripped". Setting or enabling the thresholds for a sensor will clear * the unread event count for that sensor. */ -#define EC_ACPI_MEM_TEMP_ID 0x05 -#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 -#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 /* * Here are the bits for the COMMIT register: * bit 0 selects the threshold index for the chosen sensor (0/1) @@ -378,12 +406,12 @@ extern "C" { */ /* DPTF battery charging current limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 /* Charging limit is specified in 64 mA steps */ -#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 /* Value to disable DPTF battery charging limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff /* * Report device orientation @@ -396,10 +424,10 @@ extern "C" { * 0 Tablet Mode Device Indicator (TBMD) */ #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 -#define EC_ACPI_MEM_TBMD_SHIFT 0 -#define EC_ACPI_MEM_TBMD_MASK 0x1 -#define EC_ACPI_MEM_DDPN_SHIFT 1 -#define EC_ACPI_MEM_DDPN_MASK 0x7 +#define EC_ACPI_MEM_TBMD_SHIFT 0 +#define EC_ACPI_MEM_TBMD_MASK 0x1 +#define EC_ACPI_MEM_DDPN_SHIFT 1 +#define EC_ACPI_MEM_DDPN_MASK 0x7 /* * Report device features. Uses the same format as the host command, except: @@ -422,7 +450,7 @@ extern "C" { #define EC_ACPI_MEM_DEVICE_FEATURES6 0x10 #define EC_ACPI_MEM_DEVICE_FEATURES7 0x11 -#define EC_ACPI_MEM_BATTERY_INDEX 0x12 +#define EC_ACPI_MEM_BATTERY_INDEX 0x12 /* * USB Port Power. Each bit indicates whether the corresponding USB ports' power @@ -461,40 +489,38 @@ extern "C" { #define EC_ACPI_MEM_USB_RETIMER_FW_UPDATE 0x14 #define USB_RETIMER_FW_UPDATE_OP_SHIFT 4 -#define USB_RETIMER_FW_UPDATE_ERR 0xfe +#define USB_RETIMER_FW_UPDATE_ERR 0xfe #define USB_RETIMER_FW_UPDATE_INVALID_MUX 0xff /* Mask to clear unused MUX bits in retimer firmware update */ -#define USB_RETIMER_FW_UPDATE_MUX_MASK (USB_PD_MUX_USB_ENABLED | \ - USB_PD_MUX_DP_ENABLED | \ - USB_PD_MUX_SAFE_MODE | \ - USB_PD_MUX_TBT_COMPAT_ENABLED | \ - USB_PD_MUX_USB4_ENABLED) +#define USB_RETIMER_FW_UPDATE_MUX_MASK \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) /* Retimer firmware update operations */ #define USB_RETIMER_FW_UPDATE_QUERY_PORT 0 /* Which ports has retimer */ #define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */ -#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */ -#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */ -#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */ -#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */ -#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ +#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */ +#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */ +#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */ +#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */ +#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ #define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */ -#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x) & 0x0f) +#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x)&0x0f) #define EC_ACPI_MEM_USB_RETIMER_OP(x) \ - (((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) + (((x)&0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) /* * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. */ -#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 -#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 +#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 +#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 /* Current version of ACPI memory address space */ #define EC_ACPI_MEM_VERSION_CURRENT 2 - /* * This header file is used in coreboot both in C and ACPI code. The ACPI code * is pre-processed to handle constants but the ASL compiler is unable to @@ -514,7 +540,7 @@ extern "C" { #ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) #endif -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ /* * Attributes for EC request and response packets. Just defining __packed @@ -581,7 +607,7 @@ extern "C" { #define __ec_todo_packed __packed #define __ec_todo_unpacked -#else /* !CONFIG_HOSTCMD_ALIGNED */ +#else /* !CONFIG_HOSTCMD_ALIGNED */ /* * Packed structures make no assumption about alignment, so they do inefficient @@ -596,25 +622,25 @@ extern "C" { #define __ec_todo_packed __packed #define __ec_todo_unpacked -#endif /* !CONFIG_HOSTCMD_ALIGNED */ +#endif /* !CONFIG_HOSTCMD_ALIGNED */ /* LPC command status byte masks */ /* EC has written a byte in the data register and host hasn't read it yet */ -#define EC_LPC_STATUS_TO_HOST 0x01 +#define EC_LPC_STATUS_TO_HOST 0x01 /* Host has written a command/data byte and the EC hasn't read it yet */ -#define EC_LPC_STATUS_FROM_HOST 0x02 +#define EC_LPC_STATUS_FROM_HOST 0x02 /* EC is processing a command */ -#define EC_LPC_STATUS_PROCESSING 0x04 +#define EC_LPC_STATUS_PROCESSING 0x04 /* Last write to EC was a command, not data */ -#define EC_LPC_STATUS_LAST_CMD 0x08 +#define EC_LPC_STATUS_LAST_CMD 0x08 /* EC is in burst mode */ -#define EC_LPC_STATUS_BURST_MODE 0x10 +#define EC_LPC_STATUS_BURST_MODE 0x10 /* SCI event is pending (requesting SCI query) */ #define EC_LPC_STATUS_SCI_PENDING 0x20 /* SMI event is pending (requesting SMI query) */ #define EC_LPC_STATUS_SMI_PENDING 0x40 /* (reserved) */ -#define EC_LPC_STATUS_RESERVED 0x80 +#define EC_LPC_STATUS_RESERVED 0x80 /* * EC is busy. This covers both the EC processing a command, and the host has @@ -635,21 +661,21 @@ enum ec_status { EC_RES_INVALID_RESPONSE = 5, EC_RES_INVALID_VERSION = 6, EC_RES_INVALID_CHECKSUM = 7, - EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ - EC_RES_UNAVAILABLE = 9, /* No response available */ - EC_RES_TIMEOUT = 10, /* We got a timeout */ - EC_RES_OVERFLOW = 11, /* Table / data overflow */ - EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ - EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ - EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ - EC_RES_BUS_ERROR = 15, /* Communications bus error */ - EC_RES_BUSY = 16, /* Up but too busy. Should retry */ - EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ - EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ - EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ - EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ - - EC_RES_MAX = UINT16_MAX /**< Force enum to be 16 bits */ + EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ + EC_RES_UNAVAILABLE = 9, /* No response available */ + EC_RES_TIMEOUT = 10, /* We got a timeout */ + EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ + EC_RES_BUS_ERROR = 15, /* Communications bus error */ + EC_RES_BUSY = 16, /* Up but too busy. Should retry */ + EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ + EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ + EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ + EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ + + EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */ } __packed; BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); @@ -673,7 +699,8 @@ enum host_event_code { /* Event generated by a device attached to the EC */ EC_HOST_EVENT_DEVICE = 10, EC_HOST_EVENT_THERMAL = 11, - EC_HOST_EVENT_USB_CHARGER = 12, + /* GPU related event. Formerly named EC_HOST_EVENT_USB_CHARGER. */ + EC_HOST_EVENT_GPU = 12, EC_HOST_EVENT_KEY_PRESSED = 13, /* * EC has finished initializing the host interface. The host can check @@ -741,10 +768,50 @@ enum host_event_code { * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is * not initialized on the EC, or improperly configured on the host. */ - EC_HOST_EVENT_INVALID = 32 + EC_HOST_EVENT_INVALID = 32, }; /* Host event mask */ -#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) +#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code)-1) + +/* clang-format off */ +#define HOST_EVENT_TEXT \ + { \ + [EC_HOST_EVENT_NONE] = "NONE", \ + [EC_HOST_EVENT_LID_CLOSED] = "LID_CLOSED", \ + [EC_HOST_EVENT_LID_OPEN] = "LID_OPEN", \ + [EC_HOST_EVENT_POWER_BUTTON] = "POWER_BUTTON", \ + [EC_HOST_EVENT_AC_CONNECTED] = "AC_CONNECTED", \ + [EC_HOST_EVENT_AC_DISCONNECTED] = "AC_DISCONNECTED", \ + [EC_HOST_EVENT_BATTERY_LOW] = "BATTERY_LOW", \ + [EC_HOST_EVENT_BATTERY_CRITICAL] = "BATTERY_CRITICAL", \ + [EC_HOST_EVENT_BATTERY] = "BATTERY", \ + [EC_HOST_EVENT_THERMAL_THRESHOLD] = "THERMAL_THRESHOLD", \ + [EC_HOST_EVENT_DEVICE] = "DEVICE", \ + [EC_HOST_EVENT_THERMAL] = "THERMAL", \ + [EC_HOST_EVENT_GPU] = "GPU", \ + [EC_HOST_EVENT_KEY_PRESSED] = "KEY_PRESSED", \ + [EC_HOST_EVENT_INTERFACE_READY] = "INTERFACE_READY", \ + [EC_HOST_EVENT_KEYBOARD_RECOVERY] = "KEYBOARD_RECOVERY", \ + [EC_HOST_EVENT_THERMAL_SHUTDOWN] = "THERMAL_SHUTDOWN", \ + [EC_HOST_EVENT_BATTERY_SHUTDOWN] = "BATTERY_SHUTDOWN", \ + [EC_HOST_EVENT_THROTTLE_START] = "THROTTLE_START", \ + [EC_HOST_EVENT_THROTTLE_STOP] = "THROTTLE_STOP", \ + [EC_HOST_EVENT_HANG_DETECT] = "HANG_DETECT", \ + [EC_HOST_EVENT_HANG_REBOOT] = "HANG_REBOOT", \ + [EC_HOST_EVENT_PD_MCU] = "PD_MCU", \ + [EC_HOST_EVENT_BATTERY_STATUS] = "BATTERY_STATUS", \ + [EC_HOST_EVENT_PANIC] = "PANIC", \ + [EC_HOST_EVENT_KEYBOARD_FASTBOOT] = "KEYBOARD_FASTBOOT", \ + [EC_HOST_EVENT_RTC] = "RTC", \ + [EC_HOST_EVENT_MKBP] = "MKBP", \ + [EC_HOST_EVENT_USB_MUX] = "USB_MUX", \ + [EC_HOST_EVENT_MODE_CHANGE] = "MODE_CHANGE", \ + [EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT] = \ + "KEYBOARD_RECOVERY_HW_REINIT", \ + [EC_HOST_EVENT_WOV] = "WOV", \ + [EC_HOST_EVENT_INVALID] = "INVALID", \ + } +/* clang-format on */ /** * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS @@ -779,7 +846,7 @@ struct ec_lpc_host_args { * response. Command version is 0 and response data from EC is at * EC_LPC_ADDR_OLD_PARAM with unknown length. */ -#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 +#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 /*****************************************************************************/ /* @@ -821,12 +888,12 @@ struct ec_lpc_host_args { * request, the AP will clock in bytes until it sees the framing byte, then * clock in the response packet. */ -#define EC_SPI_FRAME_START 0xec +#define EC_SPI_FRAME_START 0xec /* * Padding bytes which are clocked out after the end of a response packet. */ -#define EC_SPI_PAST_END 0xed +#define EC_SPI_PAST_END 0xed /* * EC is ready to receive, and has ignored the byte sent by the AP. EC expects @@ -837,36 +904,36 @@ struct ec_lpc_host_args { * CS goes low. This macro has the Most Significant Bit set to zero, * so SDO will not be driven high when CS goes low. */ -#define EC_SPI_RX_READY 0x78 +#define EC_SPI_RX_READY 0x78 /* * EC has started receiving the request from the AP, but hasn't started * processing it yet. */ -#define EC_SPI_RECEIVING 0xf9 +#define EC_SPI_RECEIVING 0xf9 /* EC has received the entire request from the AP and is processing it. */ -#define EC_SPI_PROCESSING 0xfa +#define EC_SPI_PROCESSING 0xfa /* * EC received bad data from the AP, such as a packet header with an invalid * length. EC will ignore all data until chip select deasserts. */ -#define EC_SPI_RX_BAD_DATA 0xfb +#define EC_SPI_RX_BAD_DATA 0xfb /* * EC received data from the AP before it was ready. That is, the AP asserted * chip select and started clocking data before the EC was ready to receive it. * EC will ignore all data until chip select deasserts. */ -#define EC_SPI_NOT_READY 0xfc +#define EC_SPI_NOT_READY 0xfc /* * EC was ready to receive a request from the AP. EC has treated the byte sent * by the AP as part of a request packet, or (for old-style ECs) is processing * a fully received packet but is not ready to respond yet. */ -#define EC_SPI_OLD_READY 0xfd +#define EC_SPI_OLD_READY 0xfd /*****************************************************************************/ @@ -888,22 +955,22 @@ struct ec_lpc_host_args { */ #define EC_PROTO2_REQUEST_HEADER_BYTES 3 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1 -#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ - EC_PROTO2_REQUEST_TRAILER_BYTES) +#define EC_PROTO2_REQUEST_OVERHEAD \ + (EC_PROTO2_REQUEST_HEADER_BYTES + EC_PROTO2_REQUEST_TRAILER_BYTES) #define EC_PROTO2_RESPONSE_HEADER_BYTES 2 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 -#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES) +#define EC_PROTO2_RESPONSE_OVERHEAD \ + (EC_PROTO2_RESPONSE_HEADER_BYTES + EC_PROTO2_RESPONSE_TRAILER_BYTES) /* Parameter length was limited by the LPC interface */ #define EC_PROTO2_MAX_PARAM_SIZE 0xfc /* Maximum request and response packet sizes for protocol version 2 */ -#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) -#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_REQUEST_SIZE \ + (EC_PROTO2_REQUEST_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE \ + (EC_PROTO2_RESPONSE_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) /*****************************************************************************/ @@ -1075,15 +1142,15 @@ struct ec_host_response4 { } __ec_align4; /* Fields in fields0 byte */ -#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f -#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 -#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 -#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 -#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 +#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f +#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 +#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 +#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 +#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 /* Fields in fields1 byte */ -#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ -#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 +#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ +#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 /*****************************************************************************/ /* @@ -1157,7 +1224,7 @@ enum ec_image { EC_IMAGE_RW, EC_IMAGE_RW_A = EC_IMAGE_RW, EC_IMAGE_RO_B, - EC_IMAGE_RW_B + EC_IMAGE_RW_B, }; /** @@ -1170,7 +1237,7 @@ enum ec_image { struct ec_response_get_version { char version_string_ro[32]; char version_string_rw[32]; - char reserved[32]; /* Changed to cros_fwid_ro in version 1 */ + char reserved[32]; /* Changed to cros_fwid_ro in version 1 */ uint32_t current_image; } __ec_align4; @@ -1190,9 +1257,9 @@ struct ec_response_get_version { struct ec_response_get_version_v1 { char version_string_ro[32]; char version_string_rw[32]; - char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */ + char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */ uint32_t current_image; - char cros_fwid_rw[32]; /* Added in version 1 */ + char cros_fwid_rw[32]; /* Added in version 1 */ } __ec_align4; /* Read test */ @@ -1305,11 +1372,11 @@ struct ec_response_get_cmd_versions { * lpc must read the status from the command register. Attempting this on * lpc will overwrite the args/parameter space and corrupt its data. */ -#define EC_CMD_GET_COMMS_STATUS 0x0009 +#define EC_CMD_GET_COMMS_STATUS 0x0009 /* Avoid using ec_status which is for return values */ enum ec_comms_status { - EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ + EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ }; /** @@ -1318,11 +1385,11 @@ enum ec_comms_status { * @flags: Mask of enum ec_comms_status. */ struct ec_response_get_comms_status { - uint32_t flags; /* Mask of enum ec_comms_status */ + uint32_t flags; /* Mask of enum ec_comms_status */ } __ec_align4; /* Fake a variety of responses, purely for testing purposes. */ -#define EC_CMD_TEST_PROTOCOL 0x000A +#define EC_CMD_TEST_PROTOCOL 0x000A /* Tell the EC what to send back to us. */ struct ec_params_test_protocol { @@ -1337,7 +1404,7 @@ struct ec_response_test_protocol { } __ec_align4; /* Get protocol information */ -#define EC_CMD_GET_PROTOCOL_INFO 0x000B +#define EC_CMD_GET_PROTOCOL_INFO 0x000B /* Flags for ec_response_get_protocol_info.flags */ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ @@ -1359,12 +1426,11 @@ struct ec_response_get_protocol_info { uint32_t flags; } __ec_align4; - /*****************************************************************************/ /* Get/Set miscellaneous values */ /* The upper byte of .flags tells what to do (nothing means "get") */ -#define EC_GSV_SET 0x80000000 +#define EC_GSV_SET 0x80000000 /* * The lower three bytes of .flags identifies the parameter, if that has @@ -1383,11 +1449,11 @@ struct ec_response_get_set_value { } __ec_align4; /* More than one command can use these structs to get/set parameters. */ -#define EC_CMD_GSV_PAUSE_IN_S5 0x000C +#define EC_CMD_GSV_PAUSE_IN_S5 0x000C /*****************************************************************************/ /* List the features supported by the firmware */ -#define EC_CMD_GET_FEATURES 0x000D +#define EC_CMD_GET_FEATURES 0x000D /* Supported features */ enum ec_feature_code { @@ -1518,6 +1584,10 @@ enum ec_feature_code { * The EC supports entering and residing in S4. */ EC_FEATURE_S4_RESIDENCY = 44, + /* + * The EC supports the AP directing mux sets for the board. + */ + EC_FEATURE_TYPEC_AP_MUX_SET = 45, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -1688,8 +1758,15 @@ struct ec_params_flash_read { struct ec_params_flash_write { uint32_t offset; uint32_t size; - /* Followed by data to write */ + /* Followed by data to write. This union allows accessing an + * underlying buffer as uint32s or uint8s for convenience. + */ + union { + uint32_t words32[FLEXIBLE_ARRAY_MEMBER_SIZE]; + uint8_t bytes[FLEXIBLE_ARRAY_MEMBER_SIZE]; + } data; } __ec_align4; +BUILD_ASSERT(member_size(struct ec_params_flash_write, data) == 0); /* Erase flash */ #define EC_CMD_FLASH_ERASE 0x0013 @@ -1722,9 +1799,9 @@ struct ec_params_flash_erase { * permitted while erasing. (For instance, STM32F4). */ enum ec_flash_erase_cmd { - FLASH_ERASE_SECTOR, /* Erase and wait for result */ - FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ - FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ + FLASH_ERASE_SECTOR, /* Erase and wait for result */ + FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ + FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ }; /** @@ -1735,8 +1812,8 @@ enum ec_flash_erase_cmd { * @params: Same as v0 parameters. */ struct ec_params_flash_erase_v1 { - uint8_t cmd; - uint8_t reserved; + uint8_t cmd; + uint8_t reserved; uint16_t flag; struct ec_params_flash_erase params; } __ec_align4; @@ -1752,22 +1829,22 @@ struct ec_params_flash_erase_v1 { * If mask=0, simply returns the current flags state. */ #define EC_CMD_FLASH_PROTECT 0x0015 -#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ +#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ /* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW BIT(1) +#define EC_FLASH_PROTECT_RO_NOW BIT(1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW BIT(2) +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by @@ -1775,18 +1852,17 @@ struct ec_params_flash_erase_v1 { */ #define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) /* Entire flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) /* RW flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) +#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) /* RW flash code protected now. */ -#define EC_FLASH_PROTECT_RW_NOW BIT(8) +#define EC_FLASH_PROTECT_RW_NOW BIT(8) /* Rollback information flash region protected when the EC boots */ -#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) /* Rollback information flash region protected now */ -#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) +#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) /* Error - Unknown error */ -#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11) - +#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11) /** * struct ec_params_flash_protect - Parameters for the flash protect command. @@ -1865,34 +1941,6 @@ struct ec_response_flash_region_info { uint32_t size; } __ec_align4; -/* - * Read/write VbNvContext - * - * Deprecated as of February 2021. No current devices use VBNV in EC - * BBRAM anymore, so this is guaranteed to fail. - * - * TODO(b/178689388): remove from this header once no external - * dependencies reference these constants. - */ -#define EC_CMD_VBNV_CONTEXT 0x0017 -#define EC_VER_VBNV_CONTEXT 1 -#define EC_VBNV_BLOCK_SIZE 16 - -enum ec_vbnvcontext_op { - EC_VBNV_CONTEXT_OP_READ, - EC_VBNV_CONTEXT_OP_WRITE, -}; - -struct ec_params_vbnvcontext { - uint32_t op; - uint8_t block[EC_VBNV_BLOCK_SIZE]; -} __ec_align4; - -struct ec_response_vbnvcontext { - uint8_t block[EC_VBNV_BLOCK_SIZE]; -} __ec_align4; - - /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 @@ -1910,7 +1958,6 @@ struct ec_response_flash_spi_info { uint8_t sr1, sr2; } __ec_align1; - /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 @@ -1922,24 +1969,26 @@ struct ec_params_flash_select { uint8_t select; } __ec_align4; - /** * Request random numbers to be generated and returned. * Can be used to test the random number generator is truly random. * See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and * https://webhome.phy.duke.edu/~rgb/General/dieharder.php. */ -#define EC_CMD_RAND_NUM 0x001A +#define EC_CMD_RAND_NUM 0x001A #define EC_VER_RAND_NUM 0 struct ec_params_rand_num { - uint16_t num_rand_bytes; /**< num random bytes to generate */ + uint16_t num_rand_bytes; /**< num random bytes to generate */ } __ec_align4; struct ec_response_rand_num { - uint8_t rand[0]; /**< generated random numbers */ -} __ec_align4; - + /** + * generated random numbers in the range of 1 to EC_MAX_INSIZE. The true + * size of rand is determined by ec_params_rand_num's num_rand_bytes. + */ + uint8_t rand[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0); /** @@ -2005,9 +2054,9 @@ enum sysinfo_flags { }; struct ec_response_sysinfo { - uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ - uint32_t current_image; /**< enum ec_current_image */ - uint32_t flags; /**< enum sysinfo_flags */ + uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ + uint32_t current_image; /**< enum ec_current_image */ + uint32_t flags; /**< enum sysinfo_flags */ } __ec_align4; /*****************************************************************************/ @@ -2080,20 +2129,20 @@ enum ec_pwm_type { }; struct ec_params_pwm_set_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ } __ec_align4; #define EC_CMD_PWM_GET_DUTY 0x0026 struct ec_params_pwm_get_duty { - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ } __ec_align1; struct ec_response_pwm_get_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ } __ec_align2; /*****************************************************************************/ @@ -2120,8 +2169,8 @@ struct lightbar_params_v0 { int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -2129,24 +2178,24 @@ struct lightbar_params_v0 { /* Oscillation */ uint8_t new_s0; - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ + struct rgb_s color[8]; /* 0-3 are Google colors */ } __ec_todo_packed; struct lightbar_params_v1 { @@ -2154,8 +2203,8 @@ struct lightbar_params_v1 { int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -2175,27 +2224,27 @@ struct lightbar_params_v1 { uint8_t tap_idx[3]; /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ + struct rgb_s color[8]; /* 0-3 are Google colors */ } __ec_todo_packed; /* Lightbar command params v2 @@ -2212,8 +2261,8 @@ struct lightbar_params_v2_timing { int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -2237,16 +2286,16 @@ struct lightbar_params_v2_tap { struct lightbar_params_v2_oscillation { /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ } __ec_todo_packed; struct lightbar_params_v2_brightness { /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ } __ec_todo_packed; struct lightbar_params_v2_thresholds { @@ -2256,14 +2305,14 @@ struct lightbar_params_v2_thresholds { struct lightbar_params_v2_colors { /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ + struct rgb_s color[8]; /* 0-3 are Google colors */ } __ec_todo_packed; /* Lightbar program. */ @@ -2274,7 +2323,7 @@ struct lightbar_program { } __ec_todo_unpacked; struct ec_params_lightbar { - uint8_t cmd; /* Command (see enum lightbar_command) */ + uint8_t cmd; /* Command (see enum lightbar_command) */ union { /* * The following commands have no args: @@ -2339,7 +2388,6 @@ struct ec_response_lightbar { struct lightbar_params_v0 get_params_v0; struct lightbar_params_v1 get_params_v1; - struct lightbar_params_v2_timing get_params_v2_timing; struct lightbar_params_v2_tap get_params_v2_tap; struct lightbar_params_v2_oscillation get_params_v2_osc; @@ -2404,7 +2452,7 @@ enum lightbar_command { LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, - LIGHTBAR_NUM_CMDS + LIGHTBAR_NUM_CMDS, }; /*****************************************************************************/ @@ -2431,12 +2479,12 @@ enum ec_led_id { /* LED to indicate sysrq debug mode. */ EC_LED_ID_SYSRQ_DEBUG_LED, - EC_LED_ID_COUNT + EC_LED_ID_COUNT, }; /* LED control flags */ #define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ enum ec_led_colors { EC_LED_COLOR_RED = 0, @@ -2446,12 +2494,12 @@ enum ec_led_colors { EC_LED_COLOR_WHITE, EC_LED_COLOR_AMBER, - EC_LED_COLOR_COUNT + EC_LED_COLOR_COUNT, }; struct ec_params_led_control { - uint8_t led_id; /* Which LED to control */ - uint8_t flags; /* Control flags */ + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ uint8_t brightness[EC_LED_COLOR_COUNT]; } __ec_align1; @@ -2479,30 +2527,30 @@ struct ec_response_led_control { #define EC_CMD_VBOOT_HASH 0x002A struct ec_params_vboot_hash { - uint8_t cmd; /* enum ec_vboot_hash_cmd */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t nonce_size; /* Nonce size; may be 0 */ - uint8_t reserved0; /* Reserved; set 0 */ - uint32_t offset; /* Offset in flash to hash */ - uint32_t size; /* Number of bytes to hash */ - uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ + uint8_t cmd; /* enum ec_vboot_hash_cmd */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t nonce_size; /* Nonce size; may be 0 */ + uint8_t reserved0; /* Reserved; set 0 */ + uint32_t offset; /* Offset in flash to hash */ + uint32_t size; /* Number of bytes to hash */ + uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ } __ec_align4; struct ec_response_vboot_hash { - uint8_t status; /* enum ec_vboot_hash_status */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t digest_size; /* Size of hash digest in bytes */ - uint8_t reserved0; /* Ignore; will be 0 */ - uint32_t offset; /* Offset in flash which was hashed */ - uint32_t size; /* Number of bytes hashed */ + uint8_t status; /* enum ec_vboot_hash_status */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t digest_size; /* Size of hash digest in bytes */ + uint8_t reserved0; /* Ignore; will be 0 */ + uint32_t offset; /* Offset in flash which was hashed */ + uint32_t size; /* Number of bytes hashed */ uint8_t hash_digest[64]; /* Hash digest data */ } __ec_align4; enum ec_vboot_hash_cmd { - EC_VBOOT_HASH_GET = 0, /* Get current hash status */ - EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ - EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ - EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ + EC_VBOOT_HASH_GET = 0, /* Get current hash status */ + EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ + EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ + EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ }; enum ec_vboot_hash_type { @@ -2520,9 +2568,9 @@ enum ec_vboot_hash_status { * If one of these is specified, the EC will automatically update offset and * size to the correct values for the specified image (RO or RW). */ -#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe -#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd -#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc +#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe +#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd +#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc /* * 'RW' is vague if there are multiple RW images; we mean the active one, @@ -2671,7 +2719,7 @@ enum motionsense_command { MOTIONSENSE_CMD_GET_ACTIVITY = 20, /* Number of motionsense sub-commands. */ - MOTIONSENSE_NUM_CMDS + MOTIONSENSE_NUM_CMDS, }; /* List of motion sensor types. */ @@ -2753,16 +2801,16 @@ struct ec_response_motion_sensor_data { uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; /* for sensors using unsigned data */ - uint16_t udata[3]; + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { struct ec_response_activity_data activity_data; - int16_t add_info[2]; + int16_t add_info[2]; }; }; } __ec_todo_packed; @@ -2806,7 +2854,7 @@ enum motionsensor_activity { struct ec_motion_sense_activity { uint8_t sensor_num; uint8_t activity; /* one of enum motionsensor_activity */ - uint8_t enable; /* 1: enable, 0: disable */ + uint8_t enable; /* 1: enable, 0: disable */ uint8_t reserved; uint16_t parameters[3]; /* activity dependent parameters */ } __ec_todo_unpacked; @@ -2974,7 +3022,6 @@ struct ec_params_motion_sense { uint16_t scale[3]; } sensor_scale; - /* Used for MOTIONSENSE_CMD_FIFO_INFO */ /* (no params) */ @@ -3058,7 +3105,7 @@ struct ec_params_motion_sense { */ struct __ec_todo_unpacked { uint8_t sensor_num; - uint8_t activity; /* enum motionsensor_activity */ + uint8_t activity; /* enum motionsensor_activity */ } get_activity; }; } __ec_todo_packed; @@ -3159,19 +3206,19 @@ struct ec_response_motion_sense { /* Current value of the parameter queried. */ int32_t ret; } ec_rate, sensor_odr, sensor_range, kb_wake_angle, - fifo_int_enable, spoof; + fifo_int_enable, spoof; /* * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, * PERFORM_CALIB. */ - struct __ec_todo_unpacked { + struct __ec_todo_unpacked { int16_t temp; int16_t offset[3]; } sensor_offset, perform_calib; /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ - struct __ec_todo_unpacked { + struct __ec_todo_unpacked { int16_t temp; uint16_t scale[3]; } sensor_scale; @@ -3262,20 +3309,20 @@ enum usb_charge_mode { /* Set USB port to CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE. */ USB_CHARGE_MODE_DEFAULT, - USB_CHARGE_MODE_COUNT + USB_CHARGE_MODE_COUNT, }; enum usb_suspend_charge { /* Enable charging in suspend */ USB_ALLOW_SUSPEND_CHARGE, /* Disable charging in suspend */ - USB_DISALLOW_SUSPEND_CHARGE + USB_DISALLOW_SUSPEND_CHARGE, }; struct ec_params_usb_charge_set_mode { uint8_t usb_port_id; - uint8_t mode:7; /* enum usb_charge_mode */ - uint8_t inhibit_charge:1; /* enum usb_suspend_charge */ + uint8_t mode : 7; /* enum usb_charge_mode */ + uint8_t inhibit_charge : 1; /* enum usb_suspend_charge */ } __ec_align1; /*****************************************************************************/ @@ -3302,16 +3349,16 @@ struct ec_response_pstore_info { #define EC_CMD_PSTORE_READ 0x0041 struct ec_params_pstore_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ } __ec_align4; /* Write persistent storage */ #define EC_CMD_PSTORE_WRITE 0x0042 struct ec_params_pstore_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ + uint32_t offset; /* Byte offset to write */ + uint32_t size; /* Size to write in bytes */ uint8_t data[EC_PSTORE_SIZE_MAX]; } __ec_align4; @@ -3454,14 +3501,13 @@ struct ec_response_thermal_get_threshold { uint16_t value; } __ec_align2; - /* The version 1 structs are visible. */ enum ec_temp_thresholds { EC_TEMP_THRESH_WARN = 0, EC_TEMP_THRESH_HIGH, EC_TEMP_THRESH_HALT, - EC_TEMP_THRESH_COUNT + EC_TEMP_THRESH_COUNT, }; /* @@ -3489,8 +3535,8 @@ enum ec_temp_thresholds { struct ec_thermal_config { uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ - uint32_t temp_fan_off; /* no active cooling needed */ - uint32_t temp_fan_max; /* max active cooling needed */ + uint32_t temp_fan_off; /* no active cooling needed */ + uint32_t temp_fan_max; /* max active cooling needed */ } __ec_align4; /* Version 1 - get config for one sensor. */ @@ -3570,7 +3616,6 @@ struct ec_params_tmp006_set_calibration_v1 { float val[0]; } __ec_align4; - /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 @@ -3579,8 +3624,8 @@ struct ec_params_tmp006_get_raw { } __ec_align1; struct ec_response_tmp006_get_raw { - int32_t t; /* In 1/100 K */ - int32_t v; /* In nV */ + int32_t t; /* In 1/100 K */ + int32_t v; /* In nV */ } __ec_align4; /*****************************************************************************/ @@ -3680,17 +3725,17 @@ enum keyboard_id { /* flags */ enum mkbp_config_flags { - EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ }; enum mkbp_config_valid { - EC_MKBP_VALID_SCAN_PERIOD = BIT(0), - EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), - EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), - EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), - EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), - EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), - EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), + EC_MKBP_VALID_SCAN_PERIOD = BIT(0), + EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), + EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), + EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), + EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), + EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), }; /* @@ -3700,10 +3745,10 @@ enum mkbp_config_valid { * ec_{params/response}_mkbp_get_config. */ struct ec_mkbp_config { - uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum mkbp_config_flags) */ - uint8_t valid_flags; /* which flags are valid */ - uint16_t scan_period_us; /* period between start of scans */ + uint32_t valid_mask; /* valid fields */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ + uint8_t valid_flags; /* which flags are valid */ + uint16_t scan_period_us; /* period between start of scans */ /* revert to interrupt mode after no activity for this long */ uint32_t poll_timeout_us; /* @@ -3714,8 +3759,8 @@ struct ec_mkbp_config { uint16_t min_post_scan_delay_us; /* delay between setting up output and waiting for it to settle */ uint16_t output_settle_us; - uint16_t debounce_down_us; /* time for debounce on key down */ - uint16_t debounce_up_us; /* time for debounce on key up */ + uint16_t debounce_down_us; /* time for debounce on key down */ + uint16_t debounce_up_us; /* time for debounce on key up */ /* maximum depth to allow for fifo (0 = no keyscan output) */ uint8_t fifo_max_depth; } __ec_align_size1; @@ -3732,11 +3777,11 @@ struct ec_response_mkbp_get_config { #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 enum ec_keyscan_seq_cmd { - EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ - EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ - EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ - EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ - EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ + EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ + EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ + EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ + EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ + EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ }; enum ec_collect_flags { @@ -3744,19 +3789,19 @@ enum ec_collect_flags { * Indicates this scan was processed by the EC. Due to timing, some * scans may be skipped. */ - EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), + EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), }; struct ec_collect_item { - uint8_t flags; /* some flags (enum ec_collect_flags) */ + uint8_t flags; /* some flags (enum ec_collect_flags) */ } __ec_align1; struct ec_params_keyscan_seq_ctrl { - uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ + uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ union { struct __ec_align1 { - uint8_t active; /* still active */ - uint8_t num_items; /* number of items */ + uint8_t active; /* still active */ + uint8_t num_items; /* number of items */ /* Current item being presented */ uint8_t cur_item; } status; @@ -3766,11 +3811,11 @@ struct ec_params_keyscan_seq_ctrl { * start of the sequence. */ uint32_t time_us; - uint8_t scan[0]; /* keyscan data */ + uint8_t scan[0]; /* keyscan data */ } add; struct __ec_align1 { - uint8_t start_item; /* First item to return */ - uint8_t num_items; /* Number of items to return */ + uint8_t start_item; /* First item to return */ + uint8_t num_items; /* Number of items to return */ } collect; }; } __ec_todo_packed; @@ -3778,7 +3823,7 @@ struct ec_params_keyscan_seq_ctrl { struct ec_result_keyscan_seq_ctrl { union { struct __ec_todo_unpacked { - uint8_t num_items; /* Number of items */ + uint8_t num_items; /* Number of items */ /* Data for each item */ struct ec_collect_item item[0]; } collect; @@ -3854,6 +3899,25 @@ enum ec_mkbp_event { }; BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK); +/* clang-format off */ +#define EC_MKBP_EVENT_TEXT \ + { \ + [EC_MKBP_EVENT_KEY_MATRIX] = "KEY_MATRIX", \ + [EC_MKBP_EVENT_HOST_EVENT] = "HOST_EVENT", \ + [EC_MKBP_EVENT_SENSOR_FIFO] = "SENSOR_FIFO", \ + [EC_MKBP_EVENT_BUTTON] = "BUTTON", \ + [EC_MKBP_EVENT_SWITCH] = "SWITCH", \ + [EC_MKBP_EVENT_FINGERPRINT] = "FINGERPRINT", \ + [EC_MKBP_EVENT_SYSRQ] = "SYSRQ", \ + [EC_MKBP_EVENT_HOST_EVENT64] = "HOST_EVENT64", \ + [EC_MKBP_EVENT_CEC_EVENT] = "CEC_EVENT", \ + [EC_MKBP_EVENT_CEC_MESSAGE] = "CEC_MESSAGE", \ + [EC_MKBP_EVENT_DP_ALT_MODE_ENTERED] = "DP_ALT_MODE_ENTERED", \ + [EC_MKBP_EVENT_ONLINE_CALIBRATION] = "ONLINE_CALIBRATION", \ + [EC_MKBP_EVENT_PCHG] = "PCHG", \ + } +/* clang-format on */ + union __ec_align_offset1 ec_response_get_next_data { uint8_t key_matrix[13]; @@ -3921,58 +3985,57 @@ struct ec_response_get_next_event_v1 { /* Bit indices for buttons and switches.*/ /* Buttons */ -#define EC_MKBP_POWER_BUTTON 0 -#define EC_MKBP_VOL_UP 1 -#define EC_MKBP_VOL_DOWN 2 -#define EC_MKBP_RECOVERY 3 +#define EC_MKBP_POWER_BUTTON 0 +#define EC_MKBP_VOL_UP 1 +#define EC_MKBP_VOL_DOWN 2 +#define EC_MKBP_RECOVERY 3 /* Switches */ -#define EC_MKBP_LID_OPEN 0 -#define EC_MKBP_TABLET_MODE 1 -#define EC_MKBP_BASE_ATTACHED 2 -#define EC_MKBP_FRONT_PROXIMITY 3 +#define EC_MKBP_LID_OPEN 0 +#define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 struct ec_response_keyboard_factory_test { - uint16_t shorted; /* Keyboard pins are shorted */ + uint16_t shorted; /* Keyboard pins are shorted */ } __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ -#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) -#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) +#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events)&0x00FFFFFF) +#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events)&0x0000000F) #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 -#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \ - >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) +#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \ + (((fpe)&0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) #define EC_MKBP_FP_MATCH_IDX_OFFSET 12 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 -#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \ - >> EC_MKBP_FP_MATCH_IDX_OFFSET) -#define EC_MKBP_FP_ENROLL BIT(27) -#define EC_MKBP_FP_MATCH BIT(28) -#define EC_MKBP_FP_FINGER_DOWN BIT(29) -#define EC_MKBP_FP_FINGER_UP BIT(30) -#define EC_MKBP_FP_IMAGE_READY BIT(31) +#define EC_MKBP_FP_MATCH_IDX(fpe) \ + (((fpe)&EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) +#define EC_MKBP_FP_ENROLL BIT(27) +#define EC_MKBP_FP_MATCH BIT(28) +#define EC_MKBP_FP_FINGER_DOWN BIT(29) +#define EC_MKBP_FP_FINGER_UP BIT(30) +#define EC_MKBP_FP_IMAGE_READY BIT(31) /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ -#define EC_MKBP_FP_ERR_ENROLL_OK 0 -#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 -#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 -#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 -#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 +#define EC_MKBP_FP_ERR_ENROLL_OK 0 +#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 +#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 +#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 +#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 /* Can be used to detect if image was usable for enrollment or not. */ -#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 +#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ -#define EC_MKBP_FP_ERR_MATCH_NO 0 -#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 -#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 -#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 -#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 -#define EC_MKBP_FP_ERR_MATCH_YES 1 -#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 +#define EC_MKBP_FP_ERR_MATCH_NO 0 +#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 +#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 +#define EC_MKBP_FP_ERR_MATCH_YES 1 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 - #define EC_CMD_MKBP_WAKE_MASK 0x0069 enum ec_mkbp_event_mask_action { /* Retrieve the value of a wake mask. */ @@ -4050,7 +4113,6 @@ struct ec_response_temp_sensor_get_info { /*****************************************************************************/ /* Host event commands */ - /* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ /* * Host event mask params and response structures, shared by all of the host @@ -4065,17 +4127,17 @@ struct ec_response_host_event_mask { } __ec_align4; /* These all use ec_response_host_event_mask */ -#define EC_CMD_HOST_EVENT_GET_B 0x0087 -#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 -#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 +#define EC_CMD_HOST_EVENT_GET_B 0x0087 +#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 +#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D /* These all use ec_params_host_event_mask */ -#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A -#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B -#define EC_CMD_HOST_EVENT_CLEAR 0x008C +#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A +#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B +#define EC_CMD_HOST_EVENT_CLEAR 0x008C #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E -#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F +#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F /* * Unified host event programming interface - Should be used by newer versions @@ -4087,7 +4149,6 @@ struct ec_response_host_event_mask { */ struct ec_params_host_event { - /* Action requested by host - one of enum ec_host_event_action. */ uint8_t action; @@ -4110,7 +4171,6 @@ struct ec_params_host_event { */ struct ec_response_host_event { - /* Mask value in case of get operation */ uint64_t value; } __ec_align4; @@ -4159,7 +4219,7 @@ enum ec_host_event_mask_type { EC_HOST_EVENT_LAZY_WAKE_MASK_S5, }; -#define EC_CMD_HOST_EVENT 0x00A4 +#define EC_CMD_HOST_EVENT 0x00A4 /*****************************************************************************/ /* Switch commands */ @@ -4315,10 +4375,11 @@ enum ec_charge_control_mode { CHARGE_CONTROL_COUNT, }; -#define EC_CHARGE_MODE_TEXT { \ - [CHARGE_CONTROL_NORMAL] = "NORMAL", \ - [CHARGE_CONTROL_IDLE] = "IDLE", \ - [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \ +#define EC_CHARGE_MODE_TEXT \ + { \ + [CHARGE_CONTROL_NORMAL] = "NORMAL", \ + [CHARGE_CONTROL_IDLE] = "IDLE", \ + [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \ } enum ec_charge_control_cmd { @@ -4327,10 +4388,10 @@ enum ec_charge_control_cmd { }; struct ec_params_charge_control { - uint32_t mode; /* enum charge_control_mode */ + uint32_t mode; /* enum charge_control_mode */ /* Below are the fields added in V2. */ - uint8_t cmd; /* enum ec_charge_control_cmd. */ + uint8_t cmd; /* enum ec_charge_control_cmd. */ uint8_t reserved; /* * Lower and upper thresholds for battery sustainer. This struct isn't @@ -4341,15 +4402,15 @@ struct ec_params_charge_control { * lower=-1, upper=-1. */ struct { - int8_t lower; /* Display SoC in percentage. */ - int8_t upper; /* Display SoC in percentage. */ + int8_t lower; /* Display SoC in percentage. */ + int8_t upper; /* Display SoC in percentage. */ } sustain_soc; } __ec_align4; /* Added in v2 */ struct ec_response_charge_control { - uint32_t mode; /* enum charge_control_mode */ - struct { /* Battery sustainer thresholds */ + uint32_t mode; /* enum charge_control_mode */ + struct { /* Battery sustainer thresholds */ int8_t lower; int8_t upper; } sustain_soc; @@ -4377,7 +4438,7 @@ struct ec_response_charge_control { enum ec_console_read_subcmd { CONSOLE_READ_NEXT = 0, - CONSOLE_READ_RECENT + CONSOLE_READ_RECENT, }; struct ec_params_console_read_v1 { @@ -4395,7 +4456,7 @@ struct ec_params_console_read_v1 { */ #define EC_CMD_BATTERY_CUT_OFF 0x0099 -#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) struct ec_params_battery_cutoff { uint8_t flags; @@ -4417,8 +4478,8 @@ struct ec_params_usb_mux { /* LDOs / FETs control. */ enum ec_ldo_state { - EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ - EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ + EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ + EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ }; /* @@ -4519,33 +4580,33 @@ struct ec_response_power_info_v1 { #define EC_CMD_I2C_PASSTHRU 0x009E /* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ BIT(15) +#define EC_I2C_FLAG_READ BIT(15) /* Mask for address */ -#define EC_I2C_ADDR_MASK 0x3ff +#define EC_I2C_ADDR_MASK 0x3ff -#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ /* Any error */ -#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) struct ec_params_i2c_passthru_msg { - uint16_t addr_flags; /* I2C peripheral address and flags */ - uint16_t len; /* Number of bytes to read or write */ + uint16_t addr_flags; /* I2C peripheral address and flags */ + uint16_t len; /* Number of bytes to read or write */ } __ec_align2; struct ec_params_i2c_passthru { - uint8_t port; /* I2C port number */ - uint8_t num_msgs; /* Number of messages */ + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ struct ec_params_i2c_passthru_msg msg[]; /* Data to write for all messages is concatenated here */ } __ec_align2; struct ec_response_i2c_passthru { - uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ - uint8_t num_msgs; /* Number of messages processed */ - uint8_t data[]; /* Data read by messages concatenated here */ + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + uint8_t data[]; /* Data read by messages concatenated here */ } __ec_align1; /*****************************************************************************/ @@ -4555,16 +4616,16 @@ struct ec_response_i2c_passthru { /* Reasons to start hang detection timer */ /* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS BIT(0) +#define EC_HANG_START_ON_POWER_PRESS BIT(0) /* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE BIT(1) +#define EC_HANG_START_ON_LID_CLOSE BIT(1) - /* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN BIT(2) +/* Lid opened */ +#define EC_HANG_START_ON_LID_OPEN BIT(2) /* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME BIT(3) +#define EC_HANG_START_ON_RESUME BIT(3) /* Reasons to cancel hang detection */ @@ -4572,10 +4633,10 @@ struct ec_response_i2c_passthru { #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) /* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) +#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) /* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND BIT(10) +#define EC_HANG_STOP_ON_SUSPEND BIT(10) /* * If this flag is set, all the other fields are ignored, and the hang detect @@ -4583,14 +4644,14 @@ struct ec_response_i2c_passthru { * without reconfiguring any of the other hang detect settings. Note that * you must previously have configured the timeouts. */ -#define EC_HANG_START_NOW BIT(30) +#define EC_HANG_START_NOW BIT(30) /* * If this flag is set, all the other fields are ignored (including * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer * without reconfiguring any of the other hang detect settings. */ -#define EC_HANG_STOP_NOW BIT(31) +#define EC_HANG_STOP_NOW BIT(31) struct ec_params_hang_detect { /* Flags; see EC_HANG_* */ @@ -4617,7 +4678,7 @@ enum charge_state_command { CHARGE_STATE_CMD_GET_STATE, CHARGE_STATE_CMD_GET_PARAM, CHARGE_STATE_CMD_SET_PARAM, - CHARGE_STATE_NUM_CMDS + CHARGE_STATE_NUM_CMDS, }; /* @@ -4625,16 +4686,27 @@ enum charge_state_command { * params, which are handled by the particular implementations. */ enum charge_state_params { - CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ - CS_PARAM_CHG_CURRENT, /* charger current limit */ - CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ - CS_PARAM_CHG_STATUS, /* charger-specific status */ - CS_PARAM_CHG_OPTION, /* charger-specific options */ - CS_PARAM_LIMIT_POWER, /* - * Check if power is limited due to - * low battery and / or a weak external - * charger. READ ONLY. - */ + /* charger voltage limit */ + CS_PARAM_CHG_VOLTAGE, + + /* charger current limit */ + CS_PARAM_CHG_CURRENT, + + /* charger input current limit */ + CS_PARAM_CHG_INPUT_CURRENT, + + /* charger-specific status */ + CS_PARAM_CHG_STATUS, + + /* charger-specific options */ + CS_PARAM_CHG_OPTION, + + /* + * Check if power is limited due to low battery and / or a + * weak external charger. READ ONLY. + */ + CS_PARAM_LIMIT_POWER, + /* How many so far? */ CS_NUM_BASE_PARAMS, @@ -4657,20 +4729,20 @@ enum charge_state_params { }; struct ec_params_charge_state { - uint8_t cmd; /* enum charge_state_command */ + uint8_t cmd; /* enum charge_state_command */ union { /* get_state has no args */ struct __ec_todo_unpacked { - uint32_t param; /* enum charge_state_param */ + uint32_t param; /* enum charge_state_param */ } get_param; struct __ec_todo_unpacked { - uint32_t param; /* param to set */ - uint32_t value; /* value to set */ + uint32_t param; /* param to set */ + uint32_t value; /* value to set */ } set_param; }; - uint8_t chgnum; /* Version 1 supports chgnum */ + uint8_t chgnum; /* Version 1 supports chgnum */ } __ec_todo_packed; struct ec_response_charge_state { @@ -4691,7 +4763,6 @@ struct ec_response_charge_state { }; } __ec_align4; - /* * Set maximum battery charging current. */ @@ -4795,10 +4866,10 @@ struct ec_response_hibernation_delay { #define EC_CMD_HOST_SLEEP_EVENT 0x00A9 enum host_sleep_event { - HOST_SLEEP_EVENT_S3_SUSPEND = 1, - HOST_SLEEP_EVENT_S3_RESUME = 2, + HOST_SLEEP_EVENT_S3_SUSPEND = 1, + HOST_SLEEP_EVENT_S3_RESUME = 2, HOST_SLEEP_EVENT_S0IX_SUSPEND = 3, - HOST_SLEEP_EVENT_S0IX_RESUME = 4, + HOST_SLEEP_EVENT_S0IX_RESUME = 4, /* S3 suspend with additional enabled wake sources */ HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, }; @@ -4899,13 +4970,13 @@ struct ec_response_device_event { /* Smart battery pass-through */ /* Get / Set 16-bit smart battery registers */ -#define EC_CMD_SB_READ_WORD 0x00B0 -#define EC_CMD_SB_WRITE_WORD 0x00B1 +#define EC_CMD_SB_READ_WORD 0x00B0 +#define EC_CMD_SB_WRITE_WORD 0x00B1 /* Get / Set string smart battery parameters * formatted as SMBUS "block". */ -#define EC_CMD_SB_READ_BLOCK 0x00B2 +#define EC_CMD_SB_READ_BLOCK 0x00B2 #define EC_CMD_SB_WRITE_BLOCK 0x00B3 struct ec_params_sb_rd { @@ -4963,14 +5034,14 @@ struct ec_response_battery_vendor_param { #define EC_CMD_SB_FW_UPDATE 0x00B5 enum ec_sb_fw_update_subcmd { - EC_SB_FW_UPDATE_PREPARE = 0x0, - EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ - EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ - EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ - EC_SB_FW_UPDATE_END = 0x4, - EC_SB_FW_UPDATE_STATUS = 0x5, - EC_SB_FW_UPDATE_PROTECT = 0x6, - EC_SB_FW_UPDATE_MAX = 0x7, + EC_SB_FW_UPDATE_PREPARE = 0x0, + EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ + EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ + EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ + EC_SB_FW_UPDATE_END = 0x4, + EC_SB_FW_UPDATE_STATUS = 0x5, + EC_SB_FW_UPDATE_PROTECT = 0x6, + EC_SB_FW_UPDATE_MAX = 0x7, }; #define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32 @@ -4978,8 +5049,8 @@ enum ec_sb_fw_update_subcmd { #define SB_FW_UPDATE_CMD_INFO_SIZE 8 struct ec_sb_fw_update_header { - uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ - uint16_t fw_id; /* firmware id */ + uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ + uint16_t fw_id; /* firmware id */ } __ec_align4; struct ec_params_sb_fw_update { @@ -4995,7 +5066,7 @@ struct ec_params_sb_fw_update { /* EC_SB_FW_UPDATE_WRITE = 0x3 */ struct __ec_align4 { - uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; + uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; } write; }; } __ec_align4; @@ -5028,9 +5099,9 @@ struct ec_params_entering_mode { int vboot_mode; } __ec_align4; -#define VBOOT_MODE_NORMAL 0 +#define VBOOT_MODE_NORMAL 0 #define VBOOT_MODE_DEVELOPER 1 -#define VBOOT_MODE_RECOVERY 2 +#define VBOOT_MODE_RECOVERY 2 /*****************************************************************************/ /* @@ -5047,14 +5118,13 @@ enum ec_i2c_passthru_protect_subcmd { struct ec_params_i2c_passthru_protect { uint8_t subcmd; - uint8_t port; /* I2C port number */ + uint8_t port; /* I2C port number */ } __ec_align1; struct ec_response_i2c_passthru_protect { - uint8_t status; /* Status flags (0: unlocked, 1: locked) */ + uint8_t status; /* Status flags (0: unlocked, 1: locked) */ } __ec_align1; - /*****************************************************************************/ /* * HDMI CEC commands @@ -5124,9 +5194,9 @@ enum cec_command { /* Events from CEC to AP */ enum mkbp_cec_event { /* Outgoing message was acknowledged by a follower */ - EC_MKBP_CEC_SEND_OK = BIT(0), + EC_MKBP_CEC_SEND_OK = BIT(0), /* Outgoing message was not acknowledged */ - EC_MKBP_CEC_SEND_FAILED = BIT(1), + EC_MKBP_CEC_SEND_FAILED = BIT(1), }; /*****************************************************************************/ @@ -5175,10 +5245,8 @@ struct __ec_align4 ec_param_ec_codec { uint8_t reserved[3]; union { - struct ec_param_ec_codec_get_shm_addr - get_shm_addr_param; - struct ec_param_ec_codec_set_shm_addr - set_shm_addr_param; + struct ec_param_ec_codec_get_shm_addr get_shm_addr_param; + struct ec_param_ec_codec_set_shm_addr set_shm_addr_param; }; }; @@ -5233,10 +5301,8 @@ struct __ec_align4 ec_param_ec_codec_dmic { uint8_t reserved[3]; union { - struct ec_param_ec_codec_dmic_set_gain_idx - set_gain_idx_param; - struct ec_param_ec_codec_dmic_get_gain_idx - get_gain_idx_param; + struct ec_param_ec_codec_dmic_set_gain_idx set_gain_idx_param; + struct ec_param_ec_codec_dmic_get_gain_idx get_gain_idx_param; }; }; @@ -5303,11 +5369,9 @@ struct __ec_align4 ec_param_ec_codec_i2s_rx { union { struct ec_param_ec_codec_i2s_rx_set_sample_depth - set_sample_depth_param; - struct ec_param_ec_codec_i2s_rx_set_daifmt - set_daifmt_param; - struct ec_param_ec_codec_i2s_rx_set_bclk - set_bclk_param; + set_sample_depth_param; + struct ec_param_ec_codec_i2s_rx_set_daifmt set_daifmt_param; + struct ec_param_ec_codec_i2s_rx_set_bclk set_bclk_param; }; }; @@ -5352,10 +5416,8 @@ struct __ec_align4 ec_param_ec_codec_wov { uint8_t reserved[3]; union { - struct ec_param_ec_codec_wov_set_lang - set_lang_param; - struct ec_param_ec_codec_wov_set_lang_shm - set_lang_shm_param; + struct ec_param_ec_codec_wov_set_lang set_lang_param; + struct ec_param_ec_codec_wov_set_lang_shm set_lang_shm_param; }; }; @@ -5386,8 +5448,8 @@ enum ec_pse_subcmd { }; struct __ec_align1 ec_params_pse { - uint8_t cmd; /* enum ec_pse_subcmd */ - uint8_t port; /* PSE port */ + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ }; enum ec_pse_status { @@ -5397,7 +5459,7 @@ enum ec_pse_status { }; struct __ec_align1 ec_response_pse_status { - uint8_t status; /* enum ec_pse_status */ + uint8_t status; /* enum ec_pse_status */ }; /*****************************************************************************/ @@ -5411,25 +5473,25 @@ struct __ec_align1 ec_response_pse_status { /* Command */ enum ec_reboot_cmd { - EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ - EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ - EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ + EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ + EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ + EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ /* (command 3 was jump to RW-B) */ - EC_REBOOT_COLD = 4, /* Cold-reboot */ - EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ - EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ + EC_REBOOT_COLD = 4, /* Cold-reboot */ + EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ + EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ - EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ -#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ struct ec_params_reboot_ec { - uint8_t cmd; /* enum ec_reboot_cmd */ - uint8_t flags; /* See EC_REBOOT_FLAG_* */ + uint8_t cmd; /* enum ec_reboot_cmd */ + uint8_t flags; /* See EC_REBOOT_FLAG_* */ } __ec_align1; /* @@ -5457,7 +5519,7 @@ struct ec_params_reboot_ec { * * Use EC_CMD_REBOOT_EC to reboot the EC more politely. */ -#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ +#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ /* * Resend last response (not supported on LPC). @@ -5492,50 +5554,66 @@ struct ec_params_reboot_ec { #define EC_VER_PD_EXCHANGE_STATUS 2 enum pd_charge_state { - PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ - PD_CHARGE_NONE, /* No charging allowed */ - PD_CHARGE_5V, /* 5V charging only */ - PD_CHARGE_MAX /* Charge at max voltage */ + /* Don't change charge state */ + PD_CHARGE_NO_CHANGE = 0, + + /* No charging allowed */ + PD_CHARGE_NONE, + + /* 5V charging only */ + PD_CHARGE_5V, + + /* Charge at max voltage */ + PD_CHARGE_MAX, }; /* Status of EC being sent to PD */ -#define EC_STATUS_HIBERNATING BIT(0) +#define EC_STATUS_HIBERNATING BIT(0) struct ec_params_pd_status { - uint8_t status; /* EC status */ - int8_t batt_soc; /* battery state of charge */ - uint8_t charge_state; /* charging state (from enum pd_charge_state) */ + /* EC status */ + uint8_t status; + + /* battery state of charge */ + int8_t batt_soc; + + /* charging state (from enum pd_charge_state) */ + uint8_t charge_state; } __ec_align1; /* Status of PD being sent back to EC */ -#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ -#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ +#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ #define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ -#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ -#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ -#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ -#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ -#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ - PD_STATUS_TCPC_ALERT_1 | \ - PD_STATUS_HOST_EVENT) +#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_EC_INT_ACTIVE \ + (PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1 | PD_STATUS_HOST_EVENT) struct ec_response_pd_status { - uint32_t curr_lim_ma; /* input current limit */ - uint16_t status; /* PD MCU status */ - int8_t active_charge_port; /* active charging port */ + /* input current limit */ + uint32_t curr_lim_ma; + + /* PD MCU status */ + uint16_t status; + + /* active charging port */ + int8_t active_charge_port; } __ec_align_size1; /* AP to PD MCU host event status command, cleared on read */ #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 /* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE BIT(0) -#define PD_EVENT_POWER_CHANGE BIT(1) -#define PD_EVENT_IDENTITY_RECEIVED BIT(2) -#define PD_EVENT_DATA_SWAP BIT(3) -#define PD_EVENT_TYPEC BIT(4) +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_TYPEC BIT(4) struct ec_response_host_event_status { - uint32_t status; /* PD MCU host event status */ + uint32_t status; /* PD MCU host event status */ } __ec_align4; /* @@ -5554,7 +5632,7 @@ enum usb_pd_control_role { USB_PD_CTRL_ROLE_FORCE_SINK = 3, USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, USB_PD_CTRL_ROLE_FREEZE = 5, - USB_PD_CTRL_ROLE_COUNT + USB_PD_CTRL_ROLE_COUNT, }; enum usb_pd_control_mux { @@ -5564,7 +5642,7 @@ enum usb_pd_control_mux { USB_PD_CTRL_MUX_DP = 3, USB_PD_CTRL_MUX_DOCK = 4, USB_PD_CTRL_MUX_AUTO = 5, - USB_PD_CTRL_MUX_COUNT + USB_PD_CTRL_MUX_COUNT, }; enum usb_pd_control_swap { @@ -5572,7 +5650,7 @@ enum usb_pd_control_swap { USB_PD_CTRL_SWAP_DATA = 1, USB_PD_CTRL_SWAP_POWER = 2, USB_PD_CTRL_SWAP_VCONN = 3, - USB_PD_CTRL_SWAP_COUNT + USB_PD_CTRL_SWAP_COUNT, }; struct ec_params_usb_pd_control { @@ -5582,17 +5660,18 @@ struct ec_params_usb_pd_control { uint8_t swap; } __ec_align1; -#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ -#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ #define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ -#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ -#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ -#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ -#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ -#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ -#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ -#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) /* Partner unconstrained power */ +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +/* Partner unconstrained power */ +#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) struct ec_response_usb_pd_control { uint8_t enabled; @@ -5610,39 +5689,39 @@ struct ec_response_usb_pd_control_v1 { /* Possible port partner connections based on CC line states */ enum pd_cc_states { - PD_CC_NONE = 0, /* No port partner attached */ + PD_CC_NONE = 0, /* No port partner attached */ /* From DFP perspective */ - PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ - PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ - PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ - PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ + PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ + PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ + PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ + PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ /* From UFP perspective */ - PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ - PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ + PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ + PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ }; /* Active/Passive Cable */ -#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) /* Optical/Non-optical cable */ -#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) /* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */ -#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) /* Active Link Uni-Direction */ -#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; uint8_t polarity; char state[32]; - uint8_t cc_state; /* enum pd_cc_states representing cc state */ - uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ - uint8_t reserved; /* Reserved for future use */ - uint8_t control_flags; /* USB_PD_CTRL_*flags */ - uint8_t cable_speed; /* TBT_SS_* cable speed */ - uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ + uint8_t cc_state; /* enum pd_cc_states representing cc state */ + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ + uint8_t reserved; /* Reserved for future use */ + uint8_t control_flags; /* USB_PD_CTRL_*flags */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; #define EC_CMD_USB_PD_PORTS 0x0102 @@ -5697,7 +5776,6 @@ struct ec_response_usb_pd_power_info { uint32_t max_power; } __ec_align4; - /* * This command will return the number of USB PD charge port + the number * of dedicated port present. @@ -5731,7 +5809,10 @@ struct ec_params_usb_pd_fw_update { uint16_t dev_id; uint8_t cmd; uint8_t port; - uint32_t size; /* Size to write in bytes */ + + /* Size to write in bytes */ + uint32_t size; + /* Followed by data to write */ } __ec_align4; @@ -5742,12 +5823,16 @@ struct ec_params_usb_pd_fw_update { struct ec_params_usb_pd_rw_hash_entry { uint16_t dev_id; uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; - uint8_t reserved; /* - * For alignment of current_image - * TODO(rspangler) but it's not aligned! - * Should have been reserved[2]. - */ - uint32_t current_image; /* One of ec_image */ + + /* + * Reserved for alignment of current_image + * TODO(rspangler) but it's not aligned! + * Should have been reserved[2]. + */ + uint8_t reserved; + + /* One of ec_image */ + uint32_t current_image; } __ec_align1; /* Read USB-PD Accessory info */ @@ -5760,8 +5845,8 @@ struct ec_params_usb_pd_info_request { /* Read USB-PD Device discovery info */ #define EC_CMD_USB_PD_DISCOVERY 0x0113 struct ec_params_usb_pd_discovery_entry { - uint16_t vid; /* USB-IF VID */ - uint16_t pid; /* USB-IF PID */ + uint16_t vid; /* USB-IF VID */ + uint16_t pid; /* USB-IF PID */ uint8_t ptype; /* product type (hub,periph,cable,ama) */ } __ec_align_size1; @@ -5788,43 +5873,43 @@ struct ec_params_charge_port_override { struct ec_response_pd_log { uint32_t timestamp; /* relative timestamp in milliseconds */ - uint8_t type; /* event type : see PD_EVENT_xx below */ - uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ - uint16_t data; /* type-defined data payload */ + uint8_t type; /* event type : see PD_EVENT_xx below */ + uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ } __ec_align4; /* The timestamp is the microsecond counter shifted to get about a ms. */ #define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ -#define PD_LOG_SIZE_MASK 0x1f -#define PD_LOG_PORT_MASK 0xe0 -#define PD_LOG_PORT_SHIFT 5 -#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ - ((size) & PD_LOG_SIZE_MASK)) +#define PD_LOG_SIZE_MASK 0x1f +#define PD_LOG_PORT_MASK 0xe0 +#define PD_LOG_PORT_SHIFT 5 +#define PD_LOG_PORT_SIZE(port, size) \ + (((port) << PD_LOG_PORT_SHIFT) | ((size)&PD_LOG_SIZE_MASK)) #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) -#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) +#define PD_LOG_SIZE(size_port) ((size_port)&PD_LOG_SIZE_MASK) /* PD event log : entry types */ /* PD MCU events */ -#define PD_EVENT_MCU_BASE 0x00 -#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0) -#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1) +#define PD_EVENT_MCU_BASE 0x00 +#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE + 0) +#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE + 1) /* Reserved for custom board event */ -#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2) +#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE + 2) /* PD generic accessory events */ -#define PD_EVENT_ACC_BASE 0x20 -#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0) -#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1) +#define PD_EVENT_ACC_BASE 0x20 +#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE + 0) +#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE + 1) /* PD power supply events */ -#define PD_EVENT_PS_BASE 0x40 -#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0) +#define PD_EVENT_PS_BASE 0x40 +#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE + 0) /* PD video dongles events */ -#define PD_EVENT_VIDEO_BASE 0x60 -#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) -#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) +#define PD_EVENT_VIDEO_BASE 0x60 +#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE + 0) +#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE + 1) /* Returned in the "type" field, when there is no entry available */ -#define PD_EVENT_NO_ENTRY 0xff +#define PD_EVENT_NO_ENTRY 0xff /* * PD_EVENT_MCU_CHARGE event definition : @@ -5832,24 +5917,24 @@ struct ec_response_pd_log { * the data field contains the port state flags as defined below : */ /* Port partner is a dual role device */ -#define CHARGE_FLAGS_DUAL_ROLE BIT(15) +#define CHARGE_FLAGS_DUAL_ROLE BIT(15) /* Port is the pending override port */ -#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) +#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) /* Port is the override port */ -#define CHARGE_FLAGS_OVERRIDE BIT(13) +#define CHARGE_FLAGS_OVERRIDE BIT(13) /* Charger type */ -#define CHARGE_FLAGS_TYPE_SHIFT 3 -#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) +#define CHARGE_FLAGS_TYPE_SHIFT 3 +#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) /* Power delivery role */ -#define CHARGE_FLAGS_ROLE_MASK (7 << 0) +#define CHARGE_FLAGS_ROLE_MASK (7 << 0) /* * PD_EVENT_PS_FAULT data field flags definition : */ -#define PS_FAULT_OCP 1 -#define PS_FAULT_FAST_OCP 2 -#define PS_FAULT_OVP 3 -#define PS_FAULT_DISCH 4 +#define PS_FAULT_OCP 1 +#define PS_FAULT_FAST_OCP 2 +#define PS_FAULT_OVP 3 +#define PS_FAULT_DISCH 4 /* * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". @@ -5875,12 +5960,12 @@ struct mcdp_info { #define EC_CMD_USB_PD_GET_AMODE 0x0116 struct ec_params_usb_pd_get_mode_request { uint16_t svid_idx; /* SVID index to get */ - uint8_t port; /* port */ + uint8_t port; /* port */ } __ec_align_size1; struct ec_params_usb_pd_get_mode_response { - uint16_t svid; /* SVID */ - uint16_t opos; /* Object Position */ + uint16_t svid; /* SVID */ + uint16_t opos; /* Object Position */ uint32_t vdo[6]; /* Mode VDOs */ } __ec_align4; @@ -5894,10 +5979,10 @@ enum pd_mode_cmd { }; struct ec_params_usb_pd_set_mode_request { - uint32_t cmd; /* enum pd_mode_cmd */ + uint32_t cmd; /* enum pd_mode_cmd */ uint16_t svid; /* SVID to set */ - uint8_t opos; /* Object Position */ - uint8_t port; /* port */ + uint8_t opos; /* Object Position */ + uint8_t port; /* port */ } __ec_align4; /* Ask the PD MCU to record a log of a requested type */ @@ -5908,20 +5993,19 @@ struct ec_params_pd_write_log_entry { uint8_t port; /* port#, or 0 for events unrelated to a given port */ } __ec_align1; - /* Control USB-PD chip */ #define EC_CMD_PD_CONTROL 0x0119 enum ec_pd_control_cmd { - PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ - PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ - PD_RESET, /* Force reset the PD chip */ - PD_CONTROL_DISABLE, /* Disable further calls to this command */ - PD_CHIP_ON, /* Power on the PD chip */ + PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ + PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ + PD_RESET, /* Force reset the PD chip */ + PD_CONTROL_DISABLE, /* Disable further calls to this command */ + PD_CHIP_ON, /* Power on the PD chip */ }; struct ec_params_pd_control { - uint8_t chip; /* chip id */ + uint8_t chip; /* chip id */ uint8_t subcmd; } __ec_align1; @@ -5933,29 +6017,29 @@ struct ec_params_usb_pd_mux_info { } __ec_align1; /* Flags representing mux state */ -#define USB_PD_MUX_NONE 0 /* Open switch */ -#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ -#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ -#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ -#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ -#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */ -#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ -#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */ -#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ +#define USB_PD_MUX_NONE 0 /* Open switch */ +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ +#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */ +#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ +#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */ +#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ -#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ /* USB-C Dock connected */ -#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) +#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) struct ec_response_usb_pd_mux_info { uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ } __ec_align1; -#define EC_CMD_PD_CHIP_INFO 0x011B +#define EC_CMD_PD_CHIP_INFO 0x011B struct ec_params_pd_chip_info { - uint8_t port; /* USB-C port number */ + uint8_t port; /* USB-C port number */ /* * Fetch the live chip info or hard-coded + cached chip info * 0: hardcoded value for VID/PID, cached value for FW version @@ -5989,18 +6073,18 @@ struct ec_response_pd_chip_info_v1 { } __ec_align2; /* Run RW signature verification and get status */ -#define EC_CMD_RWSIG_CHECK_STATUS 0x011C +#define EC_CMD_RWSIG_CHECK_STATUS 0x011C struct ec_response_rwsig_check_status { uint32_t status; } __ec_align4; /* For controlling RWSIG task */ -#define EC_CMD_RWSIG_ACTION 0x011D +#define EC_CMD_RWSIG_ACTION 0x011D enum rwsig_action { - RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ - RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ + RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ + RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ }; struct ec_params_rwsig_action { @@ -6008,10 +6092,10 @@ struct ec_params_rwsig_action { } __ec_align4; /* Run verification on a slot */ -#define EC_CMD_EFS_VERIFY 0x011E +#define EC_CMD_EFS_VERIFY 0x011E struct ec_params_efs_verify { - uint8_t region; /* enum ec_flash_region */ + uint8_t region; /* enum ec_flash_region */ } __ec_align1; /* @@ -6019,25 +6103,26 @@ struct ec_params_efs_verify { * type. Integers return a uint32. Strings return a string, using the response * size to determine how big it is. */ -#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +#define EC_CMD_GET_CROS_BOARD_INFO 0x011F /* * Write info into Cros Board Info on EEPROM. Write fails if the board has * hardware write-protect enabled. */ -#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 +#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 enum cbi_data_tag { CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ - CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ - CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ + CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ + CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ - CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ - CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ - CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ - CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ + CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ + CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ + CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ /* Second Source Factory Cache */ - CBI_TAG_SSFC = 8, /* uint32_t bit field */ - CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ + CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ + CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* uint32_t bit field */ CBI_TAG_COUNT, }; @@ -6047,11 +6132,11 @@ enum cbi_data_tag { * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify * write was successful without reboot. */ -#define CBI_GET_RELOAD BIT(0) +#define CBI_GET_RELOAD BIT(0) struct ec_params_get_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_GET_* */ + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_GET_* */ } __ec_align4; /* @@ -6062,14 +6147,14 @@ struct ec_params_get_cbi { * INIT: Need to be set when creating a new CBI from scratch. All fields * will be initialized to zero first. */ -#define CBI_SET_NO_SYNC BIT(0) -#define CBI_SET_INIT BIT(1) +#define CBI_SET_NO_SYNC BIT(0) +#define CBI_SET_INIT BIT(1) struct ec_params_set_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_SET_* */ - uint32_t size; /* Data size */ - uint8_t data[]; /* For string and raw data */ + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_SET_* */ + uint32_t size; /* Data size */ + uint8_t data[]; /* For string and raw data */ } __ec_align1; /* @@ -6078,33 +6163,32 @@ struct ec_params_set_cbi { #define EC_CMD_GET_UPTIME_INFO 0x0121 /* EC reset causes */ -#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ -#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ -#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ -#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ -#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ -#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ -#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ -#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ -#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ -#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ -#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ -#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */ -#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ -#define EC_RESET_FLAG_PRESERVED BIT(13) /* Some reset flags preserved from - * previous boot - */ -#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ -#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ -#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ -#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ -#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset */ -#define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This - * enables PD in RO for Chromebox. - */ -#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ -#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ -#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ +#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ +#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ +#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ +#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ +#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ +#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ +#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ +#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ +#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ +#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ +#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ +#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */ +#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ +/* Some reset flags preserved from previous boot */ +#define EC_RESET_FLAG_PRESERVED BIT(13) +#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ +#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ +#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ +#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ +/* AP experienced a watchdog reset */ +#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) +/* Do not select RW in EFS. This enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_STAY_IN_RO BIT(19) +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ /* * Reason codes used by the AP after a shutdown to figure out why it was reset @@ -6172,7 +6256,6 @@ enum chipset_shutdown_reason { CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */ }; - struct ec_response_uptime_info { /* * Number of milliseconds since the last EC boot. Sysjump resets @@ -6221,7 +6304,7 @@ struct ec_response_uptime_info { * Depending on the chip, the operation may take a long time (e.g. to erase * flash), so the commands are asynchronous. */ -#define EC_CMD_ADD_ENTROPY 0x0122 +#define EC_CMD_ADD_ENTROPY 0x0122 enum add_entropy_action { /* Add entropy to the current secret. */ @@ -6243,7 +6326,7 @@ struct ec_params_rollback_add_entropy { /* * Perform a single read of a given ADC channel. */ -#define EC_CMD_ADC_READ 0x0123 +#define EC_CMD_ADC_READ 0x0123 struct ec_params_adc_read { uint8_t adc_channel; @@ -6256,7 +6339,7 @@ struct ec_response_adc_read { /* * Read back rollback info */ -#define EC_CMD_ROLLBACK_INFO 0x0124 +#define EC_CMD_ROLLBACK_INFO 0x0124 struct ec_response_rollback_info { int32_t id; /* Incrementing number to indicate which region to use. */ @@ -6264,7 +6347,6 @@ struct ec_response_rollback_info { int32_t rw_rollback_version; } __ec_align4; - /* Issue AP reset */ #define EC_CMD_AP_RESET 0x0125 @@ -6293,23 +6375,22 @@ enum ec_bus_type { }; struct ec_i2c_info { - uint16_t port; /* Physical port for device */ - uint16_t addr_flags; /* 7-bit (or 10-bit) address */ + uint16_t port; /* Physical port for device */ + uint16_t addr_flags; /* 7-bit (or 10-bit) address */ }; struct ec_params_locate_chip { - uint8_t type; /* enum ec_chip_type */ - uint8_t index; /* Specifies one instance of chip type */ + uint8_t type; /* enum ec_chip_type */ + uint8_t index; /* Specifies one instance of chip type */ /* Used for type specific parameters in future */ union { uint16_t reserved; }; } __ec_align2; - struct ec_response_locate_chip { - uint8_t bus_type; /* enum ec_bus_type */ - uint8_t reserved; /* Aligning the following union to 2 bytes */ + uint8_t bus_type; /* enum ec_bus_type */ + uint8_t reserved; /* Aligning the following union to 2 bytes */ union { struct ec_i2c_info i2c_info; }; @@ -6380,27 +6461,27 @@ enum ec_pd_port_location { * left side, while BACK_LEFT means the leftmost port on the back of the * device. */ - EC_PD_PORT_LOCATION_LEFT = 1, - EC_PD_PORT_LOCATION_RIGHT = 2, - EC_PD_PORT_LOCATION_BACK = 3, - EC_PD_PORT_LOCATION_FRONT = 4, - EC_PD_PORT_LOCATION_LEFT_FRONT = 5, - EC_PD_PORT_LOCATION_LEFT_BACK = 6, + EC_PD_PORT_LOCATION_LEFT = 1, + EC_PD_PORT_LOCATION_RIGHT = 2, + EC_PD_PORT_LOCATION_BACK = 3, + EC_PD_PORT_LOCATION_FRONT = 4, + EC_PD_PORT_LOCATION_LEFT_FRONT = 5, + EC_PD_PORT_LOCATION_LEFT_BACK = 6, EC_PD_PORT_LOCATION_RIGHT_FRONT = 7, - EC_PD_PORT_LOCATION_RIGHT_BACK = 8, - EC_PD_PORT_LOCATION_BACK_LEFT = 9, - EC_PD_PORT_LOCATION_BACK_RIGHT = 10, + EC_PD_PORT_LOCATION_RIGHT_BACK = 8, + EC_PD_PORT_LOCATION_BACK_LEFT = 9, + EC_PD_PORT_LOCATION_BACK_RIGHT = 10, }; struct ec_params_get_pd_port_caps { - uint8_t port; /* Which port to interrogate */ + uint8_t port; /* Which port to interrogate */ } __ec_align1; struct ec_response_get_pd_port_caps { - uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ - uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ - uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ - uint8_t pd_port_location; /* enum ec_pd_port_location */ + uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ + uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ + uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ + uint8_t pd_port_location; /* enum ec_pd_port_location */ } __ec_align1; /*****************************************************************************/ @@ -6417,27 +6498,27 @@ struct ec_response_get_pd_port_caps { struct ec_params_button { /* Button mask aligned to enum keyboard_button_type */ - uint32_t btn_mask; + uint32_t btn_mask; /* Duration in milliseconds button needs to be pressed */ - uint32_t press_ms; + uint32_t press_ms; } __ec_align1; enum keyboard_button_type { - KEYBOARD_BUTTON_POWER = 0, + KEYBOARD_BUTTON_POWER = 0, KEYBOARD_BUTTON_VOLUME_DOWN = 1, - KEYBOARD_BUTTON_VOLUME_UP = 2, - KEYBOARD_BUTTON_RECOVERY = 3, - KEYBOARD_BUTTON_CAPSENSE_1 = 4, - KEYBOARD_BUTTON_CAPSENSE_2 = 5, - KEYBOARD_BUTTON_CAPSENSE_3 = 6, - KEYBOARD_BUTTON_CAPSENSE_4 = 7, - KEYBOARD_BUTTON_CAPSENSE_5 = 8, - KEYBOARD_BUTTON_CAPSENSE_6 = 9, - KEYBOARD_BUTTON_CAPSENSE_7 = 10, - KEYBOARD_BUTTON_CAPSENSE_8 = 11, + KEYBOARD_BUTTON_VOLUME_UP = 2, + KEYBOARD_BUTTON_RECOVERY = 3, + KEYBOARD_BUTTON_CAPSENSE_1 = 4, + KEYBOARD_BUTTON_CAPSENSE_2 = 5, + KEYBOARD_BUTTON_CAPSENSE_3 = 6, + KEYBOARD_BUTTON_CAPSENSE_4 = 7, + KEYBOARD_BUTTON_CAPSENSE_5 = 8, + KEYBOARD_BUTTON_CAPSENSE_6 = 9, + KEYBOARD_BUTTON_CAPSENSE_7 = 10, + KEYBOARD_BUTTON_CAPSENSE_8 = 11, - KEYBOARD_BUTTON_COUNT + KEYBOARD_BUTTON_COUNT, }; /*****************************************************************************/ @@ -6491,15 +6572,15 @@ enum action_key { * action keys. This is possible for e.g. if the keyboard has a * dedicated Fn key. */ -#define KEYBD_CAP_FUNCTION_KEYS BIT(0) +#define KEYBD_CAP_FUNCTION_KEYS BIT(0) /* * Whether the keyboard has a dedicated numeric keyboard. */ -#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1) +#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1) /* * Whether the keyboard has a screenlock key. */ -#define KEYBD_CAP_SCRNLOCK_KEY BIT(2) +#define KEYBD_CAP_SCRNLOCK_KEY BIT(2) struct ec_response_keybd_config { /* @@ -6526,12 +6607,12 @@ struct ec_response_keybd_config { */ #define EC_CMD_SMART_DISCHARGE 0x012B -#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) /* Discharge rates when the system is in cutoff or hibernation. */ struct discharge_rate { - uint16_t cutoff; /* Discharge rate (uA) in cutoff */ - uint16_t hibern; /* Discharge rate (uA) in hibernation */ + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ }; struct smart_discharge_zone { @@ -6542,7 +6623,7 @@ struct smart_discharge_zone { }; struct ec_params_smart_discharge { - uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ /* * Desired hours for the battery to survive before reaching 0%. Set to * zero to disable smart discharging. That is, the system hibernates as @@ -6667,13 +6748,13 @@ struct ec_params_typec_discovery { struct svid_mode_info { uint16_t svid; - uint16_t mode_count; /* Number of modes partner sent */ + uint16_t mode_count; /* Number of modes partner sent */ uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ }; struct ec_response_typec_discovery { - uint8_t identity_count; /* Number of identity VDOs partner sent */ - uint8_t svid_count; /* Number of SVIDs partner sent */ + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ uint16_t reserved; uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ struct svid_mode_info svids[0]; @@ -6703,14 +6784,19 @@ enum typec_tbt_ufp_reply { TYPEC_TBT_UFP_REPLY_ACK, }; +#define TYPEC_USB_MUX_SET_ALL_CHIPS 0xFF + struct typec_usb_mux_set { - uint8_t mux_index; /* Index of the mux to set in the chain */ - uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */ + /* Index of the mux to set in the chain */ + uint8_t mux_index; + + /* USB_PD_MUX_*-encoded USB mux state to set */ + uint8_t mux_flags; } __ec_align1; struct ec_params_typec_control { uint8_t port; - uint8_t command; /* enum typec_control_command */ + uint8_t command; /* enum typec_control_command */ uint16_t reserved; /* @@ -6752,7 +6838,7 @@ struct ec_params_typec_control { */ enum pd_power_role { PD_ROLE_SINK = 0, - PD_ROLE_SOURCE = 1 + PD_ROLE_SOURCE = 1, }; /* @@ -6799,23 +6885,23 @@ enum tcpc_cc_polarity { * that this will give a hint that other places need to be * adjusted. */ - POLARITY_COUNT + POLARITY_COUNT, }; -#define MODE_DP_PIN_A BIT(0) -#define MODE_DP_PIN_B BIT(1) -#define MODE_DP_PIN_C BIT(2) -#define MODE_DP_PIN_D BIT(3) -#define MODE_DP_PIN_E BIT(4) -#define MODE_DP_PIN_F BIT(5) -#define MODE_DP_PIN_ALL GENMASK(5, 0) +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) +#define MODE_DP_PIN_ALL GENMASK(5, 0) -#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) -#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) -#define PD_STATUS_EVENT_HARD_RESET BIT(2) -#define PD_STATUS_EVENT_DISCONNECTED BIT(3) -#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) -#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) +#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) +#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +#define PD_STATUS_EVENT_HARD_RESET BIT(2) +#define PD_STATUS_EVENT_DISCONNECTED BIT(3) +#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) +#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) /* * Encode and decode for BCD revision response @@ -6824,9 +6910,9 @@ enum tcpc_cc_polarity { * Specification Revision from the PD header, which currently only maps to PD * 1.0-3.0 with the major revision being one greater than the binary value. */ -#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) -#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) -#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) /* * Decode helpers for Source and Sink Capability PDOs @@ -6834,11 +6920,11 @@ enum tcpc_cc_polarity { * Note: The Power Delivery Specification should be considered the ultimate * source of truth on the decoding of these PDOs */ -#define PDO_TYPE_FIXED (0 << 30) -#define PDO_TYPE_BATTERY (1 << 30) -#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) #define PDO_TYPE_AUGMENTED (3 << 30) -#define PDO_TYPE_MASK (3 << 30) +#define PDO_TYPE_MASK (3 << 30) /* * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 @@ -6853,13 +6939,13 @@ enum tcpc_cc_polarity { * <19:10> : Voltage in 50mV Units * <9:0> : Maximum Current in 10mA units */ -#define PDO_FIXED_DUAL_ROLE BIT(29) -#define PDO_FIXED_UNCONSTRAINED BIT(27) -#define PDO_FIXED_COMM_CAP BIT(26) -#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) #define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ -#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) -#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) /* * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 @@ -6869,9 +6955,9 @@ enum tcpc_cc_polarity { * <19:10> : Minimum Voltage in 50mV units * <9:0> : Maximum Allowable Power in 250mW units */ -#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) -#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) -#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) /* * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 @@ -6881,9 +6967,9 @@ enum tcpc_cc_polarity { * <19:10> : Minimum Voltage in 50mV units * <9:0> : Operational Current in 10mA units */ -#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) -#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) -#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) /* * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 @@ -6901,33 +6987,33 @@ enum tcpc_cc_polarity { * <7> : Reserved * <6:0> : Maximum Current in 50mA increments */ -#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) -#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) -#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) struct ec_params_typec_status { uint8_t port; } __ec_align1; struct ec_response_typec_status { - uint8_t pd_enabled; /* PD communication enabled - bool */ - uint8_t dev_connected; /* Device connected - bool */ - uint8_t sop_connected; /* Device is SOP PD capable - bool */ - uint8_t source_cap_count; /* Number of Source Cap PDOs */ + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ - uint8_t power_role; /* enum pd_power_role */ - uint8_t data_role; /* enum pd_data_role */ - uint8_t vconn_role; /* enum pd_vconn_role */ - uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ - uint8_t polarity; /* enum tcpc_cc_polarity */ - uint8_t cc_state; /* enum pd_cc_states */ - uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ - uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ - char tc_state[32]; /* TC state name */ + char tc_state[32]; /* TC state name */ - uint32_t events; /* PD_STATUS_EVENT bitmask */ + uint32_t events; /* PD_STATUS_EVENT bitmask */ /* * BCD PD revisions for partners @@ -6942,9 +7028,9 @@ struct ec_response_typec_status { uint16_t sop_revision; uint16_t sop_prime_revision; - uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ - uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ } __ec_align1; /** @@ -6968,8 +7054,8 @@ struct ec_params_pchg { } __ec_align1; struct ec_response_pchg { - uint32_t error; /* enum pchg_error */ - uint8_t state; /* enum pchg_state state */ + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ uint8_t battery_percentage; uint8_t unused0; uint8_t unused1; @@ -6979,8 +7065,8 @@ struct ec_response_pchg { } __ec_align4; struct ec_response_pchg_v2 { - uint32_t error; /* enum pchg_error */ - uint8_t state; /* enum pchg_state state */ + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ uint8_t battery_percentage; uint8_t unused0; uint8_t unused1; @@ -7014,17 +7100,20 @@ enum pchg_state { PCHG_STATE_COUNT, }; -#define EC_PCHG_STATE_TEXT { \ - [PCHG_STATE_RESET] = "RESET", \ - [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ - [PCHG_STATE_ENABLED] = "ENABLED", \ - [PCHG_STATE_DETECTED] = "DETECTED", \ - [PCHG_STATE_CHARGING] = "CHARGING", \ - [PCHG_STATE_FULL] = "FULL", \ - [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \ - [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \ - [PCHG_STATE_CONNECTED] = "CONNECTED", \ +/* clang-format off */ +#define EC_PCHG_STATE_TEXT \ + { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + [PCHG_STATE_FULL] = "FULL", \ + [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \ + [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \ + [PCHG_STATE_CONNECTED] = "CONNECTED", \ } +/* clang-format on */ /** * Update firmware of peripheral chip @@ -7032,19 +7121,18 @@ enum pchg_state { #define EC_CMD_PCHG_UPDATE 0x0136 /* Port number is encoded in bit[28:31]. */ -#define EC_MKBP_PCHG_PORT_SHIFT 28 +#define EC_MKBP_PCHG_PORT_SHIFT 28 /* Utility macros for converting MKBP event <-> port number. */ -#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) -#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) +#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) +#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) /* Utility macro for extracting event bits. */ -#define EC_MKBP_PCHG_EVENT_MASK(e) ((e) \ - & GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0)) +#define EC_MKBP_PCHG_EVENT_MASK(e) ((e)&GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) -#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) -#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) -#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2) -#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3) -#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4) +#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) +#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) +#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2) +#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3) +#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4) enum ec_pchg_update_cmd { /* Reset chip to normal mode. */ @@ -7079,28 +7167,29 @@ struct ec_params_pchg_update { uint8_t data[]; } __ec_align4; -BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT - < BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd)*8)); +BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT < + BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd) * 8)); struct ec_response_pchg_update { /* Block size */ uint32_t block_size; } __ec_align4; - #define EC_CMD_DISPLAY_SOC 0x0137 struct ec_response_display_soc { - int16_t display_soc; /* Display charge in 10ths of a % (1000=100.0%) */ - int16_t full_factor; /* Full factor in 10ths of a % (1000=100.0%) */ - int16_t shutdown_soc; /* Shutdown SoC in 10ths of a % (1000=100.0%) */ + /* Display charge in 10ths of a % (1000=100.0%) */ + int16_t display_soc; + /* Full factor in 10ths of a % (1000=100.0%) */ + int16_t full_factor; + /* Shutdown SoC in 10ths of a % (1000=100.0%) */ + int16_t shutdown_soc; } __ec_align2; - #define EC_CMD_SET_BASE_STATE 0x0138 struct ec_params_set_base_state { - uint8_t cmd; /* enum ec_set_base_state_cmd */ + uint8_t cmd; /* enum ec_set_base_state_cmd */ } __ec_align1; enum ec_set_base_state_cmd { @@ -7121,8 +7210,8 @@ enum ec_i2c_control_command { #define EC_I2C_CONTROL_SPEED_UNKNOWN 0 struct ec_params_i2c_control { - uint8_t port; /* I2C port number */ - uint8_t cmd; /* enum ec_i2c_control_command */ + uint8_t port; /* I2C port number */ + uint8_t cmd; /* enum ec_i2c_control_command */ union { uint16_t speed_khz; } cmd_params; @@ -7134,12 +7223,12 @@ struct ec_response_i2c_control { } cmd_response; } __ec_align_size1; -#define EC_CMD_RGBKBD_SET_COLOR 0x013A -#define EC_CMD_RGBKBD 0x013B +#define EC_CMD_RGBKBD_SET_COLOR 0x013A +#define EC_CMD_RGBKBD 0x013B -#define EC_RGBKBD_MAX_KEY_COUNT 128 -#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF -#define EC_RGBKBD_MAX_SCALE 0xFF +#define EC_RGBKBD_MAX_KEY_COUNT 128 +#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF +#define EC_RGBKBD_MAX_SCALE 0xFF enum rgbkbd_state { /* RGB keyboard is reset and not initialized. */ @@ -7159,6 +7248,7 @@ enum ec_rgbkbd_subcmd { EC_RGBKBD_SUBCMD_CLEAR = 1, EC_RGBKBD_SUBCMD_DEMO = 2, EC_RGBKBD_SUBCMD_SET_SCALE = 3, + EC_RGBKBD_SUBCMD_GET_CONFIG = 4, EC_RGBKBD_SUBCMD_COUNT }; @@ -7171,20 +7261,37 @@ enum ec_rgbkbd_demo { BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255); +enum ec_rgbkbd_type { + EC_RGBKBD_TYPE_UNKNOWN = 0, + EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */ + EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */ + EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */ + EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS = 4, /* e.g. Mithrax */ + EC_RGBKBD_TYPE_COUNT, +}; + struct ec_rgbkbd_set_scale { uint8_t key; struct rgb_s scale; }; struct ec_params_rgbkbd { - uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */ + uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */ union { - struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */ - uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */ + struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */ + uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */ struct ec_rgbkbd_set_scale set_scale; }; } __ec_align1; +struct ec_response_rgbkbd { + /* + * RGBKBD type supported by the device. + */ + + uint8_t rgbkbd_type; /* enum ec_rgbkbd_type */ +} __ec_align1; + struct ec_params_rgbkbd_set_color { /* Specifies the starting key ID whose color is being changed. */ uint8_t start_key; @@ -7213,49 +7320,44 @@ struct ec_params_rgbkbd_set_color { #define EC_FP_FLAG_NOT_COMPLETE 0x1 struct ec_params_fp_passthru { - uint16_t len; /* Number of bytes to write then read */ - uint16_t flags; /* EC_FP_FLAG_xxx */ - uint8_t data[]; /* Data to send */ + uint16_t len; /* Number of bytes to write then read */ + uint16_t flags; /* EC_FP_FLAG_xxx */ + uint8_t data[]; /* Data to send */ } __ec_align2; /* Configure the Fingerprint MCU behavior */ #define EC_CMD_FP_MODE 0x0402 /* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP BIT(0) +#define FP_MODE_DEEPSLEEP BIT(0) /* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN BIT(1) +#define FP_MODE_FINGER_DOWN BIT(1) /* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP BIT(2) +#define FP_MODE_FINGER_UP BIT(2) /* Capture the current finger image */ -#define FP_MODE_CAPTURE BIT(3) +#define FP_MODE_CAPTURE BIT(3) /* Finger enrollment session on-going */ #define FP_MODE_ENROLL_SESSION BIT(4) /* Enroll the current finger image */ -#define FP_MODE_ENROLL_IMAGE BIT(5) +#define FP_MODE_ENROLL_IMAGE BIT(5) /* Try to match the current finger image */ -#define FP_MODE_MATCH BIT(6) +#define FP_MODE_MATCH BIT(6) /* Reset and re-initialize the sensor. */ -#define FP_MODE_RESET_SENSOR BIT(7) +#define FP_MODE_RESET_SENSOR BIT(7) /* Sensor maintenance for dead pixels. */ #define FP_MODE_SENSOR_MAINTENANCE BIT(8) /* special value: don't change anything just read back current mode */ -#define FP_MODE_DONT_CHANGE BIT(31) - -#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \ - FP_MODE_FINGER_DOWN | \ - FP_MODE_FINGER_UP | \ - FP_MODE_CAPTURE | \ - FP_MODE_ENROLL_SESSION | \ - FP_MODE_ENROLL_IMAGE | \ - FP_MODE_MATCH | \ - FP_MODE_RESET_SENSOR | \ - FP_MODE_SENSOR_MAINTENANCE | \ - FP_MODE_DONT_CHANGE) +#define FP_MODE_DONT_CHANGE BIT(31) + +#define FP_VALID_MODES \ + (FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \ + FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | \ + FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \ + FP_MODE_DONT_CHANGE) /* Capture types defined in bits [30..28] */ #define FP_MODE_CAPTURE_TYPE_SHIFT 28 -#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) +#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) /** * enum fp_capture_type - Specifies the "mode" when capturing images. * @@ -7282,8 +7384,8 @@ enum fp_capture_type { FP_CAPTURE_TYPE_MAX, }; /* Extracts the capture type from the sensor 'mode' word */ -#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \ - >> FP_MODE_CAPTURE_TYPE_SHIFT) +#define FP_CAPTURE_TYPE(mode) \ + (((mode)&FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT) struct ec_params_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ @@ -7297,15 +7399,15 @@ struct ec_response_fp_mode { #define EC_CMD_FP_INFO 0x0403 /* Number of dead pixels detected on the last maintenance */ -#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) +#define FP_ERROR_DEAD_PIXELS(errors) ((errors)&0x3FF) /* Unknown number of dead pixels detected on the last maintenance */ #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) /* No interrupt from the sensor */ -#define FP_ERROR_NO_IRQ BIT(12) +#define FP_ERROR_NO_IRQ BIT(12) /* SPI communication error */ -#define FP_ERROR_SPI_COMM BIT(13) +#define FP_ERROR_SPI_COMM BIT(13) /* Invalid sensor Hardware ID */ -#define FP_ERROR_BAD_HWID BIT(14) +#define FP_ERROR_BAD_HWID BIT(14) /* Sensor initialization failed */ #define FP_ERROR_INIT_FAIL BIT(15) @@ -7338,8 +7440,8 @@ struct ec_response_fp_info { uint16_t bpp; uint16_t errors; /* see FP_ERROR_ flags above */ /* Template/finger current information */ - uint32_t template_size; /* max template size in bytes */ - uint16_t template_max; /* maximum number of fingers/templates */ + uint32_t template_size; /* max template size in bytes */ + uint16_t template_max; /* maximum number of fingers/templates */ uint16_t template_valid; /* number of valid fingers/templates */ uint32_t template_dirty; /* bitmap of templates with MCU side changes */ uint32_t template_version; /* version of the template format */ @@ -7349,13 +7451,13 @@ struct ec_response_fp_info { #define EC_CMD_FP_FRAME 0x0404 /* constants defining the 'offset' field which also contains the frame index */ -#define FP_FRAME_INDEX_SHIFT 28 +#define FP_FRAME_INDEX_SHIFT 28 /* Frame buffer where the captured image is stored */ -#define FP_FRAME_INDEX_RAW_IMAGE 0 +#define FP_FRAME_INDEX_RAW_IMAGE 0 /* First frame buffer holding a template */ -#define FP_FRAME_INDEX_TEMPLATE 1 +#define FP_FRAME_INDEX_TEMPLATE 1 #define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) -#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF +#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF /* Version of the format of the encrypted templates. */ #define FP_TEMPLATE_FORMAT_VERSION 4 @@ -7422,14 +7524,14 @@ enum fp_context_action { /* Version 1 of the command is "asynchronous". */ struct ec_params_fp_context_v1 { - uint8_t action; /**< enum fp_context_action */ - uint8_t reserved[3]; /**< padding for alignment */ + uint8_t action; /**< enum fp_context_action */ + uint8_t reserved[3]; /**< padding for alignment */ uint32_t userid[FP_CONTEXT_USERID_WORDS]; } __ec_align4; #define EC_CMD_FP_STATS 0x0407 -#define FPSTATS_CAPTURE_INV BIT(0) +#define FPSTATS_CAPTURE_INV BIT(0) #define FPSTATS_MATCHING_INV BIT(1) struct ec_response_fp_stats { @@ -7699,14 +7801,14 @@ struct ec_params_usb_pd_mux_ack { * switch to the new names soon, as the old names may not be carried forward * forever. */ -#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE -#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 -#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE +#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE +#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 +#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE -#endif /* !__ACPI__ */ +#endif /* !__ACPI__ */ #ifdef __cplusplus } #endif -#endif /* __CROS_EC_EC_COMMANDS_H */ +#endif /* __CROS_EC_EC_COMMANDS_H */ diff --git a/include/ec_ec_comm_client.h b/include/ec_ec_comm_client.h index 9a60daffe4..9b506dd402 100644 --- a/include/ec_ec_comm_client.h +++ b/include/ec_ec_comm_client.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -42,8 +42,7 @@ int ec_ec_client_base_get_static_info(void); * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error, * else forwards the error code from the server. */ -int ec_ec_client_base_charge_control(int max_current, - int otg_voltage, +int ec_ec_client_base_charge_control(int max_current, int otg_voltage, int allow_charging); /** diff --git a/include/ec_ec_comm_server.h b/include/ec_ec_comm_server.h index 1ed5588666..0eb094fea3 100644 --- a/include/ec_ec_comm_server.h +++ b/include/ec_ec_comm_server.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/eeprom.h b/include/eeprom.h index 368491c959..41e464c1f5 100644 --- a/include/eeprom.h +++ b/include/eeprom.h @@ -1,4 +1,4 @@ -/* Copyright 2011 The Chromium OS Authors. All rights reserved. +/* Copyright 2011 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -52,4 +52,4 @@ int eeprom_write(int block, int offset, int size, const char *data); */ int eeprom_hide(int block); -#endif /* __CROS_EC_EEPROM_H */ +#endif /* __CROS_EC_EEPROM_H */ diff --git a/include/espi.h b/include/espi.h index a717e7e414..4768d8f12f 100644 --- a/include/espi.h +++ b/include/espi.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,29 +14,29 @@ enum espi_vw_signal { /* The first valid VW signal is 0x2000 */ VW_SIGNAL_START = IOEX_LIMIT + 1, - VW_SLP_S3_L = VW_SIGNAL_START, /* index 02h (In) */ + VW_SLP_S3_L = VW_SIGNAL_START, /* index 02h (In) */ VW_SLP_S4_L, VW_SLP_S5_L, - VW_SUS_STAT_L, /* index 03h (In) */ + VW_SUS_STAT_L, /* index 03h (In) */ VW_PLTRST_L, VW_OOB_RST_WARN, - VW_OOB_RST_ACK, /* index 04h (Out) */ + VW_OOB_RST_ACK, /* index 04h (Out) */ VW_WAKE_L, VW_PME_L, - VW_ERROR_FATAL, /* index 05h (Out) */ + VW_ERROR_FATAL, /* index 05h (Out) */ VW_ERROR_NON_FATAL, /* Merge bit 3/0 into one signal. Need to set them simultaneously */ VW_PERIPHERAL_BTLD_STATUS_DONE, - VW_SCI_L, /* index 06h (Out) */ + VW_SCI_L, /* index 06h (Out) */ VW_SMI_L, VW_RCIN_L, VW_HOST_RST_ACK, - VW_HOST_RST_WARN, /* index 07h (In) */ - VW_SUS_ACK, /* index 40h (Out) */ - VW_SUS_WARN_L, /* index 41h (In) */ + VW_HOST_RST_WARN, /* index 07h (In) */ + VW_SUS_ACK, /* index 40h (Out) */ + VW_SUS_WARN_L, /* index 41h (In) */ VW_SUS_PWRDN_ACK_L, VW_SLP_A_L, - VW_SLP_LAN, /* index 42h (In) */ + VW_SLP_LAN, /* index 42h (In) */ VW_SLP_WLAN, VW_SIGNAL_END, VW_LIMIT = 0x2FFF @@ -99,6 +99,6 @@ int espi_signal_is_vw(int signal); * @param timeout max time in microseconds to poll. */ void espi_wait_vw_not_dirty(enum espi_vw_signal signal, - unsigned int timeout_us); + unsigned int timeout_us); -#endif /* __CROS_EC_ESPI_H */ +#endif /* __CROS_EC_ESPI_H */ diff --git a/include/event_log.h b/include/event_log.h index 45b10a3a2d..bd3b88510b 100644 --- a/include/event_log.h +++ b/include/event_log.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,14 +8,14 @@ struct event_log_entry { uint32_t timestamp; /* relative timestamp in milliseconds */ - uint8_t type; /* event type, caller-defined */ - uint8_t size; /* [7:5] caller-def'd [4:0] payload size in bytes */ - uint16_t data; /* type-defined data payload */ + uint8_t type; /* event type, caller-defined */ + uint8_t size; /* [7:5] caller-def'd [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ } __packed; -#define EVENT_LOG_SIZE_MASK 0x1f -#define EVENT_LOG_SIZE(size) ((size) & EVENT_LOG_SIZE_MASK) +#define EVENT_LOG_SIZE_MASK 0x1f +#define EVENT_LOG_SIZE(size) ((size)&EVENT_LOG_SIZE_MASK) /* The timestamp is the microsecond counter shifted to get about a ms. */ #define EVENT_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ @@ -23,8 +23,8 @@ struct event_log_entry { #define EVENT_LOG_NO_ENTRY 0xff /* Add an entry to the event log. */ -void log_add_event(uint8_t type, uint8_t size, uint16_t data, - void *payload, uint32_t timestamp); +void log_add_event(uint8_t type, uint8_t size, uint16_t data, void *payload, + uint32_t timestamp); /* * Remove and return an entry from the event log, if available. diff --git a/include/extpower.h b/include/extpower.h index 1e9f7976e6..08bec3f0bc 100644 --- a/include/extpower.h +++ b/include/extpower.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,7 +10,7 @@ #include "common.h" -enum gpio_signal; /* from gpio_signal.h */ +enum gpio_signal; /* from gpio_signal.h */ /** * Run board specific code to update extpower status. The default @@ -21,7 +21,7 @@ __override_proto void board_check_extpower(void); /** * Return non-zero if external power is present. */ -int extpower_is_present(void); +test_mockable int extpower_is_present(void); /** * Interrupt handler for external power GPIOs. @@ -37,4 +37,4 @@ void extpower_interrupt(enum gpio_signal signal); */ void extpower_handle_update(int is_present); -#endif /* __CROS_EC_EXTPOWER_H */ +#endif /* __CROS_EC_EXTPOWER_H */ diff --git a/include/fan.h b/include/fan.h index 87c8f4b7a6..946d0607c9 100644 --- a/include/fan.h +++ b/include/fan.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,7 +17,7 @@ enum fan_channel { #if DT_NODE_EXISTS(DT_INST(0, cros_ec_fans)) DT_FOREACH_CHILD(DT_INST(0, cros_ec_fans), NODE_ID_AND_COMMA) #endif /* cros_ec_fans */ - FAN_CH_COUNT + FAN_CH_COUNT }; BUILD_ASSERT(FAN_CH_COUNT == CONFIG_PLATFORM_EC_NUM_FANS); @@ -50,7 +50,7 @@ struct fan_t { /* Values for .flags field */ /* Enable automatic RPM control using tach input */ -#define FAN_USE_RPM_MODE BIT(0) +#define FAN_USE_RPM_MODE BIT(0) /* Require a higher duty cycle to start up than to keep running */ #define FAN_USE_FAST_START BIT(1) @@ -62,7 +62,7 @@ extern const struct fan_t fans[]; #endif /* For convenience */ -#define FAN_CH(fan) fans[fan].conf->ch +#define FAN_CH(fan) fans[fan].conf->ch /** * Set the amount of active cooling needed. The thermal control task will call @@ -84,7 +84,6 @@ void fan_set_percent_needed(int fan, int pct); */ int fan_percent_to_rpm(int fan, int pct); - /** * These functions require chip-specific implementations. */ @@ -143,4 +142,4 @@ void fan_set_count(int count); int is_thermal_control_enabled(int idx); -#endif /* __CROS_EC_FAN_H */ +#endif /* __CROS_EC_FAN_H */ diff --git a/include/flash.h b/include/flash.h index 240ab0369b..5df6afdb09 100644 --- a/include/flash.h +++ b/include/flash.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,11 +9,11 @@ #define __CROS_EC_FLASH_H #include "common.h" -#include "ec_commands.h" /* For EC_FLASH_PROTECT_* flags */ +#include "ec_commands.h" /* For EC_FLASH_PROTECT_* flags */ #ifdef CONFIG_FLASH_MULTIPLE_REGION -extern struct ec_flash_bank const flash_bank_array[ - CONFIG_FLASH_REGION_TYPE_COUNT]; +extern struct ec_flash_bank const + flash_bank_array[CONFIG_FLASH_REGION_TYPE_COUNT]; /* * Return the bank the offset is in. @@ -51,25 +51,25 @@ int crec_flash_bank_start_offset(int bank); int crec_flash_bank_erase_size(int bank); /* Number of physical flash banks */ -#define PHYSICAL_BANKS CONFIG_FLASH_MULTIPLE_REGION +#define PHYSICAL_BANKS CONFIG_FLASH_MULTIPLE_REGION /* WP region offset and size in units of flash banks */ -#define WP_BANK_OFFSET crec_flash_bank_index(CONFIG_WP_STORAGE_OFF) +#define WP_BANK_OFFSET crec_flash_bank_index(CONFIG_WP_STORAGE_OFF) #define WP_BANK_COUNT \ (crec_flash_bank_count(CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE)) -#else /* CONFIG_FLASH_MULTIPLE_REGION */ +#else /* CONFIG_FLASH_MULTIPLE_REGION */ /* Number of physical flash banks */ #ifndef PHYSICAL_BANKS #define PHYSICAL_BANKS (CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE) #endif /* WP region offset and size in units of flash banks */ -#define WP_BANK_OFFSET (CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE) +#define WP_BANK_OFFSET (CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE) #ifndef WP_BANK_COUNT -#define WP_BANK_COUNT (CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE) +#define WP_BANK_COUNT (CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE) #endif -#endif /* CONFIG_FLASH_MULTIPLE_REGION */ +#endif /* CONFIG_FLASH_MULTIPLE_REGION */ /* Persistent protection state flash offset / size / bank */ #if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK) @@ -82,33 +82,33 @@ int crec_flash_bank_erase_size(int bank); * When there is a dedicated flash bank used to store persistent state, * ensure the RO flash region excludes the PSTATE bank. */ -#define EC_FLASH_REGION_RO_SIZE CONFIG_RO_SIZE +#define EC_FLASH_REGION_RO_SIZE CONFIG_RO_SIZE #ifndef PSTATE_BANK -#define PSTATE_BANK (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE) +#define PSTATE_BANK (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE) #endif #ifndef PSTATE_BANK_COUNT -#define PSTATE_BANK_COUNT (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE) +#define PSTATE_BANK_COUNT (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE) #endif -#else /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ +#else /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ /* Allow flashrom to program the entire write protected area */ -#define EC_FLASH_REGION_RO_SIZE CONFIG_WP_STORAGE_SIZE -#define PSTATE_BANK_COUNT 0 -#endif /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ +#define EC_FLASH_REGION_RO_SIZE CONFIG_WP_STORAGE_SIZE +#define PSTATE_BANK_COUNT 0 +#endif /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ #ifdef CONFIG_ROLLBACK /* * ROLLBACK region offset and size in units of flash banks. */ #ifdef CONFIG_FLASH_MULTIPLE_REGION -#define ROLLBACK_BANK_OFFSET crec_flash_bank_index(CONFIG_ROLLBACK_OFF) -#define ROLLBACK_BANK_COUNT \ +#define ROLLBACK_BANK_OFFSET crec_flash_bank_index(CONFIG_ROLLBACK_OFF) +#define ROLLBACK_BANK_COUNT \ crec_flash_bank_count(CONFIG_ROLLBACK_OFF, CONFIG_ROLLBACK_SIZE) #else -#define ROLLBACK_BANK_OFFSET (CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE) -#define ROLLBACK_BANK_COUNT (CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE) -#endif /* CONFIG_FLASH_MULTIPLE_REGION */ -#endif /* CONFIG_ROLLBACK */ +#define ROLLBACK_BANK_OFFSET (CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE) +#define ROLLBACK_BANK_COUNT (CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE) +#endif /* CONFIG_FLASH_MULTIPLE_REGION */ +#endif /* CONFIG_ROLLBACK */ /* This enum is useful to identify different regions during verification. */ enum flash_region { @@ -378,7 +378,7 @@ int crec_flash_write_pstate_mac_addr(const char *mac_addr); #ifdef CONFIG_EXTERNAL_STORAGE void crec_flash_lock_mapped_storage(int lock); #else -static inline void crec_flash_lock_mapped_storage(int lock) { }; +static inline void crec_flash_lock_mapped_storage(int lock){}; #endif /* CONFIG_EXTERNAL_STORAGE */ /** @@ -390,4 +390,4 @@ static inline void crec_flash_lock_mapped_storage(int lock) { }; */ int crec_board_flash_select(int select); -#endif /* __CROS_EC_FLASH_H */ +#endif /* __CROS_EC_FLASH_H */ diff --git a/include/flash_log.h b/include/flash_log.h index e504df6ee7..7141a8b67a 100644 --- a/include/flash_log.h +++ b/include/flash_log.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,10 +16,10 @@ enum flash_event_type { FE_LOG_CORRUPTED = 1, FE_TPM_I2C_ERROR = 2, FE_LOG_OVERFLOWS = 3, /* A single byte, overflow counter. */ - FE_LOG_LOCKS = 4, /* A single byte, lock failures counter. */ - FE_LOG_NVMEM = 5, /* NVMEM failure, variable structure. */ - FE_LOG_TPM_WIPE_ERROR = 6, /* Failed to wipe the TPM */ - FE_LOG_TRNG_STALL = 7, /* Stall while retrieving a random number. */ + FE_LOG_LOCKS = 4, /* A single byte, lock failures counter. */ + FE_LOG_NVMEM = 5, /* NVMEM failure, variable structure. */ + FE_LOG_TPM_WIPE_ERROR = 6, /* Failed to wipe the TPM */ + FE_LOG_TRNG_STALL = 7, /* Stall while retrieving a random number. */ FE_LOG_DCRYPTO_FAILURE = 8, /* Dcrypto had to be reset. */ /* @@ -92,9 +92,9 @@ struct nvmem_failure_payload { #define FLASH_LOG_PAYLOAD_SIZE(size) ((size)&FLASH_LOG_PAYLOAD_SIZE_MASK) /* Size of log entry for a specific payload size. */ -#define FLASH_LOG_ENTRY_SIZE(payload_sz) \ - ((FLASH_LOG_PAYLOAD_SIZE(payload_sz) + \ - sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) & \ +#define FLASH_LOG_ENTRY_SIZE(payload_sz) \ + ((FLASH_LOG_PAYLOAD_SIZE(payload_sz) + \ + sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) & \ ~(CONFIG_FLASH_WRITE_SIZE - 1)) /* diff --git a/include/fpsensor.h b/include/fpsensor.h index 8efc4a7006..3963df86a7 100644 --- a/include/fpsensor.h +++ b/include/fpsensor.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,8 +17,9 @@ #endif /* Four-character-code */ -#define FOURCC(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ - ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) +#define FOURCC(a, b, c, d) \ + ((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | \ + ((uint32_t)(d) << 24)) /* 8-bit greyscale pixel format as defined by V4L2 headers */ #define V4L2_PIX_FMT_GREY FOURCC('G', 'R', 'E', 'Y') diff --git a/include/fpsensor_crypto.h b/include/fpsensor_crypto.h index b6252b3fd2..7dff9238fa 100644 --- a/include/fpsensor_crypto.h +++ b/include/fpsensor_crypto.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -67,11 +67,9 @@ int derive_positive_match_secret(uint8_t *output, * @param tag_size the size of |tag|. * @return EC_SUCCESS on success and error code otherwise. */ -int aes_gcm_encrypt(const uint8_t *key, int key_size, - const uint8_t *plaintext, - uint8_t *ciphertext, int text_size, - const uint8_t *nonce, int nonce_size, - uint8_t *tag, int tag_size); +int aes_gcm_encrypt(const uint8_t *key, int key_size, const uint8_t *plaintext, + uint8_t *ciphertext, int text_size, const uint8_t *nonce, + int nonce_size, uint8_t *tag, int tag_size); /** * Decrypt |plaintext| using AES-GCM128. @@ -89,7 +87,7 @@ int aes_gcm_encrypt(const uint8_t *key, int key_size, */ int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext, const uint8_t *ciphertext, int text_size, - const uint8_t *nonce, int nonce_size, - const uint8_t *tag, int tag_size); + const uint8_t *nonce, int nonce_size, const uint8_t *tag, + int tag_size); #endif /* __CROS_EC_FPSENSOR_CRYPTO_H */ diff --git a/include/fpsensor_detect.h b/include/fpsensor_detect.h index 56e04d4ae6..e542223954 100644 --- a/include/fpsensor_detect.h +++ b/include/fpsensor_detect.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/fpsensor_state.h b/include/fpsensor_state.h index 98d5b63783..ce454233fa 100644 --- a/include/fpsensor_state.h +++ b/include/fpsensor_state.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,14 +28,13 @@ #endif #define SBP_ENC_KEY_LEN 16 -#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \ - (FP_ALGORITHM_TEMPLATE_SIZE + \ - FP_POSITIVE_MATCH_SALT_BYTES + \ - sizeof(struct ec_fp_template_encryption_metadata)) +#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \ + (FP_ALGORITHM_TEMPLATE_SIZE + FP_POSITIVE_MATCH_SALT_BYTES + \ + sizeof(struct ec_fp_template_encryption_metadata)) /* Events for the FPSENSOR task */ -#define TASK_EVENT_SENSOR_IRQ TASK_EVENT_CUSTOM_BIT(0) -#define TASK_EVENT_UPDATE_CONFIG TASK_EVENT_CUSTOM_BIT(1) +#define TASK_EVENT_SENSOR_IRQ TASK_EVENT_CUSTOM_BIT(0) +#define TASK_EVENT_UPDATE_CONFIG TASK_EVENT_CUSTOM_BIT(1) #define FP_NO_SUCH_TEMPLATE -1 @@ -53,8 +52,8 @@ extern uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE]; */ extern uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE]; /* Salt used in derivation of positive match secret. */ -extern uint8_t fp_positive_match_salt - [FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES]; +extern uint8_t fp_positive_match_salt[FP_MAX_FINGER_COUNT] + [FP_POSITIVE_MATCH_SALT_BYTES]; /* Index of the last enrolled but not retrieved template. */ extern int8_t template_newly_enrolled; /* Number of used templates */ @@ -118,7 +117,7 @@ int fp_tpm_seed_is_set(void); * @param mode_output resulting mode * @return EC_RES_SUCCESS on success. Error code on failure. */ -int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output); +enum ec_status fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output); /** * Allow reading positive match secret for |fgr| in the next 5 seconds. @@ -128,14 +127,13 @@ int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output); * @return EC_SUCCESS if the request is valid, error code otherwise. */ int fp_enable_positive_match_secret(uint32_t fgr, - struct positive_match_secret_state *state); + struct positive_match_secret_state *state); /** * Disallow positive match secret for any finger to be read. * * @param state the state of positive match secret, e.g. readable or not. */ -void fp_disable_positive_match_secret( - struct positive_match_secret_state *state); +void fp_disable_positive_match_secret(struct positive_match_secret_state *state); #endif /* __CROS_EC_FPSENSOR_STATE_H */ diff --git a/include/gesture.h b/include/gesture.h index bc0186887c..8744f3efcd 100644 --- a/include/gesture.h +++ b/include/gesture.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/gpio.h b/include/gpio.h index 4d827eb3cc..54464d1bfb 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -57,14 +57,14 @@ * Map the legacy EC GPIO flags to the Zephyr equivalent. * Refer to the descriptions below. */ -#define GPIO_FLAG_NONE GPIO_DISCONNECTED +#define GPIO_FLAG_NONE GPIO_DISCONNECTED /* GPIO_ANALOG not supported by Zephyr */ /* GPIO_OPEN_DRAIN already defined by Zephyr */ /* GPIO_DEFAULT not supported by Zephyr */ /* GPIO_PULL_UP already defined by Zephyr */ /* GPIO_PULL_DOWN already defined by Zephyr */ -#define GPIO_LOW GPIO_OUTPUT_INIT_LOW -#define GPIO_HIGH GPIO_OUTPUT_INIT_HIGH +#define GPIO_LOW GPIO_OUTPUT_INIT_LOW +#define GPIO_HIGH GPIO_OUTPUT_INIT_HIGH /* GPIO_INPUT already defined by Zephyr */ /* GPIO_OUTPUT already defined by Zephyr */ @@ -72,14 +72,14 @@ * One to one mapping of interrupt flags isn't possible. So map these * flags to not conflict with any Zephyr flags. */ -#define GPIO_INT_F_RISING BIT(28) +#define GPIO_INT_F_RISING BIT(28) #define GPIO_INT_F_FALLING BIT(29) -#define GPIO_INT_F_LOW BIT(30) -#define GPIO_INT_F_HIGH BIT(31) +#define GPIO_INT_F_LOW BIT(30) +#define GPIO_INT_F_HIGH BIT(31) /* GPIO_INT_DSLEEP not supported by Zephyr */ /* GPIO_INT_SHARED not supported by Zephyr */ -#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8 +#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8 /* GPIO_ALTERNATE not supported by Zephyr */ /* GPIO_LOCKED not supported by Zephyr */ /* GPIO_HIB_WAKE_HIGH not supported by Zephyr */ @@ -98,51 +98,52 @@ * GPIO_PULL_DOWN * GPIO_PULL_ANALOG */ -#define GPIO_FLAG_NONE 0 /* No flag needed, default setting */ -#define GPIO_ANALOG BIT(0) /* Set pin to analog-mode */ -#define GPIO_OPEN_DRAIN (BIT(1) | BIT(2)) /* Output type is open-drain */ -#define GPIO_DEFAULT BIT(3) /* Don't set up on boot */ -#define GPIO_PULL_UP BIT(4) /* Enable on-chip pullup */ -#define GPIO_PULL_DOWN BIT(5) /* Enable on-chip pulldown */ -#define GPIO_LOW BIT(6) /* If GPIO_OUTPUT, set level low */ -#define GPIO_HIGH BIT(7) /* If GPIO_OUTPUT, set level high */ -#define GPIO_INPUT BIT(8) /* Input */ -#define GPIO_OUTPUT BIT(9) /* Output */ -#define GPIO_INT_F_RISING BIT(10) /* Interrupt on rising edge */ +#define GPIO_FLAG_NONE 0 /* No flag needed, default setting */ +#define GPIO_ANALOG BIT(0) /* Set pin to analog-mode */ +#define GPIO_OPEN_DRAIN (BIT(1) | BIT(2)) /* Output type is open-drain */ +#define GPIO_DEFAULT BIT(3) /* Don't set up on boot */ +#define GPIO_PULL_UP BIT(4) /* Enable on-chip pullup */ +#define GPIO_PULL_DOWN BIT(5) /* Enable on-chip pulldown */ +#define GPIO_LOW BIT(6) /* If GPIO_OUTPUT, set level low */ +#define GPIO_HIGH BIT(7) /* If GPIO_OUTPUT, set level high */ +#define GPIO_INPUT BIT(8) /* Input */ +#define GPIO_OUTPUT BIT(9) /* Output */ +#define GPIO_INT_F_RISING BIT(10) /* Interrupt on rising edge */ #define GPIO_INT_F_FALLING BIT(11) /* Interrupt on falling edge */ -#define GPIO_INT_F_LOW BIT(12) /* Interrupt on low level */ -#define GPIO_INT_F_HIGH BIT(13) /* Interrupt on high level */ -#define GPIO_INT_DSLEEP BIT(14) /* Interrupt in deep sleep */ -#define GPIO_INT_SHARED BIT(15) /* Shared among multiple pins */ -#define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */ -#define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */ -#define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */ -#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */ -#define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */ -#define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */ +#define GPIO_INT_F_LOW BIT(12) /* Interrupt on low level */ +#define GPIO_INT_F_HIGH BIT(13) /* Interrupt on high level */ +#define GPIO_INT_DSLEEP BIT(14) /* Interrupt in deep sleep */ +#define GPIO_INT_SHARED BIT(15) /* Shared among multiple pins */ +#define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */ +#define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */ +#define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */ +#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */ +#define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */ +#define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */ #define GPIO_HIB_WAKE_FALLING BIT(22) /* Hibernate wake on falling edge */ #ifdef CONFIG_GPIO_POWER_DOWN -#define GPIO_POWER_DOWN BIT(23) /* Pin and pad is powered off */ +#define GPIO_POWER_DOWN BIT(23) /* Pin and pad is powered off */ #endif #endif /* CONFIG_ZEPHYR */ /* Common flag combinations */ -#define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) -#define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH) -#define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH) -#define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW) -#define GPIO_INT_RISING (GPIO_INPUT | GPIO_INT_F_RISING) -#define GPIO_INT_FALLING (GPIO_INPUT | GPIO_INT_F_FALLING) +#define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) +#define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH) +#define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH) +#define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW) +#define GPIO_INT_RISING (GPIO_INPUT | GPIO_INT_F_RISING) +#define GPIO_INT_FALLING (GPIO_INPUT | GPIO_INT_F_FALLING) /* TODO(crosbug.com/p/24204): "EDGE" would have been clearer than "BOTH". */ -#define GPIO_INT_BOTH (GPIO_INT_RISING | GPIO_INT_FALLING) -#define GPIO_INT_LOW (GPIO_INPUT | GPIO_INT_F_LOW) -#define GPIO_INT_HIGH (GPIO_INPUT | GPIO_INT_F_HIGH) -#define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH) -#define GPIO_INT_ANY (GPIO_INT_BOTH | GPIO_INT_LEVEL) +#define GPIO_INT_BOTH (GPIO_INT_RISING | GPIO_INT_FALLING) +#define GPIO_INT_LOW (GPIO_INPUT | GPIO_INT_F_LOW) +#define GPIO_INT_HIGH (GPIO_INPUT | GPIO_INT_F_HIGH) +#define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH) +#define GPIO_INT_ANY (GPIO_INT_BOTH | GPIO_INT_LEVEL) #define GPIO_INT_BOTH_DSLEEP (GPIO_INT_BOTH | GPIO_INT_DSLEEP) -#define GPIO_HIB_WAKE_MASK (GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | \ - GPIO_HIB_WAKE_RISING|GPIO_HIB_WAKE_FALLING) +#define GPIO_HIB_WAKE_MASK \ + (GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | GPIO_HIB_WAKE_RISING | \ + GPIO_HIB_WAKE_FALLING) /* Convert GPIO mask to GPIO number / index. */ #define GPIO_MASK_TO_NUM(mask) (__fls(mask)) @@ -151,9 +152,7 @@ * some boards and unit tests don't have a gpio_signal enum defined, so we * define an emtpy one here.*/ #ifndef __CROS_EC_GPIO_SIGNAL_H -enum gpio_signal { - GPIO_COUNT -}; +enum gpio_signal { GPIO_COUNT }; #endif /* __CROS_EC_GPIO_SIGNAL_H */ /* Alternate functions for GPIOs */ @@ -207,7 +206,7 @@ extern const int unused_pin_count; * If the signal's interrupt is enabled, this will be called in the * context of the GPIO interrupt handler. */ -extern void (* const gpio_irq_handlers[])(enum gpio_signal signal); +extern void (*const gpio_irq_handlers[])(enum gpio_signal signal); extern const int gpio_ih_count; #define GPIO_IH_COUNT gpio_ih_count @@ -440,7 +439,6 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal); */ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags); - /** * Set alternate function for GPIO(s). * @@ -454,7 +452,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags); * the specified GPIOs for normal GPIO operation. */ void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func); + enum gpio_alternate_func func); #ifdef CONFIG_GPIO_POWER_DOWN /** @@ -486,4 +484,4 @@ int signal_is_gpio(int signal); */ void gpio_set_wakepin(enum gpio_signal signal, uint32_t flags); -#endif /* __CROS_EC_GPIO_H */ +#endif /* __CROS_EC_GPIO_H */ diff --git a/include/gpio.wrap b/include/gpio.wrap index d03f8a9588..84055d3ba3 100644 --- a/include/gpio.wrap +++ b/include/gpio.wrap @@ -1,6 +1,6 @@ /* -*- mode:c -*- * - * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/gpio_list.h b/include/gpio_list.h index 6bd43187d9..17fc0d3b09 100644 --- a/include/gpio_list.h +++ b/include/gpio_list.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,35 +8,35 @@ #include "gpio_signal.h" #ifdef CONFIG_COMMON_GPIO_SHORTNAMES -#define GPIO(name, pin, flags) {GPIO_NAME_BY_##pin, GPIO_##pin, flags}, +#define GPIO(name, pin, flags) { GPIO_NAME_BY_##pin, GPIO_##pin, flags }, #define GPIO_INT(name, pin, flags, signal) \ - {GPIO_NAME_BY_##pin, GPIO_##pin, flags}, + { GPIO_NAME_BY_##pin, GPIO_##pin, flags }, #else -#define GPIO(name, pin, flags) {#name, GPIO_##pin, flags}, -#define GPIO_INT(name, pin, flags, signal) {#name, GPIO_##pin, flags}, +#define GPIO(name, pin, flags) { #name, GPIO_##pin, flags }, +#define GPIO_INT(name, pin, flags, signal) { #name, GPIO_##pin, flags }, #endif -#define UNIMPLEMENTED(name) {#name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT}, +#define UNIMPLEMENTED(name) { #name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT }, /* GPIO signal list. */ __const_data const struct gpio_info gpio_list[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; BUILD_ASSERT(ARRAY_SIZE(gpio_list) == GPIO_COUNT); -#define UNUSED(pin) {GPIO_##pin}, +#define UNUSED(pin) { GPIO_##pin }, /* Unconnected pin list. */ __const_data const struct unused_pin_info unused_pin_list[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; const int unused_pin_count = ARRAY_SIZE(unused_pin_list); /* GPIO Interrupt Handlers */ #define GPIO_INT(name, pin, flags, signal) signal, -void (* const gpio_irq_handlers[])(enum gpio_signal signal) = { - #include "gpio.wrap" +void (*const gpio_irq_handlers[])(enum gpio_signal signal) = { +#include "gpio.wrap" }; const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); @@ -47,7 +47,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * * This constraint is handled within gpio.wrap. */ -#define GPIO_INT(name, pin, flags, signal) \ +#define GPIO_INT(name, pin, flags, signal) \ BUILD_ASSERT(GPIO_##name < ARRAY_SIZE(gpio_irq_handlers)); #include "gpio.wrap" @@ -64,8 +64,9 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * The compiler will complain if we use the same name twice. The linker ignores * anything that gets by. */ -#define PIN(a, b...) static const int _pin_ ## a ## _ ## b \ - __attribute__((unused, section(".unused"))) = __LINE__; +#define PIN(a, b...) \ + static const int _pin_##a##_##b \ + __attribute__((unused, section(".unused"))) = __LINE__; #include "gpio.wrap" #include "ioexpander.h" @@ -83,7 +84,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * - flags: the same as the flags of GPIO. * */ -#define IOEX(name, expin, flags) {#name, IOEX_##expin, flags}, +#define IOEX(name, expin, flags) { #name, IOEX_##expin, flags }, /* * Define the IO expander IO which supports interrupt in gpio.inc by * the format: @@ -97,18 +98,18 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * - flags: the same as the flags of GPIO. * - handler: the IOEX IO's interrupt handler. */ -#define IOEX_INT(name, expin, flags, handler) {#name, IOEX_##expin, flags}, +#define IOEX_INT(name, expin, flags, handler) { #name, IOEX_##expin, flags }, /* IO expander signal list. */ const struct ioex_info ioex_list[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; BUILD_ASSERT(ARRAY_SIZE(ioex_list) == IOEX_COUNT); /* IO Expander Interrupt Handlers */ #define IOEX_INT(name, expin, flags, handler) handler, -void (* const ioex_irq_handlers[])(enum ioex_signal signal) = { - #include "gpio.wrap" +void (*const ioex_irq_handlers[])(enum ioex_signal signal) = { +#include "gpio.wrap" }; const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers); /* @@ -116,9 +117,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers); * IOEX's declaration in the gpio.inc * file. */ -#define IOEX_INT(name, expin, flags, handler) \ - BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START \ - < ARRAY_SIZE(ioex_irq_handlers)); +#define IOEX_INT(name, expin, flags, handler) \ + BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START < \ + ARRAY_SIZE(ioex_irq_handlers)); #include "gpio.wrap" #define IOEX(name, expin, flags) expin @@ -128,9 +129,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers); * number declared is greater or equal to CONFIG_IO_EXPANDER_PORT_COUNT. * The linker ignores anything that gets by. */ -#define EXPIN(a, b, c...) \ - static const int _expin_ ## a ## _ ## b ## _ ## c \ - __attribute__((unused, section(".unused"))) = __LINE__; \ +#define EXPIN(a, b, c...) \ + static const int _expin_##a##_##b##_##c \ + __attribute__((unused, section(".unused"))) = __LINE__; \ BUILD_ASSERT(a < CONFIG_IO_EXPANDER_PORT_COUNT); #include "gpio.wrap" diff --git a/include/gpio_signal.h b/include/gpio_signal.h index 86fd5d7822..a499108b40 100644 --- a/include/gpio_signal.h +++ b/include/gpio_signal.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -27,7 +27,7 @@ #define GPIO_SIGNAL_START 0 /* The first valid GPIO signal is 0 */ enum gpio_signal { - #include "gpio.wrap" +#include "gpio.wrap" GPIO_COUNT, /* Ensure that sizeof gpio_signal is large enough for ioex_signal */ GPIO_LIMIT = 0x0FFF @@ -42,7 +42,7 @@ enum ioex_signal { IOEX_SIGNAL_START = GPIO_LIMIT + 1, /* Used to ensure that the first IOEX signal is same as start */ __IOEX_PLACEHOLDER = GPIO_LIMIT, - #include "gpio.wrap" +#include "gpio.wrap" IOEX_SIGNAL_END, IOEX_LIMIT = 0x1FFF }; diff --git a/include/gyro_cal.h b/include/gyro_cal.h index fb69464aec..fe48d71360 100644 --- a/include/gyro_cal.h +++ b/include/gyro_cal.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/gyro_still_det.h b/include/gyro_still_det.h index a776da7ae7..a0332d598a 100644 --- a/include/gyro_still_det.h +++ b/include/gyro_still_det.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/hooks.h b/include/hooks.h index e629ffbd9b..1002c7c93d 100644 --- a/include/hooks.h +++ b/include/hooks.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,12 +12,12 @@ enum hook_priority { /* Generic values across all hooks */ - HOOK_PRIO_FIRST = 1, /* Highest priority */ + HOOK_PRIO_FIRST = 1, /* Highest priority */ HOOK_PRIO_POST_FIRST = HOOK_PRIO_FIRST + 1, - HOOK_PRIO_DEFAULT = 5000, /* Default priority */ + HOOK_PRIO_DEFAULT = 5000, /* Default priority */ HOOK_PRIO_PRE_DEFAULT = HOOK_PRIO_DEFAULT - 1, HOOK_PRIO_POST_DEFAULT = HOOK_PRIO_DEFAULT + 1, - HOOK_PRIO_LAST = 9999, /* Lowest priority */ + HOOK_PRIO_LAST = 9999, /* Lowest priority */ /* Specific hook vales for HOOK_INIT */ /* DMA inits before ADC, I2C, SPI */ @@ -253,6 +253,11 @@ enum hook_type { */ HOOK_USB_PD_CONNECT, + /* + * Power supply change event. + */ + HOOK_POWER_SUPPLY_CHANGE, + #ifdef TEST_BUILD /* * Special hook types to be used by unit tests of the hooks @@ -261,7 +266,7 @@ enum hook_type { HOOK_TEST_1, HOOK_TEST_2, HOOK_TEST_3, -#endif /* TEST_BUILD */ +#endif /* TEST_BUILD */ /* * Not a hook type (instead the number of hooks). This should @@ -346,11 +351,12 @@ int hook_call_deferred(const struct deferred_data *data, int us); * unless there's a compelling reason to care about the * order in which hooks are called. */ -#define DECLARE_HOOK(hooktype, routine, priority) \ - const struct hook_data __keep __no_sanitize_address \ - CONCAT4(__hook_, hooktype, _, routine) \ - __attribute__((section(".rodata." STRINGIFY(hooktype)))) \ - = {routine, priority} +#define DECLARE_HOOK(hooktype, routine, priority) \ + const struct hook_data __keep __no_sanitize_address CONCAT4( \ + __hook_, hooktype, _, routine) \ + __attribute__((section(".rodata." STRINGIFY(hooktype)))) = { \ + routine, priority \ + } /** * Register a deferred function call. @@ -371,21 +377,26 @@ int hook_call_deferred(const struct deferred_data *data, int us); * * @param routine Function pointer, with prototype void routine(void) */ -#define DECLARE_DEFERRED(routine) \ - const struct deferred_data __keep __no_sanitize_address \ - CONCAT2(routine, _data) \ - __attribute__((section(".rodata.deferred"))) \ - = {routine} +#define DECLARE_DEFERRED(routine) \ + const struct deferred_data __keep __no_sanitize_address CONCAT2( \ + routine, _data) \ + __attribute__((section(".rodata.deferred"))) = { routine } #else /* * Stub implementation in case hooks are disabled (neither * CONFIG_COMMON_RUNTIME nor CONFIG_PLATFORM_EC_HOOKS is defined) */ #define hook_call_deferred(unused1, unused2) -1 -#define DECLARE_HOOK(t, func, p) \ - void CONCAT2(unused_hook_, func)(void) { func(); } -#define DECLARE_DEFERRED(func) \ - void CONCAT2(unused_deferred_, func)(void) { func(); } +#define DECLARE_HOOK(t, func, p) \ + void CONCAT2(unused_hook_, func)(void) \ + { \ + func(); \ + } +#define DECLARE_DEFERRED(func) \ + void CONCAT2(unused_deferred_, func)(void) \ + { \ + func(); \ + } #endif -#endif /* __CROS_EC_HOOKS_H */ +#endif /* __CROS_EC_HOOKS_H */ diff --git a/include/host_command.h b/include/host_command.h index 3ab3d54351..59389107c7 100644 --- a/include/host_command.h +++ b/include/host_command.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,6 +12,10 @@ #include "common.h" #include "ec_commands.h" +#ifdef __cplusplus +extern "C" { +#endif + /* Args for host command handler */ struct host_cmd_handler_args { /* @@ -20,11 +24,11 @@ struct host_cmd_handler_args { * send the response back to the host. */ void (*send_response)(struct host_cmd_handler_args *args); - uint16_t command; /* Command (e.g., EC_CMD_FLASH_GET_INFO) */ - uint8_t version; /* Version of command (0-31) */ + uint16_t command; /* Command (e.g., EC_CMD_FLASH_GET_INFO) */ + uint8_t version; /* Version of command (0-31) */ const void *params; /* Input parameters */ - uint16_t params_size; /* Size of input parameters in bytes */ + uint16_t params_size; /* Size of input parameters in bytes */ /* * Pointer to output response data buffer. On input to the handler, @@ -130,14 +134,13 @@ struct host_command { #ifdef CONFIG_HOST_EVENT64 typedef uint64_t host_event_t; -#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%016" PRIx64, str, e) -#define HOST_EVENT_CCPRINTF(str, e) \ - ccprintf("%s 0x%016" PRIx64 "\n", str, e) +#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%016" PRIx64, str, e) +#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%016" PRIx64 "\n", str, e) #else typedef uint32_t host_event_t; -#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%08x", str, e) -#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%08x\n", str, e) +#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%08x", str, e) +#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%08x\n", str, e) #endif /** @@ -256,44 +259,46 @@ void host_packet_receive(struct host_packet *pkt); #ifndef CONFIG_ZEPHYR __error("This function should only be called from Zephyr OS code") #endif -struct host_command *zephyr_find_host_command(int command); + struct host_command *zephyr_find_host_command(int command); #if defined(CONFIG_ZEPHYR) #include "zephyr_host_command.h" #elif defined(HAS_TASK_HOSTCMD) #define EXPAND(off, cmd) __host_cmd_(off, cmd) #define __host_cmd_(off, cmd) __host_cmd_##off##cmd -#define EXPANDSTR(off, cmd) "__host_cmd_"#off#cmd +#define EXPANDSTR(off, cmd) "__host_cmd_" #off #cmd /* * Register a host command handler with * commands starting at offset 0x0000 */ -#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ - static enum ec_status(routine)(struct host_cmd_handler_args *args); \ - const struct host_command __keep __no_sanitize_address \ - EXPAND(0x0000, command) \ - __attribute__((section(".rodata.hcmds." EXPANDSTR(0x0000, command)))) \ - = {routine, command, version_mask} +#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ + static enum ec_status(routine)(struct host_cmd_handler_args * args); \ + const struct host_command __keep __no_sanitize_address EXPAND(0x0000, \ + command) \ + __attribute__((section(".rodata.hcmds." EXPANDSTR( \ + 0x0000, command)))) = { routine, command, \ + version_mask } /* * Register a private host command handler with * commands starting at offset EC_CMD_BOARD_SPECIFIC_BASE, */ -#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ - static enum ec_status(routine)(struct host_cmd_handler_args *args); \ - const struct host_command __keep __no_sanitize_address \ - EXPAND(EC_CMD_BOARD_SPECIFIC_BASE, command) \ - __attribute__((section(".rodata.hcmds."\ - EXPANDSTR(EC_CMD_BOARD_SPECIFIC_BASE, command)))) \ - = {routine, EC_PRIVATE_HOST_COMMAND_VALUE(command), \ - version_mask} +#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ + static enum ec_status(routine)(struct host_cmd_handler_args * args); \ + const struct host_command __keep __no_sanitize_address EXPAND( \ + EC_CMD_BOARD_SPECIFIC_BASE, command) \ + __attribute__((section(".rodata.hcmds." EXPANDSTR( \ + EC_CMD_BOARD_SPECIFIC_BASE, command)))) = { \ + routine, EC_PRIVATE_HOST_COMMAND_VALUE(command), \ + version_mask \ + } #else /* !CONFIG_ZEPHYR && !HAS_TASK_HOSTCMD */ -#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ - static enum ec_status (routine)(struct host_cmd_handler_args *args) \ +#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ + static enum ec_status(routine)(struct host_cmd_handler_args * args) \ __attribute__((unused)) -#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ +#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ DECLARE_HOST_COMMAND(command, routine, version_mask) #endif /* CONFIG_ZEPHYR */ @@ -304,7 +309,6 @@ struct host_command *zephyr_find_host_command(int command); */ void host_throttle_cpu(int throttle); - /** * Signal host command task to send status to PD MCU. * @@ -335,8 +339,7 @@ int pd_get_active_charge_port(void); * @param indata Pointer to buffer to store response * @param insize Size of buffer to store response */ -int pd_host_command(int command, int version, - const void *outdata, int outsize, +int pd_host_command(int command, int version, const void *outdata, int outsize, void *indata, int insize); /* @@ -358,29 +361,33 @@ stub_send_response_callback(struct host_cmd_handler_args *args) ARG_UNUSED(args); } -#define BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, PARAMS) \ - { \ - .command = (CMD), .version = (VERSION), \ - .send_response = stub_send_response_callback, \ - .response_size = 0, \ - COND_CODE_0(IS_EMPTY(RESPONSE), \ - (.response = &(RESPONSE), \ - .response_max = sizeof(RESPONSE)), \ - (.response = NULL, .response_max = 0)), \ - COND_CODE_0(IS_EMPTY(PARAMS), \ - (.params = &(PARAMS), \ - .params_size = sizeof(PARAMS)), \ - (.params = NULL, .params_size = 0)) \ +#define BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, PARAMS) \ + { \ + .send_response = stub_send_response_callback, \ + .command = (CMD), .version = (VERSION), \ + COND_CODE_0(IS_EMPTY(PARAMS), \ + (.params = &(PARAMS), \ + .params_size = sizeof(PARAMS)), \ + (.params = NULL, .params_size = 0)), \ + COND_CODE_0(IS_EMPTY(RESPONSE), \ + (.response = &(RESPONSE), \ + .response_max = sizeof(RESPONSE)), \ + (.response = NULL, .response_max = 0)), \ + .response_size = 0, \ } -#define BUILD_HOST_COMMAND_RESPONSE(CMD, VERSION, RESPONSE) \ +#define BUILD_HOST_COMMAND_RESPONSE(CMD, VERSION, RESPONSE) \ BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, EMPTY) -#define BUILD_HOST_COMMAND_PARAMS(CMD, VERSION, PARAMS) \ +#define BUILD_HOST_COMMAND_PARAMS(CMD, VERSION, PARAMS) \ BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, PARAMS) -#define BUILD_HOST_COMMAND_SIMPLE(CMD, VERSION) \ +#define BUILD_HOST_COMMAND_SIMPLE(CMD, VERSION) \ BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, EMPTY) #endif /* CONFIG_ZTEST */ -#endif /* __CROS_EC_HOST_COMMAND_H */ +#ifdef __cplusplus +} +#endif + +#endif /* __CROS_EC_HOST_COMMAND_H */ diff --git a/include/host_command_heci.h b/include/host_command_heci.h index 1dcb054ff6..5595724b59 100644 --- a/include/host_command_heci.h +++ b/include/host_command_heci.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/hotword_dsp_api.h b/include/hotword_dsp_api.h index 369af00ede..311add6675 100644 --- a/include/hotword_dsp_api.h +++ b/include/hotword_dsp_api.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -44,4 +44,4 @@ int GoogleHotwordDspGetMaximumAudioPreambleMs(void); /* Returns an internal version number that this library was built at. */ extern int GoogleHotwordVersion(void); -#endif /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */ +#endif /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */ diff --git a/include/hwtimer.h b/include/hwtimer.h index 3c0e9aaf8a..093a44cad1 100644 --- a/include/hwtimer.h +++ b/include/hwtimer.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,7 +34,8 @@ void __hw_clock_event_clear(void); #ifdef CONFIG_HWTIMER_64BIT __override_proto #endif -uint32_t __hw_clock_source_read(void); + uint32_t + __hw_clock_source_read(void); /** * Override the lower 32-bits of the hardware counter @@ -115,4 +116,4 @@ void hwtimer_setup_watchdog(void); /* Reset the watchdog timer, to avoid the watchdog warning */ void hwtimer_reset_watchdog(void); -#endif /* __CROS_EC_HWTIMER_H */ +#endif /* __CROS_EC_HWTIMER_H */ diff --git a/include/i2c.h b/include/i2c.h index c799b9599d..4da9306abb 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,15 +34,15 @@ * used here and in motion_sense to give specific meaning to the * address that is pertinent to its use. */ -#define I2C_ADDR_MASK 0x03FF -#define I2C_FLAG_PEC BIT(13) -#define I2C_FLAG_BIG_ENDIAN BIT(14) +#define I2C_ADDR_MASK 0x03FF +#define I2C_FLAG_PEC BIT(13) +#define I2C_FLAG_BIG_ENDIAN BIT(14) /* BIT(15) SPI_FLAG - used in motion_sense to overload address */ -#define I2C_FLAG_ADDR_IS_SPI BIT(15) +#define I2C_FLAG_ADDR_IS_SPI BIT(15) -#define I2C_STRIP_FLAGS(addr_flags) ((addr_flags) & I2C_ADDR_MASK) -#define I2C_USE_PEC(addr_flags) ((addr_flags) & I2C_FLAG_PEC) -#define I2C_IS_BIG_ENDIAN(addr_flags) ((addr_flags) & I2C_FLAG_BIG_ENDIAN) +#define I2C_STRIP_FLAGS(addr_flags) ((addr_flags)&I2C_ADDR_MASK) +#define I2C_USE_PEC(addr_flags) ((addr_flags)&I2C_FLAG_PEC) +#define I2C_IS_BIG_ENDIAN(addr_flags) ((addr_flags)&I2C_FLAG_BIG_ENDIAN) /* * All 7-bit addresses in the following formats @@ -51,8 +51,8 @@ * are reserved for various purposes. Valid 7-bit client adderesses start at * 0x08 and end at 0x77 inclusive. */ -#define I2C_FIRST_VALID_ADDR 0x08 -#define I2C_LAST_VALID_ADDR 0x77 +#define I2C_FIRST_VALID_ADDR 0x08 +#define I2C_LAST_VALID_ADDR 0x77 /* * Max data size for a version 3 request/response packet. This is @@ -67,7 +67,7 @@ #define I2C_RESPONSE_HEADER_SIZE 2 /* This port allows changing speed at runtime */ -#define I2C_PORT_FLAG_DYNAMIC_SPEED BIT(0) +#define I2C_PORT_FLAG_DYNAMIC_SPEED BIT(0) /* * Supported I2C CLK frequencies. @@ -85,13 +85,10 @@ enum i2c_freq { * MASK_SET will OR the mask into the old value * MASK_CLR will AND the ~mask from the old value */ -enum mask_update_action { - MASK_CLR, - MASK_SET -}; +enum mask_update_action { MASK_CLR, MASK_SET }; struct i2c_info_t { - uint16_t port; /* Physical port for device */ + uint16_t port; /* Physical port for device */ uint16_t addr_flags; }; @@ -99,17 +96,16 @@ struct i2c_port_t; /* forward declaration */ struct i2c_drv { int (*xfer)(const struct i2c_port_t *i2c_port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, + const uint16_t addr_flags, const uint8_t *out, int out_size, uint8_t *in, int in_size, int flags); }; /* Data structure to define I2C port configuration. */ struct i2c_port_t { - int port; /* Port */ + int port; /* Port */ #ifndef CONFIG_ZEPHYR - const char *name; /* Port name */ - int kbps; /* Speed in kbps */ + const char *name; /* Port name */ + int kbps; /* Speed in kbps */ enum gpio_signal scl; /* Port SCL GPIO line */ enum gpio_signal sda; /* Port SDA GPIO line */ #endif /* CONFIG_ZEPHYR */ @@ -118,7 +114,7 @@ struct i2c_port_t { int (*passthru_allowed)(const struct i2c_port_t *port, uint16_t addr_flags); const struct i2c_drv *drv; - uint16_t flags; /* I2C_PORT_FLAG_* flags */ + uint16_t flags; /* I2C_PORT_FLAG_* flags */ }; extern const struct i2c_port_t i2c_ports[]; @@ -126,27 +122,25 @@ extern const unsigned int i2c_ports_used; #ifdef CONFIG_CMD_I2C_STRESS_TEST struct i2c_test_reg_info { - int read_reg; /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */ - int read_val; /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */ - int write_reg; /* Read/Write reg which doesn't impact the system */ + int read_reg; /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */ + int read_val; /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */ + int write_reg; /* Read/Write reg which doesn't impact the system */ }; struct i2c_test_results { - int read_success; /* Successful read count */ - int read_fail; /* Read fail count */ + int read_success; /* Successful read count */ + int read_fail; /* Read fail count */ int write_success; /* Successful write count */ - int write_fail; /* Write fail count */ + int write_fail; /* Write fail count */ }; /* Data structure to define I2C test configuration. */ struct i2c_stress_test_dev { struct i2c_test_reg_info reg_info; struct i2c_test_results test_results; - int (*i2c_read)(const int port, - const uint16_t addr_flags, + int (*i2c_read)(const int port, const uint16_t addr_flags, const int reg, int *data); - int (*i2c_write)(const int port, - const uint16_t addr_flags, + int (*i2c_write)(const int port, const uint16_t addr_flags, const int reg, int data); int (*i2c_read_dev)(const int reg, int *data); int (*i2c_write_dev)(const int reg, int data); @@ -166,15 +160,15 @@ extern const int i2c_test_dev_used; * Data structure to define I2C Parameters for a command */ struct i2c_cmd_desc_t { - uint8_t port; /* I2C port */ - uint16_t addr_flags; /* Peripheral address and flags */ - uint8_t cmd; /* command, only valid on write operations */ + uint8_t port; /* I2C port */ + uint16_t addr_flags; /* Peripheral address and flags */ + uint8_t cmd; /* command, only valid on write operations */ }; /* Flags for i2c_xfer_unlocked() */ -#define I2C_XFER_START BIT(0) /* Start smbus session from idle state */ -#define I2C_XFER_STOP BIT(1) /* Terminate smbus session with stop bit */ -#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) /* One transaction */ +#define I2C_XFER_START BIT(0) /* Start smbus session from idle state */ +#define I2C_XFER_STOP BIT(1) /* Terminate smbus session with stop bit */ +#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) /* One transaction */ /** * Transmit one block of raw data, then receive one block of raw data. However, @@ -190,10 +184,8 @@ struct i2c_cmd_desc_t { * @param in_size Number of bytes to receive * @return EC_SUCCESS, or non-zero if error. */ -int i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size); +int i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size); /** * Same as i2c_xfer, but the bus is not implicitly locked. It must be called @@ -201,10 +193,9 @@ int i2c_xfer(const int port, * * @param flags Flags (see I2C_XFER_* above) */ -int i2c_xfer_unlocked(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int i2c_xfer_unlocked(const int port, const uint16_t addr_flags, + const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); #define I2C_LINE_SCL_HIGH BIT(0) #define I2C_LINE_SDA_HIGH BIT(1) @@ -305,54 +296,46 @@ void i2c_set_timeout(int port, uint32_t timeout); * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address * space. */ -int i2c_read32(const int port, - const uint16_t addr_flags, - int offset, int *data); +int i2c_read32(const int port, const uint16_t addr_flags, int offset, + int *data); /** * Write a 32-bit register to the peripheral at 7-bit peripheral address * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address * space. */ -int i2c_write32(const int port, - const uint16_t addr_flags, - int offset, int data); +int i2c_write32(const int port, const uint16_t addr_flags, int offset, + int data); /** * Read a 16-bit register from the peripheral at 7-bit peripheral address * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address * space. */ -int i2c_read16(const int port, - const uint16_t addr_flags, - int offset, int *data); +int i2c_read16(const int port, const uint16_t addr_flags, int offset, + int *data); /** * Write a 16-bit register to the peripheral at 7-bit peripheral address * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address * space. */ -int i2c_write16(const int port, - const uint16_t addr_flags, - int offset, int data); +int i2c_write16(const int port, const uint16_t addr_flags, int offset, + int data); /** * Read an 8-bit register from the peripheral at 7-bit peripheral address * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address * space. */ -int i2c_read8(const int port, - const uint16_t addr_flags, - int offset, int *data); +int i2c_read8(const int port, const uint16_t addr_flags, int offset, int *data); /** * Write an 8-bit register to the peripheral at 7-bit peripheral address * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address * space. */ -int i2c_write8(const int port, - const uint16_t addr_flags, - int offset, int data); +int i2c_write8(const int port, const uint16_t addr_flags, int offset, int data); /** * Read, modify, write an i2c register to the peripheral at 7-bit peripheral @@ -362,17 +345,11 @@ int i2c_write8(const int port, * is the same as the original value of the register, the write will not be * performed. */ -int i2c_update8(const int port, - const uint16_t addr_flags, - const int offset, - const uint8_t mask, - const enum mask_update_action action); +int i2c_update8(const int port, const uint16_t addr_flags, const int offset, + const uint8_t mask, const enum mask_update_action action); -int i2c_update16(const int port, - const uint16_t addr_flags, - const int offset, - const uint16_t mask, - const enum mask_update_action action); +int i2c_update16(const int port, const uint16_t addr_flags, const int offset, + const uint16_t mask, const enum mask_update_action action); /** * Read, modify, write field of an i2c register to the peripheral at 7-bit @@ -383,48 +360,40 @@ int i2c_update16(const int port, * new value is not the same as the original value, the new value will be * written back out to the device, otherwise no write will be performed. */ -int i2c_field_update8(const int port, - const uint16_t addr_flags, - const int offset, - const uint8_t field_mask, +int i2c_field_update8(const int port, const uint16_t addr_flags, + const int offset, const uint8_t field_mask, const uint8_t set_value); -int i2c_field_update16(const int port, - const uint16_t addr_flags, - const int offset, - const uint16_t field_mask, +int i2c_field_update16(const int port, const uint16_t addr_flags, + const int offset, const uint16_t field_mask, const uint16_t set_value); /** * Read one or two bytes data from the peripheral at 7-bit peripheral address * <addr_flags>, at 16-bit <offset> in the peripheral's address space. */ -int i2c_read_offset16(const int port, - const uint16_t addr_flags, +int i2c_read_offset16(const int port, const uint16_t addr_flags, uint16_t offset, int *data, int len); /** * Write one or two bytes data to the peripheral at 7-bit peripheral address * <addr_flags>, at 16-bit <offset> in the peripheral's address space. */ -int i2c_write_offset16(const int port, - const uint16_t addr_flags, +int i2c_write_offset16(const int port, const uint16_t addr_flags, uint16_t offset, int data, int len); /** * Read <len> bytes block data from the peripheral at 7-bit peripheral address * * <addr_flags>, at 16-bit <offset> in the peripheral's address space. */ -int i2c_read_offset16_block(const int port, - const uint16_t addr_flags, +int i2c_read_offset16_block(const int port, const uint16_t addr_flags, uint16_t offset, uint8_t *data, int len); /** * Write <len> bytes block data to the peripheral at 7-bit peripheral address * <addr_flags>, at 16-bit <offset> in the peripheral's address space. */ -int i2c_write_offset16_block(const int port, - const uint16_t addr_flags, +int i2c_write_offset16_block(const int port, const uint16_t addr_flags, uint16_t offset, const uint8_t *data, int len); /** @@ -448,9 +417,8 @@ int i2c_unwedge(int port); * * <len> : the max length of receiving buffer */ -int i2c_read_sized_block(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int max_len, int *read_len); +int i2c_read_sized_block(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int max_len, int *read_len); /** * Read ascii string using smbus read block protocol. @@ -462,27 +430,24 @@ int i2c_read_sized_block(const int port, * terminating 0. Similar to strlcpy, the terminating null is * always written into the output buffer. */ -int i2c_read_string(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int len); +int i2c_read_string(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int len); /** * Read a data block of <len> 8-bit transfers from the peripheral at 7-bit * peripheral address <addr_flags>, at the specified 8-bit <offset> in the * peripheral's address space. */ -int i2c_read_block(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int len); +int i2c_read_block(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int len); /** * Write a data block of <len> 8-bit transfers to the peripheral at 7-bit * peripheral address <addr_flags>, at the specified 8-bit <offset> in the * peripheral's address space. */ -int i2c_write_block(const int port, - const uint16_t addr_flags, - int offset, const uint8_t *data, int len); +int i2c_write_block(const int port, const uint16_t addr_flags, int offset, + const uint8_t *data, int len); /** * Convert port number to controller number, for multi-port controllers. @@ -548,8 +513,7 @@ int board_is_i2c_port_powered(int port); * @param addr_flags: Peripheral device address * */ -void i2c_start_xfer_notify(const int port, - const uint16_t addr_flags); +void i2c_start_xfer_notify(const int port, const uint16_t addr_flags); /** * Function to allow board to take any action after an i2c transaction on a @@ -560,8 +524,7 @@ void i2c_start_xfer_notify(const int port, * @param addr_flags: Peripheral device address * */ -void i2c_end_xfer_notify(const int port, - const uint16_t addr_flags); +void i2c_end_xfer_notify(const int port, const uint16_t addr_flags); /** * Defined in common/i2c_trace.c, used by i2c controller to notify tracing @@ -575,9 +538,9 @@ void i2c_end_xfer_notify(const int port, * @param in_size: size of data read * @param ret: return of i2c transaction (EC_SUCCESS or otherwise on failure) */ -void i2c_trace_notify(int port, uint16_t addr_flags, - const uint8_t *out_data, size_t out_size, - const uint8_t *in_data, size_t in_size, int ret); +void i2c_trace_notify(int port, uint16_t addr_flags, const uint8_t *out_data, + size_t out_size, const uint8_t *in_data, size_t in_size, + int ret); /** * Convert an enum i2c_freq constant to numeric frequency in kHz. @@ -622,18 +585,10 @@ enum i2c_freq i2c_get_freq(int port); /* Find the matching port in i2c_ports[] table. */ const struct i2c_port_t *get_i2c_port(const int port); -/** - * @brief Get soc's i2c port number where i2c device is connected to. - * - * This function translate a i2c port enum value (enum-name property listed in - * named-i2c-ports) to soc's i2c port. Devices which are connected to the - * same port of soc should have the same number. - * - * @param enum_port i2c port enum value. - * @return i2c port of soc used in mutex_lock(). - * -1 if physical port is not defined or i2c port number is out of - * port_mutex space. - */ -int i2c_get_physical_port(int enum_port); +#ifdef CONFIG_ZTEST +int i2c_port_is_locked(int port); +#endif + +__test_only void i2c_passthru_protect_reset(void); -#endif /* __CROS_EC_I2C_H */ +#endif /* __CROS_EC_I2C_H */ diff --git a/include/i2c_bitbang.h b/include/i2c_bitbang.h index 12486b7ee6..cc9b5cbc11 100644 --- a/include/i2c_bitbang.h +++ b/include/i2c_bitbang.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/i2c_hid.h b/include/i2c_hid.h index 8568b42837..03b216d3c5 100644 --- a/include/i2c_hid.h +++ b/include/i2c_hid.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,25 +26,25 @@ * I2C_HID_HID_DESC_REGISTER is defined in the ACPI table so please make sure * you have put in the same value there. */ -#define I2C_HID_HID_DESC_REGISTER 0x0001 -#define I2C_HID_REPORT_DESC_REGISTER 0x1000 -#define I2C_HID_INPUT_REPORT_REGISTER 0x2000 -#define I2C_HID_COMMAND_REGISTER 0x3000 -#define I2C_HID_DATA_REGISTER 0x3000 +#define I2C_HID_HID_DESC_REGISTER 0x0001 +#define I2C_HID_REPORT_DESC_REGISTER 0x1000 +#define I2C_HID_INPUT_REPORT_REGISTER 0x2000 +#define I2C_HID_COMMAND_REGISTER 0x3000 +#define I2C_HID_DATA_REGISTER 0x3000 /* I2C-HID commands */ -#define I2C_HID_CMD_RESET 0x01 -#define I2C_HID_CMD_GET_REPORT 0x02 -#define I2C_HID_CMD_SET_REPORT 0x03 -#define I2C_HID_CMD_GET_IDLE 0x04 -#define I2C_HID_CMD_SET_IDLE 0x05 -#define I2C_HID_CMD_GET_PROTOCOL 0x06 -#define I2C_HID_CMD_SET_PROTOCOL 0x07 -#define I2C_HID_CMD_SET_POWER 0x08 +#define I2C_HID_CMD_RESET 0x01 +#define I2C_HID_CMD_GET_REPORT 0x02 +#define I2C_HID_CMD_SET_REPORT 0x03 +#define I2C_HID_CMD_GET_IDLE 0x04 +#define I2C_HID_CMD_SET_IDLE 0x05 +#define I2C_HID_CMD_GET_PROTOCOL 0x06 +#define I2C_HID_CMD_SET_PROTOCOL 0x07 +#define I2C_HID_CMD_SET_POWER 0x08 /* Common HID fields */ -#define I2C_HID_DESC_LENGTH sizeof(struct i2c_hid_descriptor) -#define I2C_HID_BCD_VERSION 0x0100 +#define I2C_HID_DESC_LENGTH sizeof(struct i2c_hid_descriptor) +#define I2C_HID_BCD_VERSION 0x0100 /* I2C-HID HID descriptor */ struct __packed i2c_hid_descriptor { diff --git a/include/i2c_hid_touchpad.h b/include/i2c_hid_touchpad.h index d5d728a488..d425650c40 100644 --- a/include/i2c_hid_touchpad.h +++ b/include/i2c_hid_touchpad.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,7 +13,7 @@ #include "stdint.h" /* Max fingers to support */ -#define I2C_HID_TOUCHPAD_MAX_FINGERS 5 +#define I2C_HID_TOUCHPAD_MAX_FINGERS 5 /* * Struct holding a touchpad event diff --git a/include/i2c_ite_flash_support.h b/include/i2c_ite_flash_support.h index f70bec877a..241524f4b9 100644 --- a/include/i2c_ite_flash_support.h +++ b/include/i2c_ite_flash_support.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/i2c_peripheral.h b/include/i2c_peripheral.h index 488e886b0e..dd4e4b0c7b 100644 --- a/include/i2c_peripheral.h +++ b/include/i2c_peripheral.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,9 +10,9 @@ /* Data structure to define I2C peripheral port configuration. */ struct i2c_periph_port_t { - const char *name; /* Port name */ - int port; /* Port */ - uint8_t addr; /* address(7-bit without R/W) */ + const char *name; /* Port name */ + int port; /* Port */ + uint8_t addr; /* address(7-bit without R/W) */ }; extern const struct i2c_periph_port_t i2c_periph_ports[]; diff --git a/include/i2c_private.h b/include/i2c_private.h index 0759f86ef2..269b6810bd 100644 --- a/include/i2c_private.h +++ b/include/i2c_private.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -29,10 +29,8 @@ * @param flags Flags (see I2C_XFER_* above) * @return EC_SUCCESS, or non-zero if error. */ -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags); /** * Chip level function to set bus speed. diff --git a/include/i8042_protocol.h b/include/i8042_protocol.h index 7e554fc03e..23f500da17 100644 --- a/include/i8042_protocol.h +++ b/include/i8042_protocol.h @@ -1,8 +1,12 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * i8042 keyboard protocol constants + * i8042 keyboard protocol constants. + * + * See the IBM PS/2 Hardware Interface Technical Reference Manual + * + * https://archive.org/details/ps-2-hardware-interface-technical-reference-ocr/PS2HardwareInterfaceTechnicalReference-OCR/page/n371/mode/1up */ #ifndef __CROS_EC_I8042_PROTOCOL_H @@ -10,83 +14,52 @@ /* Some commands appear more than once. Why? */ -/* port 0x60 */ -#define I8042_CMD_MOUSE_1_1 0xe6 -#define I8042_CMD_MOUSE_2_1 0xe7 -#define I8042_CMD_MOUSE_RES 0xe8 -#define I8042_CMD_OK_GETID 0xe8 -#define I8042_CMD_GET_MOUSE 0xe9 -#define I8042_CMD_EX_ENABLE 0xea -#define I8042_CMD_EX_SETLEDS 0xeb -#define I8042_CMD_SETLEDS 0xed -#define I8042_CMD_DIAG_ECHO 0xee -#define I8042_CMD_GSCANSET 0xf0 -#define I8042_CMD_SSCANSET 0xf0 -#define I8042_CMD_GETID 0xf2 -#define I8042_CMD_SETREP 0xf3 -#define I8042_CMD_ENABLE 0xf4 -#define I8042_CMD_RESET_DIS 0xf5 -#define I8042_CMD_RESET_DEF 0xf6 -#define I8042_CMD_ALL_TYPEM 0xf7 -#define I8042_CMD_SETALL_MB 0xf8 -#define I8042_CMD_SETALL_MBR 0xfa -#define I8042_CMD_SET_A_KEY_T 0xfb -#define I8042_CMD_SET_A_KEY_MR 0xfc -#define I8042_CMD_SET_A_KEY_M 0xfd -#define I8042_CMD_RESET 0xff -#define I8042_CMD_RESEND 0xfe - /* port 0x64 */ -#define I8042_READ_CMD_BYTE 0x20 -#define I8042_READ_CTL_RAM 0x21 -#define I8042_READ_CTL_RAM_END 0x3f -#define I8042_WRITE_CMD_BYTE 0x60 /* expect a byte on port 0x60 */ -#define I8042_WRITE_CTL_RAM 0x61 +#define I8042_READ_CMD_BYTE 0x20 +#define I8042_READ_CTL_RAM 0x21 +#define I8042_READ_CTL_RAM_END 0x3f +#define I8042_WRITE_CMD_BYTE 0x60 /* expect a byte on port 0x60 */ +#define I8042_WRITE_CTL_RAM 0x61 #define I8042_WRITE_CTL_RAM_END 0x7f -#define I8042_ROUTE_AUX0 0x90 -#define I8042_ROUTE_AUX1 0x91 -#define I8042_ROUTE_AUX2 0x92 -#define I8042_ROUTE_AUX3 0x93 -#define I8042_ENA_PASSWORD 0xa6 -#define I8042_DIS_MOUSE 0xa7 -#define I8042_ENA_MOUSE 0xa8 -#define I8042_TEST_MOUSE 0xa9 -#define I8042_RESET_SELF_TEST 0xaa -#define I8042_TEST_KB_PORT 0xab -#define I8042_DIS_KB 0xad -#define I8042_ENA_KB 0xae -#define I8042_READ_OUTPUT_PORT 0xd0 +#define I8042_ROUTE_AUX0 0x90 +#define I8042_ROUTE_AUX1 0x91 +#define I8042_ROUTE_AUX2 0x92 +#define I8042_ROUTE_AUX3 0x93 +#define I8042_ENA_PASSWORD 0xa6 +#define I8042_DIS_MOUSE 0xa7 +#define I8042_ENA_MOUSE 0xa8 +#define I8042_TEST_MOUSE 0xa9 +#define I8042_TEST_MOUSE_NO_ERROR 0x00 +#define I8042_TEST_MOUSE_CLK_STUCK_LOW 0x01 +#define I8042_TEST_MOUSE_CLK_STUCK_HIGH 0x02 +#define I8042_TEST_MOUSE_DATA_STUCK_LOW 0x03 +#define I8042_TEST_MOUSE_DATA_STUCK_HIGH 0x04 +#define I8042_RESET_SELF_TEST 0xaa +#define I8042_TEST_KB_PORT 0xab +#define I8042_DIS_KB 0xad +#define I8042_ENA_KB 0xae +#define I8042_READ_OUTPUT_PORT 0xd0 #define I8042_WRITE_OUTPUT_PORT 0xd1 -#define I8042_ECHO_MOUSE 0xd3 /* expect a byte on port 0x60 */ -#define I8042_SEND_TO_MOUSE 0xd4 /* expect a byte on port 0x60 */ -#define I8042_DISABLE_A20 0xdd -#define I8042_ENABLE_A20 0xdf -#define I8042_PULSE_START 0xf0 -#define I8042_SYSTEM_RESET 0xfe -#define I8042_PULSE_END 0xff +#define I8042_ECHO_MOUSE 0xd3 /* expect a byte on port 0x60 */ +#define I8042_SEND_TO_MOUSE 0xd4 /* expect a byte on port 0x60 */ +#define I8042_DISABLE_A20 0xdd +#define I8042_ENABLE_A20 0xdf +#define I8042_PULSE_START 0xf0 +#define I8042_SYSTEM_RESET 0xfe +#define I8042_PULSE_END 0xff /* port 0x60 return value */ -#define I8042_RET_EMUL0 0xe0 -#define I8042_RET_EMUL1 0xe1 -#define I8042_RET_ECHO 0xee -#define I8042_RET_RELEASE 0xf0 -#define I8042_RET_HANJA 0xf1 -#define I8042_RET_HANGEUL 0xf2 -#define I8042_RET_ACK 0xfa -#define I8042_RET_TEST_FAIL 0xfc -#define I8042_RET_INTERNAL_FAIL 0xfd -#define I8042_RET_NAK 0xfe -#define I8042_RET_ERR 0xff +#define I8042_RET_NAK 0xfe /* port 64 - command byte bits */ -#define I8042_XLATE BIT(6) -#define I8042_AUX_DIS BIT(5) -#define I8042_KBD_DIS BIT(4) -#define I8042_SYS_FLAG BIT(2) -#define I8042_ENIRQ12 BIT(1) -#define I8042_ENIRQ1 BIT(0) +#define I8042_XLATE BIT(6) +#define I8042_AUX_DIS BIT(5) +#define I8042_KBD_DIS BIT(4) +#define I8042_SYS_FLAG BIT(2) +#define I8042_ENIRQ12 BIT(1) +#define I8042_ENIRQ1 BIT(0) /* Status Flags */ -#define I8042_AUX_DATA BIT(5) +#define I8042_AUX_DATA BIT(5) #endif /* __CROS_EC_I8042_PROTOCOL_H */ diff --git a/include/inductive_charging.h b/include/inductive_charging.h index 5c44e410aa..d4d1dd4d71 100644 --- a/include/inductive_charging.h +++ b/include/inductive_charging.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/init_rom.h b/include/init_rom.h index 84fe53d4ff..79a683752b 100644 --- a/include/init_rom.h +++ b/include/init_rom.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/ioexpander.h b/include/ioexpander.h index 21d7034303..9aff67dfaf 100644 --- a/include/ioexpander.h +++ b/include/ioexpander.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,7 +11,7 @@ #define ioex_signal gpio_signal #include "gpio.h" #else -enum ioex_signal; /* from gpio_signal.h */ +enum ioex_signal; /* from gpio_signal.h */ #endif /* IO expander signal definition structure */ @@ -34,11 +34,11 @@ struct ioex_info { /* Signal information from board.c. Must match order from enum ioex_signal. */ extern const struct ioex_info ioex_list[]; -extern void (* const ioex_irq_handlers[])(enum ioex_signal signal); +extern void (*const ioex_irq_handlers[])(enum ioex_signal signal); extern const int ioex_ih_count; /* Get ioex_info structure for specified signal */ -#define IOEX_GET_INFO(signal) (ioex_list + (signal) - IOEX_SIGNAL_START) +#define IOEX_GET_INFO(signal) (ioex_list + (signal)-IOEX_SIGNAL_START) struct ioexpander_drv { /* Initialize IO expander chip/driver */ @@ -60,9 +60,9 @@ struct ioexpander_drv { }; /* IO expander default init disabled. No I2C communication will be attempted. */ -#define IOEX_FLAGS_DEFAULT_INIT_DISABLED BIT(0) +#define IOEX_FLAGS_DEFAULT_INIT_DISABLED BIT(0) /* IO Expander has been initialized */ -#define IOEX_FLAGS_INITIALIZED BIT(1) +#define IOEX_FLAGS_INITIALIZED BIT(1) /* * BITS 24 to 31 are used by io-expander drivers that need to control multiple diff --git a/include/kasa.h b/include/kasa.h index 6157b5632d..06e5c29dbe 100644 --- a/include/kasa.h +++ b/include/kasa.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/keyboard_8042.h b/include/keyboard_8042.h index 6826eb98ac..34c98c2a38 100644 --- a/include/keyboard_8042.h +++ b/include/keyboard_8042.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -59,4 +59,4 @@ void send_aux_data_to_host_interrupt(uint8_t data); */ void send_aux_data_to_device(uint8_t data); -#endif /* __CROS_EC_KEYBOARD_8042_H */ +#endif /* __CROS_EC_KEYBOARD_8042_H */ diff --git a/include/keyboard_8042_sharedlib.h b/include/keyboard_8042_sharedlib.h index e4a2e9a77f..bd7a7b5ec7 100644 --- a/include/keyboard_8042_sharedlib.h +++ b/include/keyboard_8042_sharedlib.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -47,42 +47,42 @@ extern const uint8_t scancode_translate_table[]; extern uint8_t scancode_translate_set2_to_1(uint8_t code); #ifdef CONFIG_KEYBOARD_DEBUG -#define KEYCAP_LONG_LABEL_BIT (0x80) -#define KEYCAP_LONG_LABEL_INDEX_BITMASK (~KEYCAP_LONG_LABEL_BIT) +#define KEYCAP_LONG_LABEL_BIT (0x80) +#define KEYCAP_LONG_LABEL_INDEX_BITMASK (~KEYCAP_LONG_LABEL_BIT) enum keycap_long_label_idx { - KLLI_UNKNO = 0x80, /* UNKNOWN */ - KLLI_F1 = 0x81, /* F1 or PREVIOUS */ - KLLI_F2 = 0x82, /* F2 or NEXT */ - KLLI_F3 = 0x83, /* F3 or REFRESH */ - KLLI_F4 = 0x84, /* F4 or FULL_SCREEN */ - KLLI_F5 = 0x85, /* F5 or OVERVIEW */ - KLLI_F6 = 0x86, /* F6 or DIM */ - KLLI_F7 = 0x87, /* F7 or BRIGHT */ - KLLI_F8 = 0x88, /* F8 or MUTE */ - KLLI_F9 = 0x89, /* F9 or VOLUME DOWN */ - KLLI_F10 = 0x8A, /* F10 or VOLUME UP */ - KLLI_F11 = 0x8B, /* F11 or POWER */ - KLLI_F12 = 0x8C, /* F12 or DEV TOOLS */ - KLLI_F13 = 0x8D, /* F13 or GOOGLE ASSISTANT */ - KLLI_F14 = 0x8E, /* F14 */ - KLLI_F15 = 0x8F, /* F15 */ - KLLI_L_ALT = 0x90, /* LEFT ALT */ - KLLI_R_ALT = 0x91, /* RIGHT ALT */ - KLLI_L_CTR = 0x92, /* LEFT CONTROL */ - KLLI_R_CTR = 0x93, /* RIGHT CONTROL */ - KLLI_L_SHT = 0x94, /* LEFT SHIFT */ - KLLI_R_SHT = 0x95, /* RIGHT SHIFT */ - KLLI_ENTER = 0x96, /* ENTER */ - KLLI_SPACE = 0x97, /* SPACE */ - KLLI_B_SPC = 0x98, /* BACk SPACE*/ - KLLI_TAB = 0x99, /* TAB */ - KLLI_SEARC = 0x9A, /* SEARCH */ - KLLI_LEFT = 0x9B, /* LEFT ARROW */ - KLLI_RIGHT = 0x9C, /* RIGHT ARROW */ - KLLI_DOWN = 0x9D, /* DOWN ARROW */ - KLLI_UP = 0x9E, /* UP ARROW */ - KLLI_ESC = 0x9F, /* ESCAPE */ + KLLI_UNKNO = 0x80, /* UNKNOWN */ + KLLI_F1 = 0x81, /* F1 or PREVIOUS */ + KLLI_F2 = 0x82, /* F2 or NEXT */ + KLLI_F3 = 0x83, /* F3 or REFRESH */ + KLLI_F4 = 0x84, /* F4 or FULL_SCREEN */ + KLLI_F5 = 0x85, /* F5 or OVERVIEW */ + KLLI_F6 = 0x86, /* F6 or DIM */ + KLLI_F7 = 0x87, /* F7 or BRIGHT */ + KLLI_F8 = 0x88, /* F8 or MUTE */ + KLLI_F9 = 0x89, /* F9 or VOLUME DOWN */ + KLLI_F10 = 0x8A, /* F10 or VOLUME UP */ + KLLI_F11 = 0x8B, /* F11 or POWER */ + KLLI_F12 = 0x8C, /* F12 or DEV TOOLS */ + KLLI_F13 = 0x8D, /* F13 or GOOGLE ASSISTANT */ + KLLI_F14 = 0x8E, /* F14 */ + KLLI_F15 = 0x8F, /* F15 */ + KLLI_L_ALT = 0x90, /* LEFT ALT */ + KLLI_R_ALT = 0x91, /* RIGHT ALT */ + KLLI_L_CTR = 0x92, /* LEFT CONTROL */ + KLLI_R_CTR = 0x93, /* RIGHT CONTROL */ + KLLI_L_SHT = 0x94, /* LEFT SHIFT */ + KLLI_R_SHT = 0x95, /* RIGHT SHIFT */ + KLLI_ENTER = 0x96, /* ENTER */ + KLLI_SPACE = 0x97, /* SPACE */ + KLLI_B_SPC = 0x98, /* BACk SPACE*/ + KLLI_TAB = 0x99, /* TAB */ + KLLI_SEARC = 0x9A, /* SEARCH */ + KLLI_LEFT = 0x9B, /* LEFT ARROW */ + KLLI_RIGHT = 0x9C, /* RIGHT ARROW */ + KLLI_DOWN = 0x9D, /* DOWN ARROW */ + KLLI_UP = 0x9E, /* UP ARROW */ + KLLI_ESC = 0x9F, /* ESCAPE */ KLLI_MAX }; @@ -127,41 +127,41 @@ enum scancode_values { SCANCODE_B = 0x0032, SCANCODE_T = 0x002c, - SCANCODE_F1 = 0x0005, /* Translates to 3b in codeset 1 */ - SCANCODE_F2 = 0x0006, /* Translates to 3c in codeset 1 */ - SCANCODE_F3 = 0x0004, /* Translates to 3d in codeset 1 */ - SCANCODE_F4 = 0x000c, /* Translates to 3e in codeset 1 */ - SCANCODE_F5 = 0x0003, /* Translates to 3f in codeset 1 */ - SCANCODE_F6 = 0x000b, /* Translates to 40 in codeset 1 */ - SCANCODE_F7 = 0x0083, /* Translates to 41 in codeset 1 */ - SCANCODE_F8 = 0x000a, /* Translates to 42 in codeset 1 */ - SCANCODE_F9 = 0x0001, /* Translates to 43 in codeset 1 */ - SCANCODE_F10 = 0x0009, /* Translates to 44 in codeset 1 */ - SCANCODE_F11 = 0x0078, /* Translates to 57 in codeset 1 */ - SCANCODE_F12 = 0x0007, /* Translates to 58 in codeset 1 */ - SCANCODE_F13 = 0x000f, /* Translates to 59 in codeset 1 */ - SCANCODE_F14 = 0x0017, /* Translates to 5a in codeset 1 */ - SCANCODE_F15 = 0x001f, /* Translates to 5b in codeset 1 */ - - SCANCODE_BACK = 0xe038, /* e06a in codeset 1 */ - SCANCODE_REFRESH = 0xe020, /* e067 in codeset 1 */ - SCANCODE_FORWARD = 0xe030, /* e069 in codeset 1 */ - SCANCODE_FULLSCREEN = 0xe01d, /* e011 in codeset 1 */ - SCANCODE_OVERVIEW = 0xe024, /* e012 in codeset 1 */ - SCANCODE_SNAPSHOT = 0xe02d, /* e013 in codeset 1 */ - SCANCODE_BRIGHTNESS_DOWN = 0xe02c, /* e014 in codeset 1 */ - SCANCODE_BRIGHTNESS_UP = 0xe035, /* e015 in codeset 1 */ - SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c, /* e016 in codeset 1 */ - SCANCODE_VOLUME_MUTE = 0xe023, /* e020 in codeset 1 */ - SCANCODE_VOLUME_DOWN = 0xe021, /* e02e in codeset 1 */ - SCANCODE_VOLUME_UP = 0xe032, /* e030 in codeset 1 */ - SCANCODE_KBD_BKLIGHT_DOWN = 0xe043, /* e017 in codeset 1 */ - SCANCODE_KBD_BKLIGHT_UP = 0xe044, /* e018 in codeset 1 */ - SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c, /* e01e in codeset 1 */ - SCANCODE_NEXT_TRACK = 0xe04d, /* e019 in codeset 1 */ - SCANCODE_PREV_TRACK = 0xe015, /* e010 in codeset 1 */ - SCANCODE_PLAY_PAUSE = 0xe054, /* e01a in codeset 1 */ - SCANCODE_MICMUTE = 0xe05b, /* e01b in codeset 1 */ + SCANCODE_F1 = 0x0005, /* Translates to 3b in codeset 1 */ + SCANCODE_F2 = 0x0006, /* Translates to 3c in codeset 1 */ + SCANCODE_F3 = 0x0004, /* Translates to 3d in codeset 1 */ + SCANCODE_F4 = 0x000c, /* Translates to 3e in codeset 1 */ + SCANCODE_F5 = 0x0003, /* Translates to 3f in codeset 1 */ + SCANCODE_F6 = 0x000b, /* Translates to 40 in codeset 1 */ + SCANCODE_F7 = 0x0083, /* Translates to 41 in codeset 1 */ + SCANCODE_F8 = 0x000a, /* Translates to 42 in codeset 1 */ + SCANCODE_F9 = 0x0001, /* Translates to 43 in codeset 1 */ + SCANCODE_F10 = 0x0009, /* Translates to 44 in codeset 1 */ + SCANCODE_F11 = 0x0078, /* Translates to 57 in codeset 1 */ + SCANCODE_F12 = 0x0007, /* Translates to 58 in codeset 1 */ + SCANCODE_F13 = 0x000f, /* Translates to 59 in codeset 1 */ + SCANCODE_F14 = 0x0017, /* Translates to 5a in codeset 1 */ + SCANCODE_F15 = 0x001f, /* Translates to 5b in codeset 1 */ + + SCANCODE_BACK = 0xe038, /* e06a in codeset 1 */ + SCANCODE_REFRESH = 0xe020, /* e067 in codeset 1 */ + SCANCODE_FORWARD = 0xe030, /* e069 in codeset 1 */ + SCANCODE_FULLSCREEN = 0xe01d, /* e011 in codeset 1 */ + SCANCODE_OVERVIEW = 0xe024, /* e012 in codeset 1 */ + SCANCODE_SNAPSHOT = 0xe02d, /* e013 in codeset 1 */ + SCANCODE_BRIGHTNESS_DOWN = 0xe02c, /* e014 in codeset 1 */ + SCANCODE_BRIGHTNESS_UP = 0xe035, /* e015 in codeset 1 */ + SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c, /* e016 in codeset 1 */ + SCANCODE_VOLUME_MUTE = 0xe023, /* e020 in codeset 1 */ + SCANCODE_VOLUME_DOWN = 0xe021, /* e02e in codeset 1 */ + SCANCODE_VOLUME_UP = 0xe032, /* e030 in codeset 1 */ + SCANCODE_KBD_BKLIGHT_DOWN = 0xe043, /* e017 in codeset 1 */ + SCANCODE_KBD_BKLIGHT_UP = 0xe044, /* e018 in codeset 1 */ + SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c, /* e01e in codeset 1 */ + SCANCODE_NEXT_TRACK = 0xe04d, /* e019 in codeset 1 */ + SCANCODE_PREV_TRACK = 0xe015, /* e010 in codeset 1 */ + SCANCODE_PLAY_PAUSE = 0xe054, /* e01a in codeset 1 */ + SCANCODE_MICMUTE = 0xe05b, /* e01b in codeset 1 */ SCANCODE_UP = 0xe075, SCANCODE_DOWN = 0xe072, @@ -173,7 +173,7 @@ enum scancode_values { SCANCODE_LEFT_ALT = 0x0011, SCANCODE_RIGHT_ALT = 0xe011, - SCANCODE_LEFT_WIN = 0xe01f, /* Also known as GUI or Super key. */ + SCANCODE_LEFT_WIN = 0xe01f, /* Also known as GUI or Super key. */ SCANCODE_RIGHT_WIN = 0xe027, SCANCODE_MENU = 0xe02f, diff --git a/include/keyboard_backlight.h b/include/keyboard_backlight.h index 194bec66f4..cf68805235 100644 --- a/include/keyboard_backlight.h +++ b/include/keyboard_backlight.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -94,4 +94,16 @@ int kblight_register(const struct kblight_drv *drv); extern const struct kblight_drv kblight_pwm; +#ifdef TEST_BUILD +/** + * @brief Get internal backlight enabled state. The value reported by + * kblight_get_enabled() can be outdated due to a deferred function call + * being required to update it. Using this function in tests improves + * reliability and reduces the need to sleep. + * + * @return uint8_t 0 if disabled, 1 otherwise. + */ +uint8_t kblight_get_current_enable(void); +#endif /* TEST_BUILD */ + #endif /* __CROS_EC_KEYBOARD_BACKLIGHT_H */ diff --git a/include/keyboard_config.h b/include/keyboard_config.h index 2e6a6eb80d..afb69bf141 100644 --- a/include/keyboard_config.h +++ b/include/keyboard_config.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,8 +20,8 @@ #endif /* Keyboard matrix is 13 (or 15 with keypad) output columns x 8 input rows */ -#define KEYBOARD_COLS_WITH_KEYPAD 15 -#define KEYBOARD_COLS_NO_KEYPAD 13 +#define KEYBOARD_COLS_WITH_KEYPAD 15 +#define KEYBOARD_COLS_NO_KEYPAD 13 /* * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate @@ -44,59 +44,59 @@ extern uint8_t keyboard_cols; #define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) /* Columns and masks for keys we particularly care about */ -#define KEYBOARD_COL_DOWN 11 -#define KEYBOARD_ROW_DOWN 6 -#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) -#define KEYBOARD_COL_ESC 1 -#define KEYBOARD_ROW_ESC 1 -#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) -#define KEYBOARD_COL_KEY_H 6 -#define KEYBOARD_ROW_KEY_H 1 -#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) -#define KEYBOARD_COL_KEY_R 3 -#define KEYBOARD_ROW_KEY_R 7 -#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) -#define KEYBOARD_COL_LEFT_ALT 10 -#define KEYBOARD_ROW_LEFT_ALT 6 -#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) -#define KEYBOARD_COL_REFRESH 2 +#define KEYBOARD_COL_DOWN 11 +#define KEYBOARD_ROW_DOWN 6 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 1 +#define KEYBOARD_ROW_ESC 1 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 6 +#define KEYBOARD_ROW_KEY_H 1 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 3 +#define KEYBOARD_ROW_KEY_R 7 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 10 +#define KEYBOARD_ROW_LEFT_ALT 6 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 2 #ifdef CONFIG_KEYBOARD_REFRESH_ROW3 -#define KEYBOARD_ROW_REFRESH 3 +#define KEYBOARD_ROW_REFRESH 3 #else -#define KEYBOARD_ROW_REFRESH 2 +#define KEYBOARD_ROW_REFRESH 2 #endif -#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) -#define KEYBOARD_COL_RIGHT_ALT 10 -#define KEYBOARD_ROW_RIGHT_ALT 0 -#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) -#define KEYBOARD_DEFAULT_COL_VOL_UP 4 -#define KEYBOARD_DEFAULT_ROW_VOL_UP 0 -#define KEYBOARD_COL_LEFT_CTRL 0 -#define KEYBOARD_ROW_LEFT_CTRL 2 +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 10 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 4 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 0 +#define KEYBOARD_COL_LEFT_CTRL 0 +#define KEYBOARD_ROW_LEFT_CTRL 2 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) #define KEYBOARD_COL_RIGHT_CTRL 0 #define KEYBOARD_ROW_RIGHT_CTRL 4 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) -#define KEYBOARD_COL_SEARCH 1 -#define KEYBOARD_ROW_SEARCH 0 -#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) -#define KEYBOARD_COL_KEY_0 8 -#define KEYBOARD_ROW_KEY_0 6 -#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) -#define KEYBOARD_COL_KEY_1 1 -#define KEYBOARD_ROW_KEY_1 6 -#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) -#define KEYBOARD_COL_KEY_2 4 -#define KEYBOARD_ROW_KEY_2 6 -#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_SEARCH 1 +#define KEYBOARD_ROW_SEARCH 0 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 8 +#define KEYBOARD_ROW_KEY_0 6 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 1 +#define KEYBOARD_ROW_KEY_1 6 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 4 +#define KEYBOARD_ROW_KEY_2 6 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) #define KEYBOARD_COL_LEFT_SHIFT 7 #define KEYBOARD_ROW_LEFT_SHIFT 5 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) #ifdef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2) +#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2) #elif defined(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3) -#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3) +#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3) #endif #endif /* CONFIG_KEYBOARD_CUSTOMIZATION */ -#endif /* __CROS_EC_KEYBOARD_CONFIG_H */ +#endif /* __CROS_EC_KEYBOARD_CONFIG_H */ diff --git a/include/keyboard_mkbp.h b/include/keyboard_mkbp.h index 03e84550a7..ff2344937b 100644 --- a/include/keyboard_mkbp.h +++ b/include/keyboard_mkbp.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -9,6 +9,7 @@ #define __CROS_EC_KEYBOARD_MKBP_H #include "common.h" +#include "ec_commands.h" #include "keyboard_config.h" /** @@ -18,4 +19,8 @@ */ int mkbp_keyboard_add(const uint8_t *buffp); -#endif /* __CROS_EC_KEYBOARD_MKBP_H */ +#ifdef TEST_BUILD +void get_keyscan_config(struct ec_mkbp_config *dst); +#endif + +#endif /* __CROS_EC_KEYBOARD_MKBP_H */ diff --git a/include/keyboard_protocol.h b/include/keyboard_protocol.h index 362364ced4..7b9006fcc0 100644 --- a/include/keyboard_protocol.h +++ b/include/keyboard_protocol.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -39,7 +39,9 @@ void keyboard_update_button(enum keyboard_button_type button, int is_pressed); /* MKBP protocol takes the whole keyboard matrix, and does not care about * individual key presses. */ -static inline void keyboard_state_changed(int row, int col, int is_pressed) {} +static inline void keyboard_state_changed(int row, int col, int is_pressed) +{ +} #else /** * Called by keyboard scan code once any key state change (after de-bounce), @@ -60,7 +62,7 @@ int board_has_keyboard_backlight(void); * to change KEYBOARD_ROW_REFRESH accordingly so that recovery mode can work on * the EC side of things (also see related CONFIG_KEYBOARD_REFRESH_ROW3) */ -__override_proto -const struct ec_response_keybd_config *board_vivaldi_keybd_config(void); +__override_proto const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void); -#endif /* __CROS_EC_KEYBOARD_PROTOCOL_H */ +#endif /* __CROS_EC_KEYBOARD_PROTOCOL_H */ diff --git a/include/keyboard_raw.h b/include/keyboard_raw.h index 6989ae36a7..dca7b3c79a 100644 --- a/include/keyboard_raw.h +++ b/include/keyboard_raw.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -11,14 +11,14 @@ #ifndef __CROS_EC_KEYBOARD_RAW_H #define __CROS_EC_KEYBOARD_RAW_H -#include "assert.h" +#include "builtin/assert.h" #include "common.h" #include "gpio_signal.h" #include "keyboard_config.h" /* Column values for keyboard_raw_drive_column() */ enum keyboard_column_index { - KEYBOARD_COLUMN_ALL = -2, /* Drive all columns */ + KEYBOARD_COLUMN_ALL = -2, /* Drive all columns */ KEYBOARD_COLUMN_NONE = -1, /* Drive no columns (tri-state all) */ /* 0 ~ KEYBOARD_COLS_MAX-1 for the corresponding column */ }; @@ -70,7 +70,9 @@ void keyboard_raw_enable_interrupt(int enable); void keyboard_raw_gpio_interrupt(enum gpio_signal signal); #else -static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal) { } +static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal) +{ +} #endif /* !HAS_TASK_KEYSCAN */ /** @@ -89,11 +91,13 @@ int keyboard_factory_test_scan(void); */ int keyboard_raw_is_input_low(int port, int id); -static inline int keyboard_raw_get_cols(void) { +static inline int keyboard_raw_get_cols(void) +{ return keyboard_cols; } -static inline void keyboard_raw_set_cols(int cols) { +static inline void keyboard_raw_set_cols(int cols) +{ #ifdef CONFIG_KEYBOARD_LANGUAGE_ID /* Keyboard ID is probably encoded right after the last column. Scanner * would read keyboard ID if the column size is decreased. */ @@ -118,4 +122,4 @@ static inline void keyboard_raw_set_cols(int cols) { void board_keyboard_drive_col(int col); #endif -#endif /* __CROS_EC_KEYBOARD_RAW_H */ +#endif /* __CROS_EC_KEYBOARD_RAW_H */ diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h index 1e164bca37..e235a47c1c 100644 --- a/include/keyboard_scan.h +++ b/include/keyboard_scan.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,6 +38,12 @@ struct keyboard_scan_config { #endif }; +/* Boot key list. Must be in same order as enum boot_key. */ +struct boot_key_entry { + uint8_t col; + uint8_t row; +}; + /** * Initializes the module. */ @@ -89,10 +95,10 @@ const uint8_t *keyboard_scan_get_state(void); enum kb_scan_disable_masks { /* Reasons why keyboard scanning should be disabled */ - KB_SCAN_DISABLE_LID_CLOSED = (1<<0), - KB_SCAN_DISABLE_POWER_BUTTON = (1<<1), - KB_SCAN_DISABLE_LID_ANGLE = (1<<2), - KB_SCAN_DISABLE_USB_SUSPENDED = (1<<3), + KB_SCAN_DISABLE_LID_CLOSED = (1 << 0), + KB_SCAN_DISABLE_POWER_BUTTON = (1 << 1), + KB_SCAN_DISABLE_LID_ANGLE = (1 << 2), + KB_SCAN_DISABLE_USB_SUSPENDED = (1 << 3), }; #ifdef HAS_TASK_KEYSCAN @@ -111,7 +117,9 @@ void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask); void clear_typematic_key(void); #else static inline void keyboard_scan_enable(int enable, - enum kb_scan_disable_masks mask) { } + enum kb_scan_disable_masks mask) +{ +} #endif #ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE @@ -136,7 +144,9 @@ int keyboard_get_keyboard_id(void); #ifdef CONFIG_KEYBOARD_RUNTIME_KEYS void set_vol_up_key(uint8_t row, uint8_t col); #else -static inline void set_vol_up_key(uint8_t row, uint8_t col) {} +static inline void set_vol_up_key(uint8_t row, uint8_t col) +{ +} #endif #ifdef CONFIG_KEYBOARD_FACTORY_TEST @@ -148,5 +158,52 @@ extern const int keyboard_factory_scan_pins[][2]; extern const int keyboard_factory_scan_pins_used; #endif +#ifdef CONFIG_KEYBOARD_MULTIPLE +extern struct boot_key_entry boot_key_list[3]; + +struct keyboard_type { + int col_esc; + int row_esc; + int col_down; + int row_down; + int col_left_shift; + int row_left_shift; + int col_refresh; + int row_refresh; + int col_right_alt; + int row_right_alt; + int col_left_alt; + int row_left_alt; + int col_key_r; + int row_key_r; + int col_key_h; + int row_key_h; +}; + +extern struct keyboard_type key_typ; +#endif + +#ifdef TEST_BUILD +/** + * @brief Get the value of print_state_changes + * + * @return non-zero if state change printing is enabled, zero if not. + */ +__test_only int keyboard_scan_get_print_state_changes(void); + +/** + * @brief Forcibly set the value of print_state_changes + * + * @param val Value to set + */ +__test_only void keyboard_scan_set_print_state_changes(int val); + +/** + * @brief Checks if keyboard scanning is currently enabled. + * + * @return int non-zero if enabled, zero otherwise. + */ +int keyboard_scan_is_enabled(void); +#endif /* TEST_BUILD */ -#endif /* __CROS_EC_KEYBOARD_SCAN_H */ +#endif /* __CROS_EC_KEYBOARD_SCAN_H */ diff --git a/include/keyboard_test.h b/include/keyboard_test.h index 142cff5e53..be12f08372 100644 --- a/include/keyboard_test.h +++ b/include/keyboard_test.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 The Chromium OS Authors. All rights reserved. + * Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,9 +16,9 @@ * logic. */ struct keyscan_item { - timestamp_t abs_time; /* absolute timestamp to present this item */ - uint32_t time_us; /* time for this item relative to test start */ - uint8_t done; /* 1 if we managed to present this */ + timestamp_t abs_time; /* absolute timestamp to present this item */ + uint32_t time_us; /* time for this item relative to test start */ + uint8_t done; /* 1 if we managed to present this */ uint8_t scan[KEYBOARD_COLS_MAX]; }; diff --git a/include/lb_common.h b/include/lb_common.h index 327c810cad..29f666d33b 100644 --- a/include/lb_common.h +++ b/include/lb_common.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,4 +38,4 @@ void lb_hc_cmd_reg(const struct ec_params_lightbar *in); */ int lb_power(int enabled); -#endif /* __CROS_EC_LB_COMMON_H */ +#endif /* __CROS_EC_LB_COMMON_H */ diff --git a/include/led_common.h b/include/led_common.h index 8e9f1441f3..71c8211fec 100644 --- a/include/led_common.h +++ b/include/led_common.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -79,8 +79,8 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness); void led_enable(int enable); enum ec_led_state { - LED_STATE_OFF = 0, - LED_STATE_ON = 1, + LED_STATE_OFF = 0, + LED_STATE_ON = 1, LED_STATE_RESET = 2, }; diff --git a/include/led_onoff_states.h b/include/led_onoff_states.h index 63955e590a..bfad06aabc 100644 --- a/include/led_onoff_states.h +++ b/include/led_onoff_states.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,19 +10,15 @@ #include "ec_commands.h" -#define LED_INDEFINITE UINT8_MAX -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_OFF EC_LED_COLOR_COUNT +#define LED_INDEFINITE UINT8_MAX +#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define LED_OFF EC_LED_COLOR_COUNT /* * All LED states should have one phase defined, * and an additional phase can be defined for blinking */ -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; +enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES }; /* * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1 diff --git a/include/led_pwm.h b/include/led_pwm.h index 26a44913b8..1c8cec9ff4 100644 --- a/include/led_pwm.h +++ b/include/led_pwm.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,20 +15,12 @@ #ifdef CONFIG_ZEPHYR #define PWM_LED_NO_CHANNEL NULL -/* This could really be pwm_dt_spec. */ -struct pwm_led_dt_channel { - const struct device *dev; - uint32_t channel; - pwm_flags_t flags; - uint32_t period_ns; -}; - struct pwm_led { - const struct pwm_led_dt_channel *ch0; - const struct pwm_led_dt_channel *ch1; - const struct pwm_led_dt_channel *ch2; + const struct pwm_dt_spec *ch0; + const struct pwm_dt_spec *ch1; + const struct pwm_dt_spec *ch2; - void (*set_duty)(const struct pwm_led_dt_channel *ch, int percent); + void (*set_duty)(const struct pwm_dt_spec *pwm, int percent); }; #else #define PWM_LED_NO_CHANNEL ((enum pwm_channel)(-1)) diff --git a/include/libsharedobjs.h b/include/libsharedobjs.h index 3801ccaca0..ee767ff127 100644 --- a/include/libsharedobjs.h +++ b/include/libsharedobjs.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -17,7 +17,7 @@ * NOTE: I know that this doesn't cover all possible cases, but it will catch * an obvious case. */ -#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF) +#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF) #error "The shared library is NOT compatible with this EC." #endif @@ -28,12 +28,12 @@ */ #undef SHAREDLIB #ifdef SHAREDLIB_IMAGE -#define SHAREDLIB(...) __attribute__ ((section(".roshared"))) __VA_ARGS__ +#define SHAREDLIB(...) __attribute__((section(".roshared"))) __VA_ARGS__ #else /* !defined(SHAREDLIB_IMAGE) */ #define SHAREDLIB(...) #endif /* defined(SHAREDLIB_IMAGE) */ #define SHAREDLIB_FUNC(...) \ - extern __VA_ARGS__ __attribute__ ((section(".roshared.text"))) + extern __VA_ARGS__ __attribute__((section(".roshared.text"))) #else /* !defined(CONFIG_SHAREDLIB) */ diff --git a/include/lid_angle.h b/include/lid_angle.h index 24275db313..8836c91238 100644 --- a/include/lid_angle.h +++ b/include/lid_angle.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -32,4 +32,4 @@ void lid_angle_set_wake_angle(int ang); */ __override_proto void lid_angle_peripheral_enable(int enable); -#endif /* __CROS_EC_LID_ANGLE_H */ +#endif /* __CROS_EC_LID_ANGLE_H */ diff --git a/include/lid_switch.h b/include/lid_switch.h index 93d093a21f..3d639b5782 100644 --- a/include/lid_switch.h +++ b/include/lid_switch.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,7 +14,7 @@ /** * Debounce time for lid switch */ -#define LID_DEBOUNCE_US (30 * MSEC) +#define LID_DEBOUNCE_US (30 * MSEC) /** * Return non-zero if lid is open. @@ -37,4 +37,4 @@ void lid_interrupt(enum gpio_signal signal); */ void enable_lid_detect(bool enable); -#endif /* __CROS_EC_LID_SWITCH_H */ +#endif /* __CROS_EC_LID_SWITCH_H */ diff --git a/include/lightbar.h b/include/lightbar.h index 2c8c143922..aff5e6fc68 100644 --- a/include/lightbar.h +++ b/include/lightbar.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,26 +13,13 @@ /* Define the types of sequences */ #define LBMSG(state) LIGHTBAR_##state #include "lightbar_msg_list.h" -enum lightbar_sequence { - LIGHTBAR_MSG_LIST - LIGHTBAR_NUM_SEQUENCES -}; +enum lightbar_sequence { LIGHTBAR_MSG_LIST LIGHTBAR_NUM_SEQUENCES }; #undef LBMSG /* Bytecode field constants */ -enum lb_color { - LB_COL_RED, - LB_COL_GREEN, - LB_COL_BLUE, - LB_COL_ALL -}; +enum lb_color { LB_COL_RED, LB_COL_GREEN, LB_COL_BLUE, LB_COL_ALL }; -enum lb_control { - LB_CONT_COLOR0, - LB_CONT_COLOR1, - LB_CONT_PHASE, - LB_CONT_MAX -}; +enum lb_control { LB_CONT_COLOR0, LB_CONT_COLOR1, LB_CONT_PHASE, LB_CONT_MAX }; #ifdef CONFIG_ALS_LIGHTBAR_DIMMING /* @@ -67,4 +54,4 @@ extern void demo_battery_level(int inc); extern void demo_is_charging(int ischarge); extern void demo_brightness(int inc); extern void demo_tap(void); -#endif /* __CROS_EC_LIGHTBAR_H */ +#endif /* __CROS_EC_LIGHTBAR_H */ diff --git a/include/lightbar_msg_list.h b/include/lightbar_msg_list.h index 15c7d14bf6..be87913c83 100644 --- a/include/lightbar_msg_list.h +++ b/include/lightbar_msg_list.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -6,17 +6,17 @@ * we can automatically derive the correct constants, functions, and message * types. */ -#define LIGHTBAR_MSG_LIST \ - LBMSG(ERROR), /* 0 */ \ - LBMSG(S5), /* 1 */ \ - LBMSG(S3), /* 2 */ \ - LBMSG(S0), /* 3 */ \ - LBMSG(S5S3), /* 4 */ \ - LBMSG(S3S0), /* 5 */ \ - LBMSG(S0S3), /* 6 */ \ - LBMSG(S3S5), /* 7 */ \ - LBMSG(STOP), /* 8 */ \ - LBMSG(RUN), /* 9 */ \ - LBMSG(KONAMI), /* A */ \ - LBMSG(TAP), /* B */ \ - LBMSG(PROGRAM), /* C */ +#define LIGHTBAR_MSG_LIST \ + LBMSG(ERROR), /* 0 */ \ + LBMSG(S5), /* 1 */ \ + LBMSG(S3), /* 2 */ \ + LBMSG(S0), /* 3 */ \ + LBMSG(S5S3), /* 4 */ \ + LBMSG(S3S0), /* 5 */ \ + LBMSG(S0S3), /* 6 */ \ + LBMSG(S3S5), /* 7 */ \ + LBMSG(STOP), /* 8 */ \ + LBMSG(RUN), /* 9 */ \ + LBMSG(KONAMI), /* A */ \ + LBMSG(TAP), /* B */ \ + LBMSG(PROGRAM), /* C */ diff --git a/include/lightbar_opcode_list.h b/include/lightbar_opcode_list.h index 5d75feb459..c8feae682f 100644 --- a/include/lightbar_opcode_list.h +++ b/include/lightbar_opcode_list.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -6,21 +6,21 @@ */ /* NAME OPERAND BYTES MNEMONIC*/ -#define LIGHTBAR_OPCODE_TABLE \ - OP(ON, 0, "on" )\ - OP(OFF, 0, "off" )\ - OP(JUMP, 1, "jump" )\ - OP(JUMP_BATTERY, 2, "jbat" )\ - OP(JUMP_IF_CHARGING, 1, "jcharge" )\ - OP(SET_WAIT_DELAY, 4, "delay.w" )\ - OP(SET_RAMP_DELAY, 4, "delay.r" )\ - OP(WAIT, 0, "wait" )\ - OP(SET_BRIGHTNESS, 1, "bright" )\ - OP(SET_COLOR_SINGLE, 2, "set.1" )\ - OP(SET_COLOR_RGB, 4, "set.rgb" )\ - OP(GET_COLORS, 0, "get" )\ - OP(SWAP_COLORS, 0, "swap" )\ - OP(RAMP_ONCE, 0, "ramp.1" )\ - OP(CYCLE_ONCE, 0, "cycle.1" )\ - OP(CYCLE, 0, "cycle" )\ - OP(HALT, 0, "halt" ) +#define LIGHTBAR_OPCODE_TABLE \ + OP(ON, 0, "on") \ + OP(OFF, 0, "off") \ + OP(JUMP, 1, "jump") \ + OP(JUMP_BATTERY, 2, "jbat") \ + OP(JUMP_IF_CHARGING, 1, "jcharge") \ + OP(SET_WAIT_DELAY, 4, "delay.w") \ + OP(SET_RAMP_DELAY, 4, "delay.r") \ + OP(WAIT, 0, "wait") \ + OP(SET_BRIGHTNESS, 1, "bright") \ + OP(SET_COLOR_SINGLE, 2, "set.1") \ + OP(SET_COLOR_RGB, 4, "set.rgb") \ + OP(GET_COLORS, 0, "get") \ + OP(SWAP_COLORS, 0, "swap") \ + OP(RAMP_ONCE, 0, "ramp.1") \ + OP(CYCLE_ONCE, 0, "cycle.1") \ + OP(CYCLE, 0, "cycle") \ + OP(HALT, 0, "halt") diff --git a/include/link_defs.h b/include/link_defs.h index 79b1a99159..ed7e9d1cfe 100644 --- a/include/link_defs.h +++ b/include/link_defs.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -82,6 +82,8 @@ extern const struct hook_data __hooks_usb_pd_disconnect[]; extern const struct hook_data __hooks_usb_pd_disconnect_end[]; extern const struct hook_data __hooks_usb_pd_connect[]; extern const struct hook_data __hooks_usb_pd_connect_end[]; +extern const struct hook_data __hooks_power_supply_change[]; +extern const struct hook_data __hooks_power_supply_change_end[]; /* Deferrable functions and firing times*/ extern const struct deferred_data __deferred_funcs[]; @@ -131,7 +133,7 @@ extern void *__dram_bss_end; /* Helper for special chip-specific memory sections */ #if defined(CONFIG_CHIP_MEMORY_REGIONS) || defined(CONFIG_DRAM_BASE) #define __SECTION(name) __attribute__((section("." STRINGIFY(name) ".50_auto"))) -#define __SECTION_KEEP(name) \ +#define __SECTION_KEEP(name) \ __keep __attribute__((section("." STRINGIFY(name) ".keep.50_auto"))) #else #define __SECTION(name) @@ -146,7 +148,7 @@ extern void *__dram_bss_end; #endif /* __CROS_EC_LINK_DEFS_H */ #ifdef CONFIG_PRESERVE_LOGS -#define __preserved_logs(name) \ +#define __preserved_logs(name) \ __attribute__((section(".preserved_logs." STRINGIFY(name)))) /* preserved_logs section. */ extern const char __preserved_logs_start[]; diff --git a/include/lpc.h b/include/lpc.h index 2a69cbced8..2e0a2eea74 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -89,6 +89,13 @@ enum lpc_host_event_type { */ host_event_t lpc_get_host_events(void); +#ifdef TEST_BUILD +/** + * Set host events. + */ +void lpc_set_host_event_state(host_event_t events); +#endif + /** * Get host events that are set based on the type provided. * @@ -162,4 +169,4 @@ void lpc_init_mask(void); */ void lpc_s3_resume_clear_masks(void); -#endif /* __CROS_EC_LPC_H */ +#endif /* __CROS_EC_LPC_H */ diff --git a/include/mag_cal.h b/include/mag_cal.h index 61b24c7da9..66281bba4e 100644 --- a/include/mag_cal.h +++ b/include/mag_cal.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,8 +14,8 @@ #include "kasa.h" #define MAG_CAL_MAX_SAMPLES 0xffff -#define MAG_CAL_MIN_BATCH_WINDOW_US (2 * SECOND) -#define MAG_CAL_MIN_BATCH_SIZE 50 /* samples */ +#define MAG_CAL_MIN_BATCH_WINDOW_US (2 * SECOND) +#define MAG_CAL_MIN_BATCH_SIZE 50 /* samples */ struct mag_cal_t { struct kasa_fit kasa_fit; @@ -38,4 +38,4 @@ void init_mag_cal(struct mag_cal_t *moc); * @return 1 if a new calibration value is available, 0 otherwise. */ int mag_cal_update(struct mag_cal_t *moc, const intv3_t v); -#endif /* __CROS_EC_MAG_CAL_H */ +#endif /* __CROS_EC_MAG_CAL_H */ diff --git a/include/mat33.h b/include/mat33.h index fdd7e954ac..43826af1b1 100644 --- a/include/mat33.h +++ b/include/mat33.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,6 +26,6 @@ void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t eigenvals, size_t mat33_fp_maxind(mat33_fp_t A, size_t k); -void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, - size_t k, size_t l, size_t i, size_t j); -#endif /* __CROS_EC_MAT_33_H */ +void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, size_t k, size_t l, size_t i, + size_t j); +#endif /* __CROS_EC_MAT_33_H */ diff --git a/include/mat44.h b/include/mat44.h index 2faa093c8e..909c6e0ee7 100644 --- a/include/mat44.h +++ b/include/mat44.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,4 +22,4 @@ void mat44_fp_swap_rows(mat44_fp_t A, const size_t i, const size_t j); void mat44_fp_solve(mat44_fp_t A, fpv4_t x, const fpv4_t b, const sizev4_t pivot); -#endif /* __CROS_EC_MAT_44_H */ +#endif /* __CROS_EC_MAT_44_H */ diff --git a/include/math_util.h b/include/math_util.h index 9ee075839e..51065d2bce 100644 --- a/include/math_util.h +++ b/include/math_util.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -40,9 +40,9 @@ typedef int64_t fp_inter_t; #define INT_TO_FP(x) ((fp_t)(x) << FP_BITS) #define FP_TO_INT(x) ((int32_t)((x) >> FP_BITS)) /* Float to fixed-point, only for compile-time constants and unit tests */ -#define FLOAT_TO_FP(x) ((fp_t)((x) * (float)(1<<FP_BITS))) +#define FLOAT_TO_FP(x) ((fp_t)((x) * (float)(1 << FP_BITS))) /* Fixed-point to float, for unit tests */ -#define FP_TO_FLOAT(x) ((float)(x) / (float)(1<<FP_BITS)) +#define FP_TO_FLOAT(x) ((float)(x) / (float)(1 << FP_BITS)) #define FLT_MAX INT32_MAX #define FLT_MIN INT32_MIN @@ -158,9 +158,7 @@ typedef fp_t mat33_fp_t[3][3]; typedef int intv3_t[3]; /* For vectors, define which coordinates are in which location. */ -enum { - X, Y, Z, W -}; +enum { X, Y, Z, W }; /* * Return absolute value of x. Note that as a macro expansion, this may have * side effects if x includes function calls, which is why inline functions @@ -194,7 +192,6 @@ void cross_product(const intv3_t v1, const intv3_t v2, intv3_t v); */ void vector_scale(intv3_t v, fp_t s); - /** * Find the cosine of the angle between two vectors. * diff --git a/include/memory_commands.h b/include/memory_commands.h index 91020d8920..666a6ef508 100644 --- a/include/memory_commands.h +++ b/include/memory_commands.h @@ -1,4 +1,4 @@ -/* Copyright 2011 The Chromium OS Authors. All rights reserved. +/* Copyright 2011 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,4 +13,4 @@ /* Initializes the module. */ int memory_commands_init(void); -#endif /* __CROS_EC_MEMORY_COMMANDS_H */ +#endif /* __CROS_EC_MEMORY_COMMANDS_H */ diff --git a/include/mkbp_event.h b/include/mkbp_event.h index d9237dd33b..d31bd82cb2 100644 --- a/include/mkbp_event.h +++ b/include/mkbp_event.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -51,11 +51,22 @@ struct mkbp_event_source { #ifdef CONFIG_PLATFORM_EC_MKBP_EVENT #include "zephyr_mkbp_event.h" #else -#define DECLARE_EVENT_SOURCE(type, func) \ - const struct mkbp_event_source __keep \ - __no_sanitize_address _evt_src_##type \ - __attribute__((section(".rodata.evtsrcs"))) \ - = {type, func} +#define DECLARE_EVENT_SOURCE(type, func) \ + const struct mkbp_event_source __keep __no_sanitize_address \ + _evt_src_##type \ + __attribute__((section(".rodata.evtsrcs"))) = { type, func } #endif -#endif /* __CROS_EC_MKBP_EVENT_H */ +#ifdef TEST_BUILD +/* Allow directly raising events in unit tests */ +void activate_mkbp_with_events(uint32_t events_to_add); + +/** + * @brief Force the event bits to zero, causing the event handling code to + * believe there are no pending events to service. This has no effect on + * any event sources' internal queues or logic. + */ +__test_only void mkbp_event_clear_all(void); +#endif /* TEST_BUILD */ + +#endif /* __CROS_EC_MKBP_EVENT_H */ diff --git a/include/mkbp_fifo.h b/include/mkbp_fifo.h index 347f94e2a7..408980a10b 100644 --- a/include/mkbp_fifo.h +++ b/include/mkbp_fifo.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,10 +11,8 @@ #include "common.h" #include "ec_commands.h" - #define FIFO_DEPTH 16 - /** * Update the "soft" FIFO depth (size). The new depth should be less or * equal FIFO_DEPTH diff --git a/include/mkbp_info.h b/include/mkbp_info.h index 64daa52dce..61378f9c22 100644 --- a/include/mkbp_info.h +++ b/include/mkbp_info.h @@ -19,4 +19,9 @@ */ __override_proto int mkbp_support_volume_buttons(void); +#ifdef TEST_BUILD +uint32_t get_supported_buttons(void); +uint32_t get_supported_switches(void); +#endif /* TEST_BUILD */ + #endif /* __CROS_EC_MKBP_INFO_H */ diff --git a/include/mkbp_input_devices.h b/include/mkbp_input_devices.h index 2557aab3f2..920f944fdf 100644 --- a/include/mkbp_input_devices.h +++ b/include/mkbp_input_devices.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/mock/charge_manager_mock.h b/include/mock/charge_manager_mock.h index 8a791f6121..afae5a19a2 100644 --- a/include/mock/charge_manager_mock.h +++ b/include/mock/charge_manager_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,7 +16,7 @@ struct mock_ctrl_charge_manager { }; #define MOCK_CTRL_DEFAULT_CHARGE_MANAGER \ - ((struct mock_ctrl_charge_manager) { \ + ((struct mock_ctrl_charge_manager){ \ .vbus_voltage_mv = 0, \ }) diff --git a/include/mock/dp_alt_mode_mock.h b/include/mock/dp_alt_mode_mock.h index 27811140c7..152d5d8b37 100644 --- a/include/mock/dp_alt_mode_mock.h +++ b/include/mock/dp_alt_mode_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/mock/fp_sensor_mock.h b/include/mock/fp_sensor_mock.h index 432802348c..338a03b7e9 100644 --- a/include/mock/fp_sensor_mock.h +++ b/include/mock/fp_sensor_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,20 +28,21 @@ struct mock_ctrl_fp_sensor { int fp_maintenance_return; }; -#define MOCK_CTRL_DEFAULT_FP_SENSOR \ -(struct mock_ctrl_fp_sensor) { \ - .fp_sensor_init_return = EC_SUCCESS, \ - .fp_sensor_deinit_return = EC_SUCCESS, \ - .fp_sensor_get_info_return = EC_SUCCESS, \ - .fp_sensor_finger_status_return = FINGER_NONE, \ - .fp_sensor_acquire_image_return = 0, \ - .fp_sensor_acquire_image_with_mode_return = 0, \ - .fp_finger_match_return = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \ - .fp_enrollment_begin_return = 0, \ - .fp_enrollment_finish_return = 0, \ - .fp_finger_enroll_return = EC_MKBP_FP_ERR_ENROLL_OK, \ - .fp_maintenance_return = EC_SUCCESS \ -} +#define MOCK_CTRL_DEFAULT_FP_SENSOR \ + (struct mock_ctrl_fp_sensor) \ + { \ + .fp_sensor_init_return = EC_SUCCESS, \ + .fp_sensor_deinit_return = EC_SUCCESS, \ + .fp_sensor_get_info_return = EC_SUCCESS, \ + .fp_sensor_finger_status_return = FINGER_NONE, \ + .fp_sensor_acquire_image_return = 0, \ + .fp_sensor_acquire_image_with_mode_return = 0, \ + .fp_finger_match_return = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \ + .fp_enrollment_begin_return = 0, \ + .fp_enrollment_finish_return = 0, \ + .fp_finger_enroll_return = EC_MKBP_FP_ERR_ENROLL_OK, \ + .fp_maintenance_return = EC_SUCCESS \ + } extern struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor; diff --git a/include/mock/fpsensor_crypto_mock.h b/include/mock/fpsensor_crypto_mock.h new file mode 100644 index 0000000000..8462dc1baf --- /dev/null +++ b/include/mock/fpsensor_crypto_mock.h @@ -0,0 +1,30 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * @file fpsensor_crypto_mock.h + * @brief Controls for the mock fpsensor_crypto library + */ + +#ifndef __MOCK_FPSENSOR_CRYPTO_MOCK_H +#define __MOCK_FPSENSOR_CRYPTO_MOCK_H + +enum mock_ctrl_fpsensor_crypto_sha256_type { + MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL, + MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_ZEROS, + MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_FF, +}; + +struct mock_ctrl_fpsensor_crypto { + enum mock_ctrl_fpsensor_crypto_sha256_type output_type; +}; + +#define MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO \ + ((struct mock_ctrl_fpsensor_crypto){ \ + .output_type = MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL }) + +extern struct mock_ctrl_fpsensor_crypto mock_ctrl_fpsensor_crypto; + +#endif /* __MOCK_FPSENSOR_CRYPTO_MOCK_H */ diff --git a/include/mock/fpsensor_detect_mock.h b/include/mock/fpsensor_detect_mock.h index da23dded96..b8594ebdd9 100644 --- a/include/mock/fpsensor_detect_mock.h +++ b/include/mock/fpsensor_detect_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/mock/fpsensor_state_mock.h b/include/mock/fpsensor_state_mock.h index eafe01851c..32450e3cc0 100644 --- a/include/mock/fpsensor_state_mock.h +++ b/include/mock/fpsensor_state_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,11 +8,19 @@ #include <stdbool.h> #include <stdint.h> + +#include "driver/fingerprint/fpsensor.h" #include "ec_commands.h" extern const uint8_t default_fake_tpm_seed[FP_CONTEXT_TPM_BYTES]; +extern const uint8_t + default_fake_fp_positive_match_salt[FP_MAX_FINGER_COUNT] + [FP_POSITIVE_MATCH_SALT_BYTES]; +extern const uint8_t + trivial_fp_positive_match_salt[FP_MAX_FINGER_COUNT] + [FP_POSITIVE_MATCH_SALT_BYTES]; int fpsensor_state_mock_set_tpm_seed( const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES]); -#endif /* __MOCK_FPSENSOR_STATE_MOCK_H */ +#endif /* __MOCK_FPSENSOR_STATE_MOCK_H */ diff --git a/include/mock/mkbp_events_mock.h b/include/mock/mkbp_events_mock.h index 3d686e3618..22600e4f96 100644 --- a/include/mock/mkbp_events_mock.h +++ b/include/mock/mkbp_events_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,10 +15,11 @@ struct mock_ctrl_mkbp_events { int mkbp_send_event_return; }; -#define MOCK_CTRL_DEFAULT_MKBP_EVENTS \ -(struct mock_ctrl_mkbp_events) { \ - .mkbp_send_event_return = 1, \ -} +#define MOCK_CTRL_DEFAULT_MKBP_EVENTS \ + (struct mock_ctrl_mkbp_events) \ + { \ + .mkbp_send_event_return = 1, \ + } extern struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events; diff --git a/include/mock/rollback_mock.h b/include/mock/rollback_mock.h index 576f87e6b9..890e2539a7 100644 --- a/include/mock/rollback_mock.h +++ b/include/mock/rollback_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,11 +17,12 @@ struct mock_ctrl_rollback { bool get_secret_fail; }; -#define MOCK_CTRL_DEFAULT_ROLLBACK \ -(struct mock_ctrl_rollback) { \ - .get_secret_fail = false, \ -} +#define MOCK_CTRL_DEFAULT_ROLLBACK \ + (struct mock_ctrl_rollback) \ + { \ + .get_secret_fail = false, \ + } extern struct mock_ctrl_rollback mock_ctrl_rollback; -#endif /* __MOCK_ROLLBACK_MOCK_H */ +#endif /* __MOCK_ROLLBACK_MOCK_H */ diff --git a/include/mock/tcpc_mock.h b/include/mock/tcpc_mock.h index f4db14efb7..2f3a78c69a 100644 --- a/include/mock/tcpc_mock.h +++ b/include/mock/tcpc_mock.h @@ -1,8 +1,8 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ - /* Mock for the TCPC interface */ +/* Mock for the TCPC interface */ #include "usb_pd_tcpm.h" #include "usb_pd.h" @@ -28,7 +28,6 @@ struct mock_tcpc_ctrl { enum tcpc_rp_value rp; enum tcpc_cc_polarity polarity; } last; - }; /* Reset this TCPC mock */ diff --git a/include/mock/tcpci_i2c_mock.h b/include/mock/tcpci_i2c_mock.h index 1d4a986ebe..ae86a8c50b 100644 --- a/include/mock/tcpci_i2c_mock.h +++ b/include/mock/tcpci_i2c_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,15 +28,11 @@ int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type, int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, - enum pd_data_msg_type data_msg, - int timeout); + enum pd_data_msg_type data_msg, int timeout); int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type, - enum pd_data_msg_type data_msg, - uint8_t *data, - int data_bytes, - int *msg_len, - int timeout); + enum pd_data_msg_type data_msg, uint8_t *data, + int data_bytes, int *msg_len, int timeout); struct possible_tx { enum tcpci_msg_type tx_type; @@ -44,13 +40,9 @@ struct possible_tx { enum pd_data_msg_type data_msg; }; -int verify_tcpci_possible_tx(struct possible_tx possible[], - int possible_cnt, - int *found_index, - uint8_t *data, - int data_bytes, - int *msg_len, - int timeout); +int verify_tcpci_possible_tx(struct possible_tx possible[], int possible_cnt, + int *found_index, uint8_t *data, int data_bytes, + int *msg_len, int timeout); void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header, uint32_t *payload); diff --git a/include/mock/tcpm_mock.h b/include/mock/tcpm_mock.h index 7fd89919f5..2733863b62 100644 --- a/include/mock/tcpm_mock.h +++ b/include/mock/tcpm_mock.h @@ -1,8 +1,8 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ - /* Mock for the TCPM interface */ +/* Mock for the TCPM interface */ #include "common.h" #include "tcpm/tcpm.h" diff --git a/include/mock/timer_mock.h b/include/mock/timer_mock.h index 04dc01e9ab..cc294521cc 100644 --- a/include/mock/timer_mock.h +++ b/include/mock/timer_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,4 +12,4 @@ void set_time(timestamp_t now_); timestamp_t get_time(void); -#endif /* __MOCK_TIMER_MOCK_H */ +#endif /* __MOCK_TIMER_MOCK_H */ diff --git a/include/mock/usb_mux_mock.h b/include/mock/usb_mux_mock.h index 128286796b..c2d154ad72 100644 --- a/include/mock/usb_mux_mock.h +++ b/include/mock/usb_mux_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/mock/usb_pd_dpm_mock.h b/include/mock/usb_pd_dpm_mock.h index c61594fd2b..8f91cfb390 100644 --- a/include/mock/usb_pd_dpm_mock.h +++ b/include/mock/usb_pd_dpm_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/mock/usb_pe_sm_mock.h b/include/mock/usb_pe_sm_mock.h index fcd6e268a0..819f086c5a 100644 --- a/include/mock/usb_pe_sm_mock.h +++ b/include/mock/usb_pe_sm_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/mock/usb_prl_mock.h b/include/mock/usb_prl_mock.h index ee37d6e6e2..eef1d8de63 100644 --- a/include/mock/usb_prl_mock.h +++ b/include/mock/usb_prl_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,17 +13,14 @@ void mock_prl_reset(void); -int mock_prl_wait_for_tx_msg(int port, - enum tcpci_msg_type tx_type, +int mock_prl_wait_for_tx_msg(int port, enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, - enum pd_data_msg_type data_msg, - int timeout); + enum pd_data_msg_type data_msg, int timeout); enum pd_ctrl_msg_type mock_prl_get_last_sent_ctrl_msg(int port); enum pd_data_msg_type mock_prl_get_last_sent_data_msg(int port); - void mock_prl_clear_last_sent_msg(int port); void mock_prl_message_sent(int port); diff --git a/include/mock/usb_tc_sm_mock.h b/include/mock/usb_tc_sm_mock.h index ca16fb4d98..532f2bfb54 100644 --- a/include/mock/usb_tc_sm_mock.h +++ b/include/mock/usb_tc_sm_mock.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/mock_filter.h b/include/mock_filter.h index 113c227a3b..83beead6c7 100644 --- a/include/mock_filter.h +++ b/include/mock_filter.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,5 +18,4 @@ CONFIG_TEST_MOCK_LIST #endif - #endif /* __CROS_EC_MOCK_FILTER_H */ diff --git a/include/module_id.h b/include/module_id.h index 8872bdd45c..bfc780e70f 100644 --- a/include/module_id.h +++ b/include/module_id.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/motion_lid.h b/include/motion_lid.h index 28ddcaec24..917a545ab6 100644 --- a/include/motion_lid.h +++ b/include/motion_lid.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,4 +34,4 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args); void motion_lid_calc(void); -#endif /* __CROS_EC_MOTION_LID_H */ +#endif /* __CROS_EC_MOTION_LID_H */ diff --git a/include/motion_orientation.h b/include/motion_orientation.h index 641f97a799..4b1daaa58c 100644 --- a/include/motion_orientation.h +++ b/include/motion_orientation.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,13 +12,13 @@ #include "ec_commands.h" #include "motion_sense.h" -enum motionsensor_orientation motion_orientation_remap( - const struct motion_sensor_t *s, - enum motionsensor_orientation orientation); +enum motionsensor_orientation +motion_orientation_remap(const struct motion_sensor_t *s, + enum motionsensor_orientation orientation); bool motion_orientation_changed(const struct motion_sensor_t *s); -enum motionsensor_orientation *motion_orientation_ptr( - const struct motion_sensor_t *s); +enum motionsensor_orientation * +motion_orientation_ptr(const struct motion_sensor_t *s); void motion_orientation_update(const struct motion_sensor_t *s); -#endif /* __CROS_EC_MOTION_ORIENTATION_H */ +#endif /* __CROS_EC_MOTION_ORIENTATION_H */ diff --git a/include/motion_sense.h b/include/motion_sense.h index 1f2e912ce5..6033d52ff9 100644 --- a/include/motion_sense.h +++ b/include/motion_sense.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -39,7 +39,6 @@ enum sensor_config { #define SENSOR_ACTIVE_S0_S3 (SENSOR_ACTIVE_S3 | SENSOR_ACTIVE_S0) #define SENSOR_ACTIVE_S0_S3_S5 (SENSOR_ACTIVE_S0_S3 | SENSOR_ACTIVE_S5) - /* * Events layout: * 0 8 10 @@ -49,29 +48,27 @@ enum sensor_config { */ /* First 8 events for sensor interrupt lines */ -#define TASK_EVENT_MOTION_INTERRUPT_NUM 8 +#define TASK_EVENT_MOTION_INTERRUPT_NUM 8 #define TASK_EVENT_MOTION_INTERRUPT_MASK \ ((1 << TASK_EVENT_MOTION_INTERRUPT_NUM) - 1) -#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id) \ - BUILD_CHECK_INLINE( \ - TASK_EVENT_CUSTOM_BIT(_sensor_id), \ - _sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM) +#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id) \ + BUILD_CHECK_INLINE(TASK_EVENT_CUSTOM_BIT(_sensor_id), \ + _sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM) /* Internal events to motion sense task.*/ #define TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT TASK_EVENT_MOTION_INTERRUPT_NUM -#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM 2 +#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM 2 #define TASK_EVENT_MOTION_FLUSH_PENDING \ TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT) #define TASK_EVENT_MOTION_ODR_CHANGE \ TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT + 1) /* Activity events */ -#define TASK_EVENT_MOTION_FIRST_SW_EVENT \ +#define TASK_EVENT_MOTION_FIRST_SW_EVENT \ (TASK_EVENT_MOTION_INTERRUPT_NUM + TASK_EVENT_MOTION_INTERNAL_EVENT_NUM) -#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id) \ - (TASK_EVENT_CUSTOM_BIT( \ - TASK_EVENT_MOTION_FIRST_SW_EVENT + (_activity_id))) - +#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id) \ + (TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_SW_EVENT + \ + (_activity_id))) #define ROUND_UP_FLAG ((uint32_t)BIT(31)) #define BASE_ODR(_odr) ((_odr) & ~ROUND_UP_FLAG) @@ -87,13 +84,13 @@ enum sensor_config { * use peripheral addressing, it is up to the driver to use this * field as it sees fit */ -#define ACCEL_MK_I2C_ADDR_FLAGS(addr) (addr) -#define ACCEL_MK_SPI_ADDR_FLAGS(addr) ((addr) | I2C_FLAG_ADDR_IS_SPI) +#define ACCEL_MK_I2C_ADDR_FLAGS(addr) (addr) +#define ACCEL_MK_SPI_ADDR_FLAGS(addr) ((addr) | I2C_FLAG_ADDR_IS_SPI) -#define ACCEL_GET_I2C_ADDR(addr_flags) (I2C_STRIP_FLAGS(addr_flags)) -#define ACCEL_GET_SPI_ADDR(addr_flags) ((addr_flags) & I2C_ADDR_MASK) +#define ACCEL_GET_I2C_ADDR(addr_flags) (I2C_STRIP_FLAGS(addr_flags)) +#define ACCEL_GET_SPI_ADDR(addr_flags) ((addr_flags)&I2C_ADDR_MASK) -#define ACCEL_ADDR_IS_SPI(addr_flags) ((addr_flags) & I2C_FLAG_ADDR_IS_SPI) +#define ACCEL_ADDR_IS_SPI(addr_flags) ((addr_flags)&I2C_FLAG_ADDR_IS_SPI) /* * Define the frequency to use in max_frequency based on the maximal frequency @@ -101,9 +98,10 @@ enum sensor_config { * Return a frequency the sensor supports. * Trigger a compilation error when the EC way to slow for the sensor. */ -#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step) GENERIC_MIN( \ - (_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \ - (_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step))) +#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step) \ + GENERIC_MIN( \ + (_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \ + (_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step))) struct motion_data_t { /* @@ -126,7 +124,7 @@ struct motion_data_t { * When set, spoof mode will allow the EC to report arbitrary values for any of * the components. */ -#define MOTIONSENSE_FLAG_IN_SPOOF_MODE BIT(1) +#define MOTIONSENSE_FLAG_IN_SPOOF_MODE BIT(1) struct online_calib_data { /** @@ -222,12 +220,6 @@ struct motion_sensor_t { uint16_t oversampling_ratio; /* - * How many vector events are lost in the FIFO since last time - * FIFO info has been transmitted. - */ - uint16_t lost; - - /* * For sensors in forced mode the ideal time to collect the next * measurement. * @@ -353,8 +345,9 @@ static inline void ec_motion_sensor_clamp_i16s(int16_t *arr, const int32_t *v) } /* direct assignment */ -static inline void ec_motion_sensor_fill_values( - struct ec_response_motion_sensor_data *dst, const int32_t *v) +static inline void +ec_motion_sensor_fill_values(struct ec_response_motion_sensor_data *dst, + const int32_t *v) { dst->data[0] = v[0]; dst->data[1] = v[1]; diff --git a/include/motion_sense_fifo.h b/include/motion_sense_fifo.h index 90d3f78879..e4012e2372 100644 --- a/include/motion_sense_fifo.h +++ b/include/motion_sense_fifo.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,8 +12,8 @@ enum motion_sense_async_event { ASYNC_EVENT_FLUSH = MOTIONSENSE_SENSOR_FLAG_FLUSH | MOTIONSENSE_SENSOR_FLAG_TIMESTAMP, - ASYNC_EVENT_ODR = MOTIONSENSE_SENSOR_FLAG_ODR | - MOTIONSENSE_SENSOR_FLAG_TIMESTAMP, + ASYNC_EVENT_ODR = MOTIONSENSE_SENSOR_FLAG_ODR | + MOTIONSENSE_SENSOR_FLAG_TIMESTAMP, }; /** @@ -22,6 +22,15 @@ enum motion_sense_async_event { void motion_sense_fifo_init(void); /** + * Set the expected period between samples. Must be call under + * g_mutex_lock each time the sensor ODR changes. + * + * @param sensor_num Affected sensor + * @param data_period expected milliseconds between samples. + */ +void motion_sense_set_data_period(int sensor_num, uint32_t data_period); + +/** * Whether or not we need to bypass the FIFO to send an important message. * * @return Non zero when a bypass is needed. @@ -48,9 +57,8 @@ void motion_sense_fifo_reset_needed_flags(void); * @param sensor The sensor that generated the async event. * @param event The event to insert. */ -void motion_sense_fifo_insert_async_event( - struct motion_sensor_t *sensor, - enum motion_sense_async_event event); +void motion_sense_fifo_insert_async_event(struct motion_sensor_t *sensor, + enum motion_sense_async_event event); /** * Insert a timestamp into the fifo. @@ -69,11 +77,9 @@ void motion_sense_fifo_add_timestamp(uint32_t timestamp); * @param time accurate time (ideally measured in an interrupt) the sample * was taken at */ -void motion_sense_fifo_stage_data( - struct ec_response_motion_sensor_data *data, - struct motion_sensor_t *sensor, - int valid_data, - uint32_t time); +void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data, + struct motion_sensor_t *sensor, + int valid_data, uint32_t time); /** * Commit all the currently staged data to the fifo. Doing so makes it readable @@ -85,12 +91,12 @@ void motion_sense_fifo_commit_data(void); * Get information about the fifo. * * @param fifo_info The struct to modify with the current information about the - * fifo. + * fifo. WARNING: This must point to a buffer big enough for the struct + * and also sizeof(uint16_t) * MAX_MOTION_SENSORS of extra space. * @param reset Whether or not to reset statistics after reading them. */ void motion_sense_fifo_get_info( - struct ec_response_motion_sense_fifo_info *fifo_info, - int reset); + struct ec_response_motion_sense_fifo_info *fifo_info, int reset); /** * Check whether or not the fifo has gone over its threshold. diff --git a/include/newton_fit.h b/include/newton_fit.h index b4db64c814..2fb1994083 100644 --- a/include/newton_fit.h +++ b/include/newton_fit.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/ocpc.h b/include/ocpc.h index 3f7b08827f..da1c6907d4 100644 --- a/include/ocpc.h +++ b/include/ocpc.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,7 +17,7 @@ struct ocpc_data { int active_chg_chip; int combined_rsys_rbatt_mo; /* System resistance b/w output and Vbatt */ - int rsys_mo; /* System resistance b/w output and VSYS node */ + int rsys_mo; /* System resistance b/w output and VSYS node */ int rbatt_mo; /* Resistance between VSYS node and battery */ /* ADC values */ @@ -38,7 +38,7 @@ struct ocpc_data { #endif /* HAS_TASK_PD_C1 */ }; -#define OCPC_NO_ISYS_MEAS_CAP BIT(0) +#define OCPC_NO_ISYS_MEAS_CAP BIT(0) /** Set the VSYS target for the secondary charger IC. * @@ -49,8 +49,8 @@ struct ocpc_data { * @return EC_SUCCESS on success, error otherwise. */ int ocpc_config_secondary_charger(int *desired_input_current, - struct ocpc_data *ocpc, - int voltage_mv, int current_ma); + struct ocpc_data *ocpc, int voltage_mv, + int current_ma); /** Get the runtime data from the various ADCs. * @@ -59,9 +59,8 @@ int ocpc_config_secondary_charger(int *desired_input_current, void ocpc_get_adcs(struct ocpc_data *ocpc); /* Set the PID constants for the charging loop */ -__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div); +__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div); /* ** Set up some initial values for the OCPC data structure. This will call off diff --git a/include/onewire.h b/include/onewire.h index 58899360a4..0b328ceedc 100644 --- a/include/onewire.h +++ b/include/onewire.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -40,4 +40,4 @@ int onewire_read(void); */ void onewire_write(int data); -#endif /* __CROS_EC_ONEWIRE_H */ +#endif /* __CROS_EC_ONEWIRE_H */ diff --git a/include/online_calibration.h b/include/online_calibration.h index e3b259e14d..abeb192b75 100644 --- a/include/online_calibration.h +++ b/include/online_calibration.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,10 +22,9 @@ void online_calibration_init(void); * @param timestamp The time associated with the sample * @return EC_SUCCESS when successful. */ -int online_calibration_process_data( - struct ec_response_motion_sensor_data *data, - struct motion_sensor_t *sensor, - uint32_t timestamp); +int online_calibration_process_data(struct ec_response_motion_sensor_data *data, + struct motion_sensor_t *sensor, + uint32_t timestamp); /** * Check if new calibration values are available since the last read. diff --git a/include/otp.h b/include/otp.h index 7851411202..2047a2e19f 100644 --- a/include/otp.h +++ b/include/otp.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -29,4 +29,4 @@ int otp_write_serial(const char *serialno); */ const char *otp_read_serial(void); -#endif /* __CROS_EC_OTP_H */ +#endif /* __CROS_EC_OTP_H */ diff --git a/include/overflow.h b/include/overflow.h index 42eab6a094..884eec884a 100644 --- a/include/overflow.h +++ b/include/overflow.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,7 +26,7 @@ __has_builtin(__builtin_mul_overflow) #define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1 #endif -#endif /* __clang__ */ +#endif /* __clang__ */ #include "third_party/linux/overflow.h" diff --git a/include/panic.h b/include/panic.h index 6e4f17fcb9..9a1a78844e 100644 --- a/include/panic.h +++ b/include/panic.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,6 +15,19 @@ #include "software_panic.h" +/* + * Define these helpers if needed. While normally they would be derived from + * common.h, we cannot include that header here because this file is also used + * in the ectool and the build breaks. + */ +#ifndef test_mockable_noreturn +#if defined(TEST_BUILD) || defined(CONFIG_ZTEST) +#define test_mockable_noreturn __attribute__((weak)) +#else +#define test_mockable_noreturn noreturn +#endif +#endif /* test_mockable_noreturn */ + #ifdef __cplusplus extern "C" { #endif @@ -66,21 +79,21 @@ struct cortex_panic_data { /* NDS32 N8 registers saved on panic */ struct nds32_n8_panic_data { uint32_t itype; - uint32_t regs[16]; /* r0-r10, r15, fp, gp, lp, sp */ + uint32_t regs[16]; /* r0-r10, r15, fp, gp, lp, sp */ uint32_t ipc; uint32_t ipsw; }; /* RISC-V RV32I registers saved on panic */ struct rv32i_panic_data { - uint32_t regs[31]; /* sp, ra, gp, tp, a0-a7, t0-t6, s0-s11 */ - uint32_t mepc; /* mepc */ - uint32_t mcause; /* mcause */ + uint32_t regs[31]; /* sp, ra, gp, tp, a0-a7, t0-t6, s0-s11 */ + uint32_t mepc; /* mepc */ + uint32_t mcause; /* mcause */ }; /* x86 registers saved on panic */ struct x86_panic_data { - uint32_t vector; /* Exception vector number */ + uint32_t vector; /* Exception vector number */ /* Data pushed when exception handler called */ uint32_t error_code; @@ -102,18 +115,18 @@ struct x86_panic_data { /* Data saved across reboots */ struct panic_data { - uint8_t arch; /* Architecture (PANIC_ARCH_*) */ - uint8_t struct_version; /* Structure version (currently 2) */ - uint8_t flags; /* Flags (PANIC_DATA_FLAG_*) */ - uint8_t reserved; /* Reserved; set 0 */ + uint8_t arch; /* Architecture (PANIC_ARCH_*) */ + uint8_t struct_version; /* Structure version (currently 2) */ + uint8_t flags; /* Flags (PANIC_DATA_FLAG_*) */ + uint8_t reserved; /* Reserved; set 0 */ /* core specific panic data */ union { - struct cortex_panic_data cm; /* Cortex-Mx registers */ + struct cortex_panic_data cm; /* Cortex-Mx registers */ struct nds32_n8_panic_data nds_n8; /* NDS32 N8 registers */ - struct x86_panic_data x86; /* Intel x86 */ + struct x86_panic_data x86; /* Intel x86 */ #ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA - struct rv32i_panic_data riscv; /* RISC-V RV32I */ + struct rv32i_panic_data riscv; /* RISC-V RV32I */ #endif }; @@ -121,21 +134,21 @@ struct panic_data { * These fields go at the END of the struct so we can find it at the * end of memory. */ - uint32_t struct_size; /* Size of this struct */ - uint32_t magic; /* PANIC_SAVE_MAGIC if valid */ + uint32_t struct_size; /* Size of this struct */ + uint32_t magic; /* PANIC_SAVE_MAGIC if valid */ }; #ifdef CONFIG_RO_PANIC_DATA_SIZE BUILD_ASSERT(sizeof(struct panic_data) == CONFIG_RO_PANIC_DATA_SIZE); #endif -#define PANIC_DATA_MAGIC 0x21636e50 /* "Pnc!" */ +#define PANIC_DATA_MAGIC 0x21636e50 /* "Pnc!" */ enum panic_arch { - PANIC_ARCH_CORTEX_M = 1, /* Cortex-M architecture */ - PANIC_ARCH_NDS32_N8 = 2, /* NDS32 N8 architecture */ - PANIC_ARCH_X86 = 3, /* Intel x86 */ + PANIC_ARCH_CORTEX_M = 1, /* Cortex-M architecture */ + PANIC_ARCH_NDS32_N8 = 2, /* NDS32 N8 architecture */ + PANIC_ARCH_X86 = 3, /* Intel x86 */ #ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA - PANIC_ARCH_RISCV_RV32I = 4, /* RISC-V RV32I */ + PANIC_ARCH_RISCV_RV32I = 4, /* RISC-V RV32I */ #endif }; @@ -144,13 +157,13 @@ enum panic_arch { /* Flags for panic_data.flags */ /* panic_data.frame is valid */ -#define PANIC_DATA_FLAG_FRAME_VALID BIT(0) +#define PANIC_DATA_FLAG_FRAME_VALID BIT(0) /* Already printed at console */ -#define PANIC_DATA_FLAG_OLD_CONSOLE BIT(1) +#define PANIC_DATA_FLAG_OLD_CONSOLE BIT(1) /* Already returned via host command */ -#define PANIC_DATA_FLAG_OLD_HOSTCMD BIT(2) +#define PANIC_DATA_FLAG_OLD_HOSTCMD BIT(2) /* Already reported via host event */ -#define PANIC_DATA_FLAG_OLD_HOSTEVENT BIT(3) +#define PANIC_DATA_FLAG_OLD_HOSTEVENT BIT(3) /** * Write a string to the panic reporting device @@ -170,8 +183,8 @@ void panic_puts(const char *s); * @param format printf-style format string * @param ... Arguments to process */ -__attribute__((__format__(__printf__, 1, 2))) -void panic_printf(const char *format, ...); +__attribute__((__format__(__printf__, 1, 2))) void +panic_printf(const char *format, ...); /* * Print saved panic information @@ -197,10 +210,10 @@ void panic_data_ccprint(const struct panic_data *pdata); * @param linenum Line number where assertion happened */ #ifdef CONFIG_DEBUG_ASSERT_BRIEF -noreturn void panic_assert_fail(const char *fname, int linenum); +test_mockable_noreturn void panic_assert_fail(const char *fname, int linenum); #else -noreturn void panic_assert_fail(const char *msg, const char *func, - const char *fname, int linenum); +test_mockable_noreturn void panic_assert_fail(const char *msg, const char *func, + const char *fname, int linenum); #endif /** @@ -208,19 +221,27 @@ noreturn void panic_assert_fail(const char *msg, const char *func, * * @param msg Panic message */ -noreturn void panic(const char *msg); +#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST)) +noreturn +#endif + void + panic(const char *msg); /** * Display a default message and reset */ -noreturn void panic_reboot(void); +#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST)) +noreturn +#endif + void + panic_reboot(void); #ifdef CONFIG_SOFTWARE_PANIC /** * Store a panic log and halt the system for a software-related reason, such as * stack overflow or assertion failure. */ -noreturn void software_panic(uint32_t reason, uint32_t info); +test_mockable_noreturn void software_panic(uint32_t reason, uint32_t info); /** * Log a panic in the panic log, but don't halt the system. Normally @@ -254,8 +275,8 @@ void ignore_bus_fault(int ignored); * Return a pointer to the saved data from a previous panic that can be * safely interpreted * - * @param pointer to the valid panic data, or NULL if none available (for example, - * the last reboot was not caused by a panic). + * @param pointer to the valid panic data, or NULL if none available (for + * example, the last reboot was not caused by a panic). */ struct panic_data *panic_get_data(void); @@ -294,4 +315,4 @@ void chip_panic_data_backup(void); } #endif -#endif /* __CROS_EC_PANIC_H */ +#endif /* __CROS_EC_PANIC_H */ diff --git a/include/peci.h b/include/peci.h index 993e7d637d..401e3f999f 100644 --- a/include/peci.h +++ b/include/peci.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,37 +10,37 @@ #include "common.h" -#define PECI_TARGET_ADDRESS 0x30 -#define PECI_WRITE_DATA_FIFO_SIZE 15 -#define PECI_READ_DATA_FIFO_SIZE 16 +#define PECI_TARGET_ADDRESS 0x30 +#define PECI_WRITE_DATA_FIFO_SIZE 15 +#define PECI_READ_DATA_FIFO_SIZE 16 -#define PECI_GET_TEMP_READ_LENGTH 2 -#define PECI_GET_TEMP_WRITE_LENGTH 0 -#define PECI_GET_TEMP_TIMEOUT_US 200 +#define PECI_GET_TEMP_READ_LENGTH 2 +#define PECI_GET_TEMP_WRITE_LENGTH 0 +#define PECI_GET_TEMP_TIMEOUT_US 200 /* PECI Command Code */ enum peci_command_code { - PECI_CMD_PING = 0x00, - PECI_CMD_GET_DIB = 0xF7, - PECI_CMD_GET_TEMP = 0x01, - PECI_CMD_RD_PKG_CFG = 0xA1, - PECI_CMD_WR_PKG_CFG = 0xA5, - PECI_CMD_RD_IAMSR = 0xB1, - PECI_CMD_WR_IAMSR = 0xB5, - PECI_CMD_RD_PCI_CFG = 0x61, - PECI_CMD_WR_PCI_CFG = 0x65, + PECI_CMD_PING = 0x00, + PECI_CMD_GET_DIB = 0xF7, + PECI_CMD_GET_TEMP = 0x01, + PECI_CMD_RD_PKG_CFG = 0xA1, + PECI_CMD_WR_PKG_CFG = 0xA5, + PECI_CMD_RD_IAMSR = 0xB1, + PECI_CMD_WR_IAMSR = 0xB5, + PECI_CMD_RD_PCI_CFG = 0x61, + PECI_CMD_WR_PCI_CFG = 0x65, PECI_CMD_RD_PCI_CFG_LOCAL = 0xE1, PECI_CMD_WR_PCI_CFG_LOCAL = 0xE5, }; struct peci_data { enum peci_command_code cmd_code; /* command code */ - uint8_t addr; /* client address */ - uint8_t w_len; /* write length */ - uint8_t r_len; /* read length */ - uint8_t *w_buf; /* buffer pointer of write data */ - uint8_t *r_buf; /* buffer pointer of read data */ - int timeout_us; /* transaction timeout unit:us */ + uint8_t addr; /* client address */ + uint8_t w_len; /* write length */ + uint8_t r_len; /* read length */ + uint8_t *w_buf; /* buffer pointer of write data */ + uint8_t *r_buf; /* buffer pointer of read data */ + int timeout_us; /* transaction timeout unit:us */ }; /** @@ -62,4 +62,4 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr); */ int peci_transaction(struct peci_data *peci); -#endif /* __CROS_EC_PECI_H */ +#endif /* __CROS_EC_PECI_H */ diff --git a/include/peripheral_charger.h b/include/peripheral_charger.h index 0479b5e7bd..ac193ba2da 100644 --- a/include/peripheral_charger.h +++ b/include/peripheral_charger.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -87,7 +87,7 @@ */ /* Size of event queue. Use it to initialize struct pchg.events. */ -#define PCHG_EVENT_QUEUE_SIZE 8 +#define PCHG_EVENT_QUEUE_SIZE 8 enum pchg_event { /* No event */ @@ -143,7 +143,7 @@ enum pchg_error { PCHG_ERROR_OTHER, }; -#define PCHG_ERROR_MASK(e) BIT(e) +#define PCHG_ERROR_MASK(e) BIT(e) enum pchg_mode { PCHG_MODE_NORMAL = 0, @@ -189,7 +189,7 @@ struct pchg_update { */ struct pchg { /* Static configuration */ - const struct pchg_config * const cfg; + const struct pchg_config *const cfg; /* Current state of the port */ enum pchg_state state; /* Event queue */ @@ -220,12 +220,23 @@ struct pchg { * Peripheral charger driver */ struct pchg_drv { - /* Reset charger chip. */ + /* + * Reset charger chip. External reset (e.g by GPIO). No + * communication or data access is expected (e.g. no I2C access). + */ int (*reset)(struct pchg *ctx); - /* Initialize the charger. */ + /* + * Initialize the charger. Run setup needed only once per reset + * (e.g. enable I2C, unlock I2C). + */ int (*init)(struct pchg *ctx); /* Enable/disable the charger. */ int (*enable)(struct pchg *ctx, bool enable); + /* + * Get chip info, identify chip and setup function pointers + * (e.g. I2C read function). It needs to work without IRQ. + */ + int (*get_chip_info)(struct pchg *ctx); /* Get event info. */ int (*get_event)(struct pchg *ctx); /* Get battery level. */ @@ -246,7 +257,7 @@ extern struct pchg pchgs[]; extern const int pchg_count; /* Utility macro converting port config to port number. */ -#define PCHG_CTX_TO_PORT(ctx) ((ctx) - &pchgs[0]) +#define PCHG_CTX_TO_PORT(ctx) ((ctx) - &pchgs[0]) /** * Interrupt handler for a peripheral charger. diff --git a/include/physical_presence.h b/include/physical_presence.h index 0acbc65691..4f93eaea62 100644 --- a/include/physical_presence.h +++ b/include/physical_presence.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/port80.h b/include/port80.h index e6212ab593..7521788ea1 100644 --- a/include/port80.h +++ b/include/port80.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,9 +11,9 @@ #include "common.h" enum port_80_event { - PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */ - PORT_80_EVENT_RESET = 0x1002, /* RESET transition */ - PORT_80_IGNORE = 0xffff, /* Invalid POST CODE */ + PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */ + PORT_80_EVENT_RESET = 0x1002, /* RESET transition */ + PORT_80_IGNORE = 0xffff, /* Invalid POST CODE */ }; /** @@ -31,4 +31,4 @@ void port_80_write(int data); */ int port_80_read(void); -#endif /* __CROS_EC_PORT80_H */ +#endif /* __CROS_EC_PORT80_H */ diff --git a/include/power.h b/include/power.h index 6200392b95..c32b2714e5 100644 --- a/include/power.h +++ b/include/power.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,33 +14,33 @@ #include "gpio_signal.h" #include "task_id.h" -FORWARD_DECLARE_ENUM(power_state) { +FORWARD_DECLARE_ENUM(power_state){ /* Steady states */ - POWER_G3 = 0, /* - * System is off (not technically all the way into G3, - * which means totally unpowered...) - */ - POWER_S5, /* System is soft-off */ - POWER_S4, /* System is suspended to disk */ - POWER_S3, /* Suspend; RAM on, processor is asleep */ - POWER_S0, /* System is on */ + POWER_G3 = 0, /* + * System is off (not technically all the way into G3, + * which means totally unpowered...) + */ + POWER_S5, /* System is soft-off */ + POWER_S4, /* System is suspended to disk */ + POWER_S3, /* Suspend; RAM on, processor is asleep */ + POWER_S0, /* System is on */ #ifdef CONFIG_POWER_S0IX POWER_S0ix, #endif /* Transitions */ - POWER_G3S5, /* G3 -> S5 (at system init time) */ - POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */ - POWER_S3S0, /* S3 -> S0 */ - POWER_S0S3, /* S0 -> S3 */ - POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */ - POWER_S5G3, /* S5 -> G3 */ - POWER_S3S4, /* S3 -> S4 */ - POWER_S4S3, /* S4 -> S3 */ - POWER_S4S5, /* S4 -> S5 */ - POWER_S5S4, /* S5 -> S4 */ + POWER_G3S5, /* G3 -> S5 (at system init time) */ + POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */ + POWER_S3S0, /* S3 -> S0 */ + POWER_S0S3, /* S0 -> S3 */ + POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */ + POWER_S5G3, /* S5 -> G3 */ + POWER_S3S4, /* S3 -> S4 */ + POWER_S4S3, /* S4 -> S3 */ + POWER_S4S5, /* S4 -> S5 */ + POWER_S5S4, /* S5 -> S4 */ #ifdef CONFIG_POWER_S0IX - POWER_S0ixS0, /* S0ix -> S0 */ - POWER_S0S0ix, /* S0 -> S0ix */ + POWER_S0ixS0, /* S0ix -> S0 */ + POWER_S0S0ix, /* S0 -> S0ix */ #endif }; @@ -58,18 +58,18 @@ FORWARD_DECLARE_ENUM(power_state) { * +-----------------+------------------------------------+ */ -#define POWER_SIGNAL_ACTIVE_STATE BIT(0) -#define POWER_SIGNAL_ACTIVE_LOW (0 << 0) -#define POWER_SIGNAL_ACTIVE_HIGH BIT(0) +#define POWER_SIGNAL_ACTIVE_STATE BIT(0) +#define POWER_SIGNAL_ACTIVE_LOW (0 << 0) +#define POWER_SIGNAL_ACTIVE_HIGH BIT(0) -#define POWER_SIGNAL_INTR_STATE BIT(1) -#define POWER_SIGNAL_DISABLE_AT_BOOT BIT(1) +#define POWER_SIGNAL_INTR_STATE BIT(1) +#define POWER_SIGNAL_DISABLE_AT_BOOT BIT(1) /* Information on an power signal */ struct power_signal_info { - enum gpio_signal gpio; /* GPIO for signal */ - uint32_t flags; /* See POWER_SIGNAL_* macros */ - const char *name; /* Name of signal */ + enum gpio_signal gpio; /* GPIO for signal */ + uint32_t flags; /* See POWER_SIGNAL_* macros */ + const char *name; /* Name of signal */ }; /* @@ -161,7 +161,6 @@ int power_wait_signals_timeout(uint32_t want, int timeout); */ int power_wait_mask_signals_timeout(uint32_t want, uint32_t mask, int timeout); - /** * Set the low-level power chipset state. * @@ -177,7 +176,8 @@ void power_set_state(enum power_state new_state); #ifdef CONFIG_AP_POWER_CONTROL enum power_state power_get_state(void); #else -static inline enum power_state power_get_state(void) { +static inline enum power_state power_get_state(void) +{ return POWER_G3; } #endif @@ -208,7 +208,9 @@ enum power_state power_handle_state(enum power_state state); #ifdef CONFIG_AP_POWER_CONTROL void power_signal_interrupt(enum gpio_signal signal); #else -static inline void power_signal_interrupt(enum gpio_signal signal) { } +static inline void power_signal_interrupt(enum gpio_signal signal) +{ +} #endif /* !CONFIG_AP_POWER_CONTROL */ /** @@ -254,7 +256,7 @@ void power_set_host_sleep_state(enum host_sleep_event state); /* Context to pass to a host sleep command handler. */ struct host_sleep_event_context { uint32_t sleep_transitions; /* Number of sleep transitions observed */ - uint16_t sleep_timeout_ms; /* Timeout in milliseconds */ + uint16_t sleep_timeout_ms; /* Timeout in milliseconds */ }; /** @@ -264,9 +266,9 @@ struct host_sleep_event_context { * @param state Current host sleep state updated by the host. * @param ctx Possible sleep parameters and return values, depending on state. */ -__override_proto void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx); +__override_proto void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx); /** * Provide callback to allow board to take any action on host sleep event @@ -274,8 +276,8 @@ __override_proto void power_chipset_handle_host_sleep_event( * * @param state Current host sleep state updated by the host. */ -__override_proto void power_board_handle_host_sleep_event( - enum host_sleep_event state); +__override_proto void +power_board_handle_host_sleep_event(enum host_sleep_event state); /* * This is the default state of host sleep event. Calls to @@ -283,7 +285,7 @@ __override_proto void power_board_handle_host_sleep_event( * value. EC components listening to host sleep event updates can check for this * special value to know if the state was reset. */ -#define HOST_SLEEP_EVENT_DEFAULT_RESET 0 +#define HOST_SLEEP_EVENT_DEFAULT_RESET 0 enum sleep_notify_type { SLEEP_NOTIFY_NONE, @@ -337,8 +339,8 @@ enum sleep_hang_type { * * @param hang_type Host sleep hang type detected. */ -__override_proto void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type); +__override_proto void +power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type); /** * Provide callback to allow board to take action on host sleep hang @@ -349,8 +351,8 @@ __override_proto void power_chipset_handle_sleep_hang( * * @param hang_type Host sleep hang type detected. */ -__override_proto void power_board_handle_sleep_hang( - enum sleep_hang_type hang_type); +__override_proto void +power_board_handle_sleep_hang(enum sleep_hang_type hang_type); /** * Start the suspend process. @@ -422,7 +424,6 @@ void power_5v_enable(task_id_t tid, int enable); void test_power_common_state(void); #endif - #ifdef CONFIG_POWERSEQ_FAKE_CONTROL /** * Enable a fake S0 state @@ -442,4 +443,4 @@ void power_fake_s0(void); void power_fake_disable(void); #endif /* defined(CONFIG_POWER_FAKE_CONTROL) */ -#endif /* __CROS_EC_POWER_H */ +#endif /* __CROS_EC_POWER_H */ diff --git a/include/power/alderlake_slg4bd44540.h b/include/power/alderlake_slg4bd44540.h index 387a583240..20a85053fd 100644 --- a/include/power/alderlake_slg4bd44540.h +++ b/include/power/alderlake_slg4bd44540.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,13 +12,13 @@ #define __CROS_EC_ALDERLAKE_SLG4BD44540_H /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK) diff --git a/include/power/amd_x86.h b/include/power/amd_x86.h new file mode 100644 index 0000000000..57011d97df --- /dev/null +++ b/include/power/amd_x86.h @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_POWER_AMD_X86_H_ +#define __CROS_EC_POWER_AMD_X86_H_ + +/* + * In legacy EC-OS, the power signals are defined as part of + * the board include headers, but with Zephyr, this is common. + */ +#if defined(CONFIG_ZEPHYR) && defined(CONFIG_AP_X86_AMD) + +/* Power input signals */ +enum power_signal { + X86_SLP_S3_N, /* SOC -> SLP_S3_L */ + X86_SLP_S5_N, /* SOC -> SLP_S5_L */ + + X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ + X86_S5_PGOOD, /* PMIC -> S5_PWROK */ + + /* Number of X86 signals */ + POWER_SIGNAL_COUNT, +}; + +#endif + +#endif /* __CROS_EC_POWER_AMD_X86_H_ */ diff --git a/include/power/apollolake.h b/include/power/apollolake.h index cc864f26c3..d0931a6b84 100644 --- a/include/power/apollolake.h +++ b/include/power/apollolake.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,16 +12,15 @@ * Input state flags. * TODO: Normalize the power signal masks from board defines to SoC headers. */ -#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N) -#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) -#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N) -#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N) +#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N) +#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) +#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N) +#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N) #define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N -#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK) -#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N) +#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK) +#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N) -#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \ - IN_SLP_S4_N) +#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | IN_SLP_S4_N) #define IN_PGOOD_ALL_CORE (IN_RSMRST_N) @@ -34,16 +33,16 @@ enum power_signal { #ifdef CONFIG_POWER_S0IX - X86_SLP_S0_N, /* PCH -> SLP_S0_L */ + X86_SLP_S0_N, /* PCH -> SLP_S0_L */ #endif - X86_SLP_S3_N, /* PCH -> SLP_S3_L */ - X86_SLP_S4_N, /* PCH -> SLP_S4_L */ - X86_SUSPWRDNACK, /* PCH -> SUSPWRDNACK */ - - X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */ - X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */ - X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */ - X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */ + X86_SLP_S3_N, /* PCH -> SLP_S3_L */ + X86_SLP_S4_N, /* PCH -> SLP_S4_L */ + X86_SUSPWRDNACK, /* PCH -> SUSPWRDNACK */ + + X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */ + X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */ + X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */ + X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */ /* Number of X86 signals */ POWER_SIGNAL_COUNT diff --git a/include/power/cannonlake.h b/include/power/cannonlake.h index a056a96ec8..53e9ba2325 100644 --- a/include/power/cannonlake.h +++ b/include/power/cannonlake.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,18 +9,19 @@ #define __CROS_EC_CANNONLAKE_H /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK) -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ - PP5000_PGOOD_POWER_SIGNAL_MASK) +#define IN_ALL_S0 \ + (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ + PP5000_PGOOD_POWER_SIGNAL_MASK) #define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED diff --git a/include/power/cometlake-discrete.h b/include/power/cometlake-discrete.h index ae1d51c32b..430cb02dce 100644 --- a/include/power/cometlake-discrete.h +++ b/include/power/cometlake-discrete.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/power/cometlake.h b/include/power/cometlake.h index 0f48346c9e..405fe7f0d7 100644 --- a/include/power/cometlake.h +++ b/include/power/cometlake.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,19 +9,21 @@ #define __CROS_EC_COMETLAKE_H /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ - PP5000_PGOOD_POWER_SIGNAL_MASK) +#define IN_ALL_S0 \ + (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ + PP5000_PGOOD_POWER_SIGNAL_MASK) -#define CHIPSET_G3S5_POWERUP_SIGNAL (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \ - POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)) +#define CHIPSET_G3S5_POWERUP_SIGNAL \ + (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \ + POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)) #define CHARGER_INITIALIZED_DELAY_MS 100 #define CHARGER_INITIALIZED_TRIES 40 diff --git a/include/power/falconlite.h b/include/power/falconlite.h index 3c0baeff66..6afbbfbb94 100644 --- a/include/power/falconlite.h +++ b/include/power/falconlite.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/power/icelake.h b/include/power/icelake.h index 95460ae80d..6a08efbb42 100644 --- a/include/power/icelake.h +++ b/include/power/icelake.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,13 +11,13 @@ #include "stdbool.h" /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK) diff --git a/include/power/intel_x86.h b/include/power/intel_x86.h index 45f4a67786..9001cf8d49 100644 --- a/include/power/intel_x86.h +++ b/include/power/intel_x86.h @@ -1,11 +1,10 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Intel X86 chipset power control module for Chrome EC */ - #ifndef __CROS_EC_INTEL_X86_H #define __CROS_EC_INTEL_X86_H @@ -33,12 +32,12 @@ #endif /* GPIO for power signal */ -#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 +#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 #define SLP_S3_SIGNAL_L VW_SLP_S3_L #else #define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L #endif -#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 +#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 #define SLP_S4_SIGNAL_L VW_SLP_S4_L #else #define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L @@ -49,7 +48,7 @@ * use SLP_S4's GPIO as a proxy for SLP_S5. This matches old behavior and * effectively prevents S4 residency. */ -#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S5 +#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 #define SLP_S5_SIGNAL_L VW_SLP_S5_L #else #define SLP_S5_SIGNAL_L SLP_S4_SIGNAL_L diff --git a/include/power/meteorlake.h b/include/power/meteorlake.h index 2e8792de20..aedf9824fc 100644 --- a/include/power/meteorlake.h +++ b/include/power/meteorlake.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,11 +11,11 @@ #include "stdbool.h" /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) diff --git a/include/power/mt8186.h b/include/power/mt8186.h index a2ad5648ed..92eb42eff2 100644 --- a/include/power/mt8186.h +++ b/include/power/mt8186.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/power/mt8192.h b/include/power/mt8192.h index 7a992001ab..19f5ce081d 100644 --- a/include/power/mt8192.h +++ b/include/power/mt8192.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/power/qcom.h b/include/power/qcom.h index 5f5247fa87..ccf61ab4a5 100644 --- a/include/power/qcom.h +++ b/include/power/qcom.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/power/skylake.h b/include/power/skylake.h index c8a656c6c5..4da8ae9ea3 100644 --- a/include/power/skylake.h +++ b/include/power/skylake.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,13 +12,13 @@ * Input state flags. * TODO: Normalize the power signal masks from board defines to SoC headers. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) /* * DPWROK is NC / stuffing option on initial boards. diff --git a/include/power_button.h b/include/power_button.h index 167ca21e2b..9ff85abe7f 100644 --- a/include/power_button.h +++ b/include/power_button.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -69,4 +69,11 @@ int64_t get_time_dsw_pwrok(void); */ void board_pwrbtn_to_pch(int level); -#endif /* __CROS_EC_POWER_BUTTON_H */ +/** + * Simulates a power button press. + * + * @param duration Simulated power button press duration in ms. + */ +void power_button_simulate_press(unsigned int duration); + +#endif /* __CROS_EC_POWER_BUTTON_H */ diff --git a/include/power_led.h b/include/power_led.h index 05ea7ead3c..d488406cac 100644 --- a/include/power_led.h +++ b/include/power_led.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,7 +28,9 @@ void powerled_set_state(enum powerled_state state); #else -static inline void powerled_set_state(enum powerled_state state) {} +static inline void powerled_set_state(enum powerled_state state) +{ +} #endif diff --git a/include/printf.h b/include/printf.h index 37c0cc3949..f797ca593e 100644 --- a/include/printf.h +++ b/include/printf.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,16 +8,17 @@ #ifndef __CROS_EC_PRINTF_H #define __CROS_EC_PRINTF_H -#include <stdarg.h> /* For va_list */ -#include <stddef.h> /* For size_t */ +#include <stdarg.h> /* For va_list */ +#include <stdbool.h> +#include <stddef.h> /* For size_t */ +#include "console.h" +#include <stdio.h> #include "common.h" -/* The declaration of snprintf is changed to crec_snprintf for Zephyr, - * so include stdio.h from Zephyr. +/** + * Buffer size in bytes large enough to hold the largest possible timestamp. */ -#ifdef CONFIG_ZEPHYR -#include <stdio.h> -#endif +#define PRINTF_TIMESTAMP_BUF_SIZE 22 /* * Printf formatting: % [flags] [width] [.precision] [length] [type] @@ -51,23 +52,14 @@ * - 'c' - character * - 's' - null-terminated ASCII string * - 'd' - signed integer - * - 'i' - signed integer if CONFIG_PRINTF_LEGACY_LI_FORMAT is set (ignore l) + * - 'i' - signed integer (if CONFIG_PRINTF_LONG_IS_32BITS is enabled) * - 'u' - unsigned integer * - 'x' - unsigned integer, print as lower-case hexadecimal * - 'X' - unsigned integer, print as upper-case hexadecimal * - 'b' - unsigned integer, print as binary - * - * Special format codes: - * - '%ph' - binary data, print as hex; Use HEX_BUF(buffer, size) to encode - * parameters. - * - '%pP' - raw pointer. - * - "%pT" - current time in seconds - interpreted as "%.6T" for precision. - * Supply PRINTF_TIMESTAMP_NOW to use the current time, or supply a - * pointer to a 64-bit timestamp to print. + * - 'p' - pointer */ -#ifndef HIDE_EC_STDLIB - /** * Print formatted output to a function, like vfprintf() * @@ -84,40 +76,78 @@ __stdlib_compat int vfnprintf(int (*addchar)(void *context, int c), void *context, const char *format, va_list args); -#ifndef CONFIG_ZEPHYR -#define snprintf crec_snprintf -#define vsnprintf crec_vsnprintf -#endif +#ifdef TEST_BUILD +/** + * Converts @val to a string written in @buf. The value is converted from + * least-significant digit to most-significant digit, so the pointer returned + * does not necessarily point to the start of @buf. + * + * This function shouldn't be used directly; it's a helper function for other + * printf functions and only exposed for testing. + * + * @param[out] buf Destination buffer + * @param[in] buf_len Length of @buf in bytes + * @param[in] val Value to convert + * @param[in] precision Fixed point precision; -1 disables fixed point + * @param[in] base Base + * @param[in] uppercase true to print hex characters uppercase + * @return pointer to start of string on success (not necessarily the start of + * @buf). + * @return NULL on error + */ +char *uint64_to_str(char *buf, int buf_len, uint64_t val, int precision, + int base, bool uppercase); +#endif /* TEST_BUILD */ + +/** + * Print timestamp as string to the provided buffer. + * + * Guarantees NUL-termination if size != 0. + * + * @param[out] str Destination string + * @param[in] size Size of @str in bytes + * @param[in] timestamp Timestamp + * @return Length of string written to @str, not including terminating NUL. + * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0] + * is set to '\0'. + * @return -EC_ERROR_INVAL when @size is 0. + */ +int snprintf_timestamp(char *str, size_t size, uint64_t timestamp); /** - * Print formatted outut to a string. + * Print the current time as a string to the provided buffer. * - * Guarantees null-termination if size!=0. + * Guarantees NUL-termination if size != 0. * - * @param str Destination string - * @param size Size of destination in bytes - * @param format Format string - * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated. + * @param[out] str Destination string + * @param[in] size Size of @str in bytes + * @return Length of string written to @str, not including terminating NUL. + * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0] + * is set to '\0'. + * @return -EC_ERROR_INVAL when @size is 0. */ -__attribute__((__format__(__printf__, 3, 4))) -__stdlib_compat int crec_snprintf(char *str, size_t size, const char *format, - ...); +int snprintf_timestamp_now(char *str, size_t size); /** - * Print formatted output to a string. + * Prints bytes as a hex string in the provided buffer. * - * Guarantees null-termination if size!=0. + * Guarantees NUL-termination if size != 0. * - * @param str Destination string - * @param size Size of destination in bytes - * @param format Format string - * @param args Parameters - * @return The string length written to str, or a negative value on error. - * The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW. + * @param[out] str Destination string + * @param[in] size Size of @str in bytes + * @param[in] params Data to print + * @return Length of string written to @str, not including terminating NUL. + * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. + * @return -EC_ERROR_INVAL when @size is 0. */ -__stdlib_compat int crec_vsnprintf(char *str, size_t size, const char *format, - va_list args); +int snprintf_hex_buffer(char *str, size_t size, + const struct hex_buffer_params *params); -#endif /* !HIDE_EC_STDLIB */ +/** + * @param[in] num_bytes + * @return number of bytes needed to store @num_bytes as a string (including + * terminating '\0'). + */ +size_t hex_str_buf_size(size_t num_bytes); -#endif /* __CROS_EC_PRINTF_H */ +#endif /* __CROS_EC_PRINTF_H */ diff --git a/include/producer.h b/include/producer.h index b6a04883d6..81ef93ecf9 100644 --- a/include/producer.h +++ b/include/producer.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/include/pwm.h b/include/pwm.h index 401d3dc0ec..2ac46b3812 100644 --- a/include/pwm.h +++ b/include/pwm.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -39,34 +39,33 @@ void pwm_set_duty(enum pwm_channel ch, int percent); */ int pwm_get_duty(enum pwm_channel ch); - /* Flags for PWM config table */ /** * PWM output signal is inverted, so 100% duty means always low */ -#define PWM_CONFIG_ACTIVE_LOW BIT(0) +#define PWM_CONFIG_ACTIVE_LOW BIT(0) /** * PWM channel has a fan controller with a tach input and can auto-adjust * its duty cycle to produce a given fan RPM. */ -#define PWM_CONFIG_HAS_RPM_MODE BIT(1) +#define PWM_CONFIG_HAS_RPM_MODE BIT(1) /** * PWM clock select alternate source. The actual clock and alternate * source are chip dependent. */ -#define PWM_CONFIG_ALT_CLOCK BIT(2) +#define PWM_CONFIG_ALT_CLOCK BIT(2) /** * PWM channel has a complementary output signal which should be enabled in * addition to the primary output. */ -#define PWM_CONFIG_COMPLEMENTARY_OUTPUT BIT(3) +#define PWM_CONFIG_COMPLEMENTARY_OUTPUT BIT(3) /** * PWM channel must stay active in low-power idle, if enabled. */ -#define PWM_CONFIG_DSLEEP BIT(4) +#define PWM_CONFIG_DSLEEP BIT(4) /** * PWM channel's IO type is open-drain, if enabled. (default IO is push-pull.) */ -#define PWM_CONFIG_OPEN_DRAIN BIT(5) -#endif /* __CROS_EC_PWM_H */ +#define PWM_CONFIG_OPEN_DRAIN BIT(5) +#endif /* __CROS_EC_PWM_H */ diff --git a/include/pwr_defs.h b/include/pwr_defs.h index c01e602397..499a5b00e4 100644 --- a/include/pwr_defs.h +++ b/include/pwr_defs.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/queue.h b/include/queue.h index 6cf72563cb..6e7d4abbf8 100644 --- a/include/queue.h +++ b/include/queue.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -75,9 +75,9 @@ struct queue { struct queue_policy const *policy; - size_t buffer_units; /* size of buffer (in units) */ - size_t buffer_units_mask; /* size of buffer (in units) - 1*/ - size_t unit_bytes; /* size of unit (in byte) */ + size_t buffer_units; /* size of buffer (in units) */ + size_t buffer_units_mask; /* size of buffer (in units) - 1*/ + size_t unit_bytes; /* size of unit (in byte) */ uint8_t *buffer; }; @@ -86,14 +86,14 @@ struct queue { * and state structure. This macro creates a compound literal that can be used * to statically initialize a queue. */ -#define QUEUE(SIZE, TYPE, POLICY) \ - ((struct queue) { \ - .state = &((struct queue_state){}), \ - .policy = &POLICY, \ +#define QUEUE(SIZE, TYPE, POLICY) \ + ((struct queue){ \ + .state = &((struct queue_state){}), \ + .policy = &POLICY, \ .buffer_units = BUILD_CHECK_INLINE(SIZE, POWER_OF_TWO(SIZE)), \ - .buffer_units_mask = SIZE - 1, \ - .unit_bytes = sizeof(TYPE), \ - .buffer = (uint8_t *) &((TYPE[SIZE]){}), \ + .buffer_units_mask = SIZE - 1, \ + .unit_bytes = sizeof(TYPE), \ + .buffer = (uint8_t *)&((TYPE[SIZE]){}), \ }) /* Initialize the queue to empty state. */ @@ -143,7 +143,7 @@ void queue_next(struct queue const *q, struct queue_iterator *it); * buffer units. */ struct queue_chunk { - size_t count; + size_t count; void *buffer; }; @@ -206,12 +206,8 @@ size_t queue_add_unit(struct queue const *q, const void *src); size_t queue_add_units(struct queue const *q, const void *src, size_t count); /* Add multiple units to queue using supplied memcpy. */ -size_t queue_add_memcpy(struct queue const *q, - const void *src, - size_t count, - void *(*memcpy)(void *dest, - const void *src, - size_t n)); +size_t queue_add_memcpy(struct queue const *q, const void *src, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)); /* Remove one unit from the begin of the queue. */ size_t queue_remove_unit(struct queue const *q, void *dest); @@ -220,27 +216,18 @@ size_t queue_remove_unit(struct queue const *q, void *dest); size_t queue_remove_units(struct queue const *q, void *dest, size_t count); /* Remove multiple units from the begin of the queue using supplied memcpy. */ -size_t queue_remove_memcpy(struct queue const *q, - void *dest, - size_t count, - void *(*memcpy)(void *dest, - const void *src, +size_t queue_remove_memcpy(struct queue const *q, void *dest, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)); /* Peek (return but don't remove) the count elements starting with the i'th. */ -size_t queue_peek_units(struct queue const *q, - void *dest, - size_t i, +size_t queue_peek_units(struct queue const *q, void *dest, size_t i, size_t count); /* Peek (return but don't remove) the count elements starting with the i'th. */ -size_t queue_peek_memcpy(struct queue const *q, - void *dest, - size_t i, - size_t count, - void *(*memcpy)(void *dest, - const void *src, - size_t n)); +size_t +queue_peek_memcpy(struct queue const *q, void *dest, size_t i, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)); /* * These macros will statically select the queue functions based on the number @@ -248,28 +235,28 @@ size_t queue_peek_memcpy(struct queue const *q, * and remove functions are much faster than calling the equivalent generic * version with a count of one. */ -#define QUEUE_ADD_UNITS(q, src, count) \ - ({ \ - size_t result; \ - \ - if (count == 1) \ - result = queue_add_unit(q, src); \ - else \ - result = queue_add_units(q, src, count); \ - \ - result; \ +#define QUEUE_ADD_UNITS(q, src, count) \ + ({ \ + size_t result; \ + \ + if (count == 1) \ + result = queue_add_unit(q, src); \ + else \ + result = queue_add_units(q, src, count); \ + \ + result; \ }) -#define QUEUE_REMOVE_UNITS(q, dest, count) \ - ({ \ - size_t result; \ - \ - if (count == 1) \ - result = queue_remove_unit(q, dest); \ - else \ - result = queue_remove_units(q, dest, count); \ - \ - result; \ +#define QUEUE_REMOVE_UNITS(q, dest, count) \ + ({ \ + size_t result; \ + \ + if (count == 1) \ + result = queue_remove_unit(q, dest); \ + else \ + result = queue_remove_units(q, dest, count); \ + \ + result; \ }) #endif /* __CROS_EC_QUEUE_H */ diff --git a/include/queue_policies.h b/include/queue_policies.h index b9d698072f..aceb477ef6 100644 --- a/include/queue_policies.h +++ b/include/queue_policies.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -27,7 +27,7 @@ struct queue_policy_direct { void queue_add_direct(struct queue_policy const *policy, size_t count); void queue_remove_direct(struct queue_policy const *policy, size_t count); -#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER) \ +#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER) \ ((struct queue_policy_direct const) { \ .policy = { \ .add = queue_add_direct, \ @@ -37,7 +37,7 @@ void queue_remove_direct(struct queue_policy const *policy, size_t count); .consumer = &CONSUMER, \ }) -#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER) \ +#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER) \ QUEUE(SIZE, TYPE, QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER).policy) /* diff --git a/include/regulator.h b/include/regulator.h index 9dae7233c1..680239593e 100644 --- a/include/regulator.h +++ b/include/regulator.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/reset_flag_desc.inc b/include/reset_flag_desc.inc index ed3ce69a0d..a29f8d8d83 100644 --- a/include/reset_flag_desc.inc +++ b/include/reset_flag_desc.inc @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/rgb_keyboard.h b/include/rgb_keyboard.h index e795389225..56a3e09a91 100644 --- a/include/rgb_keyboard.h +++ b/include/rgb_keyboard.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,16 +10,16 @@ #include "stddef.h" /* Use this instead of '3' for readability where applicable. */ -#define SIZE_OF_RGB sizeof(struct rgb_s) +#define SIZE_OF_RGB sizeof(struct rgb_s) -#define RGBKBD_MAX_GCC_LEVEL 0xff -#define RGBKBD_MAX_SCALE 0xff +#define RGBKBD_MAX_GCC_LEVEL 0xff +#define RGBKBD_MAX_SCALE 0xff -#define RGBKBD_CTX_TO_GRID(ctx) ((ctx) - &rgbkbds[0]) +#define RGBKBD_CTX_TO_GRID(ctx) ((ctx) - &rgbkbds[0]) struct rgbkbd_cfg { /* Driver for LED IC */ - const struct rgbkbd_drv * const drv; + const struct rgbkbd_drv *const drv; /* SPI/I2C port (i.e. index of spi_devices[], i2c_ports[]) */ union { const uint8_t i2c; @@ -50,7 +50,7 @@ void rgbkbd_register_init_setting(const struct rgbkbd_init *setting); struct rgbkbd { /* Static configuration */ - const struct rgbkbd_cfg * const cfg; + const struct rgbkbd_cfg *const cfg; /* Current state of the port */ enum rgbkbd_state state; /* Buffer containing color info for each dot. */ @@ -85,8 +85,8 @@ struct rgbkbd_drv { * @param len Length of LEDs to be set. * @return enum ec_error_list */ - int (*set_scale)(struct rgbkbd *ctx, uint8_t offset, - struct rgb_s scale, uint8_t len); + int (*set_scale)(struct rgbkbd *ctx, uint8_t offset, struct rgb_s scale, + uint8_t len); /** * Set global current control. * @@ -98,24 +98,24 @@ struct rgbkbd_drv { /* Represents a position of an LED in RGB matrix. */ struct rgbkbd_coord { - uint8_t y: 3; - uint8_t x: 5; + uint8_t y : 3; + uint8_t x : 5; }; - /* - * For optimization, LED coordinates are encoded in LED IDs. This saves us one - * translation. - */ +/* + * For optimization, LED coordinates are encoded in LED IDs. This saves us one + * translation. + */ union rgbkbd_coord_u8 { uint8_t u8; struct rgbkbd_coord coord; }; -#define RGBKBD_COORD(x,y) ((x) << 3 | (y)) +#define RGBKBD_COORD(x, y) ((x) << 3 | (y)) /* Delimiter for rgbkbd_map data */ -#define RGBKBD_DELM 0xff +#define RGBKBD_DELM 0xff /* Non-existent entry indicator for rgbkbd_table */ -#define RGBKBD_NONE 0x00 +#define RGBKBD_NONE 0x00 /* * The matrix consists of multiple grids: @@ -154,6 +154,12 @@ extern const uint8_t rgbkbd_hsize; extern const uint8_t rgbkbd_vsize; /* + * rgbkbd_type describes the rgb kb type supported. + * i.e. Number of zones and number of LEDs + */ +extern enum ec_rgbkbd_type rgbkbd_type; + +/* * rgbkbd_map describes a mapping from key IDs to LED IDs. * * Multiple keys can be mapped to one LED and one key can be mapped to multiple diff --git a/include/rma_auth.h b/include/rma_auth.h index 0a4d7c7e71..2ad9299fed 100644 --- a/include/rma_auth.h +++ b/include/rma_auth.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,16 +10,16 @@ #include <stdint.h> -#include "common.h" /* For __packed. */ +#include "common.h" /* For __packed. */ /* Current challenge protocol version */ #define RMA_CHALLENGE_VERSION 0 /* Getters and setters for version_key_id byte */ #define RMA_CHALLENGE_VKID_BYTE(version, keyid) \ - (((version) << 6) | ((keyid) & 0x3f)) + (((version) << 6) | ((keyid)&0x3f)) #define RMA_CHALLENGE_GET_VERSION(vkidbyte) ((vkidbyte) >> 6) -#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte) & 0x3f) +#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte)&0x3f) #define RMA_DEVICE_ID_SIZE 8 diff --git a/include/rollback.h b/include/rollback.h index 8e439eaac3..55cff3a534 100644 --- a/include/rollback.h +++ b/include/rollback.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -71,4 +71,4 @@ int board_get_entropy(void *buffer, int len); #endif -#endif /* __CROS_EC_ROLLBACK_H */ +#endif /* __CROS_EC_ROLLBACK_H */ diff --git a/include/rsa.h b/include/rsa.h index 60d56711ca..bbc3795c68 100644 --- a/include/rsa.h +++ b/include/rsa.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -45,23 +45,21 @@ /* RSA public key definition, VBoot2 packing */ struct rsa_public_key { uint32_t size; - uint32_t n0inv; /* -1 / n[0] mod 2^32 */ - uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ + uint32_t n0inv; /* -1 / n[0] mod 2^32 */ + uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */ }; #else /* RSA public key definition */ struct rsa_public_key { - uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ + uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */ - uint32_t n0inv; /* -1 / n[0] mod 2^32 */ + uint32_t n0inv; /* -1 / n[0] mod 2^32 */ }; #endif -int rsa_verify(const struct rsa_public_key *key, - const uint8_t *signature, - const uint8_t *sha, - uint32_t *workbuf32); +int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature, + const uint8_t *sha, uint32_t *workbuf32); #endif /* !__ASSEMBLER__ */ diff --git a/include/rtc.h b/include/rtc.h index cff1ee0f64..0225801e71 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,14 +10,14 @@ #include "common.h" -#define SECS_PER_MINUTE 60 -#define SECS_PER_HOUR (60 * SECS_PER_MINUTE) -#define SECS_PER_DAY (24 * SECS_PER_HOUR) -#define SECS_PER_WEEK (7 * SECS_PER_DAY) -#define SECS_PER_YEAR (365 * SECS_PER_DAY) +#define SECS_PER_MINUTE 60 +#define SECS_PER_HOUR (60 * SECS_PER_MINUTE) +#define SECS_PER_DAY (24 * SECS_PER_HOUR) +#define SECS_PER_WEEK (7 * SECS_PER_DAY) +#define SECS_PER_YEAR (365 * SECS_PER_DAY) /* The seconds elapsed from 01-01-1970 to 01-01-2000 */ -#define SECS_TILL_YEAR_2K (946684800) -#define IS_LEAP_YEAR(x) \ +#define SECS_TILL_YEAR_2K (946684800) +#define IS_LEAP_YEAR(x) \ (((x) % 4 == 0) && (((x) % 100 != 0) || ((x) % 400 == 0))) struct calendar_date { diff --git a/include/rwsig.h b/include/rwsig.h index 425618490b..4abecfddd0 100644 --- a/include/rwsig.h +++ b/include/rwsig.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -77,22 +77,21 @@ void rwsig_jump_now(void); #endif /* ! CONFIG_RO_PUBKEY_SIZE */ #ifndef CONFIG_RO_PUBKEY_ADDR #ifdef CONFIG_RWSIG_TYPE_RWSIG -#define CONFIG_RO_PUBKEY_STORAGE_OFF (CONFIG_RO_STORAGE_OFF \ - + CONFIG_RO_SIZE \ - - CONFIG_RO_PUBKEY_SIZE) +#define CONFIG_RO_PUBKEY_STORAGE_OFF \ + (CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_RO_PUBKEY_SIZE) /* The pubkey resides at the end of the RO image */ -#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE \ - + CONFIG_EC_PROTECTED_STORAGE_OFF \ - + CONFIG_RO_PUBKEY_STORAGE_OFF) +#define CONFIG_RO_PUBKEY_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF + \ + CONFIG_RO_PUBKEY_STORAGE_OFF) #else /* * usbpd1 type assumes pubkey location at the end of first half of flash, * which might actually be in the PSTATE region. */ -#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE \ - + (CONFIG_FLASH_SIZE_BYTES / 2) \ - - CONFIG_RO_PUBKEY_SIZE) +#define CONFIG_RO_PUBKEY_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + (CONFIG_FLASH_SIZE_BYTES / 2) - \ + CONFIG_RO_PUBKEY_SIZE) #endif #endif /* CONFIG_RO_PUBKEY_ADDR */ @@ -108,19 +107,19 @@ void rwsig_jump_now(void); #endif #endif /* ! CONFIG_RW_SIG_SIZE */ /* The signature resides at the end of each RW copy */ -#define RW_SIG_OFFSET (CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) -#define RW_A_ADDR (CONFIG_PROGRAM_MEMORY_BASE + \ - CONFIG_EC_WRITABLE_STORAGE_OFF + \ - CONFIG_RW_STORAGE_OFF) +#define RW_SIG_OFFSET (CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define RW_A_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \ + CONFIG_RW_STORAGE_OFF) /* Assume the layout is same as RW_A and it sits right after RW_A */ -#define RW_B_ADDR (CONFIG_PROGRAM_MEMORY_BASE + \ - CONFIG_EC_WRITABLE_STORAGE_OFF + \ - CONFIG_RW_B_STORAGE_OFF) +#define RW_B_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \ + CONFIG_RW_B_STORAGE_OFF) #ifndef CONFIG_RW_SIG_ADDR -#define CONFIG_RW_SIG_ADDR (RW_A_ADDR + RW_SIG_OFFSET) +#define CONFIG_RW_SIG_ADDR (RW_A_ADDR + RW_SIG_OFFSET) #endif #ifndef CONFIG_RW_B_SIG_ADDR -#define CONFIG_RW_B_SIG_ADDR (RW_B_ADDR + RW_SIG_OFFSET) +#define CONFIG_RW_B_SIG_ADDR (RW_B_ADDR + RW_SIG_OFFSET) #endif #endif /* __CROS_EC_RWSIG_H */ diff --git a/include/sfdp.h b/include/sfdp.h index 087708d799..e1cd6372f2 100644 --- a/include/sfdp.h +++ b/include/sfdp.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,22 +12,20 @@ * Helper macros to declare and access SFDP defined bitfields at a JEDEC SFDP * defined double word (32b) granularity. */ -#define SFDP_DEFINE_BITMASK_32(name, hi, lo) \ - static const uint32_t name = (((1ULL << ((hi) - (lo) + 1)) - 1UL) \ - << (lo)); -#define SFDP_DEFINE_SHIFT_32(name, hi, lo) \ - static const size_t name = (lo); -#define SFDP_DEFINE_BITFIELD(name, hi, lo) \ - SFDP_DEFINE_BITMASK_32(name ## _MASK, hi, lo) \ - SFDP_DEFINE_SHIFT_32(name ## _SHIFT, hi, lo) -#define SFDP_GET_BITFIELD(name, dw) \ - (((dw) & name ## _MASK) >> name ## _SHIFT) +#define SFDP_DEFINE_BITMASK_32(name, hi, lo) \ + static const uint32_t name = \ + (((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo)); +#define SFDP_DEFINE_SHIFT_32(name, hi, lo) static const size_t name = (lo); +#define SFDP_DEFINE_BITFIELD(name, hi, lo) \ + SFDP_DEFINE_BITMASK_32(name##_MASK, hi, lo) \ + SFDP_DEFINE_SHIFT_32(name##_SHIFT, hi, lo) +#define SFDP_GET_BITFIELD(name, dw) (((dw)&name##_MASK) >> name##_SHIFT) /** * Helper macros to construct SFDP defined double words (32b). Note reserved or * unused fields must always be set to all 1's. */ -#define SFDP_BITFIELD(name, value) (((value) << name ## _SHIFT) & name ## _MASK) +#define SFDP_BITFIELD(name, value) (((value) << name##_SHIFT) & name##_MASK) #define SFDP_UNUSED(hi, lo) (((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo)) /******************************************************************************/ @@ -85,10 +83,9 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_S, 7, 0); SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_NPH, 23, 16); SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, 15, 8); SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0); -#define SFDP_HEADER_DWORD_2(nph, major, minor) \ - (SFDP_UNUSED(31, 24) | \ - SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) | \ - SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) | \ +#define SFDP_HEADER_DWORD_2(nph, major, minor) \ + (SFDP_UNUSED(31, 24) | SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) | \ + SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) | \ SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, minor)) /******************************************************************************/ @@ -98,7 +95,7 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0); /* In SFDP v1.0, the only reserved ID was the Basic Flash Parameter Table ID of * 0x00. Otherwise this field must be set to the vendor's manufacturer ID. Note, * the spec does not call out how to report the manufacturer bank number. */ - #define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00 +#define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00 /* * SFDP v1.0: Parameter Header 1st DWORD @@ -178,8 +175,8 @@ SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB, 7, 0); */ SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, 31, 24); SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, 23, 0); -#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp) \ - (SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) | \ +#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp) \ + (SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) | \ SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, ptp)) /******************************************************************************/ @@ -226,20 +223,20 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, 4, 4); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_REQ, 3, 3); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, 2, 2); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, 1, 0); -#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112, \ - rm4kb, wrenop, wrenrq, wrgr, ergr) \ - (SFDP_UNUSED(31, 23) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) | \ - SFDP_UNUSED(7, 5) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) | \ +#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112, rm4kb, wrenop, \ + wrenrq, wrgr, ergr) \ + (SFDP_UNUSED(31, 23) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) | \ + SFDP_UNUSED(7, 5) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) | \ SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, ergr)) /* Basic Flash Parameter Table v1.0 2nd DWORD @@ -270,13 +267,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, 15, 8); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, 7, 5); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, 4, 0); -#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc, \ - fr144op, fr144mb, fr144dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) | \ +#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc, fr144op, fr144mb, fr144dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) | \ SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, fr144dc)) /* Basic Flash Parameter Table v1.0 4th DWORD @@ -294,13 +290,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, 15, 8); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, 7, 5); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, 4, 0); -#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc, \ - fr112op, fr112mb, fr112dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) | \ +#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc, fr112op, fr112mb, fr112dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) | \ SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, fr112dc)) /* Basic Flash Parameter Table v1.0 5th DWORD @@ -328,9 +323,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW5_2_2_2_SUPPORTED, 0, 0); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, 23, 21); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16); -#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) | \ - SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) | \ +#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) | \ + SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) | \ SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, fr222dc) | \ SFDP_UNUSED(15, 0)) @@ -344,9 +339,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, 23, 21); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, 20, 16); -#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) | \ - SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) | \ +#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) | \ + SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) | \ SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, fr444dc) | \ SFDP_UNUSED(15, 0)) @@ -419,17 +414,16 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, 15, 11); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, 10, 9); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, 8, 4); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, 3, 0); -#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit, \ - rm3count, rm2unit, rm2count, \ - rm1unit, rm1count, maxmult) \ - (SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) | \ +#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit, rm3count, rm2unit, \ + rm2count, rm1unit, rm1count, maxmult) \ + (SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) | \ SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, maxmult)) /* Basic Flash Parameter Table v1.5 11th DWORD @@ -464,18 +458,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_WR_TIME_MAX_MULT, 3, 0); #define BFPT_1_5_DWORD_11(crmunit, crmcount, mrbunit, mrbcount, initunit, \ initcount, pgwrunit, pgwrcount, pagesz, maxmult) \ (SFDP_UNUSED(31, 31) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT, \ - crmunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT, \ - crmcount) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT, \ - mrbunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT, \ - mrbcount) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT, \ - initunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT, \ - initcount) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT, crmunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT, crmcount) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT, mrbunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT, mrbcount) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT, initunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT, initcount) | \ SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_UNIT, pgwrunit) | \ SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_CNT, pgwrcount) | \ SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, pagesz) | \ @@ -532,26 +520,21 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, 17, 13); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, 12, 9); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, 7, 4); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, 3, 0); -#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt, \ - suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt, \ - prohibopsrmsusp, prohibopswrsusp) \ - (SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT, \ - susprmlatun) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT, \ - susprmlatcnt) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT, \ - rmressusplatcnt) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT, \ - suspwrmaxlatunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, \ - suspwrmaxlatcnt) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, \ - wrressuspcnt) | \ - SFDP_UNUSED(8, 8) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, \ - prohibopsrmsusp) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, \ +#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt, \ + suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt, \ + prohibopsrmsusp, prohibopswrsusp) \ + (SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT, susprmlatun) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT, susprmlatcnt) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT, \ + rmressusplatcnt) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT, suspwrmaxlatunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, suspwrmaxlatcnt) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, wrressuspcnt) | \ + SFDP_UNUSED(8, 8) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, \ + prohibopsrmsusp) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, \ prohibopswrsusp)) /* Basic Flash Parameter Table v1.5 13th DWORD @@ -600,12 +583,10 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, 12, 8); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, 7, 2); #define BFPT_1_5_DWORD_14(pwrdwnunsup, pwrdwnop, pwrupop, pwrupunit, pwrupcnt, \ busypollflags) \ - (SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED, \ - pwrdwnunsup) | \ + (SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED, pwrdwnunsup) | \ SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_OPCODE, pwrdwnop) | \ SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_OPCODE, pwrupop) | \ - SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT, \ - pwrupunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT, pwrupunit) | \ SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, pwrupcnt) | \ SFDP_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, busypollflags) | \ SFDP_UNUSED(1, 0)) @@ -702,7 +683,6 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, 3, 0); SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_ENTRY, fr444entry) | \ SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, fr444exit)) - /* Basic Flash Parameter Table v1.5 16th DWORD * ------------------------------------------- * <31:24> : Enter 4-Byte Addressing, where @@ -804,4 +784,4 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, 6, 0); SFDP_UNUSED(7, 7) | \ SFDP_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, statusreg1)) -#endif /* __CROS_EC_SFDP_H */ +#endif /* __CROS_EC_SFDP_H */ diff --git a/include/sha1.h b/include/sha1.h index 42c0f2612f..12d277d1ac 100644 --- a/include/sha1.h +++ b/include/sha1.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,7 +11,7 @@ #include "common.h" #ifdef HOST_TOOLS_BUILD #include <string.h> -#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y)) +#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y)) #else #include "util.h" #endif @@ -33,4 +33,4 @@ void sha1_init(struct sha1_ctx *ctx); void sha1_update(struct sha1_ctx *ctx, const uint8_t *data, uint32_t len); uint8_t *sha1_final(struct sha1_ctx *ctx); -#endif /* __CROS_EC_SHA1_H */ +#endif /* __CROS_EC_SHA1_H */ diff --git a/include/sha256.h b/include/sha256.h index 130a666788..d1193c2661 100644 --- a/include/sha256.h +++ b/include/sha256.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,7 +26,7 @@ struct sha256_ctx { uint32_t tot_len; uint32_t len; uint8_t block[2 * SHA256_BLOCK_SIZE]; - uint8_t buf[SHA256_DIGEST_SIZE]; /* Used to store the final digest. */ + uint8_t buf[SHA256_DIGEST_SIZE]; /* Used to store the final digest. */ }; #endif @@ -37,4 +37,4 @@ uint8_t *SHA256_final(struct sha256_ctx *ctx); void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len, const uint8_t *message, const int message_len); -#endif /* __CROS_EC_SHA256_H */ +#endif /* __CROS_EC_SHA256_H */ diff --git a/include/shared_mem.h b/include/shared_mem.h index eadac22a48..307ce9f5e5 100644 --- a/include/shared_mem.h +++ b/include/shared_mem.h @@ -1,4 +1,4 @@ -/* Copyright 2011 The Chromium OS Authors. All rights reserved. +/* Copyright 2011 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -46,10 +46,10 @@ int shared_mem_size(void); */ int shared_mem_acquire(int size, char **dest_ptr); -#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr) \ - ({ \ - SHARED_MEM_CHECK_SIZE(size); \ - shared_mem_acquire((size), (dest_ptr)); \ +#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr) \ + ({ \ + SHARED_MEM_CHECK_SIZE(size); \ + shared_mem_acquire((size), (dest_ptr)); \ }) /** @@ -85,4 +85,4 @@ extern struct shm_buffer *free_buf_chain; extern struct shm_buffer *allocced_buf_chain; #endif -#endif /* __CROS_EC_SHARED_MEM_H */ +#endif /* __CROS_EC_SHARED_MEM_H */ diff --git a/include/software_panic.h b/include/software_panic.h index 2702c6dc92..d5eb8685b3 100644 --- a/include/software_panic.h +++ b/include/software_panic.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,23 +9,23 @@ #define __CROS_EC_SOFTWARE_PANIC_H /* Holds software panic reason PANIC_SW_* */ -#define SOFTWARE_PANIC_REASON_REG r4 -#define SOFTWARE_PANIC_INFO_REG r5 +#define SOFTWARE_PANIC_REASON_REG r4 +#define SOFTWARE_PANIC_INFO_REG r5 -#define PANIC_SW_BASE 0xDEAD6660 +#define PANIC_SW_BASE 0xDEAD6660 /* Software panic reasons */ -#define PANIC_SW_DIV_ZERO (PANIC_SW_BASE + 0) -#define PANIC_SW_STACK_OVERFLOW (PANIC_SW_BASE + 1) -#define PANIC_SW_PD_CRASH (PANIC_SW_BASE + 2) -#define PANIC_SW_ASSERT (PANIC_SW_BASE + 3) -#define PANIC_SW_WATCHDOG (PANIC_SW_BASE + 4) -#define PANIC_SW_BAD_RNG (PANIC_SW_BASE + 5) -#define PANIC_SW_PMIC_FAULT (PANIC_SW_BASE + 6) +#define PANIC_SW_DIV_ZERO (PANIC_SW_BASE + 0) +#define PANIC_SW_STACK_OVERFLOW (PANIC_SW_BASE + 1) +#define PANIC_SW_PD_CRASH (PANIC_SW_BASE + 2) +#define PANIC_SW_ASSERT (PANIC_SW_BASE + 3) +#define PANIC_SW_WATCHDOG (PANIC_SW_BASE + 4) +#define PANIC_SW_BAD_RNG (PANIC_SW_BASE + 5) +#define PANIC_SW_PMIC_FAULT (PANIC_SW_BASE + 6) #ifndef __ASSEMBLER__ -extern const char * const panic_sw_reasons[]; +extern const char *const panic_sw_reasons[]; extern int panic_sw_reason_is_valid(uint32_t vec); #endif -#endif /* __CROS_EC_SOFTWARE_PANIC_H */ +#endif /* __CROS_EC_SOFTWARE_PANIC_H */ diff --git a/include/spi.h b/include/spi.h index 28fc166f73..965f941fa3 100644 --- a/include/spi.h +++ b/include/spi.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -89,8 +89,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable); * @param rxlen number of bytes in rxdata or SPI_READBACK_ALL. */ int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen); /* * Similar to spi_transaction(), but hands over to DMA for reading response. @@ -100,8 +100,8 @@ int spi_transaction(const struct spi_device_t *spi_device, * SPI port, it's up to the caller to ensure proper mutual exclusion if needed. */ int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen); /* Wait for async response received */ int spi_transaction_flush(const struct spi_device_t *spi_device); @@ -131,4 +131,4 @@ static inline void spi_event(enum gpio_signal signal) #endif -#endif /* __CROS_EC_SPI_H */ +#endif /* __CROS_EC_SPI_H */ diff --git a/include/spi_flash.h b/include/spi_flash.h index ca3e796fd3..05fe8c098b 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,40 +12,40 @@ #define SPI_FLASH_SIZE(x) (1 << (x)) /* SPI flash instructions */ -#define SPI_FLASH_WRITE_ENABLE 0x06 -#define SPI_FLASH_WRITE_DISABLE 0x04 -#define SPI_FLASH_READ_SR1 0x05 -#define SPI_FLASH_READ_SR2 0x35 -#define SPI_FLASH_WRITE_SR 0x01 -#define SPI_FLASH_ERASE_4KB 0x20 -#define SPI_FLASH_ERASE_32KB 0x52 -#define SPI_FLASH_ERASE_64KB 0xD8 -#define SPI_FLASH_ERASE_CHIP 0xC7 -#define SPI_FLASH_READ 0x03 -#define SPI_FLASH_PAGE_PRGRM 0x02 -#define SPI_FLASH_REL_PWRDWN 0xAB -#define SPI_FLASH_MFR_DEV_ID 0x90 -#define SPI_FLASH_JEDEC_ID 0x9F -#define SPI_FLASH_UNIQUE_ID 0x4B -#define SPI_FLASH_SFDP 0x44 -#define SPI_FLASH_ERASE_SEC_REG 0x44 -#define SPI_FLASH_PRGRM_SEC_REG 0x42 -#define SPI_FLASH_READ_SEC_REG 0x48 -#define SPI_FLASH_ENABLE_RESET 0x66 -#define SPI_FLASH_RESET 0x99 +#define SPI_FLASH_WRITE_ENABLE 0x06 +#define SPI_FLASH_WRITE_DISABLE 0x04 +#define SPI_FLASH_READ_SR1 0x05 +#define SPI_FLASH_READ_SR2 0x35 +#define SPI_FLASH_WRITE_SR 0x01 +#define SPI_FLASH_ERASE_4KB 0x20 +#define SPI_FLASH_ERASE_32KB 0x52 +#define SPI_FLASH_ERASE_64KB 0xD8 +#define SPI_FLASH_ERASE_CHIP 0xC7 +#define SPI_FLASH_READ 0x03 +#define SPI_FLASH_PAGE_PRGRM 0x02 +#define SPI_FLASH_REL_PWRDWN 0xAB +#define SPI_FLASH_MFR_DEV_ID 0x90 +#define SPI_FLASH_JEDEC_ID 0x9F +#define SPI_FLASH_UNIQUE_ID 0x4B +#define SPI_FLASH_SFDP 0x44 +#define SPI_FLASH_ERASE_SEC_REG 0x44 +#define SPI_FLASH_PRGRM_SEC_REG 0x42 +#define SPI_FLASH_READ_SEC_REG 0x48 +#define SPI_FLASH_ENABLE_RESET 0x66 +#define SPI_FLASH_RESET 0x99 /* Maximum single write size (in bytes) for the W25Q64FV SPI flash */ -#define SPI_FLASH_MAX_WRITE_SIZE 256 +#define SPI_FLASH_MAX_WRITE_SIZE 256 /* * Maximum message size (in bytes) for the W25Q64FV SPI flash * Instruction (1) + Address (3) + Data (256) = 260 * Limited by chip maximum input length of write instruction */ -#define SPI_FLASH_MAX_MESSAGE_SIZE (SPI_FLASH_MAX_WRITE_SIZE + 4) +#define SPI_FLASH_MAX_MESSAGE_SIZE (SPI_FLASH_MAX_WRITE_SIZE + 4) /* Maximum single read size in bytes. Limited by size of the message buffer */ -#define SPI_FLASH_MAX_READ_SIZE (SPI_FLASH_MAX_MESSAGE_SIZE - 4) +#define SPI_FLASH_MAX_READ_SIZE (SPI_FLASH_MAX_MESSAGE_SIZE - 4) /* Status register write protect structure */ enum spi_flash_wp { @@ -120,7 +120,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes); * @return EC_SUCCESS, or non-zero if any error. */ int spi_flash_write(unsigned int offset, unsigned int bytes, - const uint8_t *data); + const uint8_t *data); /** * Gets the SPI flash JEDEC ID (manufacturer ID, memory type, and capacity) @@ -185,4 +185,4 @@ int spi_flash_check_protect(unsigned int offset, unsigned int bytes); */ int spi_flash_set_protect(unsigned int offset, unsigned int bytes); -#endif /* __CROS_EC_SPI_FLASH_H */ +#endif /* __CROS_EC_SPI_FLASH_H */ diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h index a0ffefc721..0d70d6982d 100644 --- a/include/spi_flash_reg.h +++ b/include/spi_flash_reg.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 The Chromium OS Authors. All rights reserved. + * Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,21 +15,21 @@ * Common register bits for SPI flash. All registers / bits may not be valid * for all parts. */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* SR2 register existence based upon chip */ #ifdef CONFIG_SPI_FLASH_W25X40 @@ -70,4 +70,4 @@ int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start, int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1, uint8_t *sr2); -#endif /* __CROS_EC_SPI_FLASH_REG_H */ +#endif /* __CROS_EC_SPI_FLASH_REG_H */ diff --git a/include/spi_nor.h b/include/spi_nor.h index f0c379cd43..9ffe3ebac9 100644 --- a/include/spi_nor.h +++ b/include/spi_nor.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -63,32 +63,32 @@ extern const unsigned int spi_nor_devices_used; /* Industry standard Serial NOR Flash opcodes. All other opcodes are part * specific and require SFDP discovery. */ -#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */ -#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */ -#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */ +#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */ +#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */ +#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */ #define SPI_NOR_OPCODE_WRITE_DISABLE 0x04 -#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */ -#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06 -#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */ -#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */ -#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */ -#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */ -#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */ +#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */ +#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06 +#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */ +#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */ +#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */ +#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */ +#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */ /* Flags for SPI_NOR_OPCODE_READ_STATUS */ -#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */ -#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */ +#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */ +#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */ /* If needed in the future this driver can be extended to discover SFDP * advertised erase sizes and opcodes for SFDP v1.0+. */ -#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20 +#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8 /* If needed in the future this driver can be extended to discover 4B entry and * exit methods for SFDP v1.5+. */ #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7 -#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9 +#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9 /* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */ #define SPI_NOR_JEDEC_ID_BANKS 12 @@ -144,8 +144,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device, * @param data Destination buffer for data. * @return ec_error_list (non-zero on error and timeout). */ -int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, - uint32_t offset, size_t size, uint8_t *data); +int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset, + size_t size, uint8_t *data); /** * Erase flash on the Serial Flash Device. @@ -181,5 +181,4 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device, int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device, const uint8_t value); - -#endif /* __CROS_EC_SPI_NOR_H */ +#endif /* __CROS_EC_SPI_NOR_H */ diff --git a/include/stack_trace.h b/include/stack_trace.h index 52ebe3619f..90d20519b9 100644 --- a/include/stack_trace.h +++ b/include/stack_trace.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,8 +18,12 @@ void task_register_tracedump(void); /* Dump current stack trace */ void task_dump_trace(void); #else -static inline void task_register_tracedump(void) { } -static inline void task_dump_trace(void) { } +static inline void task_register_tracedump(void) +{ +} +static inline void task_dump_trace(void) +{ +} #endif -#endif /* __CROS_EC_STACK_TRACE_H */ +#endif /* __CROS_EC_STACK_TRACE_H */ diff --git a/include/stillness_detector.h b/include/stillness_detector.h index 65598d4d5c..79de2de79f 100644 --- a/include/stillness_detector.h +++ b/include/stillness_detector.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/switch.h b/include/switch.h index e026408af9..97d428e356 100644 --- a/include/switch.h +++ b/include/switch.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,7 +19,9 @@ */ void switch_interrupt(enum gpio_signal signal); #else -static inline void switch_interrupt(enum gpio_signal signal) { } -#endif /* !CONFIG_SWITCH */ +static inline void switch_interrupt(enum gpio_signal signal) +{ +} +#endif /* !CONFIG_SWITCH */ -#endif /* __CROS_EC_SWITCH_H */ +#endif /* __CROS_EC_SWITCH_H */ diff --git a/include/sysjump.h b/include/sysjump.h index f5bf5f5a09..7d86df2e61 100644 --- a/include/sysjump.h +++ b/include/sysjump.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,10 +16,10 @@ * images. */ -#define JUMP_DATA_MAGIC 0x706d754a /* "Jump" */ +#define JUMP_DATA_MAGIC 0x706d754a /* "Jump" */ #define JUMP_DATA_VERSION 3 -#define JUMP_DATA_SIZE_V1 12 /* Size of version 1 jump data struct */ -#define JUMP_DATA_SIZE_V2 16 /* Size of version 2 jump data struct */ +#define JUMP_DATA_SIZE_V1 12 /* Size of version 1 jump data struct */ +#define JUMP_DATA_SIZE_V2 16 /* Size of version 2 jump data struct */ struct jump_data { /* @@ -29,19 +29,19 @@ struct jump_data { */ /* Fields from version 3 */ - uint8_t reserved0; /* (used in proto1 to signal recovery mode) */ - int struct_size; /* Size of struct jump_data */ + uint8_t reserved0; /* (used in proto1 to signal recovery mode) */ + int struct_size; /* Size of struct jump_data */ /* Fields from version 2 */ - int jump_tag_total; /* Total size of all jump tags */ + int jump_tag_total; /* Total size of all jump tags */ /* Fields from version 1 */ uint32_t reset_flags; /* Reset flags from the previous boot */ - int version; /* Version (JUMP_DATA_VERSION) */ - int magic; /* Magic number (JUMP_DATA_MAGIC). If this - * doesn't match at pre-init time, assume no valid - * data from the previous image. - */ + int version; /* Version (JUMP_DATA_VERSION) */ + int magic; /* Magic number (JUMP_DATA_MAGIC). If this + * doesn't match at pre-init time, assume no valid + * data from the previous image. + */ }; /** @@ -49,4 +49,4 @@ struct jump_data { */ struct jump_data *get_jump_data(void); -#endif /* __CROS_EC_SYSJUMP_IMPL_H */ +#endif /* __CROS_EC_SYSJUMP_IMPL_H */ diff --git a/include/system.h b/include/system.h index 0fc0206bb3..f55e091e90 100644 --- a/include/system.h +++ b/include/system.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -89,6 +89,12 @@ void system_enter_hibernate(uint32_t seconds, uint32_t microseconds); __test_only void system_common_reset_state(void); /** + * Return the value of reboot_at_shutdown and reset its value, useful for + * testing. + */ +__test_only enum ec_reboot_cmd system_common_get_reset_reboot_at_shutdown(void); + +/** * @brief Allow tests to manually set the jump data address. * * This function allows an override of the location of the jump data (which is @@ -328,17 +334,17 @@ const char *system_get_build_info(void); * Hard reset. Cuts power to the entire system. If not present, does a soft * reset which just resets the core and on-chip peripherals. */ -#define SYSTEM_RESET_HARD BIT(0) +#define SYSTEM_RESET_HARD BIT(0) /* * Preserve existing reset flags. Used by flash pre-init when it discovers it * needs to do a hard reset to clear write protect registers. */ -#define SYSTEM_RESET_PRESERVE_FLAGS BIT(1) +#define SYSTEM_RESET_PRESERVE_FLAGS BIT(1) /* * Leave AP off on next reboot, instead of powering it on to do EC software * sync. */ -#define SYSTEM_RESET_LEAVE_AP_OFF BIT(2) +#define SYSTEM_RESET_LEAVE_AP_OFF BIT(2) /* * Indicate that this was a manually triggered reset. */ @@ -346,30 +352,33 @@ const char *system_get_build_info(void); /* * Wait for reset pin to be driven, rather that resetting ourselves. */ -#define SYSTEM_RESET_WAIT_EXT BIT(4) +#define SYSTEM_RESET_WAIT_EXT BIT(4) /* * Indicate that this reset was triggered by an AP watchdog */ -#define SYSTEM_RESET_AP_WATCHDOG BIT(5) +#define SYSTEM_RESET_AP_WATCHDOG BIT(5) /* * Stay in RO next reboot, instead of potentially selecting RW during EFS. */ -#define SYSTEM_RESET_STAY_IN_RO BIT(6) +#define SYSTEM_RESET_STAY_IN_RO BIT(6) /* * Hibernate reset. Reset EC when wake up from hibernate mode * (the most power saving mode). */ -#define SYSTEM_RESET_HIBERNATE BIT(7) +#define SYSTEM_RESET_HIBERNATE BIT(7) /** * Reset the system. * * @param flags Reset flags; see SYSTEM_RESET_* above. */ -#ifndef TEST_FUZZ +#if (defined(TEST_FUZZ) || defined(CONFIG_ZTEST)) +test_mockable +#else noreturn #endif -void system_reset(int flags); + void + system_reset(int flags); /** * Set a scratchpad register to the specified value. @@ -440,7 +449,6 @@ __override_proto const char *board_read_serial(void); */ __override_proto int board_write_serial(const char *serial); - /** * Optional board-level callback functions to read a unique MAC address per * chip. Default implementation reads from flash. @@ -525,7 +533,9 @@ timestamp_t system_get_rtc(void); #ifdef CONFIG_RTC void print_system_rtc(enum console_channel channel); #else -static inline void print_system_rtc(enum console_channel channel) { } +static inline void print_system_rtc(enum console_channel channel) +{ +} #endif /* !defined(CONFIG_RTC) */ /** @@ -538,32 +548,31 @@ enum { /* * Sleep masks to prevent going in to deep sleep. */ - SLEEP_MASK_AP_RUN = BIT(0), /* the main CPU is running */ - SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */ + SLEEP_MASK_AP_RUN = BIT(0), /* the main CPU is running */ + SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */ SLEEP_MASK_I2C_CONTROLLER = BIT(2), /* I2C controller comms ongoing */ - SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */ - SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */ - SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */ - SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */ + SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */ + SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */ + SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */ + SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */ SLEEP_MASK_I2C_PERIPHERAL = BIT(7), /* I2C peripheral comms ongoing */ - SLEEP_MASK_FAN = BIT(8), /* Fan control loop ongoing */ + SLEEP_MASK_FAN = BIT(8), /* Fan control loop ongoing */ SLEEP_MASK_USB_DEVICE = BIT(9), /* Generic USB device in use */ - SLEEP_MASK_PWM = BIT(10), /* PWM output is enabled */ - SLEEP_MASK_PHYSICAL_PRESENCE = BIT(11), /* Physical presence - * detection ongoing */ - SLEEP_MASK_PLL = BIT(12), /* High-speed PLL in-use */ - SLEEP_MASK_ADC = BIT(13), /* ADC conversion ongoing */ - SLEEP_MASK_EMMC = BIT(14), /* eMMC emulation ongoing */ - SLEEP_MASK_FORCE_NO_DSLEEP = BIT(15), /* Force disable. */ - + SLEEP_MASK_PWM = BIT(10), /* PWM output is enabled */ + SLEEP_MASK_PHYSICAL_PRESENCE = BIT(11), /* Physical presence + * detection ongoing */ + SLEEP_MASK_PLL = BIT(12), /* High-speed PLL in-use */ + SLEEP_MASK_ADC = BIT(13), /* ADC conversion ongoing */ + SLEEP_MASK_EMMC = BIT(14), /* eMMC emulation ongoing */ + SLEEP_MASK_FORCE_NO_DSLEEP = BIT(15), /* Force disable. */ /* * Sleep masks to prevent using slow speed clock in deep sleep. */ - SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */ - SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */ + SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */ + SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */ - SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */ + SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */ }; /* @@ -578,10 +587,9 @@ extern atomic_t sleep_mask; */ #ifndef CONFIG_LOW_POWER_S0 -#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff)) +#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff)) #else -#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff & \ - (~SLEEP_MASK_AP_RUN))) +#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff & (~SLEEP_MASK_AP_RUN))) #endif #define LOW_SPEED_DEEP_SLEEP_ALLOWED (!(sleep_mask & 0xffff0000)) @@ -650,6 +658,13 @@ void disable_deep_sleep(void); void enable_deep_sleep(void); /** + * This function is made visible for tests only, it allows overriding the RTC. + * + * @param seconds + */ +void system_set_rtc(uint32_t seconds); + +/** * Use hibernate module to set up an RTC interrupt at a given * time from now * @@ -761,4 +776,4 @@ uint32_t flash_get_rw_offset(enum ec_image copy); */ void system_compensate_rtc(void); -#endif /* __CROS_EC_SYSTEM_H */ +#endif /* __CROS_EC_SYSTEM_H */ diff --git a/include/tablet_mode.h b/include/tablet_mode.h index 6ad565628c..e257fedc04 100644 --- a/include/tablet_mode.h +++ b/include/tablet_mode.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,8 +14,8 @@ int tablet_get_mode(void); /* Bit mask of tablet mode trigger */ -#define TABLET_TRIGGER_LID BIT(0) -#define TABLET_TRIGGER_BASE BIT(1) +#define TABLET_TRIGGER_LID BIT(0) +#define TABLET_TRIGGER_BASE BIT(1) /** * Set tablet mode state @@ -56,4 +56,7 @@ void gmr_tablet_switch_disable(void); */ int board_sensor_at_360(void); -#endif /* __CROS_EC_TABLET_MODE_H */ +/** Reset internal tablet mode state, used for testing. */ +__test_only void tablet_reset(void); + +#endif /* __CROS_EC_TABLET_MODE_H */ diff --git a/include/task.h b/include/task.h index 0343644437..5010900e59 100644 --- a/include/task.h +++ b/include/task.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,48 +22,47 @@ #define TASK_EVENT_SYSJUMP_READY BIT(16) /* Used to signal that IPC layer is available for sending new data */ -#define TASK_EVENT_IPC_READY BIT(17) +#define TASK_EVENT_IPC_READY BIT(17) -#define TASK_EVENT_PD_AWAKE BIT(18) +#define TASK_EVENT_PD_AWAKE BIT(18) /* npcx peci event */ -#define TASK_EVENT_PECI_DONE BIT(19) +#define TASK_EVENT_PECI_DONE BIT(19) /* I2C tx/rx interrupt handler completion event. */ #ifdef CHIP_STM32 -#define TASK_EVENT_I2C_COMPLETION(port) \ - (1 << ((port) + 20)) -#define TASK_EVENT_I2C_IDLE (TASK_EVENT_I2C_COMPLETION(0)) -#define TASK_EVENT_MAX_I2C 6 +#define TASK_EVENT_I2C_COMPLETION(port) (1 << ((port) + 20)) +#define TASK_EVENT_I2C_IDLE (TASK_EVENT_I2C_COMPLETION(0)) +#define TASK_EVENT_MAX_I2C 6 #ifdef I2C_PORT_COUNT #if (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) #error "Too many i2c ports for i2c events" #endif #endif #else -#define TASK_EVENT_I2C_IDLE BIT(20) -#define TASK_EVENT_PS2_DONE BIT(21) +#define TASK_EVENT_I2C_IDLE BIT(20) +#define TASK_EVENT_PS2_DONE BIT(21) #endif /* DMA transmit complete event */ -#define TASK_EVENT_DMA_TC BIT(26) +#define TASK_EVENT_DMA_TC BIT(26) /* ADC interrupt handler event */ -#define TASK_EVENT_ADC_DONE BIT(27) +#define TASK_EVENT_ADC_DONE BIT(27) /* * task_reset() that was requested has been completed * * For test-only builds, may be used by some tasks to restart themselves. */ -#define TASK_EVENT_RESET_DONE BIT(28) +#define TASK_EVENT_RESET_DONE BIT(28) /* task_wake() called on task */ -#define TASK_EVENT_WAKE BIT(29) +#define TASK_EVENT_WAKE BIT(29) /* Mutex unlocking */ -#define TASK_EVENT_MUTEX BIT(30) +#define TASK_EVENT_MUTEX BIT(30) /* * Timer expired. For example, task_wait_event() timed out before receiving * another event. */ -#define TASK_EVENT_TIMER (1U << 31) +#define TASK_EVENT_TIMER (1U << 31) /* Maximum time for task_wait_event() */ #define TASK_MAX_WAIT_US 0x7fffffff @@ -402,7 +401,7 @@ typedef struct mutex mutex_t; * initialize it. We provide the same macro for CrOS EC OS so that we * can use it in shared code. */ -#define K_MUTEX_DEFINE(name) static mutex_t name = { } +#define K_MUTEX_DEFINE(name) static mutex_t name = {} /** * Lock a mutex. @@ -456,8 +455,8 @@ struct irq_def { #define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler) #define IRQ_HANDLER_OPT(irqname) CONCAT3(irq_, irqname, _handler_optional) #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority) -#define DECLARE_IRQ_(irq, routine, priority) \ - static void __keep routine(void); \ +#define DECLARE_IRQ_(irq, routine, priority) \ + static void __keep routine(void); \ void IRQ_HANDLER_OPT(irq)(void) __attribute__((alias(#routine))) /* Include ec.irqlist here for compilation dependency */ @@ -468,4 +467,4 @@ struct irq_def { #endif /* CONFIG_COMMON_RUNTIME */ #endif /* !CONFIG_ZEPHYR */ -#endif /* __CROS_EC_TASK_H */ +#endif /* __CROS_EC_TASK_H */ diff --git a/include/task_filter.h b/include/task_filter.h index 2cd5e8bbf8..50fc46ce7f 100644 --- a/include/task_filter.h +++ b/include/task_filter.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -50,5 +50,4 @@ CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST #endif - #endif /* __CROS_EC_TASK_FILTER_H */ diff --git a/include/task_id.h b/include/task_id.h index 2ea10c9595..e617d820b5 100644 --- a/include/task_id.h +++ b/include/task_id.h @@ -1,4 +1,4 @@ -/* Copyright 2011 The Chromium OS Authors. All rights reserved. +/* Copyright 2011 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,8 +17,8 @@ #include "task_filter.h" /* define the name of the header containing the list of tasks */ -#define STRINGIFY0(name) #name -#define STRINGIFY(name) STRINGIFY0(name) +#define STRINGIFY0(name) #name +#define STRINGIFY(name) STRINGIFY0(name) #define CTS_TASK_LIST STRINGIFY(CTS_TASKFILE) #define TEST_TASK_LIST STRINGIFY(TEST_TASKFILE) #define BOARD_TASK_LIST STRINGIFY(BOARD_TASKFILE) @@ -46,16 +46,17 @@ enum { TASK_ID_IDLE, /* CONFIG_TASK_LIST is a macro coming from the BOARD_TASK_LIST file */ CONFIG_TASK_LIST - /* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file */ - CONFIG_TEST_TASK_LIST - /* For CTS tasks */ - CONFIG_CTS_TASK_LIST + /* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file + */ + CONFIG_TEST_TASK_LIST + /* For CTS tasks */ + CONFIG_CTS_TASK_LIST #ifdef EMU_BUILD - TASK_ID_TEST_RUNNER, + TASK_ID_TEST_RUNNER, #endif /* Number of tasks */ TASK_ID_COUNT, - /* Special task identifiers */ +/* Special task identifiers */ #ifdef EMU_BUILD TASK_ID_INT_GEN = 0xfe, /* interrupt generator */ #endif diff --git a/include/temp_sensor.h b/include/temp_sensor.h index f8b6f64508..469d4d4764 100644 --- a/include/temp_sensor.h +++ b/include/temp_sensor.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,7 +38,7 @@ struct temp_sensor_t { * to all use OO style sensor argument to get adc idx. */ #ifdef CONFIG_ZEPHYR - struct zephyr_temp_sensor *zephyr_info; + const struct zephyr_temp_sensor *zephyr_info; #else /* Read sensor value in K into temp_ptr; return non-zero if error. */ int (*read)(int idx, int *temp_ptr); @@ -72,4 +72,4 @@ int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr); */ int print_temps(void); -#endif /* __CROS_EC_TEMP_SENSOR_H */ +#endif /* __CROS_EC_TEMP_SENSOR_H */ diff --git a/include/temp_sensor_chip.h b/include/temp_sensor_chip.h index 4f9ddf0bc0..de9cb45452 100644 --- a/include/temp_sensor_chip.h +++ b/include/temp_sensor_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/test_util.h b/include/test_util.h index 9dcb31297f..8a7f29643d 100644 --- a/include/test_util.h +++ b/include/test_util.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,60 +8,66 @@ #ifndef __CROS_EC_TEST_UTIL_H #define __CROS_EC_TEST_UTIL_H +#include "compile_time_macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + #include "common.h" #include "console.h" #include "stack_trace.h" #ifdef CONFIG_ZTEST -#include <ztest.h> +#include <zephyr/ztest.h> #include "ec_tasks.h" #endif /* CONFIG_ZTEST */ /* This allows tests to be easily commented out in run_test for debugging */ #define test_static static __attribute__((unused)) -#define RUN_TEST(n) \ - do { \ +#define RUN_TEST(n) \ + do { \ ccprintf("Running %s...\n", #n); \ - cflush(); \ - before_test(); \ - if (n() == EC_SUCCESS) { \ - ccputs("OK\n"); \ - } else { \ - ccputs("Fail\n"); \ - __test_error_count++; \ - } \ - after_test(); \ + cflush(); \ + before_test(); \ + if (n() == EC_SUCCESS) { \ + ccputs("OK\n"); \ + } else { \ + ccputs("Fail\n"); \ + __test_error_count++; \ + } \ + after_test(); \ } while (0) -#define TEST_ASSERT(n) \ - do { \ - if (!(n)) { \ - ccprintf("%s:%d: ASSERTION failed: %s\n", \ - __FILE__, __LINE__, #n); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } \ +#define TEST_ASSERT(n) \ + do { \ + if (!(n)) { \ + ccprintf("%s:%d: ASSERTION failed: %s\n", __FILE__, \ + __LINE__, #n); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } \ } while (0) #if defined(__cplusplus) && !defined(__auto_type) #define __auto_type auto #endif -#define TEST_OPERATOR(a, b, op, fmt) \ - do { \ - __auto_type _a = (a); \ - __auto_type _b = (b); \ - if (!(_a op _b)) { \ - ccprintf("%s:%d: ASSERTION failed: %s " #op " %s\n", \ - __FILE__, __LINE__, #a, #b); \ - ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n", \ - _a, _b); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } else { \ - ccprintf("Pass: %s " #op " %s\n", #a, #b); \ - } \ +#define TEST_OPERATOR(a, b, op, fmt) \ + do { \ + __auto_type _a = (a); \ + __auto_type _b = (b); \ + if (!(_a op _b)) { \ + ccprintf("%s:%d: ASSERTION failed: %s " #op " %s\n", \ + __FILE__, __LINE__, #a, #b); \ + ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n", _a, \ + _b); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } else { \ + ccprintf("Pass: %s " #op " %s\n", #a, #b); \ + } \ } while (0) #define TEST_EQ(a, b, fmt) TEST_OPERATOR(a, b, ==, fmt) @@ -70,8 +76,8 @@ #define TEST_LE(a, b, fmt) TEST_OPERATOR(a, b, <=, fmt) #define TEST_GT(a, b, fmt) TEST_OPERATOR(a, b, >, fmt) #define TEST_GE(a, b, fmt) TEST_OPERATOR(a, b, >=, fmt) -#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a & (int)bits, (int)bits, ==, "%u") -#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a & (int)bits, 0, ==, "%u") +#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a &(int)bits, (int)bits, ==, "%u") +#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a &(int)bits, 0, ==, "%u") #define TEST_NEAR(a, b, epsilon, fmt) \ TEST_OPERATOR(ABS((a) - (b)), epsilon, <, fmt) @@ -79,40 +85,32 @@ #define TEST_ASSERT_ABS_LESS(n, t) TEST_OPERATOR(__ABS(n), t, <, "%d") -#define TEST_ASSERT_ARRAY_EQ(s, d, n) \ - do { \ - int __i; \ - for (__i = 0; __i < n; ++__i) \ - if ((s)[__i] != (d)[__i]) { \ +#define TEST_ASSERT_ARRAY_EQ(s, d, n) \ + do { \ + int __i; \ + for (__i = 0; __i < n; ++__i) \ + if ((s)[__i] != (d)[__i]) { \ ccprintf("%s:%d: ASSERT_ARRAY_EQ failed at " \ - "index=%d: %d != %d\n", \ - __FILE__, __LINE__, \ - __i, (int)(s)[__i], (int)(d)[__i]); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } \ + "index=%d: %d != %d\n", \ + __FILE__, __LINE__, __i, \ + (int)(s)[__i], (int)(d)[__i]); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } \ } while (0) -#define TEST_ASSERT_MEMSET(d, c, n) \ - do { \ - int __i; \ - for (__i = 0; __i < n; ++__i) \ - if ((d)[__i] != (c)) { \ +#define TEST_ASSERT_MEMSET(d, c, n) \ + do { \ + int __i; \ + for (__i = 0; __i < n; ++__i) \ + if ((d)[__i] != (c)) { \ ccprintf("%s:%d: ASSERT_MEMSET failed at " \ - "index=%d: %d != %d\n", \ - __FILE__, __LINE__, \ - __i, (int)(d)[__i], (c)); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } \ - } while (0) - -#define TEST_CHECK(n) \ - do { \ - if (n) \ - return EC_SUCCESS; \ - else \ - return EC_ERROR_UNKNOWN; \ + "index=%d: %d != %d\n", \ + __FILE__, __LINE__, __i, \ + (int)(d)[__i], (c)); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } \ } while (0) /* Mutlistep test states */ @@ -147,7 +145,7 @@ void before_test(void); void after_test(void); /* Test entry point */ -void run_test(int argc, char **argv); +void run_test(int argc, const char **argv); /* Test entry point for fuzzing tests. */ int test_fuzz_one_input(const uint8_t *data, unsigned int size); @@ -195,8 +193,12 @@ void interrupt_generator_udelay(unsigned us); void wait_for_task_started(void); void wait_for_task_started_nosleep(void); #else -static inline void wait_for_task_started(void) { } -static inline void wait_for_task_started_nosleep(void) { } +static inline void wait_for_task_started(void) +{ +} +static inline void wait_for_task_started_nosleep(void) +{ +} #endif uint32_t prng(uint32_t seed); @@ -271,8 +273,8 @@ struct test_i2c_read_string_dev { struct test_i2c_xfer { /* I2C xfer handler */ int (*routine)(const int port, const uint16_t i2c_addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); + const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); }; struct test_i2c_write_dev { @@ -290,11 +292,10 @@ struct test_i2c_write_dev { * * @param routine Function pointer, with the same prototype as i2c_xfer() */ -#define DECLARE_TEST_I2C_XFER(routine) \ - const struct test_i2c_xfer __no_sanitize_address \ - __test_i2c_xfer_##routine \ - __attribute__((section(".rodata.test_i2c.xfer"))) \ - = {routine} +#define DECLARE_TEST_I2C_XFER(routine) \ + const struct test_i2c_xfer __no_sanitize_address \ + __test_i2c_xfer_##routine __attribute__(( \ + section(".rodata.test_i2c.xfer"))) = { routine } /* * Detach an I2C device. Once detached, any read/write command regarding the @@ -377,14 +378,14 @@ int test_attach_i2c(const int port, const uint16_t addr_flags); #define TEST_MAIN() void test_main(void) #define TEST_SUITE(name) void name(void) #else -#define TEST_MAIN() \ - void test_main(void); \ - void run_test(int argc, char **argv) \ - { \ - test_reset(); \ - test_main(); \ - test_print_result(); \ - } \ +#define TEST_MAIN() \ + void test_main(void); \ + void run_test(int argc, const char **argv) \ + { \ + test_reset(); \ + test_main(); \ + test_print_result(); \ + } \ void test_main(void) #define TEST_SUITE(name) TEST_MAIN() #endif @@ -413,7 +414,7 @@ struct unit_test { */ #define ztest_unit_test_setup_teardown(fn, setup, teardown) \ { \ - #fn, fn, setup, teardown \ +#fn, fn, setup, teardown \ } /** @@ -477,7 +478,7 @@ void z_ztest_run_test_suite(const char *name, struct unit_test *suite); #define zassert_unreachable(msg, ...) TEST_ASSERT(0) #define zassert_true(cond, msg, ...) TEST_ASSERT(cond) #define zassert_false(cond, msg, ...) TEST_ASSERT(!(cond)) -#define zassert_ok(cond, msg, ...) TEST_ASSERT(cond) +#define zassert_ok(cond, msg, ...) TEST_ASSERT(!(cond)) #define zassert_is_null(ptr, msg, ...) TEST_ASSERT((ptr) == NULL) #define zassert_not_null(ptr, msg, ...) TEST_ASSERT((ptr) != NULL) #define zassert_equal(a, b, msg, ...) TEST_EQ((a), (b), "0x%x") @@ -489,4 +490,8 @@ void z_ztest_run_test_suite(const char *name, struct unit_test *suite); TEST_ASSERT_ARRAY_EQ(buf, exp, size) #endif /* CONFIG_ZEPHYR */ +#ifdef __cplusplus +} +#endif + #endif /* __CROS_EC_TEST_UTIL_H */ diff --git a/include/tests/enum_strings.h b/include/tests/enum_strings.h index ece2df362f..2ad0725f8f 100644 --- a/include/tests/enum_strings.h +++ b/include/tests/enum_strings.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/thermal.h b/include/thermal.h index 29d8073ca0..33d0e27f51 100644 --- a/include/thermal.h +++ b/include/thermal.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -27,4 +27,4 @@ int thermal_fan_percent(int low, int high, int cur); */ void board_override_fan_control(int fan, int *tmp); -#endif /* __CROS_EC_THERMAL_H */ +#endif /* __CROS_EC_THERMAL_H */ diff --git a/include/throttle_ap.h b/include/throttle_ap.h index 09669d70b1..43a5f48e2c 100644 --- a/include/throttle_ap.h +++ b/include/throttle_ap.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,8 +20,8 @@ enum throttle_level { * Types of throttling desired. These are independent. */ enum throttle_type { - THROTTLE_SOFT = 0, /* for example, host events */ - THROTTLE_HARD, /* for example, PROCHOT */ + THROTTLE_SOFT = 0, /* for example, host events */ + THROTTLE_HARD, /* for example, PROCHOT */ NUM_THROTTLE_TYPES }; @@ -32,6 +32,7 @@ enum throttle_sources { THROTTLE_SRC_THERMAL = 0, THROTTLE_SRC_BAT_DISCHG_CURRENT, THROTTLE_SRC_BAT_VOLTAGE, + THROTTLE_SRC_AC, }; /** @@ -57,12 +58,11 @@ struct prochot_cfg { * @param type Type of throttling desired * @param source Which task is requesting throttling */ -#if defined(CONFIG_THROTTLE_AP) || \ +#if defined(CONFIG_THROTTLE_AP) || \ defined(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT) || \ defined(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE) -void throttle_ap(enum throttle_level level, - enum throttle_type type, +void throttle_ap(enum throttle_level level, enum throttle_type type, enum throttle_sources source); /** @@ -102,7 +102,11 @@ void throttle_ap_c10_input_interrupt(enum gpio_signal signal); static inline void throttle_ap(enum throttle_level level, enum throttle_type type, enum throttle_sources source) -{} +{ +} #endif -#endif /* __CROS_EC_THROTTLE_AP_H */ +void throttle_gpu(enum throttle_level level, enum throttle_type type, + enum throttle_sources source); + +#endif /* __CROS_EC_THROTTLE_AP_H */ diff --git a/include/timer.h b/include/timer.h index 6f9b4ea7b0..7170a35056 100644 --- a/include/timer.h +++ b/include/timer.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,11 +19,11 @@ typedef long clock_t; #include "task_id.h" /* Time units in microseconds */ -#define MSEC 1000 -#define SECOND 1000000 -#define SEC_UL 1000000ul -#define MINUTE 60000000 -#define HOUR 3600000000ull /* Too big to fit in a signed int */ +#define MSEC 1000 +#define SECOND 1000000 +#define SEC_UL 1000000ul +#define MINUTE 60000000 +#define HOUR 3600000000ull /* Too big to fit in a signed int */ /* Microsecond timestamp. */ typedef union { @@ -34,7 +34,6 @@ typedef union { } le /* little endian words */; } timestamp_t; - /** * Initialize the timer module. */ @@ -195,4 +194,4 @@ static inline int time_after(uint32_t a, uint32_t b) extern timestamp_t *get_time_mock; #endif /* CONFIG_ZTEST */ -#endif /* __CROS_EC_TIMER_H */ +#endif /* __CROS_EC_TIMER_H */ diff --git a/include/touchpad.h b/include/touchpad.h index 4e746d8dc1..8ae985318e 100644 --- a/include/touchpad.h +++ b/include/touchpad.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/trng.h b/include/trng.h index cea4555b41..cf8326e5bf 100644 --- a/include/trng.h +++ b/include/trng.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,32 +14,30 @@ * * Not supported by all platforms. **/ -void init_trng(void); +void trng_init(void); /** * Shutdown the true random number generator. * - * The opposite operation of init_trng(), disable the hardware resources + * The opposite operation of trng_init(), disable the hardware resources * used by the TRNG to save power. * * Not supported by all platforms. **/ -void exit_trng(void); +void trng_exit(void); /** * Retrieve a 32 bit random value. * * Not supported on all platforms. **/ -#ifndef HIDE_EC_STDLIB -uint32_t rand(void); -#endif +uint32_t trng_rand(void); /** * Output len random bytes into buffer. * * Not supported on all platforms. **/ -void rand_bytes(void *buffer, size_t len); +void trng_rand_bytes(void *buffer, size_t len); #endif /* __EC_INCLUDE_TRNG_H */ diff --git a/include/typec_control.h b/include/typec_control.h index b162467663..849a661490 100644 --- a/include/typec_control.h +++ b/include/typec_control.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,7 +33,7 @@ void typec_set_sbu(int port, bool enable); * @param rp Pull-up values to be aplied as a SRC to advertise current limits */ __override_proto void typec_set_source_current_limit(int port, - enum tcpc_rp_value rp); + enum tcpc_rp_value rp); /** * Turn on/off the VCONN FET diff --git a/include/uart.h b/include/uart.h index 3789ce127c..851b331fd2 100644 --- a/include/uart.h +++ b/include/uart.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #ifndef __CROS_EC_UART_H #define __CROS_EC_UART_H -#include <stdarg.h> /* For va_list */ +#include <stdarg.h> /* For va_list */ #include "common.h" #include "gpio_signal.h" @@ -72,8 +72,8 @@ int uart_put_raw(const char *out, int len); * * @return EC_SUCCESS, or non-zero if output was truncated. */ -__attribute__((__format__(__printf__, 1, 2))) -int uart_printf(const char *format, ...); +__attribute__((__format__(__printf__, 1, 2))) int +uart_printf(const char *format, ...); /** * Print formatted output to the UART, like vprintf(). @@ -258,7 +258,9 @@ void uart_exit_dsleep(void); */ void uart_deepsleep_interrupt(enum gpio_signal signal); #else -static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { } +static inline void uart_deepsleep_interrupt(enum gpio_signal signal) +{ +} #endif /* !CONFIG_LOW_POWER_IDLE */ #if defined(HAS_TASK_CONSOLE) && defined(CONFIG_FORCE_CONSOLE_RESUME) @@ -269,7 +271,9 @@ static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { } */ void uart_enable_wakeup(int enable); #elif !defined(CHIP_FAMILY_NPCX5) -static inline void uart_enable_wakeup(int enable) {} +static inline void uart_enable_wakeup(int enable) +{ +} #endif #ifdef CONFIG_UART_INPUT_FILTER @@ -335,7 +339,7 @@ void uart_reset_default_pad_panic(void); * time specified in timeout_us. */ int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len, - int timeout_us); + int timeout_us); /** * Interrupt handler for default UART RX pin transition when UART is switched @@ -372,9 +376,7 @@ enum ec_status uart_console_read_buffer_init(void); * * @return result status (EC_RES_*) */ -int uart_console_read_buffer(uint8_t type, - char *dest, - uint16_t dest_size, +int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size, uint16_t *write_count); /** @@ -382,4 +384,4 @@ int uart_console_read_buffer(uint8_t type, */ void uart_init_buffer(void); -#endif /* __CROS_EC_UART_H */ +#endif /* __CROS_EC_UART_H */ diff --git a/include/update_fw.h b/include/update_fw.h index d345c4f667..dc520c2eb9 100644 --- a/include/update_fw.h +++ b/include/update_fw.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -43,8 +43,8 @@ * block_base: offset of this PDU into the flash SPI. */ struct update_command { - uint32_t block_digest; - uint32_t block_base; + uint32_t block_digest; + uint32_t block_base; /* The actual payload goes here. */ } __packed; @@ -112,8 +112,8 @@ struct first_response_pdu { /* cr50 (header_type = UPDATE_HEADER_TYPE_CR50) */ struct { /* The below fields are present in versions 3 and up. */ - uint32_t backup_ro_offset; - uint32_t backup_rw_offset; + uint32_t backup_ro_offset; + uint32_t backup_rw_offset; /* The below fields are present in versions 4 and up. */ /* @@ -154,8 +154,8 @@ enum first_response_pdu_header_type { }; /* TODO: Handle this in update_fw.c, not usb_update.c */ -#define UPDATE_DONE 0xB007AB1E -#define UPDATE_EXTRA_CMD 0xB007AB1F +#define UPDATE_DONE 0xB007AB1E +#define UPDATE_EXTRA_CMD 0xB007AB1F enum update_extra_command { UPDATE_EXTRA_CMD_IMMEDIATE_RESET = 0, @@ -235,8 +235,7 @@ struct touchpad_info { */ BUILD_ASSERT(sizeof(struct touchpad_info) <= 50); -void fw_update_command_handler(void *body, - size_t cmd_size, +void fw_update_command_handler(void *body, size_t cmd_size, size_t *response_size); /* Used to tell fw update the update ran successfully and is finished */ @@ -286,4 +285,4 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, /* SHA256 hash of the touchpad firmware expected by this image. */ extern const uint8_t touchpad_fw_full_hash[32]; -#endif /* ! __CROS_EC_UPDATE_FW_H */ +#endif /* ! __CROS_EC_UPDATE_FW_H */ diff --git a/include/usb_api.h b/include/usb_api.h index 79ee9406e9..85e82d11e0 100644 --- a/include/usb_api.h +++ b/include/usb_api.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -76,7 +76,9 @@ void usb_restore_suspended_state(void); #ifdef CONFIG_USB_REMOTE_WAKEUP void usb_wake(void); #else -static inline void usb_wake(void) {} +static inline void usb_wake(void) +{ +} #endif /* Board-specific USB wake, for side-band wake, called by usb_wake above. */ diff --git a/include/usb_bb.h b/include/usb_bb.h index e2303f13e6..d28d4be441 100644 --- a/include/usb_bb.h +++ b/include/usb_bb.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -17,7 +17,6 @@ #define USB_BB_EP0_PACKET_SIZE 8 #define USB_BB_CAP_DESC_TYPE 0x0d - #define USB_BB_CAPS_SVID_SIZE 4 struct usb_bb_caps_svid_descriptor { uint16_t wSVID; @@ -38,16 +37,14 @@ struct usb_bb_caps_base_descriptor { uint32_t bReserved; /* SBZ */ } __packed; - -#define USB_BB_VCONN_PWRON(x) (x << 15) -#define USB_BB_VCONN_PWR_1W 0 -#define USB_BB_VCONN_PWR_1p5W 1 -#define USB_BB_VCONN_PWR_2W 2 -#define USB_BB_VCONN_PWR_3W 3 -#define USB_BB_VCONN_PWR_4W 4 -#define USB_BB_VCONN_PWR_5W 5 -#define USB_BB_VCONN_PWR_6W 6 +#define USB_BB_VCONN_PWRON(x) (x << 15) +#define USB_BB_VCONN_PWR_1W 0 +#define USB_BB_VCONN_PWR_1p5W 1 +#define USB_BB_VCONN_PWR_2W 2 +#define USB_BB_VCONN_PWR_3W 3 +#define USB_BB_VCONN_PWR_4W 4 +#define USB_BB_VCONN_PWR_5W 5 +#define USB_BB_VCONN_PWR_6W 6 /* Note, 7W (111b) is reserved */ - #endif /* __CROS_EC_USB_BB_H */ diff --git a/include/usb_charge.h b/include/usb_charge.h index 135258c7cf..cd022d5f51 100644 --- a/include/usb_charge.h +++ b/include/usb_charge.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,7 +14,7 @@ #include "task.h" /* USB charger voltage */ -#define USB_CHARGER_VOLTAGE_MV 5000 +#define USB_CHARGER_VOLTAGE_MV 5000 /* USB charger minimum current */ #define USB_CHARGER_MIN_CURR_MA 500 /* @@ -65,13 +65,13 @@ int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode, #define USB_CHARGER_EVENT_BIT(x) TASK_EVENT_CUSTOM_BIT(x) #endif -#define USB_CHG_EVENT_BC12 USB_CHARGER_EVENT_BIT(0) -#define USB_CHG_EVENT_VBUS USB_CHARGER_EVENT_BIT(1) -#define USB_CHG_EVENT_INTR USB_CHARGER_EVENT_BIT(2) -#define USB_CHG_EVENT_DR_UFP USB_CHARGER_EVENT_BIT(3) -#define USB_CHG_EVENT_DR_DFP USB_CHARGER_EVENT_BIT(4) -#define USB_CHG_EVENT_CC_OPEN USB_CHARGER_EVENT_BIT(5) -#define USB_CHG_EVENT_MUX USB_CHARGER_EVENT_BIT(6) +#define USB_CHG_EVENT_BC12 USB_CHARGER_EVENT_BIT(0) +#define USB_CHG_EVENT_VBUS USB_CHARGER_EVENT_BIT(1) +#define USB_CHG_EVENT_INTR USB_CHARGER_EVENT_BIT(2) +#define USB_CHG_EVENT_DR_UFP USB_CHARGER_EVENT_BIT(3) +#define USB_CHG_EVENT_DR_DFP USB_CHARGER_EVENT_BIT(4) +#define USB_CHG_EVENT_CC_OPEN USB_CHARGER_EVENT_BIT(5) +#define USB_CHG_EVENT_MUX USB_CHARGER_EVENT_BIT(6) /* * Define USB_CHG_PORT_TO_TASK_ID() and TASK_ID_TO_USB_CHG_PORT() macros to @@ -80,11 +80,11 @@ int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode, */ #ifdef HAS_TASK_USB_CHG_P0 #define USB_CHG_PORT_TO_TASK_ID(port) (TASK_ID_USB_CHG_P0 + (port)) -#define TASK_ID_TO_USB_CHG_PORT(id) ((id) - TASK_ID_USB_CHG_P0) +#define TASK_ID_TO_USB_CHG_PORT(id) ((id)-TASK_ID_USB_CHG_P0) #else #define USB_CHG_PORT_TO_TASK_ID(port) -1 /* stub task ID */ #define TASK_ID_TO_USB_CHG_PORT(id) 0 -#endif /* HAS_TASK_USB_CHG_P0 */ +#endif /* HAS_TASK_USB_CHG_P0 */ /** * Returns true if the passed port is a power source. @@ -214,4 +214,4 @@ int board_is_sourcing_vbus(int port); */ int board_vbus_sink_enable(int port, int enable); -#endif /* __CROS_EC_USB_CHARGE_H */ +#endif /* __CROS_EC_USB_CHARGE_H */ diff --git a/include/usb_common.h b/include/usb_common.h index bd779780ee..1e1d210f8c 100644 --- a/include/usb_common.h +++ b/include/usb_common.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,10 +33,10 @@ enum pd_drp_next_states { * us of a connection. * */ -enum pd_drp_next_states drp_auto_toggle_next_state(uint64_t *drp_sink_time, - enum pd_power_role power_role, enum pd_dual_role_states drp_state, - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2, - bool auto_toggle_supported); +enum pd_drp_next_states drp_auto_toggle_next_state( + uint64_t *drp_sink_time, enum pd_power_role power_role, + enum pd_dual_role_states drp_state, enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2, bool auto_toggle_supported); enum pd_pref_type { /* prefer voltage larger than or equal to pd_pref_config.mv */ @@ -105,7 +105,8 @@ int usb_get_battery_soc(void); * @return current limit (mA) with DTS flag set if appropriate */ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity, - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2); /** * Returns the polarity of a Sink. @@ -115,7 +116,7 @@ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity, * @return polarity */ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc2); /** * Returns the polarity of a Source. @@ -125,7 +126,7 @@ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, * @return polarity */ enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc2); /** * Find PDO index that offers the most amount of power and stays within @@ -137,8 +138,8 @@ enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1, * @param pdo raw pdo corresponding to index, or index 0 on error (output) * @return index of PDO within source cap packet */ -int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps, - int max_mv, uint32_t *selected_pdo); +int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t *const src_caps, + int max_mv, uint32_t *selected_pdo); /** * Extract power information out of a Power Data Object (PDO) @@ -161,7 +162,7 @@ void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv, * @param port USB-C port number */ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma, - uint32_t *mv, int port); + uint32_t *mv, int port); /** * Notifies a task that is waiting on a system jump, that it's complete. diff --git a/include/usb_console.h b/include/usb_console.h index 2e0aa7dfa6..cbc322ce6c 100644 --- a/include/usb_console.h +++ b/include/usb_console.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -80,7 +80,7 @@ int usb_console_tx_blocked(void); #define usb_getc(x) (-1) #define usb_va_start(x, y) #define usb_va_end(x) -#define usb_console_tx_blocked() (0) +#define usb_console_tx_blocked() (0) #endif #endif /* __CROS_EC_USB_CONSOLE_H */ diff --git a/include/usb_descriptor.h b/include/usb_descriptor.h index 47f6e8805e..a40b858876 100644 --- a/include/usb_descriptor.h +++ b/include/usb_descriptor.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,17 +15,17 @@ /* USB 2.0 chapter 9 definitions */ /* Descriptor types */ -#define USB_DT_DEVICE 0x01 -#define USB_DT_CONFIGURATION 0x02 -#define USB_DT_STRING 0x03 -#define USB_DT_INTERFACE 0x04 -#define USB_DT_ENDPOINT 0x05 -#define USB_DT_DEVICE_QUALIFIER 0x06 -#define USB_DT_OTHER_SPEED_CONFIG 0x07 -#define USB_DT_INTERFACE_POWER 0x08 -#define USB_DT_DEBUG 0x0a -#define USB_DT_BOS 0x0f -#define USB_DT_DEVICE_CAPABILITY 0x10 +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIGURATION 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONFIG 0x07 +#define USB_DT_INTERFACE_POWER 0x08 +#define USB_DT_DEBUG 0x0a +#define USB_DT_BOS 0x0f +#define USB_DT_DEVICE_CAPABILITY 0x10 /* USB Device Descriptor */ struct usb_device_descriptor { @@ -44,7 +44,7 @@ struct usb_device_descriptor { uint8_t iSerialNumber; uint8_t bNumConfigurations; } __packed; -#define USB_DT_DEVICE_SIZE 18 +#define USB_DT_DEVICE_SIZE 18 /* BOS Descriptor ( USB3.1 rev1 Section 9.6.2 ) */ struct bos_context { @@ -55,158 +55,160 @@ struct bos_context { struct usb_bos_hdr_descriptor { uint8_t bLength; uint8_t bDescriptorType; /* USB_DT_BOS */ - uint16_t wTotalLength; /* Total length of of hdr + all dev caps */ - uint8_t bNumDeviceCaps; /* Container ID Descriptor + others */ + uint16_t wTotalLength; /* Total length of of hdr + all dev caps */ + uint8_t bNumDeviceCaps; /* Container ID Descriptor + others */ } __packed; #define USB_DT_BOS_SIZE 5 /* Container ID Descriptor */ struct usb_contid_caps_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ - uint8_t bDevCapabilityType; /* USB_DC_DTYPE_xxx */ - uint8_t bReserved; /* SBZ */ - uint8_t ContainerID[16]; /* UUID */ + uint8_t bLength; + uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ + uint8_t bDevCapabilityType; /* USB_DC_DTYPE_xxx */ + uint8_t bReserved; /* SBZ */ + uint8_t ContainerID[16]; /* UUID */ } __packed; -#define USB_DT_CONTID_SIZE 20 +#define USB_DT_CONTID_SIZE 20 /* Device Cap Type Codes ( offset 2 of Device Capability Descriptor */ -#define USB_DC_DTYPE_WIRELESS 0x01 -#define USB_DC_DTYPE_USB20EXT 0x02 -#define USB_DC_DTYPE_USBSS 0x03 -#define USB_DC_DTYPE_CONTID 0x04 -#define USB_DC_DTYPE_PLATFORM 0x05 -#define USB_DC_DTYPE_PD 0x06 -#define USB_DC_DTYPE_BATTINFO 0x07 -#define USB_DC_DTYPE_CONSUMER 0x08 -#define USB_DC_DTYPE_PRODUCER 0x09 -#define USB_DC_DTYPE_USBSSP 0x0a -#define USB_DC_DTYPE_PCSTIME 0x0b -#define USB_DC_DTYPE_WUSBEXT 0x0c +#define USB_DC_DTYPE_WIRELESS 0x01 +#define USB_DC_DTYPE_USB20EXT 0x02 +#define USB_DC_DTYPE_USBSS 0x03 +#define USB_DC_DTYPE_CONTID 0x04 +#define USB_DC_DTYPE_PLATFORM 0x05 +#define USB_DC_DTYPE_PD 0x06 +#define USB_DC_DTYPE_BATTINFO 0x07 +#define USB_DC_DTYPE_CONSUMER 0x08 +#define USB_DC_DTYPE_PRODUCER 0x09 +#define USB_DC_DTYPE_USBSSP 0x0a +#define USB_DC_DTYPE_PCSTIME 0x0b +#define USB_DC_DTYPE_WUSBEXT 0x0c #define USB_DC_DTYPE_BILLBOARD 0x0d /* RESERVED 0x00, 0xOe - 0xff */ /* Platform descriptor */ struct usb_platform_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ - uint8_t bDevCapabilityType; /* USB_DC_DTYPE_PLATFORM */ - uint8_t bReserved; /* SBZ */ - uint8_t PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */ - uint16_t bcdVersion; /* 0x0100 */ - uint8_t bVendorCode; - uint8_t iLandingPage; + uint8_t bLength; + uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ + uint8_t bDevCapabilityType; /* USB_DC_DTYPE_PLATFORM */ + uint8_t bReserved; /* SBZ */ + uint8_t PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */ + uint16_t bcdVersion; /* 0x0100 */ + uint8_t bVendorCode; + uint8_t iLandingPage; } __packed; -#define USB_DT_PLATFORM_SIZE 24 +#define USB_DT_PLATFORM_SIZE 24 /* Platform Capability UUIDs */ -#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/ \ - {0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, \ - 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65} +#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/ \ + { \ + 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, 0x8B, 0xFD, \ + 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65 \ + } /* Qualifier Descriptor */ struct usb_qualifier_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; } __packed; -#define USB_DT_QUALIFIER_SIZE 10 +#define USB_DT_QUALIFIER_SIZE 10 /* Configuration Descriptor */ struct usb_config_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; } __packed; -#define USB_DT_CONFIG_SIZE 9 +#define USB_DT_CONFIG_SIZE 9 /* String Descriptor */ struct usb_string_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t wData[1]; } __packed; /* Interface Descriptor */ struct usb_interface_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; } __packed; -#define USB_DT_INTERFACE_SIZE 9 +#define USB_DT_INTERFACE_SIZE 9 /* Endpoint Descriptor */ struct usb_endpoint_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; uint16_t wMaxPacketSize; - uint8_t bInterval; + uint8_t bInterval; } __packed; -#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_SIZE 7 /* USB Class codes */ -#define USB_CLASS_PER_INTERFACE 0x00 -#define USB_CLASS_AUDIO 0x01 -#define USB_CLASS_COMM 0x02 -#define USB_CLASS_HID 0x03 -#define USB_CLASS_PHYSICAL 0x05 -#define USB_CLASS_STILL_IMAGE 0x06 -#define USB_CLASS_PRINTER 0x07 -#define USB_CLASS_MASS_STORAGE 0x08 -#define USB_CLASS_HUB 0x09 -#define USB_CLASS_CDC_DATA 0x0a -#define USB_CLASS_CSCID 0x0b -#define USB_CLASS_CONTENT_SEC 0x0d -#define USB_CLASS_VIDEO 0x0e -#define USB_CLASS_BILLBOARD 0x11 -#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 -#define USB_CLASS_MISC 0xef -#define USB_CLASS_APP_SPEC 0xfe -#define USB_CLASS_VENDOR_SPEC 0xff - -/* USB Vendor ID assigned to Google Inc. */ +#define USB_CLASS_PER_INTERFACE 0x00 +#define USB_CLASS_AUDIO 0x01 +#define USB_CLASS_COMM 0x02 +#define USB_CLASS_HID 0x03 +#define USB_CLASS_PHYSICAL 0x05 +#define USB_CLASS_STILL_IMAGE 0x06 +#define USB_CLASS_PRINTER 0x07 +#define USB_CLASS_MASS_STORAGE 0x08 +#define USB_CLASS_HUB 0x09 +#define USB_CLASS_CDC_DATA 0x0a +#define USB_CLASS_CSCID 0x0b +#define USB_CLASS_CONTENT_SEC 0x0d +#define USB_CLASS_VIDEO 0x0e +#define USB_CLASS_BILLBOARD 0x11 +#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 +#define USB_CLASS_MISC 0xef +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff + +/* USB Vendor ID assigned to Google LLC */ #define USB_VID_GOOGLE 0x18d1 /* Google specific SubClass/Protocol assignments */ #define USB_SUBCLASS_GOOGLE_SERIAL 0x50 #define USB_PROTOCOL_GOOGLE_SERIAL 0x01 -#define USB_SUBCLASS_GOOGLE_SPI 0x51 -#define USB_PROTOCOL_GOOGLE_SPI 0x02 +#define USB_SUBCLASS_GOOGLE_SPI 0x51 +#define USB_PROTOCOL_GOOGLE_SPI 0x02 -#define USB_SUBCLASS_GOOGLE_I2C 0x52 -#define USB_PROTOCOL_GOOGLE_I2C 0x01 +#define USB_SUBCLASS_GOOGLE_I2C 0x52 +#define USB_PROTOCOL_GOOGLE_I2C 0x01 #define USB_SUBCLASS_GOOGLE_UPDATE 0x53 #define USB_PROTOCOL_GOOGLE_UPDATE 0xff /* Double define for cr50 code freeze. * TODO(vbendeb): dedupe this. */ -#define USB_SUBCLASS_GOOGLE_CR50 0x53 +#define USB_SUBCLASS_GOOGLE_CR50 0x53 /* We can use any protocol we want */ #define USB_PROTOCOL_GOOGLE_CR50_NON_HC_FW_UPDATE 0xff -#define USB_SUBCLASS_GOOGLE_POWER 0x54 -#define USB_PROTOCOL_GOOGLE_POWER 0x01 +#define USB_SUBCLASS_GOOGLE_POWER 0x54 +#define USB_PROTOCOL_GOOGLE_POWER 0x01 #define USB_SUBCLASS_GOOGLE_HEATMAP 0x55 #define USB_PROTOCOL_GOOGLE_HEATMAP 0x01 @@ -218,72 +220,71 @@ struct usb_endpoint_descriptor { /* bRequestType fields */ /* direction field */ -#define USB_DIR_OUT 0 /* from host to uC */ -#define USB_DIR_IN 0x80 /* from uC to host */ +#define USB_DIR_OUT 0 /* from host to uC */ +#define USB_DIR_IN 0x80 /* from uC to host */ /* type field */ -#define USB_TYPE_MASK (0x03 << 5) -#define USB_TYPE_STANDARD (0x00 << 5) -#define USB_TYPE_CLASS (0x01 << 5) -#define USB_TYPE_VENDOR (0x02 << 5) -#define USB_TYPE_RESERVED (0x03 << 5) +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) /* recipient field */ -#define USB_RECIP_MASK 0x1f -#define USB_RECIP_DEVICE 0x00 -#define USB_RECIP_INTERFACE 0x01 -#define USB_RECIP_ENDPOINT 0x02 -#define USB_RECIP_OTHER 0x03 +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 /* Standard requests for bRequest field in a SETUP packet. */ -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_GET_STATUS_SELF_POWERED BIT(0) +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_GET_STATUS_SELF_POWERED BIT(0) #define USB_REQ_GET_STATUS_REMOTE_WAKEUP BIT(1) -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_FEATURE_ENDPOINT_HALT 0x0000 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_FEATURE_ENDPOINT_HALT 0x0000 #define USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP 0x0001 -#define USB_REQ_FEATURE_TEST_MODE 0x0002 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_FEATURE_TEST_MODE 0x0002 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C /* WebUSB URL descriptors */ -#define WEBUSB_REQ_GET_URL 0x02 -#define USB_DT_WEBUSB_URL 0x03 +#define WEBUSB_REQ_GET_URL 0x02 +#define USB_DT_WEBUSB_URL 0x03 -#define USB_URL_SCHEME_HTTP 0x00 -#define USB_URL_SCHEME_HTTPS 0x01 -#define USB_URL_SCHEME_NONE 0xff +#define USB_URL_SCHEME_HTTP 0x00 +#define USB_URL_SCHEME_HTTPS 0x01 +#define USB_URL_SCHEME_NONE 0xff /* * URL descriptor helper. * (similar to string descriptor but UTF-8 instead of UTF-16) */ -#define USB_URL_DESC(scheme, str) \ - (const void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - uint8_t _scheme; \ - char _data[sizeof(str)]; \ - }) { \ - /* Total size of the descriptor is : \ +#define USB_URL_DESC(scheme, str) \ + (const void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + uint8_t _scheme; \ + char _data[sizeof(str)]; \ + }) \ + { \ + /* Total size of the descriptor is : \ * size of the UTF-8 text plus the len/type fields \ - * minus the string 0-termination \ - */ \ - sizeof(str) + 3 - 1, \ - USB_DT_WEBUSB_URL, \ - USB_URL_SCHEME_##scheme, \ - str \ + * minus the string 0-termination \ + */ \ + sizeof(str) + 3 - 1, USB_DT_WEBUSB_URL, \ + USB_URL_SCHEME_##scheme, str \ } /* Setup Packet */ struct usb_setup_packet { - uint8_t bmRequestType; - uint8_t bRequest; + uint8_t bmRequestType; + uint8_t bRequest; uint16_t wValue; uint16_t wIndex; uint16_t wLength; @@ -326,19 +327,18 @@ struct usb_ms_ext_compat_id_desc { #define WIDESTR(quote) WIDESTR2(quote) #define WIDESTR2(quote) L##quote -#define USB_STRING_DESC(str) \ - (const void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(str)]; \ - }) { \ - /* Total size of the descriptor is : \ - * size of the UTF-16 text plus the len/type fields \ - * minus the string 0-termination \ - */ \ - sizeof(WIDESTR(str)) + 2 - 2, \ - USB_DT_STRING, \ - WIDESTR(str) \ +#define USB_STRING_DESC(str) \ + (const void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(str)]; \ + }) \ + { \ + /* Total size of the descriptor is : \ + * size of the UTF-16 text plus the len/type fields \ + * minus the string 0-termination \ + */ \ + sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) \ } /* @@ -346,21 +346,21 @@ struct usb_ms_ext_compat_id_desc { * windows to request a MS Compatible ID Descriptor and then enables Windows OS * to load the correct driver for a USB-EP */ -#define USB_MS_STRING_DESC(str) \ - ((const void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(str) - 1]; \ - uint16_t _vendor; \ - }) { \ - /* Total size of the descriptor is : \ - * size of the UTF-16 text plus the len/type fields \ +#define USB_MS_STRING_DESC(str) \ + ((const void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(str) - 1]; \ + uint16_t _vendor; \ + }){ \ + /* Total size of the descriptor is : \ + * size of the UTF-16 text plus the len/type fields \ * plus 2 bytes for vendor code minus the string 0-termination \ - */ \ - sizeof(WIDESTR(str)) + 2 - 2 + 2, \ - USB_DT_STRING, \ - WIDESTR(str), \ - USB_MS_STRING_DESC_VENDOR_CODE, \ + */ \ + sizeof(WIDESTR(str)) + 2 - 2 + 2, \ + USB_DT_STRING, \ + WIDESTR(str), \ + USB_MS_STRING_DESC_VENDOR_CODE, \ }) #ifdef CONFIG_USB_SERIALNO @@ -370,22 +370,20 @@ struct usb_string_desc { uint8_t _type; wchar_t _data[CONFIG_SERIALNO_LEN]; }; -#define USB_WR_STRING_DESC(str) \ - (&(struct usb_string_desc) { \ +#define USB_WR_STRING_DESC(str) \ + (&(struct usb_string_desc){ \ /* As above, two bytes metadata, no null terminator. */ \ - sizeof(WIDESTR(str)) + 2 - 2, \ - USB_DT_STRING, \ - WIDESTR(str) \ -}) + sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) }) extern struct usb_string_desc *usb_serialno_desc; #endif /* Use these macros for declaring descriptors, to order them properly */ -#define USB_CONF_DESC_VAR(name, varname) varname \ - __keep __attribute__((section(".rodata.usb_desc_" STRINGIFY(name)))) +#define USB_CONF_DESC_VAR(name, varname) \ + varname __keep \ + __attribute__((section(".rodata.usb_desc_" STRINGIFY(name)))) #define USB_CONF_DESC(name) USB_CONF_DESC_VAR(name, CONCAT2(usb_desc_, name)) #define USB_IFACE_DESC(num) USB_CONF_DESC(CONCAT3(iface, num, _0iface)) -#define USB_CUSTOM_DESC_VAR(i, name, varname) \ +#define USB_CUSTOM_DESC_VAR(i, name, varname) \ USB_CONF_DESC_VAR(CONCAT4(iface, i, _1, name), varname) #define USB_CUSTOM_DESC(i, name) USB_CONF_DESC(CONCAT4(iface, i, _1, name)) #define USB_EP_DESC(i, num) USB_CONF_DESC(CONCAT4(iface, i, _2ep, num)) @@ -396,10 +394,10 @@ extern const uint8_t __usb_desc_end[]; #define USB_DESC_SIZE (__usb_desc_end - __usb_desc) /* These descriptors defined in board code */ -extern const void * const usb_strings[]; +extern const void *const usb_strings[]; extern const uint8_t usb_string_desc[]; /* USB string descriptor with the firmware version */ -extern const void * const usb_fw_version; +extern const void *const usb_fw_version; extern const struct bos_context bos_ctx; extern const void *webusb_url; diff --git a/include/usb_dp_alt_mode.h b/include/usb_dp_alt_mode.h index 40b7c321dd..83dc35b085 100644 --- a/include/usb_dp_alt_mode.h +++ b/include/usb_dp_alt_mode.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,6 +34,17 @@ void dp_init(int port); bool dp_is_active(int port); /* + * Returns True if DisplayPort mode entry has not started, or mode exit has + * already finished. + * TODO(b/235984702): Consolidate the DP state API + * + * @param port USB-C port number + * @return True if DisplayPort mode is in inactive state + * False otherwise. + */ +bool dp_is_idle(int port); + +/* * Checks whether the mode entry sequence for DisplayPort alternate mode is done * for a port. * @@ -52,7 +63,7 @@ bool dp_entry_is_done(int port); * @param vdm VDM from ACK */ void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm); + uint32_t *vdm); /* * Handles NAKed (or Not Supported or timed out) DisplayPort VDM requests. @@ -77,4 +88,4 @@ void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd); enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count, uint32_t *vdm); -#endif /* __CROS_EC_USB_DP_ALT_MODE_H */ +#endif /* __CROS_EC_USB_DP_ALT_MODE_H */ diff --git a/include/usb_emsg.h b/include/usb_emsg.h index 7b418cefdc..181065156c 100644 --- a/include/usb_emsg.h +++ b/include/usb_emsg.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/usb_hid.h b/include/usb_hid.h index e7b1cfe74b..0d49a9b38e 100644 --- a/include/usb_hid.h +++ b/include/usb_hid.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -8,39 +8,39 @@ #ifndef __CROS_EC_USB_HID_H #define __CROS_EC_USB_HID_H -#define USB_HID_SUBCLASS_BOOT 1 +#define USB_HID_SUBCLASS_BOOT 1 #define USB_HID_PROTOCOL_KEYBOARD 1 -#define USB_HID_PROTOCOL_MOUSE 2 +#define USB_HID_PROTOCOL_MOUSE 2 /* USB HID Class requests */ -#define USB_HID_REQ_GET_REPORT 0x01 -#define USB_HID_REQ_GET_IDLE 0x02 -#define USB_HID_REQ_GET_PROTOCOL 0x03 -#define USB_HID_REQ_SET_REPORT 0x09 -#define USB_HID_REQ_SET_IDLE 0x0A -#define USB_HID_REQ_SET_PROTOCOL 0x0B +#define USB_HID_REQ_GET_REPORT 0x01 +#define USB_HID_REQ_GET_IDLE 0x02 +#define USB_HID_REQ_GET_PROTOCOL 0x03 +#define USB_HID_REQ_SET_REPORT 0x09 +#define USB_HID_REQ_SET_IDLE 0x0A +#define USB_HID_REQ_SET_PROTOCOL 0x0B /* USB HID class descriptor types */ -#define USB_HID_DT_HID (USB_TYPE_CLASS | 0x01) -#define USB_HID_DT_REPORT (USB_TYPE_CLASS | 0x02) -#define USB_HID_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) +#define USB_HID_DT_HID (USB_TYPE_CLASS | 0x01) +#define USB_HID_DT_REPORT (USB_TYPE_CLASS | 0x02) +#define USB_HID_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) /* Pre-defined report types */ -#define REPORT_TYPE_INPUT 0x01 -#define REPORT_TYPE_OUTPUT 0x02 -#define REPORT_TYPE_FEATURE 0x03 +#define REPORT_TYPE_INPUT 0x01 +#define REPORT_TYPE_OUTPUT 0x02 +#define REPORT_TYPE_FEATURE 0x03 struct usb_hid_class_descriptor { - uint8_t bDescriptorType; + uint8_t bDescriptorType; uint16_t wDescriptorLength; } __packed; struct usb_hid_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t bcdHID; - uint8_t bCountryCode; - uint8_t bNumDescriptors; + uint8_t bCountryCode; + uint8_t bNumDescriptors; struct usb_hid_class_descriptor desc[1]; } __packed; diff --git a/include/usb_hid_touchpad.h b/include/usb_hid_touchpad.h index 1e6d4cf832..23c16a0201 100644 --- a/include/usb_hid_touchpad.h +++ b/include/usb_hid_touchpad.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,27 +10,27 @@ #define USB_HID_TOUCHPAD_TIMESTAMP_UNIT 100 /* usec */ -#define REPORT_ID_TOUCHPAD 0x01 -#define REPORT_ID_DEVICE_CAPS 0x0A -#define REPORT_ID_DEVICE_CERT 0x0B +#define REPORT_ID_TOUCHPAD 0x01 +#define REPORT_ID_DEVICE_CAPS 0x0A +#define REPORT_ID_DEVICE_CERT 0x0B -#define MAX_FINGERS 5 +#define MAX_FINGERS 5 struct usb_hid_touchpad_report { uint8_t id; /* 0x01 */ struct { - uint16_t confidence:1; - uint16_t tip:1; - uint16_t inrange:1; - uint16_t id:4; - uint16_t pressure:9; - uint16_t width:12; - uint16_t height:12; - uint16_t x:12; - uint16_t y:12; + uint16_t confidence : 1; + uint16_t tip : 1; + uint16_t inrange : 1; + uint16_t id : 4; + uint16_t pressure : 9; + uint16_t width : 12; + uint16_t height : 12; + uint16_t x : 12; + uint16_t y : 12; } __packed finger[MAX_FINGERS]; - uint8_t count:7; - uint8_t button:1; + uint8_t count : 7; + uint8_t button : 1; uint16_t timestamp; } __packed; diff --git a/include/usb_i2c.h b/include/usb_i2c.h index fd79293014..5c8bf8c874 100644 --- a/include/usb_i2c.h +++ b/include/usb_i2c.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -99,28 +99,28 @@ */ enum usb_i2c_error { - USB_I2C_SUCCESS = 0x0000, - USB_I2C_TIMEOUT = 0x0001, - USB_I2C_BUSY = 0x0002, + USB_I2C_SUCCESS = 0x0000, + USB_I2C_TIMEOUT = 0x0001, + USB_I2C_BUSY = 0x0002, USB_I2C_WRITE_COUNT_INVALID = 0x0003, - USB_I2C_READ_COUNT_INVALID = 0x0004, - USB_I2C_PORT_INVALID = 0x0005, - USB_I2C_DISABLED = 0x0006, - USB_I2C_MISSING_HANDLER = 0x0007, + USB_I2C_READ_COUNT_INVALID = 0x0004, + USB_I2C_PORT_INVALID = 0x0005, + USB_I2C_DISABLED = 0x0006, + USB_I2C_MISSING_HANDLER = 0x0007, USB_I2C_UNSUPPORTED_COMMAND = 0x0008, - USB_I2C_UNKNOWN_ERROR = 0x8000, + USB_I2C_UNKNOWN_ERROR = 0x8000, }; - #define USB_I2C_WRITE_BUFFER (CONFIG_USB_I2C_MAX_WRITE_COUNT + 4) /* If read payload is larger or equal to 128 bytes, header contains rc1 */ -#define USB_I2C_READ_BUFFER ((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ? \ - (CONFIG_USB_I2C_MAX_READ_COUNT + 4) : \ - (CONFIG_USB_I2C_MAX_READ_COUNT + 6)) +#define USB_I2C_READ_BUFFER \ + ((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ? \ + (CONFIG_USB_I2C_MAX_READ_COUNT + 4) : \ + (CONFIG_USB_I2C_MAX_READ_COUNT + 6)) -#define USB_I2C_BUFFER_SIZE \ - (USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ? \ - USB_I2C_READ_BUFFER : USB_I2C_WRITE_BUFFER) +#define USB_I2C_BUFFER_SIZE \ + (USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ? USB_I2C_READ_BUFFER : \ + USB_I2C_WRITE_BUFFER) BUILD_ASSERT(POWER_OF_TWO(USB_I2C_READ_BUFFER)); BUILD_ASSERT(POWER_OF_TWO(USB_I2C_WRITE_BUFFER)); @@ -156,28 +156,18 @@ extern struct consumer_ops const usb_i2c_consumer_ops; * ENDPOINT is the index of the USB bulk endpoint used for receiving and * transmitting bytes. */ -#define USB_I2C_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT) \ - static uint16_t \ - CONCAT2(NAME, _buffer_) \ - [USB_I2C_BUFFER_SIZE / 2]; \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - static struct queue const CONCAT2(NAME, _to_usb_); \ - static struct queue const CONCAT3(usb_to_, NAME, _); \ - USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_), \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_I2C, \ - USB_PROTOCOL_GOOGLE_I2C, \ - INTERFACE_NAME, \ - ENDPOINT, \ - USB_MAX_PACKET_SIZE, \ - USB_MAX_PACKET_SIZE, \ - CONCAT3(usb_to_, NAME, _), \ - CONCAT2(NAME, _to_usb_)) \ +#define USB_I2C_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT) \ + static uint16_t CONCAT2(NAME, _buffer_)[USB_I2C_BUFFER_SIZE / 2]; \ + static void CONCAT2(NAME, _deferred_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ + static struct queue const CONCAT2(NAME, _to_usb_); \ + static struct queue const CONCAT3(usb_to_, NAME, _); \ + USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_), INTERFACE, \ + USB_CLASS_VENDOR_SPEC, USB_SUBCLASS_GOOGLE_I2C, \ + USB_PROTOCOL_GOOGLE_I2C, INTERFACE_NAME, \ + ENDPOINT, USB_MAX_PACKET_SIZE, \ + USB_MAX_PACKET_SIZE, CONCAT3(usb_to_, NAME, _), \ + CONCAT2(NAME, _to_usb_)) \ struct usb_i2c_config const NAME = { \ .buffer = CONCAT2(NAME, _buffer_), \ .deferred = &CONCAT2(NAME, _deferred__data), \ @@ -186,15 +176,17 @@ extern struct consumer_ops const usb_i2c_consumer_ops; .ops = &usb_i2c_consumer_ops, \ }, \ .tx_queue = &CONCAT2(NAME, _to_usb_), \ - }; \ - static struct queue const CONCAT2(NAME, _to_usb_) = \ - QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t, \ - null_producer, CONCAT2(NAME, _usb_).consumer); \ - static struct queue const CONCAT3(usb_to_, NAME, _) = \ - QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t, \ - CONCAT2(NAME, _usb_).producer, NAME.consumer); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_i2c_deferred(&NAME); } + }; \ + static struct queue const CONCAT2(NAME, _to_usb_) = \ + QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t, null_producer, \ + CONCAT2(NAME, _usb_).consumer); \ + static struct queue const CONCAT3(usb_to_, NAME, _) = \ + QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t, \ + CONCAT2(NAME, _usb_).producer, NAME.consumer); \ + static void CONCAT2(NAME, _deferred_)(void) \ + { \ + usb_i2c_deferred(&NAME); \ + } /* * Handle I2C request in a deferred callback. @@ -224,11 +216,7 @@ int usb_i2c_board_is_enabled(void); * Function to call to register a handler for commands sent to the special i2c * address above. */ -int usb_i2c_register_cros_cmd_handler(int (*cmd_handler) - (void *data_in, - size_t in_size, - void *data_out, - size_t out_size)); - +int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)( + void *data_in, size_t in_size, void *data_out, size_t out_size)); -#endif /* __CROS_USB_I2C_H */ +#endif /* __CROS_USB_I2C_H */ diff --git a/include/usb_mode.h b/include/usb_mode.h index 4333cc851e..4cf7710960 100644 --- a/include/usb_mode.h +++ b/include/usb_mode.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/usb_mux.h b/include/usb_mux.h index 0d43257994..d510a347d4 100644 --- a/include/usb_mux.h +++ b/include/usb_mux.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,6 +28,7 @@ #define USB_MUX_FLAG_NOT_TCPC BIT(0) /* TCPC/MUX device used only as MUX */ #define USB_MUX_FLAG_SET_WITHOUT_FLIP BIT(1) /* SET should not flip */ #define USB_MUX_FLAG_RESETS_IN_G3 BIT(2) /* Mux chip will reset in G3 */ +#define USB_MUX_FLAG_POLARITY_INVERTED BIT(3) /* Mux polarity is inverted */ #endif /* CONFIG_ZEPHYR */ @@ -127,9 +128,6 @@ struct usb_mux { /* Mux driver */ const struct usb_mux_driver *driver; - /* Linked list chain of secondary MUXes. NULL terminated */ - const struct usb_mux *next_mux; - /** * Optional method for tuning for USB mux during mux->driver->init(). * @@ -157,11 +155,19 @@ struct usb_mux { * @param[out] ack_required: indication of whether this function * requires a wait for an AP ACK after */ - void (*hpd_update)(const struct usb_mux *me, - mux_state_t mux_state, + void (*hpd_update)(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required); }; +/* Linked list chain of secondary MUXes. NULL terminated */ +struct usb_mux_chain { + /* Structure describing USB mux */ + const struct usb_mux *mux; + + /* Pointer to next mux */ + const struct usb_mux_chain *next; +}; + /* Supported USB mux drivers */ extern const struct usb_mux_driver amd_fp5_usb_mux_driver; extern const struct usb_mux_driver amd_fp6_usb_mux_driver; @@ -177,9 +183,9 @@ extern const struct usb_mux_driver virtual_usb_mux_driver; /* USB muxes present in system, ordered by PD port #, defined at board-level */ #ifdef CONFIG_USB_MUX_RUNTIME_CONFIG -extern struct usb_mux usb_muxes[]; +extern struct usb_mux_chain usb_muxes[]; #else -extern const struct usb_mux usb_muxes[]; +extern const struct usb_mux_chain usb_muxes[]; #endif /* Supported hpd_update functions */ @@ -193,30 +199,30 @@ void virtual_hpd_update(const struct usb_mux *me, mux_state_t mux_state, #ifdef CONFIG_USB_PD_TCPM_MUX static inline int mux_write(const struct usb_mux *me, int reg, int val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_write(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_write(me->usb_port, reg, val); } static inline int mux_read(const struct usb_mux *me, int reg, int *val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_read(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_read(me->usb_port, reg, val); } static inline int mux_write16(const struct usb_mux *me, int reg, int val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_write16(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_write16(me->usb_port, reg, val); } static inline int mux_read16(const struct usb_mux *me, int reg, int *val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_read16(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_read16(me->usb_port, reg, val); } #endif /* CONFIG_USB_PD_TCPM_MUX */ @@ -235,8 +241,8 @@ void usb_mux_init(int port); * @param usb_config usb2.0 selected function. * @param polarity plug polarity (0=CC1, 1=CC2). */ -void usb_mux_set(int port, mux_state_t mux_mode, - enum usb_switch usb_config, int polarity); +void usb_mux_set(int port, mux_state_t mux_mode, enum usb_switch usb_config, + int polarity); /** * Configure superspeed muxes on type-C port for only one index in the mux diff --git a/include/usb_pd.h b/include/usb_pd.h index d5b6412d69..6254feb963 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,58 +26,56 @@ */ #if defined(HAS_TASK_PD_C0) && defined(CONFIG_USB_PD_PORT_MAX_COUNT) #define PD_PORT_TO_TASK_ID(port) (TASK_ID_PD_C0 + (port)) -#define TASK_ID_TO_PD_PORT(id) ((id) - TASK_ID_PD_C0) +#define TASK_ID_TO_PD_PORT(id) ((id)-TASK_ID_PD_C0) #else #define PD_PORT_TO_TASK_ID(port) -1 /* stub task ID */ #define TASK_ID_TO_PD_PORT(id) 0 #endif /* CONFIG_USB_PD_PORT_MAX_COUNT && HAS_TASK_PD_C0 */ enum pd_rx_errors { - PD_RX_ERR_INVAL = -1, /* Invalid packet */ - PD_RX_ERR_HARD_RESET = -2, /* Got a Hard-Reset packet */ - PD_RX_ERR_CRC = -3, /* CRC mismatch */ - PD_RX_ERR_ID = -4, /* Invalid ID number */ + PD_RX_ERR_INVAL = -1, /* Invalid packet */ + PD_RX_ERR_HARD_RESET = -2, /* Got a Hard-Reset packet */ + PD_RX_ERR_CRC = -3, /* CRC mismatch */ + PD_RX_ERR_ID = -4, /* Invalid ID number */ PD_RX_ERR_UNSUPPORTED_SOP = -5, /* Unsupported SOP */ - PD_RX_ERR_CABLE_RESET = -6 /* Got a Cable-Reset packet */ + PD_RX_ERR_CABLE_RESET = -6 /* Got a Cable-Reset packet */ }; /* Events for USB PD task */ /* Outgoing packet event */ -#define PD_EVENT_TX TASK_EVENT_CUSTOM_BIT(3) +#define PD_EVENT_TX TASK_EVENT_CUSTOM_BIT(3) /* CC line change event */ -#define PD_EVENT_CC TASK_EVENT_CUSTOM_BIT(4) +#define PD_EVENT_CC TASK_EVENT_CUSTOM_BIT(4) /* TCPC has reset */ -#define PD_EVENT_TCPC_RESET TASK_EVENT_CUSTOM_BIT(5) +#define PD_EVENT_TCPC_RESET TASK_EVENT_CUSTOM_BIT(5) /* DRP state has changed */ -#define PD_EVENT_UPDATE_DUAL_ROLE TASK_EVENT_CUSTOM_BIT(6) +#define PD_EVENT_UPDATE_DUAL_ROLE TASK_EVENT_CUSTOM_BIT(6) /* * A task, other than the task owning the PD port, accessed the TCPC. The task * that owns the port does not send itself this event. */ -#define PD_EVENT_DEVICE_ACCESSED TASK_EVENT_CUSTOM_BIT(7) +#define PD_EVENT_DEVICE_ACCESSED TASK_EVENT_CUSTOM_BIT(7) /* Chipset power state changed */ -#define PD_EVENT_POWER_STATE_CHANGE TASK_EVENT_CUSTOM_BIT(8) +#define PD_EVENT_POWER_STATE_CHANGE TASK_EVENT_CUSTOM_BIT(8) /* Issue a Hard Reset. */ -#define PD_EVENT_SEND_HARD_RESET TASK_EVENT_CUSTOM_BIT(9) +#define PD_EVENT_SEND_HARD_RESET TASK_EVENT_CUSTOM_BIT(9) /* Prepare for sysjump */ -#define PD_EVENT_SYSJUMP TASK_EVENT_CUSTOM_BIT(10) +#define PD_EVENT_SYSJUMP TASK_EVENT_CUSTOM_BIT(10) /* Receive a Hard Reset. */ -#define PD_EVENT_RX_HARD_RESET TASK_EVENT_CUSTOM_BIT(11) +#define PD_EVENT_RX_HARD_RESET TASK_EVENT_CUSTOM_BIT(11) /* MUX configured notification event */ -#define PD_EVENT_AP_MUX_DONE TASK_EVENT_CUSTOM_BIT(12) +#define PD_EVENT_AP_MUX_DONE TASK_EVENT_CUSTOM_BIT(12) /* First free event on PD task */ -#define PD_EVENT_FIRST_FREE_BIT 13 +#define PD_EVENT_FIRST_FREE_BIT 13 /* Ensure TCPC is out of low power mode before handling these events. */ -#define PD_EXIT_LOW_POWER_EVENT_MASK \ - (PD_EVENT_CC | \ - PD_EVENT_UPDATE_DUAL_ROLE | \ - PD_EVENT_POWER_STATE_CHANGE | \ - PD_EVENT_TCPC_RESET) +#define PD_EXIT_LOW_POWER_EVENT_MASK \ + (PD_EVENT_CC | PD_EVENT_UPDATE_DUAL_ROLE | \ + PD_EVENT_POWER_STATE_CHANGE | PD_EVENT_TCPC_RESET) /* --- PD data message helpers --- */ -#define PDO_MAX_OBJECTS 7 +#define PDO_MAX_OBJECTS 7 #define PDO_MODES (PDO_MAX_OBJECTS - 1) /* PDO : Power Data Object */ @@ -94,108 +92,105 @@ enum pd_rx_errors { * * Note: Some bits and decode macros are defined in ec_commands.h */ -#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported */ +#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported */ /* Higher capability in vSafe5V sink PDO */ -#define PDO_FIXED_SNK_HIGHER_CAP BIT(28) -#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED (0 << 23) +#define PDO_FIXED_SNK_HIGHER_CAP BIT(28) +#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED (0 << 23) #define PDO_FIXED_FRS_CURR_DFLT_USB_POWER (1 << 23) -#define PDO_FIXED_FRS_CURR_1A5_AT_5V (2 << 23) -#define PDO_FIXED_FRS_CURR_3A0_AT_5V (3 << 23) +#define PDO_FIXED_FRS_CURR_1A5_AT_5V (2 << 23) +#define PDO_FIXED_FRS_CURR_3A0_AT_5V (3 << 23) #define PDO_FIXED_PEAK_CURR () /* [21..20] Peak current */ -#define PDO_FIXED_VOLT(mv) (((mv)/50) << 10) /* Voltage in 50mV units */ -#define PDO_FIXED_CURR(ma) (((ma)/10) << 0) /* Max current in 10mA units */ +#define PDO_FIXED_VOLT(mv) (((mv) / 50) << 10) /* Voltage in 50mV units */ +#define PDO_FIXED_CURR(ma) (((ma) / 10) << 0) /* Max current in 10mA units */ #define PDO_FIXED_GET_VOLT(pdo) (((pdo >> 10) & 0x3FF) * 50) #define PDO_FIXED_GET_CURR(pdo) ((pdo & 0x3FF) * 10) -#define PDO_FIXED(mv, ma, flags) (PDO_FIXED_VOLT(mv) |\ - PDO_FIXED_CURR(ma) | (flags)) +#define PDO_FIXED(mv, ma, flags) \ + (PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma) | (flags)) #define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20) #define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10) -#define PDO_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 0) +#define PDO_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 0) -#define PDO_VAR(min_mv, max_mv, op_ma) \ - (PDO_VAR_MIN_VOLT(min_mv) | \ - PDO_VAR_MAX_VOLT(max_mv) | \ - PDO_VAR_OP_CURR(op_ma) | \ - PDO_TYPE_VARIABLE) +#define PDO_VAR(min_mv, max_mv, op_ma) \ + (PDO_VAR_MIN_VOLT(min_mv) | PDO_VAR_MAX_VOLT(max_mv) | \ + PDO_VAR_OP_CURR(op_ma) | PDO_TYPE_VARIABLE) #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20) #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10) #define PDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 0) -#define PDO_BATT(min_mv, max_mv, op_mw) \ - (PDO_BATT_MIN_VOLT(min_mv) | \ - PDO_BATT_MAX_VOLT(max_mv) | \ - PDO_BATT_OP_POWER(op_mw) | \ - PDO_TYPE_BATTERY) +#define PDO_BATT(min_mv, max_mv, op_mw) \ + (PDO_BATT_MIN_VOLT(min_mv) | PDO_BATT_MAX_VOLT(max_mv) | \ + PDO_BATT_OP_POWER(op_mw) | PDO_TYPE_BATTERY) /* RDO : Request Data Object */ -#define RDO_OBJ_POS(n) (((n) & 0x7) << 28) -#define RDO_POS(rdo) (((rdo) >> 28) & 0x7) -#define RDO_GIVE_BACK BIT(27) -#define RDO_CAP_MISMATCH BIT(26) -#define RDO_COMM_CAP BIT(25) -#define RDO_NO_SUSPEND BIT(24) -#define RDO_FIXED_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 10) +#define RDO_OBJ_POS(n) (((n)&0x7) << 28) +#define RDO_POS(rdo) (((rdo) >> 28) & 0x7) +#define RDO_GIVE_BACK BIT(27) +#define RDO_CAP_MISMATCH BIT(26) +#define RDO_COMM_CAP BIT(25) +#define RDO_NO_SUSPEND BIT(24) +#define RDO_FIXED_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 10) #define RDO_FIXED_VAR_MAX_CURR(ma) ((((ma) / 10) & 0x3FF) << 0) -#define RDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 10) -#define RDO_BATT_MAX_POWER(mw) ((((mw) / 250) & 0x3FF) << 0) +#define RDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 10) +#define RDO_BATT_MAX_POWER(mw) ((((mw) / 250) & 0x3FF) << 0) -#define RDO_FIXED(n, op_ma, max_ma, flags) \ - (RDO_OBJ_POS(n) | (flags) | \ - RDO_FIXED_VAR_OP_CURR(op_ma) | \ - RDO_FIXED_VAR_MAX_CURR(max_ma)) +#define RDO_FIXED(n, op_ma, max_ma, flags) \ + (RDO_OBJ_POS(n) | (flags) | RDO_FIXED_VAR_OP_CURR(op_ma) | \ + RDO_FIXED_VAR_MAX_CURR(max_ma)) - -#define RDO_BATT(n, op_mw, max_mw, flags) \ - (RDO_OBJ_POS(n) | (flags) | \ - RDO_BATT_OP_POWER(op_mw) | \ - RDO_BATT_MAX_POWER(max_mw)) +#define RDO_BATT(n, op_mw, max_mw, flags) \ + (RDO_OBJ_POS(n) | (flags) | RDO_BATT_OP_POWER(op_mw) | \ + RDO_BATT_MAX_POWER(max_mw)) /* BDO : BIST Data Object * 31:28 BIST Mode * In PD 3.0, all but Carrier Mode 2 (as Carrier Mode) and Test Data are - * reserved. + * reserved, with a new BIST shared mode added * 27:16 Reserved * 15:0 Returned error counters (reserved in PD 3.0) */ -#define BDO_MODE_RECV (0 << 28) -#define BDO_MODE_TRANSMIT BIT(28) -#define BDO_MODE_COUNTERS (2 << 28) -#define BDO_MODE_CARRIER0 (3 << 28) -#define BDO_MODE_CARRIER1 (4 << 28) -#define BDO_MODE_CARRIER2 (5 << 28) -#define BDO_MODE_CARRIER3 (6 << 28) -#define BDO_MODE_EYE (7 << 28) -#define BDO_MODE_TEST_DATA (8 << 28) - -#define BDO(mode, cnt) ((mode) | ((cnt) & 0xFFFF)) - -#define BIST_MODE(n) ((n) >> 28) -#define BIST_ERROR_COUNTER(n) ((n) & 0xffff) -#define BIST_RECEIVER_MODE 0 -#define BIST_TRANSMIT_MODE 1 +#define BDO_MODE_RECV (BIST_RECEIVER_MODE << 28) +#define BDO_MODE_TRANSMIT (BIST_TRANSMIT_MODE << 28) +#define BDO_MODE_COUNTERS (BIST_RETURNED_COUNTER << 28) +#define BDO_MODE_CARRIER0 (BIST_CARRIER_MODE_0 << 28) +#define BDO_MODE_CARRIER1 (BIST_CARRIER_MODE_1 << 28) +#define BDO_MODE_CARRIER2 (BIST_CARRIER_MODE_2 << 28) +#define BDO_MODE_CARRIER3 (BIST_CARRIER_MODE_3 << 28) +#define BDO_MODE_EYE (BIST_EYE_PATTERN << 28) +#define BDO_MODE_TEST_DATA (BIST_TEST_DATA << 28) +#define BDO_MODE_SHARED_ENTER (BIST_SHARED_MODE_ENTER << 28) +#define BDO_MODE_SHARED_EXIT (BIST_SHARED_MODE_EXIT << 28) + +#define BDO(mode, cnt) ((mode) | ((cnt)&0xFFFF)) + +#define BIST_MODE(n) ((n) >> 28) +#define BIST_ERROR_COUNTER(n) ((n)&0xffff) +#define BIST_RECEIVER_MODE 0 +#define BIST_TRANSMIT_MODE 1 #define BIST_RETURNED_COUNTER 2 -#define BIST_CARRIER_MODE_0 3 -#define BIST_CARRIER_MODE_1 4 -#define BIST_CARRIER_MODE_2 5 -#define BIST_CARRIER_MODE_3 6 -#define BIST_EYE_PATTERN 7 -#define BIST_TEST_DATA 8 +#define BIST_CARRIER_MODE_0 3 +#define BIST_CARRIER_MODE_1 4 +#define BIST_CARRIER_MODE_2 5 +#define BIST_CARRIER_MODE_3 6 +#define BIST_EYE_PATTERN 7 +#define BIST_TEST_DATA 8 +#define BIST_SHARED_MODE_ENTER 9 +#define BIST_SHARED_MODE_EXIT 10 #define SVID_DISCOVERY_MAX 16 /* Timers */ -#define PD_T_SINK_TX (18*MSEC) /* between 16ms and 20 */ -#define PD_T_CHUNKING_NOT_SUPPORTED (45*MSEC) /* between 40ms and 50ms */ -#define PD_T_HARD_RESET_COMPLETE (5*MSEC) /* between 4ms and 5ms*/ -#define PD_T_HARD_RESET_RETRY (1*MSEC) /* 1ms */ -#define PD_T_SEND_SOURCE_CAP (100*MSEC) /* between 100ms and 200ms */ -#define PD_T_SINK_WAIT_CAP (575*MSEC) /* between 310ms and 620ms */ -#define PD_T_SINK_TRANSITION (35*MSEC) /* between 20ms and 35ms */ -#define PD_T_SOURCE_ACTIVITY (45*MSEC) /* between 40ms and 50ms */ +#define PD_T_SINK_TX (18 * MSEC) /* between 16ms and 20 */ +#define PD_T_CHUNKING_NOT_SUPPORTED (45 * MSEC) /* between 40ms and 50ms */ +#define PD_T_HARD_RESET_COMPLETE (5 * MSEC) /* between 4ms and 5ms*/ +#define PD_T_HARD_RESET_RETRY (1 * MSEC) /* 1ms */ +#define PD_T_SEND_SOURCE_CAP (100 * MSEC) /* between 100ms and 200ms */ +#define PD_T_SINK_WAIT_CAP (575 * MSEC) /* between 310ms and 620ms */ +#define PD_T_SINK_TRANSITION (35 * MSEC) /* between 20ms and 35ms */ +#define PD_T_SOURCE_ACTIVITY (45 * MSEC) /* between 40ms and 50ms */ /* * Adjusting for TCPMv2 PD2 Compliance. In tests like TD.PD.SRC.E5 this * value is the duration before the Hard Reset can be sent. Setting the @@ -207,92 +202,99 @@ enum pd_rx_errors { * usb_pd unit test. */ #ifndef CONFIG_USB_PD_TCPMV2 -#define PD_T_SENDER_RESPONSE (30*MSEC) /* between 24ms and 30ms */ +#define PD_T_SENDER_RESPONSE (30 * MSEC) /* between 24ms and 30ms */ #else -#define PD_T_SENDER_RESPONSE (24*MSEC) /* between 24ms and 30ms */ +/* + * In USB Power Delivery Specification Revision 3.1, Version 1.5, + * the tSenderResponse have changed to min 26/ max 32 ms. + */ +#define PD_T_SENDER_RESPONSE (26 * MSEC) /* between 26ms and 32ms */ #endif -#define PD_T_PS_TRANSITION (500*MSEC) /* between 450ms and 550ms */ -#define PD_T_PS_SOURCE_ON (480*MSEC) /* between 390ms and 480ms */ -#define PD_T_PS_SOURCE_OFF (835*MSEC) /* between 750ms and 920ms */ -#define PD_T_PS_HARD_RESET (25*MSEC) /* between 25ms and 35ms */ -#define PD_T_ERROR_RECOVERY (240*MSEC) /* min 240ms if sourcing VConn */ -#define PD_T_CC_DEBOUNCE (100*MSEC) /* between 100ms and 200ms */ +#define PD_T_PS_TRANSITION (500 * MSEC) /* between 450ms and 550ms */ +/* + * This is adjusted for PD3.1 Compliance test TEST.PD.PROT.SRC.10. + */ +#define PD_T_PS_SOURCE_ON (435 * MSEC) /* between 390ms and 480ms */ +#define PD_T_PS_SOURCE_OFF (835 * MSEC) /* between 750ms and 920ms */ +#define PD_T_PS_HARD_RESET (25 * MSEC) /* between 25ms and 35ms */ +#define PD_T_ERROR_RECOVERY (240 * MSEC) /* min 240ms if sourcing VConn */ +#define PD_T_CC_DEBOUNCE (100 * MSEC) /* between 100ms and 200ms */ /* DRP_SNK + DRP_SRC must be between 50ms and 100ms with 30%-70% duty cycle */ -#define PD_T_DRP_SNK (40*MSEC) /* toggle time for sink DRP */ -#define PD_T_DRP_SRC (30*MSEC) /* toggle time for source DRP */ -#define PD_T_DEBOUNCE (15*MSEC) /* between 10ms and 20ms */ -#define PD_T_TRY_CC_DEBOUNCE (15*MSEC) /* between 10ms and 20ms */ -#define PD_T_SINK_ADJ (55*MSEC) /* between tPDDebounce and 60ms */ -#define PD_T_SRC_RECOVER (760*MSEC) /* between 660ms and 1000ms */ -#define PD_T_SRC_RECOVER_MAX (1000*MSEC) /* 1000ms */ -#define PD_T_SRC_TURN_ON (275*MSEC) /* 275ms */ -#define PD_T_SAFE_0V (650*MSEC) /* 650ms */ -#define PD_T_NO_RESPONSE (5500*MSEC) /* between 4.5s and 5.5s */ -#define PD_T_BIST_TRANSMIT (50*MSEC) /* 50ms (for task_wait arg) */ -#define PD_T_BIST_RECEIVE (60*MSEC) /* 60ms (time to process bist) */ -#define PD_T_BIST_CONT_MODE (55*MSEC) /* 30ms to 60ms */ -#define PD_T_VCONN_SOURCE_ON (100*MSEC) /* 100ms */ -#define PD_T_DRP_TRY (125*MSEC) /* between 75ms and 150ms */ -#define PD_T_TRY_TIMEOUT (550*MSEC) /* between 550ms and 1100ms */ -#define PD_T_TRY_WAIT (600*MSEC) /* Wait time for TryWait.SNK */ -#define PD_T_SINK_REQUEST (100*MSEC) /* 100ms before next request */ -#define PD_T_PD_DEBOUNCE (15*MSEC) /* between 10ms and 20ms */ -#define PD_T_CHUNK_SENDER_RESPONSE (25*MSEC) /* 25ms */ -#define PD_T_CHUNK_SENDER_REQUEST (25*MSEC) /* 25ms */ -#define PD_T_SWAP_SOURCE_START (25*MSEC) /* Min of 20ms */ -#define PD_T_RP_VALUE_CHANGE (20*MSEC) /* 20ms */ -#define PD_T_SRC_DISCONNECT (15*MSEC) /* 15ms */ -#define PD_T_SRC_TRANSITION (25*MSEC) /* 25ms to 35 ms */ -#define PD_T_VCONN_STABLE (50*MSEC) /* 50ms */ -#define PD_T_DISCOVER_IDENTITY (45*MSEC) /* between 40ms and 50ms */ -#define PD_T_SYSJUMP (1000*MSEC) /* 1s */ -#define PD_T_PR_SWAP_WAIT (100*MSEC) /* tPRSwapWait 100ms */ -#define PD_T_DATA_RESET (225*MSEC) /* between 200ms and 250ms */ -#define PD_T_DATA_RESET_FAIL (300*MSEC) /* 300ms */ -#define PD_T_VCONN_REAPPLIED (10*MSEC) /* between 10ms and 20ms */ -#define PD_T_VCONN_DISCHARGE (240*MSEC) /* between 160ms and 240ms */ +#define PD_T_DRP_SNK (40 * MSEC) /* toggle time for sink DRP */ +#define PD_T_DRP_SRC (30 * MSEC) /* toggle time for source DRP */ +#define PD_T_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */ +#define PD_T_TRY_CC_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */ +#define PD_T_SINK_ADJ (55 * MSEC) /* between tPDDebounce and 60ms */ +#define PD_T_SRC_RECOVER (760 * MSEC) /* between 660ms and 1000ms */ +#define PD_T_SRC_RECOVER_MAX (1000 * MSEC) /* 1000ms */ +#define PD_T_SRC_TURN_ON (275 * MSEC) /* 275ms */ +#define PD_T_SAFE_0V (650 * MSEC) /* 650ms */ +#define PD_T_NO_RESPONSE (5500 * MSEC) /* between 4.5s and 5.5s */ +#define PD_T_BIST_TRANSMIT (50 * MSEC) /* 50ms (for task_wait arg) */ +#define PD_T_BIST_RECEIVE (60 * MSEC) /* 60ms (time to process bist) */ +#define PD_T_BIST_CONT_MODE (55 * MSEC) /* 30ms to 60ms */ +#define PD_T_VCONN_SOURCE_ON (100 * MSEC) /* 100ms */ +#define PD_T_DRP_TRY (125 * MSEC) /* between 75ms and 150ms */ +#define PD_T_TRY_TIMEOUT (550 * MSEC) /* between 550ms and 1100ms */ +#define PD_T_TRY_WAIT (600 * MSEC) /* Wait time for TryWait.SNK */ +#define PD_T_SINK_REQUEST (100 * MSEC) /* 100ms before next request */ +#define PD_T_PD_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */ +#define PD_T_CHUNK_SENDER_RESPONSE (25 * MSEC) /* 25ms */ +#define PD_T_CHUNK_SENDER_REQUEST (25 * MSEC) /* 25ms */ +#define PD_T_SWAP_SOURCE_START (25 * MSEC) /* Min of 20ms */ +#define PD_T_RP_VALUE_CHANGE (20 * MSEC) /* 20ms */ +#define PD_T_SRC_DISCONNECT (15 * MSEC) /* 15ms */ +#define PD_T_SRC_TRANSITION (25 * MSEC) /* 25ms to 35 ms */ +#define PD_T_VCONN_STABLE (50 * MSEC) /* 50ms */ +#define PD_T_DISCOVER_IDENTITY (45 * MSEC) /* between 40ms and 50ms */ +#define PD_T_SYSJUMP (1000 * MSEC) /* 1s */ +#define PD_T_PR_SWAP_WAIT (100 * MSEC) /* tPRSwapWait 100ms */ +#define PD_T_DATA_RESET (225 * MSEC) /* between 200ms and 250ms */ +#define PD_T_DATA_RESET_FAIL (300 * MSEC) /* 300ms */ +#define PD_T_VCONN_REAPPLIED (10 * MSEC) /* between 10ms and 20ms */ +#define PD_T_VCONN_DISCHARGE (240 * MSEC) /* between 160ms and 240ms */ /* * Non-spec timer to prevent going Unattached if Vbus drops before a partner FRS * signal comes through. This timer should be shorter than tSinkDisconnect * (40ms) to ensure we still transition out of Attached.SNK in time. */ -#define PD_T_FRS_VBUS_DEBOUNCE (5*MSEC) +#define PD_T_FRS_VBUS_DEBOUNCE (5 * MSEC) /* number of edges and time window to detect CC line is not idle */ -#define PD_RX_TRANSITION_COUNT 3 +#define PD_RX_TRANSITION_COUNT 3 #define PD_RX_TRANSITION_WINDOW 20 /* between 12us and 20us */ /* from USB Type-C Specification Table 5-1 */ -#define PD_T_AME (1*SECOND) /* timeout from UFP attach to Alt Mode Entry */ +#define PD_T_AME (1 * SECOND) /* timeout from UFP attach to Alt Mode Entry */ /* VDM Timers ( USB PD Spec Rev2.0 Table 6-30 )*/ -#define PD_T_VDM_BUSY (50*MSEC) /* at least 50ms */ -#define PD_T_VDM_E_MODE (25*MSEC) /* enter/exit the same max */ -#define PD_T_VDM_RCVR_RSP (15*MSEC) /* max of 15ms */ -#define PD_T_VDM_SNDR_RSP (30*MSEC) /* max of 30ms */ -#define PD_T_VDM_WAIT_MODE_E (100*MSEC) /* enter/exit the same max */ +#define PD_T_VDM_BUSY (50 * MSEC) /* at least 50ms */ +#define PD_T_VDM_E_MODE (25 * MSEC) /* enter/exit the same max */ +#define PD_T_VDM_RCVR_RSP (15 * MSEC) /* max of 15ms */ +#define PD_T_VDM_SNDR_RSP (30 * MSEC) /* max of 30ms */ +#define PD_T_VDM_WAIT_MODE_E (100 * MSEC) /* enter/exit the same max */ /* CTVPD Timers ( USB Type-C ECN Table 4-27 ) */ -#define PD_T_VPDDETACH (20*MSEC) /* max of 20*MSEC */ -#define PD_T_VPDCTDD (4*MSEC) /* max of 4ms */ -#define PD_T_VPDDISABLE (25*MSEC) /* min of 25ms */ +#define PD_T_VPDDETACH (20 * MSEC) /* max of 20*MSEC */ +#define PD_T_VPDCTDD (4 * MSEC) /* max of 4ms */ +#define PD_T_VPDDISABLE (25 * MSEC) /* min of 25ms */ /* Voltage thresholds in mV (Table 7-24, PD 3.0 Version 2.0 Spec) */ -#define PD_V_SAFE0V_MAX 800 -#define PD_V_SAFE5V_MIN 4750 -#define PD_V_SAFE5V_NOM 5000 -#define PD_V_SAFE5V_MAX 5500 +#define PD_V_SAFE0V_MAX 800 +#define PD_V_SAFE5V_MIN 4750 +#define PD_V_SAFE5V_NOM 5000 +#define PD_V_SAFE5V_MAX 5500 /* USB Type-C voltages in mV (Table 4-3, USB Type-C Release 2.0 Spec) */ #define PD_V_SINK_DISCONNECT_MAX 3670 /* TODO(b/149530538): Add equation for vSinkDisconnectPD */ /* Maximum voltage in mV offered by PD 3.0 Version 2.0 Spec */ -#define PD_REV3_MAX_VOLTAGE 20000 +#define PD_REV3_MAX_VOLTAGE 20000 /* Power in mW at which we will automatically charge from a DRP partner */ -#define PD_DRP_CHARGE_POWER_MIN 27000 +#define PD_DRP_CHARGE_POWER_MIN 27000 /* function table for entered mode */ struct amode_fx { @@ -325,9 +327,9 @@ struct svdm_response { * value after resetting connection information via memset. */ enum pd_discovery_state { - PD_DISC_NEEDED = 0, /* Cable or partner still needs to be probed */ - PD_DISC_COMPLETE, /* Successfully probed, valid to read VDO */ - PD_DISC_FAIL, /* Cable did not respond, or Discover* NAK */ + PD_DISC_NEEDED = 0, /* Cable or partner still needs to be probed */ + PD_DISC_COMPLETE, /* Successfully probed, valid to read VDO */ + PD_DISC_FAIL, /* Cable did not respond, or Discover* NAK */ }; /* Mode discovery state for a particular SVID with a particular transmit type */ @@ -391,8 +393,8 @@ enum hpd_event { }; /* DisplayPort flags */ -#define DP_FLAGS_DP_ON BIT(0) /* Display port mode is on */ -#define DP_FLAGS_HPD_HI_PENDING BIT(1) /* Pending HPD_HI */ +#define DP_FLAGS_DP_ON BIT(0) /* Display port mode is on */ +#define DP_FLAGS_HPD_HI_PENDING BIT(1) /* Pending HPD_HI */ /* Discover Identity ACK contents after headers */ union disc_ident_ack { @@ -408,7 +410,7 @@ union disc_ident_ack { uint32_t raw_value[PDO_MAX_OBJECTS - 1]; }; BUILD_ASSERT(sizeof(union disc_ident_ack) == - sizeof(uint32_t) * (PDO_MAX_OBJECTS - 1)); + sizeof(uint32_t) * (PDO_MAX_OBJECTS - 1)); /* Discover Identity data - ACK plus discovery state */ struct identity_data { @@ -428,10 +430,10 @@ enum pd_alternate_modes { /* Discover and possibly enter modes for all SOP* communications when enabled */ #ifdef CONFIG_USB_PD_DECODE_SOP #define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP_PRIME + 1) -#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP_PRIME_PRIME + 1) +#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP_PRIME_PRIME + 1) #else #define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP + 1) -#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP + 1) +#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP + 1) #endif /* Discovery results for a port partner (SOP) or cable plug (SOP') */ @@ -485,56 +487,53 @@ struct partner_active_modes { * <4:0> :: command */ #define VDO(vid, type, custom) \ - (((vid) << 16) | \ - ((type) << 15) | \ - ((custom) & 0x7FFF)) - -#define VDO_SVDM_TYPE BIT(15) -#define VDO_SVDM_VERS(x) (x << 13) -#define VDO_OPOS(x) (x << 8) -#define VDO_CMDT(x) (x << 6) -#define VDO_OPOS_MASK VDO_OPOS(0x7) -#define VDO_CMDT_MASK VDO_CMDT(0x3) - -#define CMDT_INIT 0 -#define CMDT_RSP_ACK 1 -#define CMDT_RSP_NAK 2 + (((vid) << 16) | ((type) << 15) | ((custom)&0x7FFF)) + +#define VDO_SVDM_TYPE BIT(15) +#define VDO_SVDM_VERS(x) (x << 13) +#define VDO_OPOS(x) (x << 8) +#define VDO_CMDT(x) (x << 6) +#define VDO_OPOS_MASK VDO_OPOS(0x7) +#define VDO_CMDT_MASK VDO_CMDT(0x3) + +#define CMDT_INIT 0 +#define CMDT_RSP_ACK 1 +#define CMDT_RSP_NAK 2 #define CMDT_RSP_BUSY 3 - /* reserved for SVDM ... for Google UVDM */ #define VDO_SRC_INITIATOR (0 << 5) #define VDO_SRC_RESPONDER BIT(5) -#define CMD_DISCOVER_IDENT 1 -#define CMD_DISCOVER_SVID 2 -#define CMD_DISCOVER_MODES 3 -#define CMD_ENTER_MODE 4 -#define CMD_EXIT_MODE 5 -#define CMD_ATTENTION 6 -#define CMD_DP_STATUS 16 -#define CMD_DP_CONFIG 17 +#define CMD_DISCOVER_IDENT 1 +#define CMD_DISCOVER_SVID 2 +#define CMD_DISCOVER_MODES 3 +#define CMD_ENTER_MODE 4 +#define CMD_EXIT_MODE 5 +#define CMD_ATTENTION 6 +#define CMD_DP_STATUS 16 +#define CMD_DP_CONFIG 17 -#define VDO_CMD_VENDOR(x) (((10 + (x)) & 0x1f)) +#define VDO_CMD_VENDOR(x) (((10 + (x)) & 0x1f)) /* ChromeOS specific commands */ -#define VDO_CMD_VERSION VDO_CMD_VENDOR(0) -#define VDO_CMD_SEND_INFO VDO_CMD_VENDOR(1) -#define VDO_CMD_READ_INFO VDO_CMD_VENDOR(2) -#define VDO_CMD_REBOOT VDO_CMD_VENDOR(5) -#define VDO_CMD_FLASH_ERASE VDO_CMD_VENDOR(6) -#define VDO_CMD_FLASH_WRITE VDO_CMD_VENDOR(7) -#define VDO_CMD_ERASE_SIG VDO_CMD_VENDOR(8) -#define VDO_CMD_PING_ENABLE VDO_CMD_VENDOR(10) -#define VDO_CMD_CURRENT VDO_CMD_VENDOR(11) -#define VDO_CMD_FLIP VDO_CMD_VENDOR(12) -#define VDO_CMD_GET_LOG VDO_CMD_VENDOR(13) -#define VDO_CMD_CCD_EN VDO_CMD_VENDOR(14) - -#define PD_VDO_VID(vdo) ((vdo) >> 16) +#define VDO_CMD_VERSION VDO_CMD_VENDOR(0) +#define VDO_CMD_SEND_INFO VDO_CMD_VENDOR(1) +#define VDO_CMD_READ_INFO VDO_CMD_VENDOR(2) +#define VDO_CMD_REBOOT VDO_CMD_VENDOR(5) +#define VDO_CMD_FLASH_ERASE VDO_CMD_VENDOR(6) +#define VDO_CMD_FLASH_WRITE VDO_CMD_VENDOR(7) +#define VDO_CMD_ERASE_SIG VDO_CMD_VENDOR(8) +#define VDO_CMD_PING_ENABLE VDO_CMD_VENDOR(10) +#define VDO_CMD_CURRENT VDO_CMD_VENDOR(11) +#define VDO_CMD_FLIP VDO_CMD_VENDOR(12) +#define VDO_CMD_GET_LOG VDO_CMD_VENDOR(13) +#define VDO_CMD_CCD_EN VDO_CMD_VENDOR(14) + +#define PD_VDO_VID(vdo) ((vdo) >> 16) #define PD_VDO_SVDM(vdo) (((vdo) >> 15) & 1) #define PD_VDO_OPOS(vdo) (((vdo) >> 8) & 0x7) -#define PD_VDO_CMD(vdo) ((vdo) & 0x1f) +#define PD_VDO_CMD(vdo) ((vdo)&0x1f) #define PD_VDO_CMDT(vdo) (((vdo) >> 6) & 0x3) /* @@ -556,51 +555,51 @@ struct partner_active_modes { * [6] :: Product type DFP VDO * */ -#define VDO_INDEX_HDR 0 -#define VDO_INDEX_IDH 1 -#define VDO_INDEX_CSTAT 2 -#define VDO_INDEX_CABLE 3 -#define VDO_INDEX_PRODUCT 3 -#define VDO_INDEX_AMA 4 +#define VDO_INDEX_HDR 0 +#define VDO_INDEX_IDH 1 +#define VDO_INDEX_CSTAT 2 +#define VDO_INDEX_CABLE 3 +#define VDO_INDEX_PRODUCT 3 +#define VDO_INDEX_AMA 4 #define VDO_INDEX_PTYPE_UFP1_VDO 4 -#define VDO_INDEX_PTYPE_CABLE1 4 +#define VDO_INDEX_PTYPE_CABLE1 4 #define VDO_INDEX_PTYPE_UFP2_VDO 5 -#define VDO_INDEX_PTYPE_CABLE2 5 -#define VDO_INDEX_PTYPE_DFP_VDO 6 +#define VDO_INDEX_PTYPE_CABLE2 5 +#define VDO_INDEX_PTYPE_DFP_VDO 6 #define VDO_I(name) VDO_INDEX_##name /* PD Rev 2.0 ID Header VDO */ -#define VDO_IDH(usbh, usbd, ptype, is_modal, vid) \ - ((usbh) << 31 | (usbd) << 30 | ((ptype) & 0x7) << 27 \ - | (is_modal) << 26 | ((vid) & 0xffff)) +#define VDO_IDH(usbh, usbd, ptype, is_modal, vid) \ + ((usbh) << 31 | (usbd) << 30 | ((ptype)&0x7) << 27 | \ + (is_modal) << 26 | ((vid)&0xffff)) /* PD Rev 3.0 ID Header VDO */ -#define VDO_IDH_REV30(usbh, usbd, ptype_u, is_modal, ptype_d, ctype, vid) \ - (VDO_IDH(usbh, usbd, ptype_u, is_modal, vid) \ - | ((ptype_d) & 0x7) << 23 | ((ctype) & 0x3) << 21) +#define VDO_IDH_REV30(usbh, usbd, ptype_u, is_modal, ptype_d, ctype, vid) \ + (VDO_IDH(usbh, usbd, ptype_u, is_modal, vid) | ((ptype_d)&0x7) << 23 | \ + ((ctype)&0x3) << 21) -#define PD_IDH_PTYPE(vdo) (((vdo) >> 27) & 0x7) +#define PD_IDH_PTYPE(vdo) (((vdo) >> 27) & 0x7) #define PD_IDH_IS_MODAL(vdo) (((vdo) >> 26) & 0x1) -#define PD_IDH_VID(vdo) ((vdo) & 0xffff) +#define PD_IDH_VID(vdo) ((vdo)&0xffff) -#define VDO_CSTAT(tid) ((tid) & 0xfffff) -#define PD_CSTAT_TID(vdo) ((vdo) & 0xfffff) +#define VDO_CSTAT(tid) ((tid)&0xfffff) +#define PD_CSTAT_TID(vdo) ((vdo)&0xfffff) -#define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff)) +#define VDO_PRODUCT(pid, bcd) (((pid)&0xffff) << 16 | ((bcd)&0xffff)) #define PD_PRODUCT_PID(vdo) (((vdo) >> 16) & 0xffff) -/* - * PD Rev 3.1 Revision Message Data Object (RMDO) - * Only bits 16-31 have data. A uint_16t is used to hold RMDOs upper 16 bits. - */ +/* PD Rev 3.1 Revision Message Data Object (RMDO) */ struct rmdo { - int reserved : 16; - int minor_ver : 4; - int major_ver : 4; - int minor_rev : 4; - int major_rev : 4; + uint32_t reserved : 16; + uint32_t minor_ver : 4; + uint32_t major_ver : 4; + uint32_t minor_rev : 4; + uint32_t major_rev : 4; }; +/* Confirm RMDO is 32 bits. */ +BUILD_ASSERT(sizeof(struct rmdo) == 4); + /* * Message id starts from 0 to 7. If last_msg_id is initialized to 0, * it will lead to repetitive message id with first received packet, @@ -622,9 +621,9 @@ enum pd_rev_type { }; #ifdef CONFIG_USB_PD_REV30 -#define PD_REVISION PD_REV30 +#define PD_REVISION PD_REV30 #else -#define PD_REVISION PD_REV20 +#define PD_REVISION PD_REV20 #endif #if defined(CONFIG_USB_PD_TCPMV1) @@ -649,18 +648,17 @@ struct pd_cable { /* Cable revision */ enum pd_rev_type rev; - }; /* Note: These flags are only used for TCPMv1 */ /* Check if Thunderbolt-compatible mode enabled */ -#define CABLE_FLAGS_TBT_COMPAT_ENABLE BIT(0) +#define CABLE_FLAGS_TBT_COMPAT_ENABLE BIT(0) /* Flag to limit speed to TBT Gen 2 passive cable */ #define CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED BIT(1) /* Flag for checking if device is USB4.0 capable */ -#define CABLE_FLAGS_USB4_CAPABLE BIT(2) +#define CABLE_FLAGS_USB4_CAPABLE BIT(2) /* Flag for entering ENTER_USB mode */ -#define CABLE_FLAGS_ENTER_USB_MODE BIT(3) +#define CABLE_FLAGS_ENTER_USB_MODE BIT(3) /* * SVDM Discover SVIDs request -> response @@ -670,9 +668,9 @@ struct pd_cable { * mark the end of SVIDs. If more than 12 SVIDs are supported command SHOULD be * repeated. */ -#define VDO_SVID(svid0, svid1) (((svid0) & 0xffff) << 16 | ((svid1) & 0xffff)) +#define VDO_SVID(svid0, svid1) (((svid0)&0xffff) << 16 | ((svid1)&0xffff)) #define PD_VDO_SVID_SVID0(vdo) ((vdo) >> 16) -#define PD_VDO_SVID_SVID1(vdo) ((vdo) & 0xffff) +#define PD_VDO_SVID_SVID1(vdo) ((vdo)&0xffff) /* * Google modes capabilities @@ -702,10 +700,9 @@ struct pd_cable { * Other bits are reserved. * <1:0> : signal direction ( 00b=rsv, 01b=sink, 10b=src 11b=both ) */ -#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir) \ - (((snkp) & 0xff) << 16 | ((srcp) & 0xff) << 8 \ - | ((usb) & 1) << 7 | ((gdr) & 1) << 6 | ((sign) & 0xF) << 2 \ - | ((sdir) & 0x3)) +#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir) \ + (((snkp)&0xff) << 16 | ((srcp)&0xff) << 8 | ((usb)&1) << 7 | \ + ((gdr)&1) << 6 | ((sign)&0xF) << 2 | ((sdir)&0x3)) #define MODE_DP_DFP_PIN_SHIFT 8 #define MODE_DP_UFP_PIN_SHIFT 16 @@ -719,11 +716,11 @@ struct pd_cable { /* Pin configs A/B/C/D/E/F */ #define MODE_DP_PIN_CAPS_MASK 0x3f -#define MODE_DP_V13 0x1 +#define MODE_DP_V13 0x1 #define MODE_DP_GEN2 0x2 -#define MODE_DP_SNK 0x1 -#define MODE_DP_SRC 0x2 +#define MODE_DP_SNK 0x1 +#define MODE_DP_SRC 0x2 #define MODE_DP_BOTH 0x3 #define MODE_DP_CABLE_SHIFT 6 @@ -740,9 +737,10 @@ struct pd_cable { * or UFP_D (if receptacle==1) * Also refer to DisplayPort Alt Mode Capabilities Clarification (4/30/2015) */ -#define PD_DP_PIN_CAPS(x) ((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) \ - ? (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) \ - : (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK)) +#define PD_DP_PIN_CAPS(x) \ + ((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) ? \ + (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) : \ + (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK)) /* * DisplayPort Status VDO @@ -758,10 +756,10 @@ struct pd_cable { * <1:0> : connect status : 00b == no (DFP|UFP)_D is connected or disabled. * 01b == DFP_D connected, 10b == UFP_D connected, 11b == both. */ -#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn) \ - (((irq) & 1) << 8 | ((lvl) & 1) << 7 | ((amode) & 1) << 6 \ - | ((usbc) & 1) << 5 | ((mf) & 1) << 4 | ((en) & 1) << 3 \ - | ((lp) & 1) << 2 | ((conn & 0x3) << 0)) +#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn) \ + (((irq)&1) << 8 | ((lvl)&1) << 7 | ((amode)&1) << 6 | \ + ((usbc)&1) << 5 | ((mf)&1) << 4 | ((en)&1) << 3 | ((lp)&1) << 2 | \ + ((conn & 0x3) << 0)) #define PD_VDO_DPSTS_MF_MASK BIT(4) @@ -770,9 +768,9 @@ struct pd_cable { #define PD_VDO_DPSTS_MF_PREF(x) (((x) >> 4) & 1) /* Per DisplayPort Spec v1.3 Section 3.3 */ -#define HPD_USTREAM_DEBOUNCE_LVL (2*MSEC) +#define HPD_USTREAM_DEBOUNCE_LVL (2 * MSEC) #define HPD_USTREAM_DEBOUNCE_IRQ (250) -#define HPD_DSTREAM_DEBOUNCE_IRQ (500) /* between 500-1000us */ +#define HPD_DSTREAM_DEBOUNCE_IRQ (500) /* between 500-1000us */ /* * DisplayPort Configure VDO @@ -786,7 +784,7 @@ struct pd_cable { * <1:0> : cfg : 00 == USB, 01 == DFP_D, 10 == UFP_D, 11 == reserved */ #define VDO_DP_CFG(pin, sig, cfg) \ - (((pin) & 0xff) << 8 | ((sig) & 0xf) << 2 | ((cfg) & 0x3)) + (((pin)&0xff) << 8 | ((sig)&0xf) << 2 | ((cfg)&0x3)) #define PD_DP_CFG_DPON(x) (((x & 0x3) == 1) || ((x & 0x3) == 2)) /* @@ -794,18 +792,18 @@ struct pd_cable { * for backward compatibility, if it is null, * get the former sink pin assignment we used to be in <23:16>. */ -#define PD_DP_CFG_PIN(x) ((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) \ - : (((x) >> 16) & 0xff)) +#define PD_DP_CFG_PIN(x) \ + ((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) : (((x) >> 16) & 0xff)) /* * ChromeOS specific PD device Hardware IDs. Used to identify unique * products and used in VDO_INFO. Note this field is 10 bits. */ -#define USB_PD_HW_DEV_ID_RESERVED 0 -#define USB_PD_HW_DEV_ID_ZINGER 1 -#define USB_PD_HW_DEV_ID_MINIMUFFIN 2 -#define USB_PD_HW_DEV_ID_DINGDONG 3 -#define USB_PD_HW_DEV_ID_HOHO 4 -#define USB_PD_HW_DEV_ID_HONEYBUNS 5 +#define USB_PD_HW_DEV_ID_RESERVED 0 +#define USB_PD_HW_DEV_ID_ZINGER 1 +#define USB_PD_HW_DEV_ID_MINIMUFFIN 2 +#define USB_PD_HW_DEV_ID_DINGDONG 3 +#define USB_PD_HW_DEV_ID_HOHO 4 +#define USB_PD_HW_DEV_ID_HONEYBUNS 5 /* * ChromeOS specific VDO_CMD_READ_INFO responds with device info including: @@ -815,86 +813,87 @@ struct pd_cable { * SW Debug Version: Software version useful for debugging (15 bits) * IS RW: True if currently in RW, False otherwise (1 bit) */ -#define VDO_INFO(id, id_minor, ver, is_rw) ((id_minor) << 26 \ - | ((id) & 0x3ff) << 16 \ - | ((ver) & 0x7fff) << 1 \ - | ((is_rw) & 1)) -#define VDO_INFO_HW_DEV_ID(x) ((x) >> 16) -#define VDO_INFO_SW_DBG_VER(x) (((x) >> 1) & 0x7fff) -#define VDO_INFO_IS_RW(x) ((x) & 1) +#define VDO_INFO(id, id_minor, ver, is_rw) \ + ((id_minor) << 26 | ((id)&0x3ff) << 16 | ((ver)&0x7fff) << 1 | \ + ((is_rw)&1)) +#define VDO_INFO_HW_DEV_ID(x) ((x) >> 16) +#define VDO_INFO_SW_DBG_VER(x) (((x) >> 1) & 0x7fff) +#define VDO_INFO_IS_RW(x) ((x)&1) #define HW_DEV_ID_MAJ(x) (x & 0x3ff) #define HW_DEV_ID_MIN(x) ((x) >> 10) /* USB-IF SIDs */ -#define USB_SID_PD 0xff00 /* power delivery */ +#define USB_SID_PD 0xff00 /* power delivery */ #define USB_SID_DISPLAYPORT 0xff01 #define USB_GOOGLE_TYPEC_URL "http://www.google.com/chrome/devices/typec" -/* USB Vendor ID assigned to Google Inc. */ +/* USB Vendor ID assigned to Google LLC */ #define USB_VID_GOOGLE 0x18d1 /* Other Vendor IDs */ -#define USB_VID_APPLE 0x05ac +#define USB_VID_APPLE 0x05ac #define USB_PID1_APPLE 0x1012 #define USB_PID2_APPLE 0x1013 -#define USB_VID_HP 0x03F0 -#define USB_PID_HP_USB_C_DOCK_G5 0x036B -#define USB_PID_HP_USB_C_A_UNIV_DOCK_G2 0x096B -#define USB_PID_HP_E24D_DOCK_MONITOR 0x0467 -#define USB_PID_HP_ELITE_E233_MONITOR 0x1747 -#define USB_PID_HP_E244D_DOCK_MONITOR 0x056D -#define USB_PID_HP_E274D_DOCK_MONITOR 0x016E +#define USB_VID_HP 0x03F0 +#define USB_PID_HP_USB_C_DOCK_G5 0x036B +#define USB_PID_HP_USB_C_A_UNIV_DOCK_G2 0x096B +#define USB_PID_HP_E24D_DOCK_MONITOR 0x0467 +#define USB_PID_HP_ELITE_E233_MONITOR 0x1747 +#define USB_PID_HP_E244D_DOCK_MONITOR 0x056D +#define USB_PID_HP_E274D_DOCK_MONITOR 0x016E -#define USB_VID_INTEL 0x8087 +#define USB_VID_INTEL 0x8087 /* Timeout for message receive in microseconds */ #define USB_PD_RX_TMOUT_US 1800 +/* Power button press length triggered by USB PD short button press */ +#define USB_PD_SHORT_BUTTON_PRESS_MS 500 + /* --- Protocol layer functions --- */ enum pd_states { - PD_STATE_DISABLED, /* C0 */ - PD_STATE_SUSPENDED, /* C1 */ - PD_STATE_SNK_DISCONNECTED, /* C2 */ - PD_STATE_SNK_DISCONNECTED_DEBOUNCE, /* C3 */ - PD_STATE_SNK_HARD_RESET_RECOVER, /* C4 */ - PD_STATE_SNK_DISCOVERY, /* C5 */ - PD_STATE_SNK_REQUESTED, /* C6 */ - PD_STATE_SNK_TRANSITION, /* C7 */ - PD_STATE_SNK_READY, /* C8 */ - PD_STATE_SNK_SWAP_INIT, /* C9 */ - PD_STATE_SNK_SWAP_SNK_DISABLE, /* C10 */ - PD_STATE_SNK_SWAP_SRC_DISABLE, /* C11 */ - PD_STATE_SNK_SWAP_STANDBY, /* C12 */ - PD_STATE_SNK_SWAP_COMPLETE, /* C13 */ - PD_STATE_SRC_DISCONNECTED, /* C14 */ - PD_STATE_SRC_DISCONNECTED_DEBOUNCE, /* C15 */ - PD_STATE_SRC_HARD_RESET_RECOVER, /* C16 */ - PD_STATE_SRC_STARTUP, /* C17 */ - PD_STATE_SRC_DISCOVERY, /* C18 */ - PD_STATE_SRC_NEGOCIATE, /* C19 */ - PD_STATE_SRC_ACCEPTED, /* C20 */ - PD_STATE_SRC_POWERED, /* C21 */ - PD_STATE_SRC_TRANSITION, /* C22 */ - PD_STATE_SRC_READY, /* C23 */ - PD_STATE_SRC_GET_SINK_CAP, /* C24 */ - PD_STATE_DR_SWAP, /* C25 */ - PD_STATE_SRC_SWAP_INIT, /* C26 */ - PD_STATE_SRC_SWAP_SNK_DISABLE, /* C27 */ - PD_STATE_SRC_SWAP_SRC_DISABLE, /* C28 */ - PD_STATE_SRC_SWAP_STANDBY, /* C29 */ - PD_STATE_VCONN_SWAP_SEND, /* C30 */ - PD_STATE_VCONN_SWAP_INIT, /* C31 */ - PD_STATE_VCONN_SWAP_READY, /* C32 */ - PD_STATE_SOFT_RESET, /* C33 */ - PD_STATE_HARD_RESET_SEND, /* C34 */ - PD_STATE_HARD_RESET_EXECUTE, /* C35 */ - PD_STATE_BIST_RX, /* C36 */ - PD_STATE_BIST_TX, /* C37 */ - PD_STATE_DRP_AUTO_TOGGLE, /* C38 */ - PD_STATE_ENTER_USB, /* C39 */ + PD_STATE_DISABLED, /* C0 */ + PD_STATE_SUSPENDED, /* C1 */ + PD_STATE_SNK_DISCONNECTED, /* C2 */ + PD_STATE_SNK_DISCONNECTED_DEBOUNCE, /* C3 */ + PD_STATE_SNK_HARD_RESET_RECOVER, /* C4 */ + PD_STATE_SNK_DISCOVERY, /* C5 */ + PD_STATE_SNK_REQUESTED, /* C6 */ + PD_STATE_SNK_TRANSITION, /* C7 */ + PD_STATE_SNK_READY, /* C8 */ + PD_STATE_SNK_SWAP_INIT, /* C9 */ + PD_STATE_SNK_SWAP_SNK_DISABLE, /* C10 */ + PD_STATE_SNK_SWAP_SRC_DISABLE, /* C11 */ + PD_STATE_SNK_SWAP_STANDBY, /* C12 */ + PD_STATE_SNK_SWAP_COMPLETE, /* C13 */ + PD_STATE_SRC_DISCONNECTED, /* C14 */ + PD_STATE_SRC_DISCONNECTED_DEBOUNCE, /* C15 */ + PD_STATE_SRC_HARD_RESET_RECOVER, /* C16 */ + PD_STATE_SRC_STARTUP, /* C17 */ + PD_STATE_SRC_DISCOVERY, /* C18 */ + PD_STATE_SRC_NEGOCIATE, /* C19 */ + PD_STATE_SRC_ACCEPTED, /* C20 */ + PD_STATE_SRC_POWERED, /* C21 */ + PD_STATE_SRC_TRANSITION, /* C22 */ + PD_STATE_SRC_READY, /* C23 */ + PD_STATE_SRC_GET_SINK_CAP, /* C24 */ + PD_STATE_DR_SWAP, /* C25 */ + PD_STATE_SRC_SWAP_INIT, /* C26 */ + PD_STATE_SRC_SWAP_SNK_DISABLE, /* C27 */ + PD_STATE_SRC_SWAP_SRC_DISABLE, /* C28 */ + PD_STATE_SRC_SWAP_STANDBY, /* C29 */ + PD_STATE_VCONN_SWAP_SEND, /* C30 */ + PD_STATE_VCONN_SWAP_INIT, /* C31 */ + PD_STATE_VCONN_SWAP_READY, /* C32 */ + PD_STATE_SOFT_RESET, /* C33 */ + PD_STATE_HARD_RESET_SEND, /* C34 */ + PD_STATE_HARD_RESET_EXECUTE, /* C35 */ + PD_STATE_BIST_RX, /* C36 */ + PD_STATE_BIST_TX, /* C37 */ + PD_STATE_DRP_AUTO_TOGGLE, /* C38 */ /* Number of states. Not an actual state. */ PD_STATE_COUNT, }; @@ -939,23 +938,23 @@ enum pd_states { #ifdef CONFIG_USB_PD_TCPMV1 /* Flags used for TCPMv1 */ -#define PD_FLAGS_PING_ENABLED BIT(0) /* SRC_READY pings enabled */ -#define PD_FLAGS_PARTNER_DR_POWER BIT(1) /* port partner is dualrole power */ -#define PD_FLAGS_PARTNER_DR_DATA BIT(2) /* port partner is dualrole data */ -#define PD_FLAGS_CHECK_IDENTITY BIT(3) /* discover identity in READY */ -#define PD_FLAGS_SNK_CAP_RECVD BIT(4) /* sink capabilities received */ -#define PD_FLAGS_TCPC_DRP_TOGGLE BIT(5) /* TCPC-controlled DRP toggling */ +#define PD_FLAGS_PING_ENABLED BIT(0) /* SRC_READY pings enabled */ +#define PD_FLAGS_PARTNER_DR_POWER BIT(1) /* port partner is dualrole power */ +#define PD_FLAGS_PARTNER_DR_DATA BIT(2) /* port partner is dualrole data */ +#define PD_FLAGS_CHECK_IDENTITY BIT(3) /* discover identity in READY */ +#define PD_FLAGS_SNK_CAP_RECVD BIT(4) /* sink capabilities received */ +#define PD_FLAGS_TCPC_DRP_TOGGLE BIT(5) /* TCPC-controlled DRP toggling */ #define PD_FLAGS_EXPLICIT_CONTRACT BIT(6) /* explicit pwr contract in place */ -#define PD_FLAGS_VBUS_NEVER_LOW BIT(7) /* VBUS input has never been low */ -#define PD_FLAGS_PREVIOUS_PD_CONN BIT(8) /* previously PD connected */ -#define PD_FLAGS_CHECK_PR_ROLE BIT(9) /* check power role in READY */ -#define PD_FLAGS_CHECK_DR_ROLE BIT(10)/* check data role in READY */ -#define PD_FLAGS_PARTNER_UNCONSTR BIT(11)/* port partner unconstrained pwr */ -#define PD_FLAGS_VCONN_ON BIT(12)/* vconn is being sourced */ -#define PD_FLAGS_TRY_SRC BIT(13)/* Try.SRC states are active */ -#define PD_FLAGS_PARTNER_USB_COMM BIT(14)/* port partner is USB comms */ -#define PD_FLAGS_UPDATE_SRC_CAPS BIT(15)/* send new source capabilities */ -#define PD_FLAGS_TS_DTS_PARTNER BIT(16)/* partner has rp/rp or rd/rd */ +#define PD_FLAGS_VBUS_NEVER_LOW BIT(7) /* VBUS input has never been low */ +#define PD_FLAGS_PREVIOUS_PD_CONN BIT(8) /* previously PD connected */ +#define PD_FLAGS_CHECK_PR_ROLE BIT(9) /* check power role in READY */ +#define PD_FLAGS_CHECK_DR_ROLE BIT(10) /* check data role in READY */ +#define PD_FLAGS_PARTNER_UNCONSTR BIT(11) /* port partner unconstrained pwr */ +#define PD_FLAGS_VCONN_ON BIT(12) /* vconn is being sourced */ +#define PD_FLAGS_TRY_SRC BIT(13) /* Try.SRC states are active */ +#define PD_FLAGS_PARTNER_USB_COMM BIT(14) /* port partner is USB comms */ +#define PD_FLAGS_UPDATE_SRC_CAPS BIT(15) /* send new source capabilities */ +#define PD_FLAGS_TS_DTS_PARTNER BIT(16) /* partner has rp/rp or rd/rd */ /* * These PD_FLAGS_LPM* flags track the software state (PD_LPM_FLAGS_REQUESTED) * and hardware state (PD_LPM_FLAGS_ENGAGED) of the TCPC low power mode. @@ -963,26 +962,26 @@ enum pd_states { * low power (when PD_LPM_FLAGS_ENGAGED is changing). */ #ifdef CONFIG_USB_PD_TCPC_LOW_POWER -#define PD_FLAGS_LPM_REQUESTED BIT(17)/* Tracks SW LPM state */ -#define PD_FLAGS_LPM_ENGAGED BIT(18)/* Tracks HW LPM state */ -#define PD_FLAGS_LPM_TRANSITION BIT(19)/* Tracks HW LPM transition */ -#define PD_FLAGS_LPM_EXIT BIT(19)/* Tracks HW LPM exit */ +#define PD_FLAGS_LPM_REQUESTED BIT(17) /* Tracks SW LPM state */ +#define PD_FLAGS_LPM_ENGAGED BIT(18) /* Tracks HW LPM state */ +#define PD_FLAGS_LPM_TRANSITION BIT(19) /* Tracks HW LPM transition */ +#define PD_FLAGS_LPM_EXIT BIT(19) /* Tracks HW LPM exit */ #endif /* * Tracks whether port negotiation may have stalled due to not starting reset * timers in SNK_DISCOVERY */ -#define PD_FLAGS_SNK_WAITING_BATT BIT(21) +#define PD_FLAGS_SNK_WAITING_BATT BIT(21) /* Check vconn state in READY */ #define PD_FLAGS_CHECK_VCONN_STATE BIT(22) #endif /* CONFIG_USB_PD_TCPMV1 */ /* Per-port battery backed RAM flags */ #define PD_BBRMFLG_EXPLICIT_CONTRACT BIT(0) -#define PD_BBRMFLG_POWER_ROLE BIT(1) -#define PD_BBRMFLG_DATA_ROLE BIT(2) -#define PD_BBRMFLG_VCONN_ROLE BIT(3) -#define PD_BBRMFLG_DBGACC_ROLE BIT(4) +#define PD_BBRMFLG_POWER_ROLE BIT(1) +#define PD_BBRMFLG_DATA_ROLE BIT(2) +#define PD_BBRMFLG_VCONN_ROLE BIT(3) +#define PD_BBRMFLG_DBGACC_ROLE BIT(4) /* Initial value for CC debounce variable */ #define PD_CC_UNSET -1 @@ -1005,31 +1004,31 @@ enum pd_dual_role_states { * NOTE: These are usually set by host commands from the AP. */ enum pd_dpm_request { - DPM_REQUEST_DR_SWAP = BIT(0), - DPM_REQUEST_PR_SWAP = BIT(1), - DPM_REQUEST_VCONN_SWAP = BIT(2), - DPM_REQUEST_GOTO_MIN = BIT(3), - DPM_REQUEST_SRC_CAP_CHANGE = BIT(4), - DPM_REQUEST_GET_SNK_CAPS = BIT(5), - DPM_REQUEST_SEND_PING = BIT(6), - DPM_REQUEST_SOURCE_CAP = BIT(7), - DPM_REQUEST_NEW_POWER_LEVEL = BIT(8), - DPM_REQUEST_VDM = BIT(9), - DPM_REQUEST_BIST_TX = BIT(10), - DPM_REQUEST_SNK_STARTUP = BIT(11), - DPM_REQUEST_SRC_STARTUP = BIT(12), - DPM_REQUEST_HARD_RESET_SEND = BIT(13), - DPM_REQUEST_SOFT_RESET_SEND = BIT(14), - DPM_REQUEST_PORT_DISCOVERY = BIT(15), - DPM_REQUEST_SEND_ALERT = BIT(16), - DPM_REQUEST_ENTER_USB = BIT(17), - DPM_REQUEST_GET_SRC_CAPS = BIT(18), - DPM_REQUEST_EXIT_MODES = BIT(19), - DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND = BIT(20), - DPM_REQUEST_FRS_DET_ENABLE = BIT(21), - DPM_REQUEST_FRS_DET_DISABLE = BIT(22), - DPM_REQUEST_DATA_RESET = BIT(23), - DPM_REQUEST_GET_REVISION = BIT(24), + DPM_REQUEST_DR_SWAP = BIT(0), + DPM_REQUEST_PR_SWAP = BIT(1), + DPM_REQUEST_VCONN_SWAP = BIT(2), + DPM_REQUEST_GOTO_MIN = BIT(3), + DPM_REQUEST_SRC_CAP_CHANGE = BIT(4), + DPM_REQUEST_GET_SNK_CAPS = BIT(5), + DPM_REQUEST_SEND_PING = BIT(6), + DPM_REQUEST_SOURCE_CAP = BIT(7), + DPM_REQUEST_NEW_POWER_LEVEL = BIT(8), + DPM_REQUEST_VDM = BIT(9), + DPM_REQUEST_BIST_TX = BIT(10), + DPM_REQUEST_SNK_STARTUP = BIT(11), + DPM_REQUEST_SRC_STARTUP = BIT(12), + DPM_REQUEST_HARD_RESET_SEND = BIT(13), + DPM_REQUEST_SOFT_RESET_SEND = BIT(14), + DPM_REQUEST_PORT_DISCOVERY = BIT(15), + DPM_REQUEST_SEND_ALERT = BIT(16), + DPM_REQUEST_ENTER_USB = BIT(17), + DPM_REQUEST_GET_SRC_CAPS = BIT(18), + DPM_REQUEST_EXIT_MODES = BIT(19), + DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND = BIT(20), + DPM_REQUEST_FRS_DET_ENABLE = BIT(21), + DPM_REQUEST_FRS_DET_DISABLE = BIT(22), + DPM_REQUEST_DATA_RESET = BIT(23), + DPM_REQUEST_GET_REVISION = BIT(24), }; /** @@ -1140,9 +1139,9 @@ bool pd_get_partner_unconstr_power(int port); */ void pd_resume_check_pr_swap_needed(int port); -/* Control Message type */ +/* Control Message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-5 */ enum pd_ctrl_msg_type { - PD_CTRL_INVALID = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */ + PD_CTRL_INVALID = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */ PD_CTRL_GOOD_CRC = 1, PD_CTRL_GOTO_MIN = 2, PD_CTRL_ACCEPT = 3, @@ -1173,45 +1172,68 @@ enum pd_ctrl_msg_type { }; /* Control message types which always mark the start of an AMS */ -#define PD_CTRL_AMS_START_MASK ((1 << PD_CTRL_GOTO_MIN) | \ - (1 << PD_CTRL_GET_SOURCE_CAP) | \ - (1 << PD_CTRL_GET_SINK_CAP) | \ - (1 << PD_CTRL_DR_SWAP) | \ - (1 << PD_CTRL_PR_SWAP) | \ - (1 << PD_CTRL_VCONN_SWAP) | \ - (1 << PD_CTRL_GET_SOURCE_CAP_EXT) | \ - (1 << PD_CTRL_GET_STATUS) | \ - (1 << PD_CTRL_FR_SWAP) | \ - (1 << PD_CTRL_GET_PPS_STATUS) | \ - (1 << PD_CTRL_GET_COUNTRY_CODES)) - +#define PD_CTRL_AMS_START_MASK \ + ((1 << PD_CTRL_GOTO_MIN) | (1 << PD_CTRL_GET_SOURCE_CAP) | \ + (1 << PD_CTRL_GET_SINK_CAP) | (1 << PD_CTRL_DR_SWAP) | \ + (1 << PD_CTRL_PR_SWAP) | (1 << PD_CTRL_VCONN_SWAP) | \ + (1 << PD_CTRL_GET_SOURCE_CAP_EXT) | (1 << PD_CTRL_GET_STATUS) | \ + (1 << PD_CTRL_FR_SWAP) | (1 << PD_CTRL_GET_PPS_STATUS) | \ + (1 << PD_CTRL_GET_COUNTRY_CODES)) /* Battery Status Data Object fields for REV 3.0 */ #define BSDO_CAP_UNKNOWN 0xffff -#define BSDO_CAP(n) (((n) & 0xffff) << 16) -#define BSDO_INVALID BIT(8) -#define BSDO_PRESENT BIT(9) +#define BSDO_CAP(n) (((n)&0xffff) << 16) +#define BSDO_INVALID BIT(8) +#define BSDO_PRESENT BIT(9) #define BSDO_DISCHARGING BIT(10) -#define BSDO_IDLE BIT(11) +#define BSDO_IDLE BIT(11) /* Battery Capability offsets for 16-bit array indexes */ -#define BCDB_VID 0 -#define BCDB_PID 1 -#define BCDB_DESIGN_CAP 2 -#define BCDB_FULL_CAP 3 -#define BCDB_BATT_TYPE 4 +#define BCDB_VID 0 +#define BCDB_PID 1 +#define BCDB_DESIGN_CAP 2 +#define BCDB_FULL_CAP 3 +#define BCDB_BATT_TYPE 4 + +/* Battery Capability Data Block (BCDB) in struct format. + * See USB-PD spec Rev 3.1, V 1.3 section 6.5.5 + */ +struct pd_bcdb { + /* Vendor ID*/ + uint16_t vid; + /* Product ID */ + uint16_t pid; + /* Battery’s design capacity in 0.1 Wh (0 = no batt, 0xFFFF = unknown) + */ + uint16_t design_cap; + /* Battery’s last full charge capacity in 0.1 Wh (0 = no batt, + * 0xFFFF = unknown) + */ + uint16_t last_full_charge_cap; + /* Bit 0 indicates if the request was invalid. Other bits reserved. */ + uint8_t battery_type; +} __packed; + +/* Maximum number of different batteries that can be queried through Get Battery + * Status and Get Battery Capability requests. Indices 0 to 3 are fixed + * batteries and indices 4 to 7 are hot-swappable batteries. Not all are + * necessarily present. + * + * See USB-PD spec Rev 3.1, V 1.3 sections 6.5.4 - .5 + */ +#define PD_BATT_MAX (8) /* * Get Battery Cap Message fields for REV 3.0 (assumes extended header is * present in first two bytes) */ -#define BATT_CAP_REF(n) (((n) >> 16) & 0xff) +#define BATT_CAP_REF(n) (((n) >> 16) & 0xff) /* SOP SDB fields for PD Rev 3.0 Section 6.5.2.1 */ enum pd_sdb_temperature_status { - PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED = 0, - PD_SDB_TEMPERATURE_STATUS_NORMAL = 2, - PD_SDB_TEMPERATURE_STATUS_WARNING = 4, + PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED = 0, + PD_SDB_TEMPERATURE_STATUS_NORMAL = 2, + PD_SDB_TEMPERATURE_STATUS_WARNING = 4, PD_SDB_TEMPERATURE_STATUS_OVER_TEMPERATURE = 6, } __packed; BUILD_ASSERT(sizeof(enum pd_sdb_temperature_status) == 1); @@ -1245,7 +1267,7 @@ enum pd_sdb_power_indicator { PD_SDB_POWER_INDICATOR_BREATHING = (3 << 3), }; -/* Extended message type for REV 3.0 */ +/* Extended message type for REV 3.0 - USB-PD Spec 3.0, Ver 1.1, Table 6-42 */ enum pd_ext_msg_type { /* 0 Reserved */ PD_EXT_SOURCE_CAP = 1, @@ -1273,16 +1295,17 @@ enum pd_ext_msg_type { }; /* Alert Data Object fields for REV 3.1 */ -#define ADO_EXTENDED_ALERT_EVENT (BIT(24) << 7) +#define ADO_EXTENDED_ALERT_EVENT (BIT(24) << 7) +#define ADO_EXTENDED_ALERT_EVENT_TYPE 0xf /* Alert Data Object fields for REV 3.0 */ -#define ADO_OVP_EVENT (BIT(24) << 6) -#define ADO_SOURCE_INPUT_CHANGE (BIT(24) << 5) -#define ADO_OPERATING_CONDITION_CHANGE (BIT(24) << 4) -#define ADO_OTP_EVENT (BIT(24) << 3) -#define ADO_OCP_EVENT (BIT(24) << 2) -#define ADO_BATTERY_STATUS_CHANGE (BIT(24) << 1) -#define ADO_FIXED_BATTERIES(n) ((n & 0xf) << 20) -#define ADO_HOT_SWAPPABLE_BATTERIES(n) ((n & 0xf) << 16) +#define ADO_OVP_EVENT (BIT(24) << 6) +#define ADO_SOURCE_INPUT_CHANGE (BIT(24) << 5) +#define ADO_OPERATING_CONDITION_CHANGE (BIT(24) << 4) +#define ADO_OTP_EVENT (BIT(24) << 3) +#define ADO_OCP_EVENT (BIT(24) << 2) +#define ADO_BATTERY_STATUS_CHANGE (BIT(24) << 1) +#define ADO_FIXED_BATTERIES(n) ((n & 0xf) << 20) +#define ADO_HOT_SWAPPABLE_BATTERIES(n) ((n & 0xf) << 16) /* Extended alert event types for REV 3.1 */ enum ado_extended_alert_event_type { @@ -1292,7 +1315,7 @@ enum ado_extended_alert_event_type { ADO_CONTROLLER_INITIATED_WAKE = 0x4, }; -/* Data message type */ +/* Data message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-6 */ enum pd_data_msg_type { /* 0 Reserved */ PD_DATA_SOURCE_CAP = 1, @@ -1314,15 +1337,11 @@ enum pd_data_msg_type { /* 16-31 Reserved */ }; - /* * Cable plug. See 6.2.1.1.7 Cable Plug. Only applies to SOP' and SOP". * Replaced by pd_power_role for SOP packets. */ -enum pd_cable_plug { - PD_PLUG_FROM_DFP_UFP = 0, - PD_PLUG_FROM_CABLE = 1 -}; +enum pd_cable_plug { PD_PLUG_FROM_DFP_UFP = 0, PD_PLUG_FROM_CABLE = 1 }; enum cable_outlet { CABLE_PLUG = 0, @@ -1331,11 +1350,11 @@ enum cable_outlet { /* Vconn role */ #define PD_ROLE_VCONN_OFF 0 -#define PD_ROLE_VCONN_ON 1 +#define PD_ROLE_VCONN_ON 1 /* chunk is a request or response in REV 3.0 */ #define CHUNK_RESPONSE 0 -#define CHUNK_REQUEST 1 +#define CHUNK_REQUEST 1 /* collision avoidance Rp values in REV 3.0 */ #define SINK_TX_OK TYPEC_RP_3A0 @@ -1352,36 +1371,37 @@ enum cable_outlet { /* Port default state at startup */ #ifdef CONFIG_USB_PD_DUAL_ROLE -#define PD_DEFAULT_STATE(port) ((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \ - PD_STATE_SRC_DISCONNECTED : \ - PD_STATE_SNK_DISCONNECTED) +#define PD_DEFAULT_STATE(port) \ + ((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \ + PD_STATE_SRC_DISCONNECTED : \ + PD_STATE_SNK_DISCONNECTED) #else #define PD_DEFAULT_STATE(port) PD_STATE_SRC_DISCONNECTED #endif -/* build extended message header */ -/* All extended messages are chunked, so set bit 15 */ +/* Build extended message header with chunking */ #define PD_EXT_HEADER(cnum, rchk, dsize) \ - (BIT(15) | ((cnum) << 11) | \ - ((rchk) << 10) | (dsize)) + (BIT(15) | ((cnum) << 11) | ((rchk) << 10) | (dsize)) + +/* Build extended message header without chunking */ +#define PD_EXT_HEADER_UNCHUNKED(dsize) (dsize) /* build message header */ -#define PD_HEADER(type, prole, drole, id, cnt, rev, ext) \ - ((type) | ((rev) << 6) | \ - ((drole) << 5) | ((prole) << 8) | \ - ((id) << 9) | ((cnt) << 12) | ((ext) << 15)) +#define PD_HEADER(type, prole, drole, id, cnt, rev, ext) \ + ((type) | ((rev) << 6) | ((drole) << 5) | ((prole) << 8) | \ + ((id) << 9) | ((cnt) << 12) | ((ext) << 15)) /* Used for processing pd header */ -#define PD_HEADER_EXT(header) (((header) >> 15) & 1) -#define PD_HEADER_CNT(header) (((header) >> 12) & 7) +#define PD_HEADER_EXT(header) (((header) >> 15) & 1) +#define PD_HEADER_CNT(header) (((header) >> 12) & 7) /* * NOTE: bit 4 was added in PD 3.0, and should be reserved and set to 0 in PD * 2.0 messages */ -#define PD_HEADER_TYPE(header) ((header) & 0x1F) -#define PD_HEADER_ID(header) (((header) >> 9) & 7) +#define PD_HEADER_TYPE(header) ((header)&0x1F) +#define PD_HEADER_ID(header) (((header) >> 9) & 7) #define PD_HEADER_PROLE(header) (((header) >> 8) & 1) -#define PD_HEADER_REV(header) (((header) >> 6) & 3) +#define PD_HEADER_REV(header) (((header) >> 6) & 3) #define PD_HEADER_DROLE(header) (((header) >> 5) & 1) /* @@ -1390,47 +1410,47 @@ enum cable_outlet { * NOTE: This is not part of the PD spec. */ #define PD_HEADER_GET_SOP(header) (((header) >> 28) & 0xf) -#define PD_HEADER_SOP(sop) (((sop) & 0xf) << 28) +#define PD_HEADER_SOP(sop) (((sop)&0xf) << 28) /* Used for processing pd extended header */ -#define PD_EXT_HEADER_CHUNKED(header) (((header) >> 15) & 1) +#define PD_EXT_HEADER_CHUNKED(header) (((header) >> 15) & 1) #define PD_EXT_HEADER_CHUNK_NUM(header) (((header) >> 11) & 0xf) #define PD_EXT_HEADER_REQ_CHUNK(header) (((header) >> 10) & 1) -#define PD_EXT_HEADER_DATA_SIZE(header) ((header) & 0x1ff) +#define PD_EXT_HEADER_DATA_SIZE(header) ((header)&0x1ff) /* Used to get extended header from the first 32-bit word of the message */ #define GET_EXT_HEADER(msg) (msg & 0xffff) /* Extended message constants (PD 3.0, Rev. 2.0, section 6.13) */ -#define PD_MAX_EXTENDED_MSG_LEN 260 -#define PD_MAX_EXTENDED_MSG_CHUNK_LEN 26 +#define PD_MAX_EXTENDED_MSG_LEN 260 +#define PD_MAX_EXTENDED_MSG_CHUNK_LEN 26 /* K-codes for special symbols */ #define PD_SYNC1 0x18 #define PD_SYNC2 0x11 #define PD_SYNC3 0x06 -#define PD_RST1 0x07 -#define PD_RST2 0x19 -#define PD_EOP 0x0D +#define PD_RST1 0x07 +#define PD_RST2 0x19 +#define PD_EOP 0x0D /* Minimum PD supply current (mA) */ -#define PD_MIN_MA 500 +#define PD_MIN_MA 500 /* Minimum PD voltage (mV) */ -#define PD_MIN_MV 5000 +#define PD_MIN_MV 5000 /* No connect voltage threshold for sources based on Rp */ -#define PD_SRC_DEF_VNC_MV 1600 -#define PD_SRC_1_5_VNC_MV 1600 -#define PD_SRC_3_0_VNC_MV 2600 +#define PD_SRC_DEF_VNC_MV 1600 +#define PD_SRC_1_5_VNC_MV 1600 +#define PD_SRC_3_0_VNC_MV 2600 /* Rd voltage threshold for sources based on Rp */ -#define PD_SRC_DEF_RD_THRESH_MV 200 -#define PD_SRC_1_5_RD_THRESH_MV 400 -#define PD_SRC_3_0_RD_THRESH_MV 800 +#define PD_SRC_DEF_RD_THRESH_MV 200 +#define PD_SRC_1_5_RD_THRESH_MV 400 +#define PD_SRC_3_0_RD_THRESH_MV 800 /* Voltage threshold to detect connection when presenting Rd */ -#define PD_SNK_VA_MV 250 +#define PD_SNK_VA_MV 250 /* --- Policy layer functions --- */ @@ -1523,7 +1543,7 @@ void pd_process_source_cap(int port, int cnt, uint32_t *src_caps); * @param ma reduce current to minimum value. * @param mv reduce voltage to minimum value. */ -void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv); +void pd_snk_give_back(int port, uint32_t *const ma, uint32_t *const mv); /** * Put a cap on the max voltage requested as a sink. @@ -1631,7 +1651,6 @@ void pd_set_external_voltage_limit(int port, int mv); void pd_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage); - /** * Update the power contract if it exists. * @@ -1703,8 +1722,7 @@ __override_proto bool pd_can_charge_from_device(int port, const int pdo_cnt, * @param data_role current data role * @return True if data swap is allowed, False otherwise */ -__override_proto int pd_check_data_swap(int port, - enum pd_data_role data_role); +__override_proto int pd_check_data_swap(int port, enum pd_data_role data_role); /** * Check if vconn swap is allowed. @@ -1722,9 +1740,8 @@ int pd_check_vconn_swap(int port); * @param pr_role Our power role * @param flags PD flags */ -__override_proto void pd_check_pr_role(int port, - enum pd_power_role pr_role, - int flags); +__override_proto void pd_check_pr_role(int port, enum pd_power_role pr_role, + int flags); /** * Check current data role for potential data swap @@ -1733,9 +1750,8 @@ __override_proto void pd_check_pr_role(int port, * @param dr_role Our data role * @param flags PD flags */ -__override_proto void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags); +__override_proto void pd_check_dr_role(int port, enum pd_data_role dr_role, + int flags); /** * Check for a potential Vconn swap if the port isn't @@ -1753,7 +1769,7 @@ __override_proto void pd_try_execute_vconn_swap(int port, int flags); * @param data_role new data role */ __override_proto void pd_execute_data_swap(int port, - enum pd_data_role data_role); + enum pd_data_role data_role); /** * Get desired dual role state when chipset is suspended. @@ -1802,7 +1818,7 @@ __override_proto int pd_custom_vdm(int port, int cnt, uint32_t *payload, * @return if >0, number of VDOs to send back. */ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload, - uint32_t head, enum tcpci_msg_type *rtype); + uint32_t head, enum tcpci_msg_type *rtype); /** * Handle Custom VDMs for flashing. @@ -1823,8 +1839,8 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload); * @param opos object position of mode to exit. * @return vdm for UFP to be sent to enter mode or zero if not. */ -uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, - uint16_t svid, int opos); +uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, uint16_t svid, + int opos); /** * Save the Enter mode command data received from the port partner for setting @@ -1862,7 +1878,7 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status); * @return 1 if UFP should be sent exit mode VDM. */ int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid, - int opos); + int opos); /** * Consume the SVDM attention data @@ -1881,7 +1897,7 @@ void dfp_consume_attention(int port, uint32_t *payload); * @param payload payload data. */ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload); + uint32_t *payload); /** * Consume the SVIDs @@ -1892,7 +1908,7 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, * @param payload payload data. */ void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload); + uint32_t *payload); /** * Consume the alternate modes @@ -1903,7 +1919,7 @@ void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt, * @param payload payload data. */ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload); + uint32_t *payload); /** * Returns true if connected VPD supports Charge Through @@ -1914,68 +1930,6 @@ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt, bool is_vpd_ct_supported(int port); /** - * Returns CTVPD ground impedance - * - * @param port USB-C port number - * @return Ground impedance through the VPD in 1 mOhm increments, else - * 0 if Charge Through isn't supported - */ -uint8_t get_vpd_ct_gnd_impedance(int port); - -/** - * Returns CTVPD VBUS impedance - * - * @param port USB-C port number - * @return VBUS impedance through the VPD in 2 mOhm increments, else - * 0 if Charge Through isn't supported - */ -uint8_t get_vpd_ct_vbus_impedance(int port); - -/** - * Returns CTVPD Current support - * - * @param port USB-C port number - * @return 0 - 3A capable or - * 1 - 5A capable - */ -uint8_t get_vpd_ct_current_support(int port); - -/** - * Returns CTVPD Maximum VBUS Voltage - * - * @param port USB-C port number - * @return 0 - 20V - * 1 - 30V - * 2 - 40V - * 3 - 50V - */ -uint8_t get_vpd_ct_max_vbus_voltage(int port); - -/** - * Returns VPD VDO Version - * - * @param port USB-C port number - * @return 0 for Version 1.0 - */ -uint8_t get_vpd_ct_vdo_version(int port); - -/** - * Returns VPD Firmware Version - * - * @param port USB-C port number - * @return Firmware version assigned by the VID owner - */ -uint8_t get_vpd_ct_firmware_verion(int port); - -/** - * Returns HW Firmware Version - * - * @param port USB-C port number - * @return HW version assigned by the VID owner - */ -uint8_t get_vpd_ct_hw_version(int port); - -/** * Initialize alternate mode discovery info for DFP * * @param port USB-C port number @@ -2007,7 +1961,7 @@ void pd_set_identity_discovery(int port, enum tcpci_msg_type type, * @return Current discovery state (failed or complete) */ enum pd_discovery_state pd_get_identity_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Set SVID discovery state for this type and port. @@ -2017,7 +1971,7 @@ enum pd_discovery_state pd_get_identity_discovery(int port, * @param disc Discovery state to set (failed or complete) */ void pd_set_svids_discovery(int port, enum tcpci_msg_type type, - enum pd_discovery_state disc); + enum pd_discovery_state disc); /** * Get SVID discovery state for this type and port @@ -2027,7 +1981,7 @@ void pd_set_svids_discovery(int port, enum tcpci_msg_type type, * @return Current discovery state (failed or complete) */ enum pd_discovery_state pd_get_svids_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Set Modes discovery state for this port, SOP* type, and SVID. @@ -2037,8 +1991,8 @@ enum pd_discovery_state pd_get_svids_discovery(int port, * @param svid SVID to set mode discovery state for * @param disc Discovery state to set (failed or complete) */ -void pd_set_modes_discovery(int port, enum tcpci_msg_type type, - uint16_t svid, enum pd_discovery_state disc); +void pd_set_modes_discovery(int port, enum tcpci_msg_type type, uint16_t svid, + enum pd_discovery_state disc); /** * Get Modes discovery state for this port and SOP* type. Modes discover is @@ -2054,7 +2008,7 @@ void pd_set_modes_discovery(int port, enum tcpci_msg_type type, * PD_DISC_FAIL) */ enum pd_discovery_state pd_get_modes_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Returns the mode vdo count of the specified SVID and sets @@ -2068,8 +2022,8 @@ enum pd_discovery_state pd_get_modes_discovery(int port, * @return Mode VDO cnt of specified SVID if is discovered, * 0 otherwise */ -int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, - uint16_t svid, uint32_t *vdo_out); +int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, uint16_t svid, + uint32_t *vdo_out); /** * Get a pointer to mode data for the next SVID that needs to be discovered. @@ -2085,7 +2039,7 @@ int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, * NULL, otherwise */ const struct svid_mode_data *pd_get_next_mode(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Return a pointer to the discover identity response structure for this SOP* @@ -2096,7 +2050,7 @@ const struct svid_mode_data *pd_get_next_mode(int port, * @return pointer to response structure, which the caller may not alter */ const union disc_ident_ack *pd_get_identity_response(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Return the VID of the USB PD accessory connected to a specified port @@ -2152,7 +2106,7 @@ uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type); * @return Pointer to modes of VDO */ const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /* * Looks for a discovered mode VDO for the specified SVID. @@ -2163,7 +2117,7 @@ const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx, * @return Whether a mode was discovered for the SVID */ bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type, - uint16_t svid); + uint16_t svid); /** * Return the alternate mode entry and exit data @@ -2173,8 +2127,8 @@ bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type, * @param svid SVID * @return pointer to SVDM mode data */ -struct svdm_amode_data *pd_get_amode_data(int port, - enum tcpci_msg_type type, uint16_t svid); +struct svdm_amode_data *pd_get_amode_data(int port, enum tcpci_msg_type type, + uint16_t svid); /* * Returns cable revision @@ -2242,8 +2196,8 @@ bool pd_discovery_access_validate(int port, enum tcpci_msg_type type); * @param type Transmit type (SOP, SOP') for discovered information * @return pointer to PD alternate mode discovery results */ -struct pd_discovery *pd_get_am_discovery_and_notify_access(int port, - enum tcpci_msg_type type); +struct pd_discovery * +pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type); /* * Returns the constant pointer to PD alternate mode discovery results @@ -2254,7 +2208,7 @@ struct pd_discovery *pd_get_am_discovery_and_notify_access(int port, * @return pointer to PD alternate mode discovery results */ const struct pd_discovery *pd_get_am_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /* * Returns the pointer to PD active alternate modes. @@ -2264,8 +2218,8 @@ const struct pd_discovery *pd_get_am_discovery(int port, * @param type Transmit type (SOP, SOP', SOP'') for active modes * @return Pointer to PD active alternate modes. */ -struct partner_active_modes *pd_get_partner_active_modes(int port, - enum tcpci_msg_type type); +struct partner_active_modes * +pd_get_partner_active_modes(int port, enum tcpci_msg_type type); /* * Sets the current object position for DP alt-mode @@ -2440,8 +2394,7 @@ enum tbt_compat_cable_speed get_tbt_cable_speed(int port); * @param payload payload data * @return Number of object filled */ -int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, - uint32_t *payload); +int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, uint32_t *payload); /** * Return maximum speed supported by the port to enter into Thunderbolt mode @@ -2476,8 +2429,7 @@ __override_proto enum tbt_compat_cable_speed board_get_max_tbt_speed(int port); * EC_RES_UNAVAILABLE if board does not support this feature */ __override_proto enum ec_status - board_set_tbt_ufp_reply(int port, - enum typec_tbt_ufp_reply reply); +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply); /** * Return true if the board's port supports TBT or USB4 @@ -2584,8 +2536,8 @@ void pd_dpm_request(int port, enum pd_dpm_request req); * must be 1 - 7 inclusive. * @return True if the setup was successful */ -bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, - uint32_t *vdm, uint32_t vdo_cnt); +bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, uint32_t *vdm, + uint32_t vdo_cnt); /* Power Data Objects for the source and the sink */ __override_proto extern const uint32_t pd_src_pdo[]; @@ -2596,6 +2548,15 @@ extern const uint32_t pd_snk_pdo[]; extern const int pd_snk_pdo_cnt; /** + * TEST ONLY: Set PD_CONTROL command to enabled on this port + * + * @param port USB-C port number + */ +#ifdef TEST_BUILD +void pd_control_port_enable(int port); +#endif + +/** * Request that a host event be sent to notify the AP of a PD power event. * * Note: per-port events should be retrieved through pd_get_events(), but this @@ -2607,7 +2568,9 @@ extern const int pd_snk_pdo_cnt; #if defined(HAS_TASK_HOSTCMD) && !defined(TEST_BUILD) void pd_send_host_event(int mask); #else -static inline void pd_send_host_event(int mask) { } +static inline void pd_send_host_event(int mask) +{ +} #endif /** @@ -2682,7 +2645,6 @@ int pd_write_preamble(int port); */ int pd_write_sym(int port, int bit_off, uint32_t val10); - /** * Ensure that we have an edge after EOP and we end up at level 0, * also fill the last byte. @@ -2943,7 +2905,7 @@ void pd_clear_events(int port, uint32_t clear_mask); * @return EC_RES_SUCCESS if a VDM message is scheduled. */ enum ec_status pd_request_vdm_attention(int port, const uint32_t *data, - int vdo_count); + int vdo_count); /* * Requests that the port enter the specified mode. A successful result just @@ -3058,7 +3020,7 @@ bool pd_waiting_on_partner_src_caps(int port); * * @param port USB-C port number */ -const uint32_t * const pd_get_src_caps(int port); +const uint32_t *const pd_get_src_caps(int port); /** * Returns the number of source caps @@ -3082,7 +3044,7 @@ void pd_set_src_caps(int port, int cnt, uint32_t *src_caps); * * @param port USB-C port number */ -const uint32_t * const pd_get_snk_caps(int port); +const uint32_t *const pd_get_snk_caps(int port); /** * Returns the number of sink caps @@ -3231,8 +3193,8 @@ __override_proto void pd_notify_dp_alt_mode_entry(int port); * Determines the PD state of the port partner according to Table 4-10 in USB PD * specification. */ -enum pd_cc_states pd_get_cc_state( - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2); +enum pd_cc_states pd_get_cc_state(enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2); /* * Optional, get the board-specific SRC DTS polarity. @@ -3255,8 +3217,8 @@ __override_proto uint8_t board_get_src_dts_polarity(int port); * @param data type-defined information * @param payload pointer to the optional payload (0..16 bytes) */ -void pd_log_event(uint8_t type, uint8_t size_port, - uint16_t data, void *payload); +void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data, + void *payload); /** * Retrieve one logged event and prepare a VDM with it. @@ -3267,10 +3229,15 @@ void pd_log_event(uint8_t type, uint8_t size_port, * @return number of 32-bit words in the VDM payload. */ int pd_vdm_get_log_entry(uint32_t *payload); -#else /* CONFIG_USB_PD_LOGGING */ -static inline void pd_log_event(uint8_t type, uint8_t size_port, - uint16_t data, void *payload) {} -static inline int pd_vdm_get_log_entry(uint32_t *payload) { return 0; } +#else /* CONFIG_USB_PD_LOGGING */ +static inline void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data, + void *payload) +{ +} +static inline int pd_vdm_get_log_entry(uint32_t *payload) +{ + return 0; +} #endif /* CONFIG_USB_PD_LOGGING */ /** @@ -3527,9 +3494,9 @@ int typec_update_cc(int port); * @param pd_sdb_power_state enum defining the New Power State field of the SDB * @return pd_sdb_power_indicator enum for the SDB */ -__override_proto enum pd_sdb_power_indicator board_get_pd_sdb_power_indicator( -enum pd_sdb_power_state power_state); +__override_proto enum pd_sdb_power_indicator +board_get_pd_sdb_power_indicator(enum pd_sdb_power_state power_state); /****************************************************************************/ -#endif /* __CROS_EC_USB_PD_H */ +#endif /* __CROS_EC_USB_PD_H */ diff --git a/include/usb_pd_dp_ufp.h b/include/usb_pd_dp_ufp.h index 64728d948e..663f4f1d83 100644 --- a/include/usb_pd_dp_ufp.h +++ b/include/usb_pd_dp_ufp.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -32,4 +32,4 @@ void usb_pd_hpd_edge_event(int signal); */ void usb_pd_hpd_converter_enable(int enable); -#endif /* __CROS_EC_USB_PD_DP_UFP_H */ +#endif /* __CROS_EC_USB_PD_DP_UFP_H */ diff --git a/include/usb_pd_dpm.h b/include/usb_pd_dpm.h index 391e7ed246..083ef216b6 100644 --- a/include/usb_pd_dpm.h +++ b/include/usb_pd_dpm.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -51,7 +51,7 @@ void dpm_data_reset_complete(int port); * @param vdm The VDM payload of the ACK */ void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm); + uint32_t *vdm); /* * Informs the DPM that a VDM NAK was received. Also applies when a VDM request @@ -63,7 +63,7 @@ void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, * @param vdm_cmd The VDM command of the request */ void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid, - uint8_t vdm_cmd); + uint8_t vdm_cmd); /* * Drives the Policy Engine through entry/exit mode process @@ -131,6 +131,20 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port); int dpm_get_source_current(const int port); /* + * Report we've been asked to enter BIST Shared Test Mode + * + * @param port USB-C port number + */ +void dpm_bist_shared_mode_enter(int port); + +/* + * Report we've been asked to exit BIST Shared Test Mode + * + * @param port USB-C port number + */ +void dpm_bist_shared_mode_exit(int port); + +/* * Build SOP Status Data Block (SDB) * * @param port USB-C port number @@ -139,6 +153,14 @@ int dpm_get_source_current(const int port); */ int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len); +/* + * DPM function to handle a received alert message + * + * @param port USB-C port number + * @param ado Alert Data Object (ado) received from partner + */ +void dpm_handle_alert(int port, uint32_t ado); + /* Enum for modules to describe to the DPM their setup status */ enum dpm_msg_setup_status { MSG_SETUP_SUCCESS, @@ -147,4 +169,9 @@ enum dpm_msg_setup_status { MSG_SETUP_MUX_WAIT, }; -#endif /* __CROS_EC_USB_DPM_H */ +/* Enum to describe current state of connected USB PD buttons */ +enum dpm_pd_button_state { + DPM_PD_BUTTON_IDLE, + DPM_PD_BUTTON_PRESSED, +}; +#endif /* __CROS_EC_USB_DPM_H */ diff --git a/include/usb_pd_flags.h b/include/usb_pd_flags.h index 8e029bcb35..70e80379a6 100644 --- a/include/usb_pd_flags.h +++ b/include/usb_pd_flags.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/usb_pd_pdo.h b/include/usb_pd_pdo.h index 4219c05183..9e75555b63 100644 --- a/include/usb_pd_pdo.h +++ b/include/usb_pd_pdo.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/usb_pd_policy.h b/include/usb_pd_policy.h index 04a7a68e7d..a5675ded4e 100644 --- a/include/usb_pd_policy.h +++ b/include/usb_pd_policy.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,8 +21,9 @@ * @param dr_swap_flag Data Role Swap Flag bit * @param return True if state machine should perform a DR swap, elsf False */ -__override_proto bool port_discovery_dr_swap_policy(int port, - enum pd_data_role dr, bool dr_swap_flag); +__override_proto bool port_discovery_dr_swap_policy(int port, + enum pd_data_role dr, + bool dr_swap_flag); /** * Port Discovery VCONN Swap Policy @@ -35,6 +36,6 @@ __override_proto bool port_discovery_dr_swap_policy(int port, * @param return True if state machine should perform a VCONN swap, elsf False */ __override_proto bool port_discovery_vconn_swap_policy(int port, - bool vconn_swap_flag); + bool vconn_swap_flag); #endif /* __CROS_EC_USB_PD_POLICY_H */ diff --git a/include/usb_pd_tbt.h b/include/usb_pd_tbt.h index e052052813..315fccb619 100644 --- a/include/usb_pd_tbt.h +++ b/include/usb_pd_tbt.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -106,7 +106,7 @@ enum vendor_specific_support { /* TBT Alternate Mode */ #define TBT_ALTERNATE_MODE 0x0001 -#define PD_VDO_RESP_MODE_INTEL_TBT(x) (((x) & 0xff) == TBT_ALTERNATE_MODE) +#define PD_VDO_RESP_MODE_INTEL_TBT(x) (((x)&0xff) == TBT_ALTERNATE_MODE) union tbt_mode_resp_device { struct { diff --git a/include/usb_pd_tcpc.h b/include/usb_pd_tcpc.h index 0a10f97e0e..a89030cdb7 100644 --- a/include/usb_pd_tcpc.h +++ b/include/usb_pd_tcpc.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,11 +18,11 @@ #ifdef TCPCI_I2C_PERIPHERAL /* Convert TCPC address to type-C port number */ -#define TCPC_ADDR_TO_PORT(addr) ((addr) \ - - I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) +#define TCPC_ADDR_TO_PORT(addr) \ + ((addr)-I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) /* Check if the i2c address belongs to TCPC */ -#define ADDR_IS_TCPC(addr) (((addr) & 0x7E) \ - == I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) +#define ADDR_IS_TCPC(addr) \ + (((addr)&0x7E) == I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) #endif /** @@ -52,7 +52,7 @@ int tcpc_alert_status(int port, int *alert); int tcpc_alert_status_clear(int port, uint16_t mask); int tcpc_alert_mask_set(int port, uint16_t mask); int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); int tcpc_select_rp_value(int port, int rp); int tcpc_set_cc(int port, int pull); int tcpc_set_polarity(int port, int polarity); diff --git a/include/usb_pd_tcpm.h b/include/usb_pd_tcpm.h index e34329eb18..9a78754a0d 100644 --- a/include/usb_pd_tcpm.h +++ b/include/usb_pd_tcpm.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,7 +15,7 @@ #include "i2c.h" /* Time to wait for TCPC to complete transmit */ -#define PD_T_TCPC_TX_TIMEOUT (100*MSEC) +#define PD_T_TCPC_TX_TIMEOUT (100 * MSEC) enum usbpd_cc_pin { USBPD_CC_PIN_1, @@ -25,8 +25,8 @@ enum usbpd_cc_pin { /* Detected resistor values of port partner */ enum tcpc_cc_voltage_status { TYPEC_CC_VOLT_OPEN = 0, - TYPEC_CC_VOLT_RA = 1, /* Port partner is applying Ra */ - TYPEC_CC_VOLT_RD = 2, /* Port partner is applying Rd */ + TYPEC_CC_VOLT_RA = 1, /* Port partner is applying Ra */ + TYPEC_CC_VOLT_RD = 2, /* Port partner is applying Rd */ TYPEC_CC_VOLT_RP_DEF = 5, /* Port partner is applying Rp (0.5A) */ TYPEC_CC_VOLT_RP_1_5 = 6, /* Port partner is applying Rp (1.5A) */ TYPEC_CC_VOLT_RP_3_0 = 7, /* Port partner is applying Rp (3.0A) */ @@ -42,7 +42,7 @@ enum tcpc_cc_pull { }; /* Pull-up values we apply as a SRC to advertise different current limits */ -FORWARD_DECLARE_ENUM(tcpc_rp_value) { +FORWARD_DECLARE_ENUM(tcpc_rp_value){ TYPEC_RP_USB = 0, TYPEC_RP_1A5 = 1, TYPEC_RP_3A0 = 2, @@ -58,8 +58,8 @@ enum tcpc_drp { /** * Returns whether the polarity without the DTS extension */ -static inline enum tcpc_cc_polarity polarity_rm_dts( - enum tcpc_cc_polarity polarity) +static inline enum tcpc_cc_polarity +polarity_rm_dts(enum tcpc_cc_polarity polarity) { BUILD_ASSERT(POLARITY_COUNT == 4); return (enum tcpc_cc_polarity)(polarity & BIT(0)); @@ -91,9 +91,9 @@ enum tcpci_msg_type { enum tcpc_transmit_complete { TCPC_TX_UNSET = -1, TCPC_TX_WAIT = 0, - TCPC_TX_COMPLETE_SUCCESS = 1, + TCPC_TX_COMPLETE_SUCCESS = 1, TCPC_TX_COMPLETE_DISCARDED = 2, - TCPC_TX_COMPLETE_FAILED = 3, + TCPC_TX_COMPLETE_FAILED = 3, }; /* @@ -102,9 +102,9 @@ enum tcpc_transmit_complete { * Return true on Vbus check if Vbus is... */ enum vbus_level { - VBUS_SAFE0V, /* less than vSafe0V max */ - VBUS_PRESENT, /* at least vSafe5V min */ - VBUS_REMOVED, /* less than vSinkDisconnect max */ + VBUS_SAFE0V, /* less than vSafe0V max */ + VBUS_PRESENT, /* at least vSafe5V min */ + VBUS_REMOVED, /* less than vSinkDisconnect max */ }; /** @@ -120,7 +120,7 @@ static inline int cc_is_rp(enum tcpc_cc_voltage_status cc) * Returns true if both CC lines are completely open. */ static inline int cc_is_open(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_OPEN; } @@ -129,7 +129,7 @@ static inline int cc_is_open(enum tcpc_cc_voltage_status cc1, * Returns true if we detect the port partner is a snk debug accessory. */ static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD; } @@ -138,7 +138,7 @@ static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1, * Returns true if we detect the port partner is a src debug accessory. */ static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc_is_rp(cc1) && cc_is_rp(cc2); } @@ -147,7 +147,7 @@ static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1, * Returns true if the port partner is an audio accessory. */ static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA; } @@ -156,7 +156,7 @@ static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1, * Returns true if the port partner is presenting at least one Rd */ static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD; } @@ -165,7 +165,7 @@ static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1, * Returns true if the port partner is presenting Rd on only one CC line. */ static inline int cc_is_only_one_rd(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc_is_at_least_one_rd(cc1, cc2) && cc1 != cc2; } @@ -200,7 +200,7 @@ struct tcpm_drv { * @return EC_SUCCESS or error */ int (*get_cc)(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); /** * Check VBUS level @@ -233,7 +233,8 @@ struct tcpm_drv { int (*select_rp_value)(int port, int rp); /** - * Set the CC pull resistor. This sets our role as either source or sink. + * Set the CC pull resistor. This sets our role as either source or + * sink. * * @param port Type-C port number * @param pull One of enum tcpc_cc_pull @@ -321,7 +322,7 @@ struct tcpm_drv { * @return EC_SUCCESS or error */ int (*transmit)(int port, enum tcpci_msg_type type, uint16_t header, - const uint32_t *data); + const uint32_t *data); /** * TCPC is asserting alert @@ -344,8 +345,7 @@ struct tcpm_drv { * @param port Type-C port number * @param enable Auto Discharge enable or disable */ - void (*tcpc_enable_auto_discharge_disconnect)(int port, - int enable); + void (*tcpc_enable_auto_discharge_disconnect)(int port, int enable); /** * Manual control of TCPC DebugAccessory enable @@ -384,7 +384,7 @@ struct tcpm_drv { * @return EC_SUCCESS or error */ int (*get_chip_info)(int port, int live, - struct ec_response_pd_chip_info_v1 *info); + struct ec_response_pd_chip_info_v1 *info); /** * Request current sinking state of the TCPC @@ -478,7 +478,7 @@ struct tcpm_drv { * * @return EC_SUCCESS or error */ - int (*set_frs_enable)(int port, int enable); + int (*set_frs_enable)(int port, int enable); #endif /** @@ -489,7 +489,20 @@ struct tcpm_drv { * * @return EC_SUCCESS or error */ - int (*handle_fault)(int port, int fault); + int (*handle_fault)(int port, int fault); + + /** + * Re-initialize registers during hard reset + * + * NOTE: If the function alters the alert mask and power status mask, + * this indicates the chip does not require a full TCPCI re-init after + * a hard reset. + * + * @param port Type-C port number + * + * @return EC_SUCCESS or error + */ + int (*hard_reset_reinit)(int port); /** * Controls BIST Test Mode (or analogous functionality) in the TCPC and @@ -500,15 +513,25 @@ struct tcpm_drv { * @param enable true to enter BIST Test Mode; false to exit * @return EC_SUCCESS or error code */ - enum ec_error_list (*set_bist_test_mode)(int port, bool enable); + enum ec_error_list (*set_bist_test_mode)(int port, bool enable); + /** + * Get control of BIST Test Mode (or analogous functionality) in the + * TCPC. + * + * @param port USB-C port number + * @param enable true for BIST Test Mode enabled; false for error + * occurred or BIST Test Mode disabled. + * @return EC_SUCCESS or error code + */ + enum ec_error_list (*get_bist_test_mode)(int port, bool *enable); #ifdef CONFIG_CMD_TCPC_DUMP /** * Dump TCPC registers * * @param port Type-C port number */ - void (*dump_registers)(int port); + void (*dump_registers)(int port); #endif /* defined(CONFIG_CMD_TCPC_DUMP) */ int (*reset_bist_type_2)(int port); @@ -534,20 +557,20 @@ struct tcpm_drv { * Bit 7 --> TCPC controls FRS (even when CONFIG_USB_PD_FRS_TCPC is off) * Bit 8 --> TCPC enable VBUS monitoring */ -#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0) -#define TCPC_FLAGS_ALERT_OD BIT(1) -#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2) -#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3) -#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4) -#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5) -#define TCPC_FLAGS_CONTROL_VCONN BIT(6) -#define TCPC_FLAGS_CONTROL_FRS BIT(7) -#define TCPC_FLAGS_VBUS_MONITOR BIT(8) +#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0) +#define TCPC_FLAGS_ALERT_OD BIT(1) +#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2) +#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3) +#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4) +#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5) +#define TCPC_FLAGS_CONTROL_VCONN BIT(6) +#define TCPC_FLAGS_CONTROL_FRS BIT(7) +#define TCPC_FLAGS_VBUS_MONITOR BIT(8) #endif /* !CONFIG_ZEPHYR */ struct tcpc_config_t { - enum ec_bus_type bus_type; /* enum ec_bus_type */ + enum ec_bus_type bus_type; /* enum ec_bus_type */ union { struct i2c_info_t i2c_info; }; @@ -632,9 +655,9 @@ int tcpc_get_vbus_voltage(int port); #ifdef CONFIG_CMD_TCPC_DUMP struct tcpc_reg_dump_map { - uint8_t addr; - uint8_t size; - const char *name; + uint8_t addr; + uint8_t size; + const char *name; }; /** @@ -654,6 +677,6 @@ void tcpc_dump_std_registers(int port); * */ void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg, - int count); + int count); #endif #endif /* __CROS_EC_USB_PD_TCPM_H */ diff --git a/include/usb_pd_timer.h b/include/usb_pd_timer.h index 3a3f388b22..439b30513d 100644 --- a/include/usb_pd_timer.h +++ b/include/usb_pd_timer.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,6 +18,18 @@ */ enum pd_task_timer { /* + * Timer to check if a USB PD power button press exceeds the long press + * time limit. + */ + DPM_TIMER_PD_BUTTON_LONG_PRESS, + + /* + * Timer to check if a USB PD power button press exceeds the short press + * time limit. + */ + DPM_TIMER_PD_BUTTON_SHORT_PRESS, + + /* * In BIST_TX mode, this timer is used by a UUT to ensure that a * Continuous BIST Mode (i.e. BIST Carrier Mode) is exited in a timely * fashion. @@ -167,7 +179,6 @@ enum pd_task_timer { */ PE_TIMER_WAIT_AND_ADD_JITTER, - /* Chunk Sender Response timer */ PR_TIMER_CHUNK_SENDER_RESPONSE, @@ -183,7 +194,6 @@ enum pd_task_timer { /* timeout to limit waiting on TCPC response (not in spec) */ PR_TIMER_TCPC_TX_TIMEOUT, - /* Time a port shall wait before it can determine it is attached */ TC_TIMER_CC_DEBOUNCE, @@ -222,18 +232,22 @@ enum pd_task_timer { }; enum pd_timer_range { + DPM_TIMER_RANGE, PE_TIMER_RANGE, PR_TIMER_RANGE, TC_TIMER_RANGE, }; -#define PE_TIMER_START PE_TIMER_BIST_CONT_MODE -#define PE_TIMER_END PE_TIMER_WAIT_AND_ADD_JITTER +#define DPM_TIMER_START DPM_TIMER_PD_BUTTON_LONG_PRESS +#define DPM_TIMER_END DPM_TIMER_PD_BUTTON_SHORT_PRESS -#define PR_TIMER_START PR_TIMER_CHUNK_SENDER_RESPONSE -#define PR_TIMER_END PR_TIMER_TCPC_TX_TIMEOUT +#define PE_TIMER_START PE_TIMER_BIST_CONT_MODE +#define PE_TIMER_END PE_TIMER_WAIT_AND_ADD_JITTER -#define TC_TIMER_START TC_TIMER_CC_DEBOUNCE -#define TC_TIMER_END TC_TIMER_VBUS_DEBOUNCE +#define PR_TIMER_START PR_TIMER_CHUNK_SENDER_RESPONSE +#define PR_TIMER_END PR_TIMER_TCPC_TX_TIMEOUT + +#define TC_TIMER_START TC_TIMER_CC_DEBOUNCE +#define TC_TIMER_END TC_TIMER_VBUS_DEBOUNCE /* * pd_timer_init @@ -311,7 +325,6 @@ void pd_timer_manage_expired(int port); */ int pd_timer_next_expiration(int port); - /* * pd_timer_dump * Debug display of the timers for a given port @@ -333,30 +346,30 @@ void pd_timer_dump(int port); */ /* exported: number of USB-C ports */ -#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT +#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT /* PD timers have three possible states: Active, Inactive and Disabled */ /* exported: timer_active indicates if a timer is currently active */ -extern ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT * MAX_PD_PORTS); +extern ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT *MAX_PD_PORTS); /* exported: timer_disabled indicates if a timer is currently disabled */ -extern ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT * MAX_PD_PORTS); +extern ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT *MAX_PD_PORTS); /* exported: set/clear/check the current timer_active for a timer */ #define PD_SET_ACTIVE(p, bit) \ - atomic_set_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_set_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) #define PD_CLR_ACTIVE(p, bit) \ - atomic_clear_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_clear_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) #define PD_CHK_ACTIVE(p, bit) \ - atomic_test_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_test_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) /* exported: set/clear/check the current timer_disabled for a timer */ #define PD_SET_DISABLED(p, bit) \ - atomic_set_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_set_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #define PD_CLR_DISABLED(p, bit) \ - atomic_clear_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_clear_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #define PD_CHK_DISABLED(p, bit) \ - atomic_test_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_test_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #endif /* TEST_BUILD */ -#endif /* __CROS_EC_USB_PD_TIMER_H */ +#endif /* __CROS_EC_USB_PD_TIMER_H */ diff --git a/include/usb_pd_vdo.h b/include/usb_pd_vdo.h index 9f6e35e117..ed1bc490f1 100644 --- a/include/usb_pd_vdo.h +++ b/include/usb_pd_vdo.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -134,20 +134,20 @@ struct product_vdo { #define PD_PRODUCT_IS_TBT3(vdo) ((vdo) >> 3 & BIT(0)) /* UFP VDO Version 1.2; update the value when UFP VDO version changes */ -#define VDO_UFP1(cap, ctype, alt, speed) \ - ((0x2) << 29 | ((cap) & 0xf) << 24 \ - | ((ctype) & 0x3) << 22 | ((alt) & 0x7) << 3 | ((speed) & 0x7)) +#define VDO_UFP1(cap, ctype, alt, speed) \ + ((0x2) << 29 | ((cap)&0xf) << 24 | ((ctype)&0x3) << 22 | \ + ((alt)&0x7) << 3 | ((speed)&0x7)) /* UFP VDO 1 Alternate Modes */ -#define VDO_UFP1_ALT_MODE_TBT3 BIT(0) -#define VDO_UFP1_ALT_MODE_RECONFIGURE BIT(1) +#define VDO_UFP1_ALT_MODE_TBT3 BIT(0) +#define VDO_UFP1_ALT_MODE_RECONFIGURE BIT(1) #define VDO_UFP1_ALT_MODE_NO_RECONFIGURE BIT(2) /* UFP VDO 1 Device Capability */ -#define VDO_UFP1_CAPABILITY_USB20 BIT(0) +#define VDO_UFP1_CAPABILITY_USB20 BIT(0) #define VDO_UFP1_CAPABILITY_USB20_BILLBOARD BIT(1) -#define VDO_UFP1_CAPABILITY_USB32 BIT(2) -#define VDO_UFP1_CAPABILITY_USB4 BIT(3) +#define VDO_UFP1_CAPABILITY_USB32 BIT(2) +#define VDO_UFP1_CAPABILITY_USB4 BIT(3) /*****************************************************************************/ /* * Table 6-37 DFP VDO @@ -170,15 +170,13 @@ struct product_vdo { * <4:0> : Port number */ /* DFP VDO Version 1.1; update the value when DFP VDO version changes */ -#define VDO_DFP(cap, ctype, port) \ - ((0x1) << 29 | ((cap) & 0x7) << 24 \ - | ((ctype) & 0x3) << 22 | ((port) & 0x1f)) +#define VDO_DFP(cap, ctype, port) \ + ((0x1) << 29 | ((cap)&0x7) << 24 | ((ctype)&0x3) << 22 | ((port)&0x1f)) /* DFP VDO Host Capability */ #define VDO_DFP_HOST_CAPABILITY_USB20 BIT(0) #define VDO_DFP_HOST_CAPABILITY_USB32 BIT(1) -#define VDO_DFP_HOST_CAPABILITY_USB4 BIT(2) - +#define VDO_DFP_HOST_CAPABILITY_USB4 BIT(2) /*****************************************************************************/ /* @@ -246,6 +244,19 @@ struct product_vdo { * Table 5-1 Certified Cables Where USB4-compatible Operation is Expected * This table lists the USB-C cables those support USB4 */ +enum usb_rev30_plug { + USB_REV30_TYPE_C = 2, + USB_REV30_CAPTIVE = 3, +}; + +enum usb_rev30_latency { + USB_REV30_LATENCY_1m = 1, + USB_REV30_LATENCY_2m = 2, + USB_REV30_LATENCY_3m = 3, + USB_REV30_LATENCY_4m = 4, + USB_REV30_LATENCY_5m = 5, + USB_REV30_LATENCY_6m = 6, +}; enum usb_rev30_ss { USB_R30_SS_U2_ONLY, @@ -267,7 +278,7 @@ enum usb_vbus_cur { union passive_cable_vdo_rev30 { struct { - enum usb_rev30_ss ss: 3; + enum usb_rev30_ss ss : 3; uint32_t reserved0 : 2; enum usb_vbus_cur vbus_cur : 2; uint32_t reserved1 : 2; @@ -284,6 +295,11 @@ union passive_cable_vdo_rev30 { uint32_t raw_value; }; +/* Macro passive VDO generator */ +#define VDO_REV30_PASSIVE(ss, vbus_cur, latency, plug) \ + ((ss & 0x7) | (vbus_cur & 0x3) << 5 | (latency & 0xf) << 13 | \ + (plug & 0x3) << 18) + /*****************************************************************************/ /* * Table 6-39 Active Cable VDO 1 @@ -355,7 +371,7 @@ enum vdo_version { union active_cable_vdo1_rev30 { struct { - enum usb_rev30_ss ss: 3; + enum usb_rev30_ss ss : 3; uint32_t sop_p_p : 1; uint32_t vbus_cable : 1; enum usb_vbus_cur vbus_cur : 2; @@ -541,17 +557,11 @@ union active_cable_vdo2_rev30 { * 1b – the VPD supports Charge Through * 0b – the VPD does not support Charge Through */ -#define VDO_VPD(hw, fw, vbus, ctc, vbusz, gndz, cts) \ - (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 \ - | ((vbus) & 0x3) << 15 \ - | ((ctc) & 0x1) << 14 \ - | ((vbusz) & 0x3f) << 7 \ - | ((gndz) & 0x3f) << 1 | (cts)) - -enum vpd_ctc_support { - VPD_CT_CURRENT_3A, - VPD_CT_CURRENT_5A -}; +#define VDO_VPD(hw, fw, vbus, ctc, vbusz, gndz, cts) \ + (((hw)&0xf) << 28 | ((fw)&0xf) << 24 | ((vbus)&0x3) << 15 | \ + ((ctc)&0x1) << 14 | ((vbusz)&0x3f) << 7 | ((gndz)&0x3f) << 1 | (cts)) + +enum vpd_ctc_support { VPD_CT_CURRENT_3A, VPD_CT_CURRENT_5A }; enum vpd_vbus { VPD_MAX_VBUS_20V, @@ -566,12 +576,12 @@ enum vpd_cts_support { }; #define VPD_VDO_MAX_VBUS(vdo) (((vdo) >> 15) & 0x3) -#define VPD_VDO_CURRENT(vdo) (((vdo) >> 14) & 1) +#define VPD_VDO_CURRENT(vdo) (((vdo) >> 14) & 1) #define VPD_VDO_VBUS_IMP(vdo) (((vdo) >> 7) & 0x3f) -#define VPD_VDO_GND_IMP(vdo) (((vdo) >> 1) & 0x3f) -#define VPD_VDO_CTS(vdo) ((vdo) & 1) -#define VPD_VBUS_IMP(mo) ((mo + 1) >> 1) -#define VPD_GND_IMP(mo) (mo) +#define VPD_VDO_GND_IMP(vdo) (((vdo) >> 1) & 0x3f) +#define VPD_VDO_CTS(vdo) ((vdo)&1) +#define VPD_VBUS_IMP(mo) ((mo + 1) >> 1) +#define VPD_GND_IMP(mo) (mo) /* * ############################################################################ @@ -625,11 +635,10 @@ enum idh_ptype { * - Table 6-29 ID Header VDO PD spec 3.0 version 2.0 and * - Table 6-23 ID Header VDO PD spec 2.0 version 1.3. */ -#define IS_PD_IDH_UFP_PTYPE(ptype) (ptype == IDH_PTYPE_HUB || \ - ptype == IDH_PTYPE_PERIPH || \ - ptype == IDH_PTYPE_PSD || \ - ptype == IDH_PTYPE_AMA || \ - ptype == IDH_PTYPE_VPD) +#define IS_PD_IDH_UFP_PTYPE(ptype) \ + (ptype == IDH_PTYPE_HUB || ptype == IDH_PTYPE_PERIPH || \ + ptype == IDH_PTYPE_PSD || ptype == IDH_PTYPE_AMA || \ + ptype == IDH_PTYPE_VPD) struct id_header_vdo_rev20 { uint16_t usb_vendor_id; @@ -715,7 +724,7 @@ enum usb_rev20_ss { union passive_cable_vdo_rev20 { struct { - enum usb_rev20_ss ss: 3; + enum usb_rev20_ss ss : 3; uint32_t reserved0 : 1; uint32_t vbus_cable : 1; enum usb_vbus_cur vbus_cur : 2; @@ -798,7 +807,7 @@ union passive_cable_vdo_rev20 { */ union active_cable_vdo_rev20 { struct { - enum usb_rev20_ss ss: 3; + enum usb_rev20_ss ss : 3; uint32_t sop_p_p : 1; uint32_t vbus_cable : 1; enum usb_vbus_cur vbus_cur : 2; @@ -866,14 +875,13 @@ union active_cable_vdo_rev20 { * 011b = [USB 2.0] billboard only * 100b..111b = Reserved, Shall Not be used */ -#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \ - (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 \ - | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8 \ - | ((vcpwr) & 0x3) << 5 | (vcr) << 4 | (vbr) << 3 \ - | ((usbss) & 0x7)) +#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \ + (((hw)&0x7) << 28 | ((fw)&0x7) << 24 | (tx1d) << 11 | (tx2d) << 10 | \ + (rx1d) << 9 | (rx2d) << 8 | ((vcpwr)&0x3) << 5 | (vcr) << 4 | \ + (vbr) << 3 | ((usbss)&0x7)) #define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1) -#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1) +#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1) enum ama_usb_ss { AMA_USBSS_U2_ONLY, diff --git a/include/usb_pe_sm.h b/include/usb_pe_sm.h index 4018f16322..a2e2a0f951 100644 --- a/include/usb_pe_sm.h +++ b/include/usb_pe_sm.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/usb_prl_sm.h b/include/usb_prl_sm.h index 6607bd2824..99b69f156f 100644 --- a/include/usb_prl_sm.h +++ b/include/usb_prl_sm.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -80,8 +80,7 @@ void prl_run(int port, int evt, int en); * @param type port address * @param rev revision */ -void prl_set_rev(int port, enum tcpci_msg_type type, - enum pd_rev_type rev); +void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type rev); /** * Get the PD revision @@ -93,6 +92,15 @@ void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type); /** + * Reset Tx and Rx message IDs for the specified partner to their initial + * values. + * + * @param port USB-C port number + * @param type Transmit type + */ +void prl_reset_msg_ids(int port, enum tcpci_msg_type type); + +/** * Sends a PD control message * * @param port USB-C port number @@ -100,7 +108,7 @@ enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type); * @param msg Control message type */ void prl_send_ctrl_msg(int port, enum tcpci_msg_type type, - enum pd_ctrl_msg_type msg); + enum pd_ctrl_msg_type msg); /** * Sends a PD data message @@ -110,7 +118,7 @@ void prl_send_ctrl_msg(int port, enum tcpci_msg_type type, * @param msg Data message type */ void prl_send_data_msg(int port, enum tcpci_msg_type type, - enum pd_data_msg_type msg); + enum pd_data_msg_type msg); /** * Sends a PD extended data message @@ -120,7 +128,7 @@ void prl_send_data_msg(int port, enum tcpci_msg_type type, * @param msg Extended data message type */ void prl_send_ext_data_msg(int port, enum tcpci_msg_type type, - enum pd_ext_msg_type msg); + enum pd_ext_msg_type msg); /** * Informs the Protocol Layer that a hard reset has completed diff --git a/include/usb_sm.h b/include/usb_sm.h index 2b5939bc04..d945ebd0ac 100644 --- a/include/usb_sm.h +++ b/include/usb_sm.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #ifndef __CROS_EC_USB_SM_H #define __CROS_EC_USB_SM_H -#include "compiler.h" /* for typeof() on Zephyr */ +#include "compiler.h" /* for typeof() on Zephyr */ /* Function pointer that implements a portion of a usb state */ typedef void (*state_execution)(const int port); @@ -101,13 +101,13 @@ struct test_sm_data { /* Size fo the state machine array above */ const int size; /* The array of names for states, can be NULL */ - const char * const * const names; + const char *const *const names; /* The size of the above names array */ const int names_size; }; #endif /* Creates a state machine state that will never link. Useful with IS_ENABLED */ -#define GEN_NOT_SUPPORTED(state) extern typeof(state) state ## _NOT_SUPPORTED +#define GEN_NOT_SUPPORTED(state) extern typeof(state) state##_NOT_SUPPORTED #endif /* __CROS_EC_USB_SM_H */ diff --git a/include/usb_tbt_alt_mode.h b/include/usb_tbt_alt_mode.h index a187c1b42b..378cd0ccce 100644 --- a/include/usb_tbt_alt_mode.h +++ b/include/usb_tbt_alt_mode.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -78,7 +78,7 @@ bool tbt_is_active(int port); * @param vdm VDM from ACK */ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm); + uint32_t *vdm); /* * Handles NAKed (or Not Supported or timed out) Thunderbolt VDM requests. diff --git a/include/usb_tc_sm.h b/include/usb_tc_sm.h index 4aaacd522b..ec6473edfd 100644 --- a/include/usb_tc_sm.h +++ b/include/usb_tc_sm.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,7 +24,7 @@ enum try_src_override_t { * This is the maximum voltage a sink can request * while charging. */ -#define TYPE_C_VOLTAGE 5000 /* mV */ +#define TYPE_C_VOLTAGE 5000 /* mV */ /* * Type C default sink current (mA) @@ -32,7 +32,7 @@ enum try_src_override_t { * This is the maximum current a sink can draw if charging * while in the Audio Accessory State. */ -#define TYPE_C_AUDIO_ACC_CURRENT 500 /* mA */ +#define TYPE_C_AUDIO_ACC_CURRENT 500 /* mA */ /** * Returns true if TypeC State machine is in attached source state. @@ -256,7 +256,7 @@ void pd_request_vconn_swap_off(int port); * @return 0 if cc1 is connected, else 1 for cc2 */ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc2); /** * Called by the state machine framework to initialize the diff --git a/include/usbc_ocp.h b/include/usbc_ocp.h index d31ce57724..6c1d641931 100644 --- a/include/usbc_ocp.h +++ b/include/usbc_ocp.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,8 +6,33 @@ #ifndef __CROS_EC_USBC_OCP_H #define __CROS_EC_USBC_OCP_H +#include "common.h" + /* Common APIs for USB Type-C Overcurrent Protection (OCP) Module */ +/* + * PD 3.1 Ver 1.3 7.1.7.1 Output Over Current Protection + * + * "After three consecutive over current events Source Shall go to + * ErrorRecovery. + * + * Sources Should attempt to send a Hard Reset message when over + * current protection engages followed by an Alert Message indicating + * an OCP event once an Explicit Contract has been established. + * + * The Source Shall prevent continual system or port cycling if over + * current protection continues to engage after initially resuming + * either default operation or renegotiation. Latching off the port or + * system is an acceptable response to recurring over current." + * + * Our policy will be first two OCPs -> hard reset + * 3rd -> ErrorRecovery + * 4th -> port latched off + */ +#define OCP_HR_CNT 2 + +#define OCP_MAX_CNT 4 + /** * Increment the overcurrent event counter. * diff --git a/include/usbc_ppc.h b/include/usbc_ppc.h index 5377f922ed..09d7107faf 100644 --- a/include/usbc_ppc.h +++ b/include/usbc_ppc.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/include/util.h b/include/util.h index e39b81ccdf..dc2e038705 100644 --- a/include/util.h +++ b/include/util.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,13 +10,19 @@ #include "common.h" #include "compile_time_macros.h" -#include "panic.h" -#include "builtin/assert.h" /* For ASSERT(). */ +#include <ctype.h> #include <stdbool.h> #include <stddef.h> +#include <stdlib.h> +#include <string.h> +#include <strings.h> #ifdef CONFIG_ZEPHYR #include <zephyr/sys/util.h> +/** + * TODO(b/237712836): Remove once Zephyr's libc has strcasecmp. + */ +#include "builtin/strings.h" #endif #ifdef __cplusplus @@ -27,21 +33,21 @@ extern "C" { #define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y)) #define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y)) #ifndef MAX -#define MAX(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MAX(temp_a, temp_b); \ +#define MAX(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MAX(temp_a, temp_b); \ }) #endif #ifndef MIN -#define MIN(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MIN(temp_a, temp_b); \ +#define MIN(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MIN(temp_a, temp_b); \ }) #endif #ifndef NULL @@ -69,11 +75,11 @@ extern "C" { * contains the base struct. This requires knowing where in the contained * struct the base struct resides, this is the member parameter to downcast. */ -#define DOWNCAST(pointer, type, member) \ - ((type *)(((uint8_t *) pointer) - offsetof(type, member))) +#define DOWNCAST(pointer, type, member) \ + ((type *)(((uint8_t *)pointer) - offsetof(type, member))) /* True of x is a power of two */ -#define POWER_OF_TWO(x) ((x) && !((x) & ((x) - 1))) +#define POWER_OF_TWO(x) ((x) && !((x) & ((x)-1))) /* Macro to check if the value is in range */ #ifndef CONFIG_ZEPHYR @@ -84,7 +90,7 @@ extern "C" { * macros for integer division with various rounding variants * default integer division rounds down. */ -#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y)) +#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y)) #define DIV_ROUND_NEAREST(x, y) (((x) + ((y) / 2)) / (y)) /* @@ -93,60 +99,14 @@ extern "C" { * Swapping composites (e.g. a+b, x++) doesn't make sense. So, <a> and <b> * can only be a variable (x) or a pointer reference (*x) without operator. */ -#define swap(a, b) \ - do { \ +#define swap(a, b) \ + do { \ typeof(a) __t__; \ - __t__ = a; \ - a = b; \ - b = __t__; \ + __t__ = a; \ + a = b; \ + b = __t__; \ } while (0) -#ifndef HIDE_EC_STDLIB - -/* Standard library functions */ -int atoi(const char *nptr); - -#ifdef CONFIG_ZEPHYR -#include <ctype.h> -#include <string.h> -#else -int isdigit(int c); -int isspace(int c); -int isalpha(int c); -int isupper(int c); -int isprint(int c); -int tolower(int c); - -int memcmp(const void *s1, const void *s2, size_t len); -void *memcpy(void *dest, const void *src, size_t len); -void *memset(void *dest, int c, size_t len); -void *memmove(void *dest, const void *src, size_t len); -void *memchr(const void *buffer, int c, size_t n); - -/** - * Find the first occurrence of the substring <s2> in the string <s1> - * - * @param s1 String where <s2> is searched. - * @param s2 Substring to be located in <s1> - * @return Pointer to the located substring or NULL if not found. - */ -char *strstr(const char *s1, const char *s2); - -/** - * Calculates the length of the initial segment of s which consists - * entirely of bytes not in reject. - */ -size_t strcspn(const char *s, const char *reject); - -size_t strlen(const char *s); -char *strncpy(char *dest, const char *src, size_t n); -int strncmp(const char *s1, const char *s2, size_t n); -#endif - -int strcasecmp(const char *s1, const char *s2); -int strncasecmp(const char *s1, const char *s2, size_t size); -size_t strnlen(const char *s, size_t maxlen); - /* Like strtol(), but for integers. */ int strtoi(const char *nptr, char **endptr, int base); @@ -173,7 +133,6 @@ char *strzcpy(char *dest, const char *src, int len); * Other strings return 0 and leave *dest unchanged. */ int parse_bool(const char *s, int *dest); -#endif /* !HIDE_EC_STDLIB */ /** * Constant time implementation of memcmp to avoid timing side channels. @@ -234,7 +193,7 @@ int alignment_log2(unsigned int x); */ void reverse(void *dest, size_t len); - +int find_base(int base, int *c, const char **nptr); /****************************************************************************/ /* Conditional stuff. * @@ -261,25 +220,49 @@ typedef uint8_t cond_t; /* Initialize a conditional to a specific state. Do this first. */ void cond_init(cond_t *c, int boolean); -static inline void cond_init_false(cond_t *c) { cond_init(c, 0); } -static inline void cond_init_true(cond_t *c) { cond_init(c, 1); } +static inline void cond_init_false(cond_t *c) +{ + cond_init(c, 0); +} +static inline void cond_init_true(cond_t *c) +{ + cond_init(c, 1); +} /* Set the current state. Do this as often as you like. */ void cond_set(cond_t *c, int boolean); -static inline void cond_set_false(cond_t *c) { cond_set(c, 0); } -static inline void cond_set_true(cond_t *c) { cond_set(c, 1); } +static inline void cond_set_false(cond_t *c) +{ + cond_set(c, 0); +} +static inline void cond_set_true(cond_t *c) +{ + cond_set(c, 1); +} /* Get the current state. Do this as often as you like. */ int cond_is(cond_t *c, int boolean); -static inline int cond_is_false(cond_t *c) { return cond_is(c, 0); } -static inline int cond_is_true(cond_t *c) { return cond_is(c, 1); } +static inline int cond_is_false(cond_t *c) +{ + return cond_is(c, 0); +} +static inline int cond_is_true(cond_t *c) +{ + return cond_is(c, 1); +} /* See if the state has transitioned. If it has, the corresponding function * will return true ONCE only, until it's changed back. */ int cond_went(cond_t *c, int boolean); -static inline int cond_went_false(cond_t *c) { return cond_went(c, 0); } -static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); } +static inline int cond_went_false(cond_t *c) +{ + return cond_went(c, 0); +} +static inline int cond_went_true(cond_t *c) +{ + return cond_went(c, 1); +} /****************************************************************************/ /* Console command parsing */ @@ -287,8 +270,8 @@ static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); } /* Parse command-line arguments given integer shift value to obtain * offset and size. */ -int parse_offset_size(int argc, char **argv, int shift, - int *offset, int *size); +int parse_offset_size(int argc, const char **argv, int shift, int *offset, + int *size); /** * Print binary in hex and ASCII @@ -396,4 +379,4 @@ int ternary_from_bits(int *bits, int nbits); } #endif -#endif /* __CROS_EC_UTIL_H */ +#endif /* __CROS_EC_UTIL_H */ diff --git a/include/vb21_struct.h b/include/vb21_struct.h index 74d0ea3ad2..c8b49ac05e 100644 --- a/include/vb21_struct.h +++ b/include/vb21_struct.h @@ -1,4 +1,4 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -28,25 +28,24 @@ */ enum vb21_struct_common_magic { /* "Vb2B" = vb21_keyblock.c.magic */ - VB21_MAGIC_KEYBLOCK = 0x42326256, + VB21_MAGIC_KEYBLOCK = 0x42326256, /* "Vb2F" = vb21_fw_preamble.c.magic */ - VB21_MAGIC_FW_PREAMBLE = 0x46326256, + VB21_MAGIC_FW_PREAMBLE = 0x46326256, /* "Vb2I" = vb21_packed_private_key.c.magic */ - VB21_MAGIC_PACKED_PRIVATE_KEY = 0x49326256, + VB21_MAGIC_PACKED_PRIVATE_KEY = 0x49326256, /* "Vb2K" = vb2_kernel_preamble.c.magic */ - VB21_MAGIC_KERNEL_PREAMBLE = 0x4b326256, + VB21_MAGIC_KERNEL_PREAMBLE = 0x4b326256, /* "Vb2P" = vb21_packed_key.c.magic */ - VB21_MAGIC_PACKED_KEY = 0x50326256, + VB21_MAGIC_PACKED_KEY = 0x50326256, /* "Vb2S" = vb21_signature.c.magic */ - VB21_MAGIC_SIGNATURE = 0x53326256, + VB21_MAGIC_SIGNATURE = 0x53326256, }; - /* * Generic struct header for all vboot2.1 structs. This makes it easy to * automatically parse and identify vboot structs (e.g., in futility). This @@ -145,7 +144,7 @@ struct vb21_packed_key { struct vb2_id id; } __attribute__((packed)); -#define EXPECTED_VB21_PACKED_KEY_SIZE \ +#define EXPECTED_VB21_PACKED_KEY_SIZE \ (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE) /* Current version of vb21_packed_private_key struct */ @@ -184,7 +183,7 @@ struct vb21_packed_private_key { struct vb2_id id; } __attribute__((packed)); -#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE \ +#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE \ (EXPECTED_VB21_STRUCT_COMMON_SIZE + 12 + EXPECTED_ID_SIZE) /* Current version of vb21_signature struct */ @@ -232,10 +231,9 @@ struct vb21_signature { struct vb2_id id; } __attribute__((packed)); -#define EXPECTED_VB21_SIGNATURE_SIZE \ +#define EXPECTED_VB21_SIGNATURE_SIZE \ (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE) - /* Current version of vb21_keyblock struct */ #define VB21_KEYBLOCK_VERSION_MAJOR 3 #define VB21_KEYBLOCK_VERSION_MINOR 0 @@ -290,7 +288,6 @@ struct vb21_keyblock { #define EXPECTED_VB21_KEYBLOCK_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16) - /* Current version of vb21_fw_preamble struct */ #define VB21_FW_PREAMBLE_VERSION_MAJOR 3 #define VB21_FW_PREAMBLE_VERSION_MINOR 0 @@ -343,4 +340,4 @@ struct vb21_fw_preamble { #define EXPECTED_VB21_FW_PREAMBLE_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 20) -#endif /* VBOOT_REFERENCE_VB21_STRUCT_H_ */ +#endif /* VBOOT_REFERENCE_VB21_STRUCT_H_ */ diff --git a/include/vboot.h b/include/vboot.h index 52ccae6e90..55359e8044 100644 --- a/include/vboot.h +++ b/include/vboot.h @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -31,7 +31,6 @@ int vb21_is_packed_key_valid(const struct vb21_packed_key *key); int vb21_is_signature_valid(const struct vb21_signature *sig, const struct vb21_packed_key *key); - /** * Returns the public key in RO that was used to sign RW. * @@ -58,8 +57,8 @@ int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end); * @param sig Signature of <data> * @return EC_SUCCESS or EC_ERROR_* */ -int vboot_verify(const uint8_t *data, int len, - const struct rsa_public_key *key, const uint8_t *sig); +int vboot_verify(const uint8_t *data, int len, const struct rsa_public_key *key, + const uint8_t *sig); /** * Entry point of EC EFS @@ -100,19 +99,19 @@ __override_proto void board_enable_packet_mode(bool enable); void packet_mode_interrupt(enum gpio_signal signal); /* Maximum number of times EC retries packet transmission before giving up. */ -#define CR50_COMM_MAX_RETRY 5 +#define CR50_COMM_MAX_RETRY 5 /* EC's timeout for packet transmission to Cr50. */ -#define CR50_COMM_TIMEOUT (50 * MSEC) +#define CR50_COMM_TIMEOUT (50 * MSEC) /* Preamble character repeated before the packet header starts. */ -#define CR50_COMM_PREAMBLE 0xec +#define CR50_COMM_PREAMBLE 0xec /* Magic characters used to identify ec-cr50-comm packets */ -#define CR50_PACKET_MAGIC 0x4345 /* 'EC' in little endian */ +#define CR50_PACKET_MAGIC 0x4345 /* 'EC' in little endian */ /* version of struct cr50_comm_request */ -#define CR50_COMM_PACKET_VERSION (0 << 4 | 0 << 0) /* 0.0 */ +#define CR50_COMM_PACKET_VERSION (0 << 4 | 0 << 0) /* 0.0 */ /** * EC-Cr50 data frame looks like the following: @@ -125,11 +124,11 @@ void packet_mode_interrupt(enum gpio_signal signal); */ struct cr50_comm_request { /* Header */ - uint16_t magic; /* CR50_PACKET_MAGIC */ - uint8_t struct_version; /* version of this struct msb:lsb=major:minor */ - uint8_t crc; /* checksum computed from all bytes after crc */ - uint16_t type; /* CR50_CMD_* */ - uint8_t size; /* Payload size. Be easy on Cr50 buffer. */ + uint16_t magic; /* CR50_PACKET_MAGIC */ + uint8_t struct_version; /* version of this struct msb:lsb=major:minor */ + uint8_t crc; /* checksum computed from all bytes after crc */ + uint16_t type; /* CR50_CMD_* */ + uint8_t size; /* Payload size. Be easy on Cr50 buffer. */ /* Payload */ uint8_t data[]; } __packed; @@ -138,33 +137,33 @@ struct cr50_comm_response { uint16_t error; } __packed; -#define CR50_COMM_MAX_REQUEST_SIZE (sizeof(struct cr50_comm_request) \ - + UINT8_MAX) -#define CR50_UART_RX_BUFFER_SIZE 32 /* TODO: Get from Cr50 header */ +#define CR50_COMM_MAX_REQUEST_SIZE \ + (sizeof(struct cr50_comm_request) + UINT8_MAX) +#define CR50_UART_RX_BUFFER_SIZE 32 /* TODO: Get from Cr50 header */ /* commands */ enum cr50_comm_cmd { - CR50_COMM_CMD_HELLO = 0x0000, - CR50_COMM_CMD_SET_BOOT_MODE = 0x0001, - CR50_COMM_CMD_VERIFY_HASH = 0x0002, - CR50_COMM_CMD_LIMIT = 0xffff, + CR50_COMM_CMD_HELLO = 0x0000, + CR50_COMM_CMD_SET_BOOT_MODE = 0x0001, + CR50_COMM_CMD_VERIFY_HASH = 0x0002, + CR50_COMM_CMD_LIMIT = 0xffff, } __packed; BUILD_ASSERT(sizeof(enum cr50_comm_cmd) == sizeof(uint16_t)); -#define CR50_COMM_ERR_PREFIX 0xec +#define CR50_COMM_ERR_PREFIX 0xec /* return code */ enum cr50_comm_err { - CR50_COMM_SUCCESS = 0xec00, - CR50_COMM_ERR_UNKNOWN = 0xec01, - CR50_COMM_ERR_MAGIC = 0xec02, - CR50_COMM_ERR_CRC = 0xec03, - CR50_COMM_ERR_SIZE = 0xec04, - CR50_COMM_ERR_TIMEOUT = 0xec05, /* Generated by EC */ - CR50_COMM_ERR_UNDEFINED_CMD = 0xec06, - CR50_COMM_ERR_BAD_PAYLOAD = 0xec07, - CR50_COMM_ERR_STRUCT_VERSION = 0xec08, - CR50_COMM_ERR_NVMEM = 0xec09, + CR50_COMM_SUCCESS = 0xec00, + CR50_COMM_ERR_UNKNOWN = 0xec01, + CR50_COMM_ERR_MAGIC = 0xec02, + CR50_COMM_ERR_CRC = 0xec03, + CR50_COMM_ERR_SIZE = 0xec04, + CR50_COMM_ERR_TIMEOUT = 0xec05, /* Generated by EC */ + CR50_COMM_ERR_UNDEFINED_CMD = 0xec06, + CR50_COMM_ERR_BAD_PAYLOAD = 0xec07, + CR50_COMM_ERR_STRUCT_VERSION = 0xec08, + CR50_COMM_ERR_NVMEM = 0xec09, } __packed; BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t)); @@ -173,8 +172,8 @@ BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t)); * BIT(0) : RECOVERY flag */ enum boot_mode { - BOOT_MODE_NORMAL = 0x00, - BOOT_MODE_NO_BOOT = 0x01, + BOOT_MODE_NORMAL = 0x00, + BOOT_MODE_NO_BOOT = 0x01, } __packed; BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t)); @@ -187,4 +186,11 @@ BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t)); */ __override_proto bool vboot_allow_usb_pd(void); -#endif /* __CROS_EC_INCLUDE_VBOOT_H */ +#ifdef TEST_BUILD +/** + * Set the vboot_allow_usb_pd flag to false. + */ +__test_only void vboot_disable_pd(void); +#endif + +#endif /* __CROS_EC_INCLUDE_VBOOT_H */ diff --git a/include/vboot_hash.h b/include/vboot_hash.h index 126872393e..980a07df0b 100644 --- a/include/vboot_hash.h +++ b/include/vboot_hash.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -49,4 +49,4 @@ int vboot_hash_in_progress(void); */ void vboot_hash_abort(void); -#endif /* __CROS_EC_VBOOT_HASH_H */ +#endif /* __CROS_EC_VBOOT_HASH_H */ diff --git a/include/vec3.h b/include/vec3.h index e7fcf92041..ebdb358cc1 100644 --- a/include/vec3.h +++ b/include/vec3.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -80,4 +80,4 @@ fp_t fpv3_norm_squared(const fpv3_t v); */ fp_t fpv3_norm(const fpv3_t v); -#endif /* __CROS_EC_VEC_3_H */ +#endif /* __CROS_EC_VEC_3_H */ diff --git a/include/vec4.h b/include/vec4.h index f1724d955e..e951c0542f 100644 --- a/include/vec4.h +++ b/include/vec4.h @@ -1,4 +1,4 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. +/* Copyright 2015 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,4 +12,4 @@ typedef float floatv4_t[4]; typedef fp_t fpv4_t[4]; -#endif /* __CROS_EC_VEC_4_H */ +#endif /* __CROS_EC_VEC_4_H */ diff --git a/include/virtual_battery.h b/include/virtual_battery.h index a5cac1140c..2bd171f43c 100644 --- a/include/virtual_battery.h +++ b/include/virtual_battery.h @@ -1,4 +1,4 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,8 +6,8 @@ #ifndef __CROS_EC_VIRTUAL_BATTERY_H #define __CROS_EC_VIRTUAL_BATTERY_H -#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART) \ - && !defined(VIRTUAL_BATTERY_ADDR_FLAGS) +#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART) && \ + !defined(VIRTUAL_BATTERY_ADDR_FLAGS) #define VIRTUAL_BATTERY_ADDR_FLAGS BATTERY_ADDR_FLAGS #endif @@ -21,10 +21,8 @@ * @return EC_SUCCESS if successful, non-zero if error. * */ -int virtual_battery_operation(const uint8_t *batt_cmd_head, - uint8_t *dest, - int read_len, - int write_len); +int virtual_battery_operation(const uint8_t *batt_cmd_head, uint8_t *dest, + int read_len, int write_len); /** * Parse a command for virtual battery function. @@ -39,10 +37,9 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head, * @param out Data to send * @return EC_SUCCESS if successful, non-zero if error. */ -int virtual_battery_handler(struct ec_response_i2c_passthru *resp, - int in_len, int *err_code, int xferflags, - int read_len, int write_len, - const uint8_t *out); +int virtual_battery_handler(struct ec_response_i2c_passthru *resp, int in_len, + int *err_code, int xferflags, int read_len, + int write_len, const uint8_t *out); /* Reset the state machine and static variables. */ void reset_parse_state(void); diff --git a/include/vstore.h b/include/vstore.h new file mode 100644 index 0000000000..692d0e3012 --- /dev/null +++ b/include/vstore.h @@ -0,0 +1,16 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_VSTORE_H +#define __CROS_EC_VSTORE_H + +#ifdef TEST_BUILD + +/* Clear all vstore locks */ +void vstore_clear_lock(void); + +#endif /* TEST_BUILD */ + +#endif /* __CROS_EC_VSTORE_H */ diff --git a/include/watchdog.h b/include/watchdog.h index 036f722d97..9bfed9c192 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -1,4 +1,4 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. +/* Copyright 2012 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -49,7 +49,9 @@ void watchdog_stop_and_unlock(void); #ifdef CONFIG_WATCHDOG void watchdog_reload(void); #else -static inline void watchdog_reload(void) { } +static inline void watchdog_reload(void) +{ +} #endif #endif /* __CROS_EC_WATCHDOG_H */ diff --git a/include/wireless.h b/include/wireless.h index d209d69fed..7232f92763 100644 --- a/include/wireless.h +++ b/include/wireless.h @@ -1,4 +1,4 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. +/* Copyright 2013 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,11 +11,7 @@ #include "common.h" /* Wireless power state for wireless_set_state() */ -enum wireless_power_state { - WIRELESS_OFF, - WIRELESS_SUSPEND, - WIRELESS_ON -}; +enum wireless_power_state { WIRELESS_OFF, WIRELESS_SUSPEND, WIRELESS_ON }; /** * Set wireless power state. @@ -23,7 +19,9 @@ enum wireless_power_state { #ifdef CONFIG_WIRELESS void wireless_set_state(enum wireless_power_state state); #else -static inline void wireless_set_state(enum wireless_power_state state) { } +static inline void wireless_set_state(enum wireless_power_state state) +{ +} #endif -#endif /* __CROS_EC_WIRELESS_H */ +#endif /* __CROS_EC_WIRELESS_H */ diff --git a/include/write_protect.h b/include/write_protect.h index 019243dd61..8e09111974 100644 --- a/include/write_protect.h +++ b/include/write_protect.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ |