diff options
Diffstat (limited to 'power/braswell.c')
| -rw-r--r-- | power/braswell.c | 41 |
1 files changed, 11 insertions, 30 deletions
diff --git a/power/braswell.c b/power/braswell.c index bfdf3dec39..0b91040cbc 100644 --- a/power/braswell.c +++ b/power/braswell.c @@ -68,38 +68,19 @@ void chipset_force_shutdown(void) forcing_shutdown = 1; } -void chipset_reset(int cold_reset) +void chipset_reset(void) { - CPRINTS("%s(%d)", __func__, cold_reset); - if (cold_reset) { - /* - * Drop and restore PWROK. This causes the PCH to reboot, - * regardless of its after-G3 setting. This type of reboot - * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so - * we actually drop power to the rest of the system (hence, a - * "cold" reboot). - */ - - /* Ignore if PWROK is already low */ - if (gpio_get_level(GPIO_PCH_SYS_PWROK) == 0) - return; - - /* PWROK must deassert for at least 3 RTC clocks = 91 us */ - gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - udelay(100); - gpio_set_level(GPIO_PCH_SYS_PWROK, 1); + CPRINTS("%s", __func__); - } else { - /* - * Send a reset pulse to the PCH. This just causes it to - * assert INIT# to the CPU without dropping power or asserting - * PLTRST# to reset the rest of the system. The PCH uses a 16 - * ms debounce time, so assert the signal for twice that. - */ - gpio_set_level(GPIO_PCH_RCIN_L, 0); - usleep(32 * MSEC); - gpio_set_level(GPIO_PCH_RCIN_L, 1); - } + /* + * Send a reset pulse to the PCH. This just causes it to + * assert INIT# to the CPU without dropping power or asserting + * PLTRST# to reset the rest of the system. The PCH uses a 16 + * ms debounce time, so assert the signal for twice that. + */ + gpio_set_level(GPIO_PCH_RCIN_L, 0); + usleep(32 * MSEC); + gpio_set_level(GPIO_PCH_RCIN_L, 1); } void chipset_throttle_cpu(int throttle) |