diff options
Diffstat (limited to 'zephyr/app/ec/chip/riscv/riscv-ite')
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 index 1d60630027..dab9e6b8b2 100644 --- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 +++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 @@ -4,6 +4,37 @@ if SOC_FAMILY_RISCV_ITE +# Code RAM base for IT8XXX2 +config CROS_EC_PROGRAM_MEMORY_BASE + default 0x80000000 + +# The total RAM size of IT8xxx2 is 60 KB. +# The first 4KB block be always reserved for ram code functions, +# so the total available RAM size will be 56KB. +config CROS_EC_RAM_BASE + default 0x80101000 + +config CROS_EC_DATA_RAM_SIZE + default 0x0000e000 + +config CROS_EC_RAM_SIZE + default 0x0000e000 + +# The 512KB flash space layout are as the below: +# - RO image starts at the beginning of flash. +# - RW image starts at the second half of flash. +config CROS_EC_RO_MEM_OFF + default 0x0 + +config CROS_EC_RO_SIZE + default 0x40000 + +config CROS_EC_RW_MEM_OFF + default 0x40000 + +config CROS_EC_RW_SIZE + default 0x40000 + config FLASH_LOAD_OFFSET default CROS_EC_RW_MEM_OFF if CROS_EC_RW |