diff options
Diffstat (limited to 'zephyr/projects/intelrvp')
44 files changed, 1251 insertions, 415 deletions
diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py index 755b6479a6..e6e617ea23 100644 --- a/zephyr/projects/intelrvp/BUILD.py +++ b/zephyr/projects/intelrvp/BUILD.py @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -43,7 +43,6 @@ register_intelrvp_project( chip="npcx9m7f", extra_dts_overlays=[ here / "adlrvp/adlrvp_npcx/adlrvp_npcx.dts", - here / "adlrvp/adlrvp_npcx/cbi_eeprom.dts", here / "adlrvp/adlrvp_npcx/fan.dts", here / "adlrvp/adlrvp_npcx/gpio.dts", here / "adlrvp/adlrvp_npcx/interrupts.dts", @@ -62,17 +61,18 @@ register_intelrvp_project( project_name="mtlrvpp_npcx", chip="npcx9m3f", extra_dts_overlays=[ - here / "adlrvp/adlrvp_npcx/cbi_eeprom.dts", here / "mtlrvp/mtlrvpp_npcx/fan.dts", here / "mtlrvp/mtlrvpp_npcx/gpio.dts", here / "mtlrvp/mtlrvpp_npcx/keyboard.dts", here / "mtlrvp/mtlrvpp_npcx/interrupts.dts", here / "mtlrvp/ioex.dts", here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts", + here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts", here / "adlrvp/adlrvp_npcx/temp_sensor.dts", + here / "mtlrvp/usbc.dts", ], extra_kconfig_files=[ - here / "legacy_ec_pwrseq.conf", + here / "zephyr_ap_pwrseq.conf", here / "mtlrvp/mtlrvpp_npcx/prj.conf", ], ) diff --git a/zephyr/projects/intelrvp/CMakeLists.txt b/zephyr/projects/intelrvp/CMakeLists.txt index f8a76be55d..25b3af3931 100644 --- a/zephyr/projects/intelrvp/CMakeLists.txt +++ b/zephyr/projects/intelrvp/CMakeLists.txt @@ -1,10 +1,10 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. cmake_minimum_required(VERSION 3.13.1) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") project(intelrvp) cros_ec_library_include_directories(include) @@ -26,4 +26,7 @@ endif() if(DEFINED CONFIG_BOARD_MTLRVP_NPCX) add_subdirectory(mtlrvp) zephyr_library_sources("src/intelrvp.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy_mecc_1_1.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd_mecc_1_1.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd.c") endif() diff --git a/zephyr/projects/intelrvp/Kconfig b/zephyr/projects/intelrvp/Kconfig index 1c8ec22073..c51c54847b 100644 --- a/zephyr/projects/intelrvp/Kconfig +++ b/zephyr/projects/intelrvp/Kconfig @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt index bd961ff89d..71dee29552 100644 --- a/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt +++ b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts index 418b68a8d7..79723beabd 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,37 +20,28 @@ named-i2c-ports { compatible = "named-i2c-ports"; - battery { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_BATTERY"; - }; i2c_charger: charger { i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - }; - eeprom { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - port80 { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_PORT80"; + enum-names = "I2C_PORT_BATTERY", + "I2C_PORT_CHARGER", + "I2C_PORT_EEPROM", + "I2C_PORT_PORT80"; }; typec_0: typec-0 { i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_TYPEC_0"; + enum-names = "I2C_PORT_TYPEC_0"; }; typec_1: typec-1 { i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_TYPEC_1"; + enum-names = "I2C_PORT_TYPEC_1"; }; typec_2: typec-2 { i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_TYPEC_2"; + enum-names = "I2C_PORT_TYPEC_2"; }; typec_3: typec-3 { i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_TYPEC_3"; + enum-names = "I2C_PORT_TYPEC_3"; }; }; @@ -58,22 +49,18 @@ compatible = "named-adc-channels"; adc_ambient: ambient { - label = "ADC_TEMP_SNS_AMBIENT"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 3>; }; adc_ddr: ddr { - label = "ADC_TEMP_SNS_DDR"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 4>; }; adc_skin: skin { - label = "ADC_TEMP_SNS_SKIN"; enum-name = "ADC_TEMP_SENSOR_3"; io-channels = <&adc0 2>; }; adc_vr: vr { - label = "ADC_TEMP_SNS_VR"; enum-name = "ADC_TEMP_SENSOR_4"; io-channels = <&adc0 1>; }; @@ -130,6 +117,21 @@ reg = <0x38>; label = "MAX695X_SEVEN_SEG_DISPLAY"; }; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; }; &i2c_ctrl7 { @@ -142,6 +144,25 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; pinctrl-names = "default"; + + tcpc_port0: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 { + compatible = "intel,jhl8040r"; + reg = <0x54>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; + + usb_c0_bb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; }; &i2c_ctrl0 { @@ -154,6 +175,25 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; pinctrl-names = "default"; + + tcpc_port1: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 { + compatible = "intel,jhl8040r"; + reg = <0x55>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; + + usb_c1_bb_retimer: jhl8040r-c1@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; }; &i2c_ctrl2 { @@ -166,6 +206,18 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; pinctrl-names = "default"; + + tcpc_port2: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c2_bb_retimer: jhl8040r-c2@58 { + compatible = "intel,jhl8040r"; + reg = <0x58>; + reset-pin = <&usb_c2_bb_retimer_rst>; + ls-en-pin = <&usb_c2_bb_retimer_ls_en>; + }; }; &i2c_ctrl1 { @@ -178,6 +230,18 @@ clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; pinctrl-names = "default"; + + tcpc_port3: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c3_bb_retimer: jhl8040r-c3@59 { + compatible = "intel,jhl8040r"; + reg = <0x59>; + reset-pin = <&usb_c3_bb_retimer_rst>; + ls-en-pin = <&usb_c3_bb_retimer_ls_en>; + }; }; &i2c_ctrl3 { diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts deleted file mode 100644 index efded14c3e..0000000000 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -&i2c7_0 { - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; -}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts index 23f72dde94..8babe53903 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - pwm-frequency = <30000>; rpm_min = <3000>; rpm_start = <3000>; rpm_max = <10000>; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts index 7e1cb9c704..1d38fc877c 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -124,6 +124,7 @@ ec-ds3 { gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; enum-name = "GPIO_EN_PP3300_A"; + alias = "GPIO_TEMP_SENSOR_POWER"; }; pch-pwrok-ec { gpios = <&gpioa 0 GPIO_INPUT>; @@ -319,11 +320,9 @@ }; usb-c2-usb-mux-cntrl-1 { gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_1"; }; usb-c2-usb-mux-cntrl-0 { gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_0"; }; usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst { gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>; @@ -337,5 +336,9 @@ gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>; enum-name = "IOEX_USB_C2_C3_OC"; }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; + }; }; }; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts index e0992ef3b3..d7bb40fad2 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts index e735234128..81d6e82f48 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf index 32919ea399..2c98fd9330 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts index 50a08a300e..eb1576dbff 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,10 +7,10 @@ pwmleds { compatible = "pwm-leds"; pwm_led0: pwm_led_0 { - pwms = <&pwm4 0 0 PWM_POLARITY_INVERTED>; + pwms = <&pwm4 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; }; pwm_led1: pwm_led_1 { - pwms = <&pwm5 0 0 PWM_POLARITY_INVERTED>; + pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; }; }; @@ -18,7 +18,6 @@ compatible = "cros-ec,pwm-leds"; leds = <&pwm_led0 &pwm_led1>; - frequency = <4800>; color-map-green = <100>; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts index a2fcacc1e1..93ecaa02f6 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,19 +6,36 @@ #include <cros/thermistor/thermistor.dtsi> / { + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_ambient>; + }; + temp_ddr: ddr { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_ddr>; + }; + temp_skin: skin { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_skin>; + }; + temp_vr: vr { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_vr>; + }; + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; ambient { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "Ambient"; - enum-name = "TEMP_SENSOR_1"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_ambient>; + sensor = <&temp_ambient>; }; /* @@ -30,7 +47,6 @@ * compatible = "cros-ec,temp-sensor-thermistor", * "cros-ec,temp-sensor"; * thermistor = < >; - * label = "Battery"; * enum-name = ""; * temp_fan_off = <15>; * temp_fan_max = <50>; @@ -42,43 +58,28 @@ */ ddr { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "DDR"; - enum-name = "TEMP_SENSOR_2"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_ddr>; + sensor = <&temp_ddr>; }; skin { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "Skin"; - enum-name = "TEMP_SENSOR_3"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_skin>; + sensor = <&temp_skin>; }; vr { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "VR"; - enum-name = "TEMP_SENSOR_4"; temp_fan_off = <15>; temp_fan_max = <50>; temp_host_high = <75>; temp_host_halt = <80>; temp_host_release_high = <65>; - adc = <&adc_vr>; + sensor = <&temp_vr>; }; }; }; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts index cd7c2b050f..471a1f52e9 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,27 +10,22 @@ usbc_port0: port0@0 { compatible = "named-usbc-port"; reg = <0>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_0>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb_mux_chain_0: usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_bb_retimer + &virtual_mux_c0>; }; - chg { - compatible = "intersil,isl9241"; - status = "okay"; - port = <&i2c_charger>; + usb_mux_alt_chain_0: usb-mux-alt-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c0_bb_retimer + &usb_c0_soc_side_bb_retimer + &virtual_mux_c0>; }; - usb-muxes = <&usb_c0_bb_retimer &virtual_mux_c0>; }; port0-muxes { - usb_c0_bb_retimer: jhl8040r-c0 { - compatible = "intel,jhl8040r"; - port = <&typec_0>; - i2c-addr-flags = <0x56>; - reset-pin = <&usb_c0_bb_retimer_rst>; - ls-en-pin = <&usb_c0_bb_retimer_ls_en>; - }; virtual_mux_c0: virtual-mux-c0 { compatible = "cros-ec,usbc-mux-virtual"; }; @@ -39,22 +34,21 @@ usbc_port1: port1@1 { compatible = "named-usbc-port"; reg = <1>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_1>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port1>; + usb_mux_chain_1: usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c1_bb_retimer + &virtual_mux_c1>; + }; + usb_mux_alt_chain_1: usb-mux-alt-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c1_bb_retimer + &usb_c1_soc_side_bb_retimer + &virtual_mux_c1>; }; - usb-muxes = <&usb_c1_bb_retimer &virtual_mux_c1>; }; port1-muxes { - usb_c1_bb_retimer: jhl8040r-c1 { - compatible = "intel,jhl8040r"; - port = <&typec_1>; - i2c-addr-flags = <0x57>; - reset-pin = <&usb_c1_bb_retimer_rst>; - ls-en-pin = <&usb_c1_bb_retimer_ls_en>; - }; virtual_mux_c1: virtual-mux-c1 { compatible = "cros-ec,usbc-mux-virtual"; }; @@ -63,22 +57,14 @@ port2@2 { compatible = "named-usbc-port"; reg = <2>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_2>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port2>; + usb_mux_chain_2: usb-mux-chain-2 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c2_bb_retimer + &virtual_mux_c2>; }; - usb-muxes = <&usb_c2_bb_retimer &virtual_mux_c2>; }; port2-muxes { - usb_c2_bb_retimer: jhl8040r-c2 { - compatible = "intel,jhl8040r"; - port = <&typec_2>; - i2c-addr-flags = <0x58>; - reset-pin = <&usb_c2_bb_retimer_rst>; - ls-en-pin = <&usb_c2_bb_retimer_ls_en>; - }; virtual_mux_c2: virtual-mux-c2 { compatible = "cros-ec,usbc-mux-virtual"; }; @@ -87,22 +73,14 @@ port3@3 { compatible = "named-usbc-port"; reg = <3>; - tcpc { - compatible = "fairchild,fusb302"; - status = "okay"; - port = <&typec_3>; - i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS"; + tcpc = <&tcpc_port3>; + usb_mux_chain_3: usb-mux-chain-3 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c3_bb_retimer + &virtual_mux_c3>; }; - usb-muxes = <&usb_c3_bb_retimer &virtual_mux_c3>; }; port3-muxes { - usb_c3_bb_retimer: jhl8040r-c3 { - compatible = "intel,jhl8040r"; - port = <&typec_3>; - i2c-addr-flags = <0x59>; - reset-pin = <&usb_c3_bb_retimer_rst>; - ls-en-pin = <&usb_c3_bb_retimer_ls_en>; - }; virtual_mux_c3: virtual-mux-c3 { compatible = "cros-ec,usbc-mux-virtual"; }; diff --git a/zephyr/projects/intelrvp/adlrvp/battery.dts b/zephyr/projects/intelrvp/adlrvp/battery.dts index 10b43d6baa..1de4111791 100644 --- a/zephyr/projects/intelrvp/adlrvp/battery.dts +++ b/zephyr/projects/intelrvp/adlrvp/battery.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h index 0061b11110..135fd4ef4f 100644 --- a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h +++ b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,27 +10,25 @@ #include "config.h" +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 - -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 - +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 /* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 #endif -#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 -#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 -#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) #define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT diff --git a/zephyr/projects/intelrvp/adlrvp/ioex.dts b/zephyr/projects/intelrvp/adlrvp/ioex.dts index 93117de943..3e2227dacb 100644 --- a/zephyr/projects/intelrvp/adlrvp/ioex.dts +++ b/zephyr/projects/intelrvp/adlrvp/ioex.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/adlrvp/prj.conf b/zephyr/projects/intelrvp/adlrvp/prj.conf index 357b0bee66..1314277bc8 100644 --- a/zephyr/projects/intelrvp/adlrvp/prj.conf +++ b/zephyr/projects/intelrvp/adlrvp/prj.conf @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -71,4 +71,4 @@ CONFIG_GPIO_PCA95XX=y CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y # eSPI -CONFIG_PLATFORM_EC_ESPI_DEFAULT_VW_WIDTH_US=150 +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150 diff --git a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c index bcb9bba1a8..ce5196c60d 100644 --- a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c +++ b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -29,9 +29,8 @@ #include "usbc_ppc.h" #include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) /* TCPC AIC GPIO Configuration */ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { @@ -96,27 +95,6 @@ struct ppc_config_t ppc_chips[] = { BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); -/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */ -static struct usb_mux soc_side_bb_retimer0_usb_mux = { - .usb_port = TYPE_C_PORT_0, - .next_mux = USB_MUX_NEXT_POINTER(DT_NODELABEL(usbc_port0), 0), - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, -}; - -#if defined(HAS_TASK_PD_C1) -static struct usb_mux soc_side_bb_retimer1_usb_mux = { - .usb_port = TYPE_C_PORT_1, - .next_mux = USB_MUX_NEXT_POINTER(DT_NODELABEL(usbc_port1), 0), - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, -}; -#endif - /* Cache BB retimer power state */ static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -124,8 +102,8 @@ void board_overcurrent_event(int port, int is_overcurrented) { /* Port 0 & 1 and 2 & 3 share same line for over current indication */ #if defined(HAS_TASK_PD_C2) - enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? - IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC; + enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC : + IOEX_USB_C2_C3_OC; #else enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; #endif @@ -211,11 +189,11 @@ void set_charger_system_voltage(void) * on AC or AC+battery */ if (extpower_is_present() && battery_is_present()) { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_min); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_min); } else { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_max); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_max); } break; @@ -224,8 +202,7 @@ void set_charger_system_voltage(void) break; } } -DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT); static void configure_charger(void) { @@ -246,26 +223,29 @@ static void configure_charger(void) static void configure_retimer_usbmux(void) { + struct usb_mux *mux; + switch (ADL_RVP_BOARD_ID(board_get_version())) { case ADLN_LP5_ERB_SKU_BOARD_ID: case ADLN_LP5_RVP_SKU_BOARD_ID: /* enable TUSB1044RNQR redriver on Port0 */ - usb_muxes[TYPE_C_PORT_0].i2c_addr_flags = - TUSB1064_I2C_ADDR14_FLAGS; - usb_muxes[TYPE_C_PORT_0].driver = - &tusb1064_usb_mux_driver; - usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update; + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_0), 0); + mux->i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS; + mux->driver = &tusb1064_usb_mux_driver; + mux->hpd_update = tusb1044_hpd_update; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].driver = NULL; - usb_muxes[TYPE_C_PORT_1].hpd_update = NULL; + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_1), 0); + mux->driver = NULL; + mux->hpd_update = NULL; #endif break; case ADLP_LP5_T4_RVP_SKU_BOARD_ID: /* No retimer on Port-2 */ #if defined(HAS_TASK_PD_C2) - usb_muxes[TYPE_C_PORT_2].driver = NULL; + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_2), 0); + mux->driver = NULL; #endif break; @@ -275,15 +255,13 @@ static void configure_retimer_usbmux(void) * Change the default usb mux config on runtime to support * dual retimer topology. */ - usb_muxes[TYPE_C_PORT_0].next_mux - = &soc_side_bb_retimer0_usb_mux; + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_0); #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].next_mux - = &soc_side_bb_retimer1_usb_mux; + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_1); #endif break; - /* Add additional board SKUs */ + /* Add additional board SKUs */ default: break; @@ -357,8 +335,7 @@ __override int board_get_version(void) * This loop retries to ensure rail is settled and read is successful */ for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { - - rv = gpio_pin_get_dt(&bom_id_config[0]); + rv = gpio_pin_get_dt(&bom_id_config[0]); if (rv >= 0) break; @@ -374,21 +351,21 @@ __override int board_get_version(void) * BOM ID [2] : IOEX[0] * BOM ID [1:0] : IOEX[15:14] */ - bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; + bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1; bom_id |= gpio_pin_get_dt(&bom_id_config[2]); /* * FAB ID [1:0] : IOEX[2:1] + 1 */ - fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; + fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; fab_id |= gpio_pin_get_dt(&fab_id_config[1]); fab_id += 1; /* * BOARD ID[5:0] : IOEX[13:8] */ - board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; + board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4; board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3; board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2; @@ -450,4 +427,4 @@ static int board_pre_task_peripheral_init(const struct device *unused) return 0; } SYS_INIT(board_pre_task_peripheral_init, APPLICATION, - CONFIG_APPLICATION_INIT_PRIORITY); + CONFIG_APPLICATION_INIT_PRIORITY); diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h deleted file mode 100644 index 3263007880..0000000000 --- a/zephyr/projects/intelrvp/include/gpio_map.h +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#define GPIO_EN_PP5000 GPIO_UNIMPLEMENTED -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A - -/* TODO: Implement GPIO_ENTERING_RW in IOEX */ -#ifdef CONFIG_BOARD_MTLRVP_NPCX -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#endif /* CONFIG_BOARD_MTLRVP_NPCK */ - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/intelrvp/include/intel_rvp_board_id.h b/zephyr/projects/intelrvp/include/intel_rvp_board_id.h index a527b19364..7825b272e3 100644 --- a/zephyr/projects/intelrvp/include/intel_rvp_board_id.h +++ b/zephyr/projects/intelrvp/include/intel_rvp_board_id.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/include/intelrvp.h b/zephyr/projects/intelrvp/include/intelrvp.h index ad6d12ae6f..9b6dc98485 100644 --- a/zephyr/projects/intelrvp/include/intelrvp.h +++ b/zephyr/projects/intelrvp/include/intelrvp.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,7 +10,7 @@ #include "stdbool.h" /* RVP ID read retry count */ -#define RVP_VERSION_READ_RETRY_CNT 2 +#define RVP_VERSION_READ_RETRY_CNT 2 #define DC_JACK_MAX_VOLTAGE_MV 19000 diff --git a/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf index cdcfbc2b13..331afb637d 100644 --- a/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf +++ b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -9,5 +9,4 @@ CONFIG_PLATFORM_EC_POWERSEQ_INTEL=y CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y CONFIG_PLATFORM_EC_POWERSEQ_S4=y -CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y CONFIG_PLATFORM_EC_THROTTLE_AP=y diff --git a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt index 75015a1068..c6729af776 100644 --- a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt +++ b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt @@ -1,5 +1,6 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. zephyr_library_sources("src/mtlrvp.c") +zephyr_library_sources("src/board_power.c") diff --git a/zephyr/projects/intelrvp/mtlrvp/ioex.dts b/zephyr/projects/intelrvp/mtlrvp/ioex.dts index bf79b12570..7d2f4b5820 100644 --- a/zephyr/projects/intelrvp/mtlrvp/ioex.dts +++ b/zephyr/projects/intelrvp/mtlrvp/ioex.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,7 +7,7 @@ /* IOEX_KBD_GPIO IT8801 */ ioex-kbd-gpio { compatible = "cros,ioex-chip"; - i2c-port = <&battery>; + i2c-port = <&i2c_charger>; i2c-addr = <0x39>; drv = "it8801_ioexpander_drv"; flags = <0x00>; @@ -30,4 +30,42 @@ ngpios = <8>; }; }; + /* IOEX_C2_CCGXXF */ + ioex-c2 { + compatible = "cros,ioex-chip"; + i2c-port = <&typec_aic2>; + i2c-addr = <0x0B>; + drv = "ccgxxf_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + ioex_c2_port0: ioex-c2-port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port1: ioex-c2-port@1 { + compatible = "cros,ioex-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port2: ioex-c2-port@2 { + compatible = "cros,ioex-port"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port3: ioex-c2-port@3 { + compatible = "cros,ioex-port"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts index 99c2cf10d0..cf85dd3413 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - pwm-frequency = <30000>; rpm_min = <3200>; rpm_start = <2200>; rpm_max = <6600>; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts index 49a40c6a54..77b4cf0573 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,7 +20,7 @@ enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; }; rsmrst_pwrgd: rsmrst-pwrgd { - gpios = <&gpio6 6 GPIO_INPUT>; /* 1.8V */ + gpios = <&gpio6 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; enum-name = "GPIO_PG_EC_RSMRST_ODL"; }; pch_slp_s0_n: pch-slp-s0-n-ec { @@ -53,32 +53,33 @@ gpio_wp: wp-l { gpios = <&gpiod 5 GPIO_INPUT>; }; - std-adp-prsnt { + std_adp_prsnt: std-adp-prsnt { gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_DC_JACK_PRESENT"; }; bc_acok: bc-acok-ec { gpios = <&gpio0 2 GPIO_INPUT>; enum-name = "GPIO_AC_PRESENT"; }; - usbc-tcpc-alrt-p0 { + usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { gpios = <&gpio4 0 GPIO_INPUT>; }; /* NOTE: Netname is USBC_TCPC_PPC_ALRT_P0 */ - usb-c0-c1-tcpc-rst-odl { + usb_c0_c1_tcpc_rst_odl: usb-c0-c1-tcpc-rst-odl { gpios = <&gpiod 0 GPIO_ODR_HIGH>; }; /* NOTE: Netname is USBC_TCPC_ALRT_P1 */ - usbc-tcpc-ppc-alrt-p0 { + usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { gpios = <&gpiod 1 GPIO_INPUT>; }; - usbc-tcpc-ppc-alrt-p1 { + usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { gpios = <&gpioe 4 GPIO_INPUT>; }; - usbc-tcpc-alrt-p2 { + usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 { gpios = <&gpio9 1 GPIO_INPUT>; }; /* NOTE: Netname is USBC_TCPC_PPC_ALRT_P3 */ - usbc-tcpc-ppc-alrt-p3 { + usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 { gpios = <&gpiof 3 GPIO_INPUT>; }; gpio_ec_pch_wake_odl: pch-wake-n { @@ -97,11 +98,11 @@ gpios = <&gpio6 0 GPIO_INPUT>; enum-name = "GPIO_CPU_PROCHOT"; }; - sys-rst-odl-ec { + sys_rst_odl: sys-rst-odl-ec { gpios = <&gpioc 5 GPIO_ODR_HIGH>; enum-name = "GPIO_SYS_RESET_L"; }; - pm-rsmrst-r-n { + ec_pch_rsmrst_l: pm-rsmrst-r-n { gpios = <&gpioa 4 GPIO_OUTPUT_LOW>; /* 1.8V */ enum-name = "GPIO_PCH_RSMRST_L"; }; @@ -112,11 +113,12 @@ ec_spi_oe_mecc: ec-spi-oe-mecc-r { gpios = <&gpioa 7 GPIO_OUTPUT_LOW>; /* 1.8V */ }; - ec-ds3-r { + en_pp3300_a: ec-ds3-r { gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; enum-name = "GPIO_EN_PP3300_A"; + alias = "GPIO_TEMP_SENSOR_POWER"; }; - pch-pwrok-ec-r { + ec_pch_pwrok_od: pch-pwrok-ec-r { gpios = <&gpiod 3 GPIO_ODR_LOW>; enum-name = "GPIO_PCH_PWROK"; }; @@ -142,8 +144,9 @@ gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; }; /* NOTE: Netname is USBC_TCPC_ALRT_P3 */ - ccd-mode-odl { + ccd_mode_odl: ccd-mode-odl { gpios = <&gpio9 2 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; }; smb-bs-clk { gpios = <&gpiob 3 GPIO_INPUT>; @@ -158,10 +161,10 @@ gpios = <&gpiob 4 GPIO_INPUT>; }; usbc-tcpc-i2c-clk-aic2 { - gpios = <&gpio9 0 GPIO_INPUT>; + gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; usbc-tcpc-i2c-data-aic2 { - gpios = <&gpio8 7 GPIO_INPUT>; + gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; /* Unused 1.8V pins */ i3c-1-sda-r { @@ -189,22 +192,22 @@ gpios = <&gpioa 6 GPIO_INPUT>; }; sml1-clk-mecc { - gpios = <&gpio3 3 GPIO_INPUT>; + gpios = <&gpio3 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; sml1-data-mecc { - gpios = <&gpio3 6 GPIO_INPUT>; + gpios = <&gpio3 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; sml1-alert { - gpios = <&gpioc 7 GPIO_INPUT>; + gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; smb-pch-alrt { gpios = <&gpioa 3 GPIO_INPUT>; }; smb-pch-data { - gpios = <&gpioc 1 GPIO_INPUT>; + gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; smb-pch-clk { - gpios = <&gpioc 2 GPIO_INPUT>; + gpios = <&gpioc 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; /* Unused 3.3V pins */ cpu-cat-err-mecc { @@ -255,7 +258,7 @@ tp-gpiof1 { gpios = <&gpiof 1 GPIO_INPUT>; }; - usbc-tcpc-ppc-alrt-p2 { + usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 { gpios = <&gpiof 2 GPIO_INPUT>; }; tp-gpiof4 { @@ -285,80 +288,79 @@ }; /* USB C IOEX configuration */ - usb-c0-hbr-ls-en { + usb_c0_hb_retimer_ls_en: usb-c0-hbr-ls-en { gpios = <&ioex_c0 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_HBR_LS_EN"; + no-auto-init; }; - usb-c0-hbr-rst { + usb_c0_hb_retimer_rst: usb-c0-hbr-rst { gpios = <&ioex_c0 3 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_HBR_RST"; + no-auto-init; }; - usb-c1-hbr-ls-en { + usb_c1_hb_retimer_ls_en: usb-c1-hbr-ls-en { gpios = <&ioex_c1 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HBR_LS_EN"; + no-auto-init; }; - usb-c1-hbr-rst { + usb_c1_hb_retimer_rst: usb-c1-hbr-rst { gpios = <&ioex_c1 3 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HBR_RST"; + no-auto-init; }; usb-c0-mux-oe-n { gpios = <&ioex_c0 4 GPIO_OUTPUT_LOW>; + no-auto-init; }; usb-c0-mux-sbu-sel-0 { gpios = <&ioex_c0 6 GPIO_OUTPUT_HIGH>; + enum-name = "IOEX_USB_C0_MUX_SBU_SEL_0"; + no-auto-init; }; usb-c0-mux-sbu-sel-1 { gpios = <&ioex_c1 4 GPIO_OUTPUT_LOW>; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = < - &lvol_io66 /* RSMRET_PWRGD */ - &lvol_io90 /* I2C1_SCL0 */ - &lvol_io87 /* I2C1_SDA0 */ - &lvol_io33 /* SML1_CLK_MECC */ - &lvol_io36 /* SML1_DATA_MECC */ - &lvol_ioc7 /* SML1_ALERT */ - &lvol_ioc1 /* SMB_PCH_DATA */ - &lvol_ioc2 /* SMB_PCH_CLK */ - >; - }; -}; - -&i2c0_0 { - nct38xx_C0:nct38xx_C0@70 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nuvoton,nct38xx-gpio"; - reg = <0x70>; - label = "NCT38XX_C0"; - - ioex_c0:gpio@0 { - compatible = "nuvoton,nct38xx-gpio-port"; - reg = <0x0>; - label = "NCT38XX_C0_GPIO0"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - pin_mask = <0xff>; - pinmux_mask = <0xf7>; - }; - }; - - nct38xx_C1:nct38xx_C1@70 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nuvoton,nct38xx-gpio"; - reg = <0x70>; - label = "NCT38XX_C1"; - - ioex_c1:gpio@0 { - compatible = "nuvoton,nct38xx-gpio-port"; - reg = <0x0>; - label = "NCT38XX_C1_GPIO0"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - pin_mask = <0xff>; - pinmux_mask = <0xf7>; + enum-name = "IOEX_USB_C0_MUX_SBU_SEL_1"; + no-auto-init; + }; + usb-c0-c1-prochot-n { + gpios = <&ioex_c1 6 GPIO_INPUT>; + no-auto-init; + }; + dg-bssb-sbu-sel { + gpios = <&ioex_c2_port1 4 GPIO_INPUT>; + no-auto-init; + }; + usb_c2_hb_retimer_rst: usb-c2-hbr-rst { + gpios = <&ioex_c2_port1 1 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C2_HBR_RST"; + no-auto-init; + }; + usb_c2_hb_retimer_ls_en: usb-c2-hbr-ls-en { + gpios = <&ioex_c2_port2 0 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C2_HBR_LS_EN"; + no-auto-init; + }; + usb_c3_hb_retimer_rst: usb-c3-hbr-rst { + gpios = <&ioex_c2_port1 3 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C3_HBR_RST"; + no-auto-init; + }; + usb_c3_hb_retimer_ls_en: usb-c3-hbr-ls-en { + gpios = <&ioex_c2_port3 3 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C3_HBR_LS_EN"; + no-auto-init; + }; + usb-c2-c3-prochot-n { + gpios = <&ioex_c2_port0 0 GPIO_INPUT>; + no-auto-init; + }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; }; }; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts index 234acb3447..b120f6c05e 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,25 +21,40 @@ flags = <GPIO_INT_EDGE_BOTH>; handler = "extpower_interrupt"; }; - int_slp_s0: slp_s0 { - irq-pin = <&pch_slp_s0_n>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "power_signal_interrupt"; - }; - int_rsmrst_pwrgd: rsmrst_pwrgd { - irq-pin = <&rsmrst_pwrgd>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "power_signal_interrupt"; - }; - int_all_sys_pwrgd: all_sys_pwrgd { - irq-pin = <&all_sys_pwrgd>; - flags = <GPIO_INT_EDGE_BOTH>; - handler = "power_signal_interrupt"; - }; int_ioex_kbd_intr_n: ioex_kbd_intr_n { irq-pin = <&ioex_kbd_intr_n>; flags = <GPIO_INT_EDGE_FALLING>; handler = "io_expander_it8801_interrupt"; }; + int_usb_c0_c1_tcpc: usb_c0_tcpc { + irq-pin = <&usbc_tcpc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&usbc_tcpc_ppc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_ppc: usb_c1_ppc { + irq-pin = <&usbc_tcpc_ppc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c2_tcpc: usb_c2_tcpc { + irq-pin = <&usbc_tcpc_alrt_p2>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c3_tcpc: usb_c3_tcpc { + irq-pin = <&usbc_tcpc_alrt_p3>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_ccd_mode: ccd_mode { + irq-pin = <&ccd_mode_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_connect_c0_sbu"; + }; }; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts index e735234128..81d6e82f48 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts index 8ff2efd460..86a46e3e7a 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts @@ -1,8 +1,10 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ + #include <dt-bindings/usb_pd_tcpm.h> + / { chosen { cros,rtc = &mtc; @@ -20,33 +22,21 @@ named-i2c-ports { compatible = "named-i2c-ports"; - battery: battery { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_BATTERY"; - }; - charger { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - }; - eeprom { + i2c_charger: charger { i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - keyboard { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_KB_DISCRETE"; - }; - port80 { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_PORT80"; + enum-names = "I2C_PORT_CHARGER", + "I2C_PORT_BATTERY", + "I2C_PORT_EEPROM", + "I2C_PORT_KB_DISCRETE", + "I2C_PORT_PORT80"; }; typec_aic1: typec-aic1{ i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_TYPEC_AIC_1"; + enum-names = "I2C_PORT_TYPEC_AIC_1"; }; typec_aic2: typec-aic2{ - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_TYPEC_AIC_2"; + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_TYPEC_AIC_2"; }; }; @@ -54,22 +44,18 @@ compatible = "named-adc-channels"; adc_ambient: ambient { - label = "ADC_TEMP_SNS_AMBIENT"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 3>; }; adc_ddr: ddr { - label = "ADC_TEMP_SNS_DDR"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 4>; }; adc_skin: skin { - label = "ADC_TEMP_SNS_SKIN"; enum-name = "ADC_TEMP_SENSOR_3"; io-channels = <&adc0 2>; }; adc_vr: vr { - label = "ADC_TEMP_SNS_VR"; enum-name = "ADC_TEMP_SENSOR_4"; io-channels = <&adc0 1>; }; @@ -78,6 +64,7 @@ /* charger */ &i2c7_0 { + label = "I2C_CHARGER"; status = "okay"; clock-frequency = <I2C_BITRATE_STANDARD>; pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; @@ -116,7 +103,6 @@ kb_discrete: ite-it8801@39 { compatible = "ite,it8801"; reg = <0x39>; - label = "KEYBOARD_DISCRETE"; }; seven_seg_display: max695x-seven-seg-display@38 { @@ -124,6 +110,21 @@ reg = <0x38>; label = "MAX695X_SEVEN_SEG_DISPLAY"; }; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; }; /* host interface */ @@ -139,10 +140,86 @@ /* typec_aic1 */ &i2c0_0 { + label = "I2C_USB_C0_C1_TCPC"; status = "okay"; clock-frequency = <I2C_BITRATE_FAST>; pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; pinctrl-names = "default"; + + tcpc_port0: nct38xx@73 { + compatible = "nuvoton,nct38xx"; + reg = <0x73>; + gpio-dev = <&nct38xx_c0>; + tcpc-flags = <( + TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>; + }; + + nct38xx_c0: nct38xx_c0@73 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x73>; + label = "NCT38XX_C0"; + + ioex_c0:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT38XX_C0_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; + }; + }; + + tcpc_port1: nct38xx@77 { + compatible = "nuvoton,nct38xx"; + reg = <0x77>; + gpio-dev = <&nct38xx_c1>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct38xx_c1: nct38xx_c1@77 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x77>; + label = "NCT38XX_C1"; + + ioex_c1:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT38XX_C1_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; + }; + }; + + nct38xx_alert_0 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct38xx_c0 &nct38xx_c1>; + label = "NCT38XX_ALERT_1"; + }; + + usb_c0_hb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + reset-pin = <&usb_c0_hb_retimer_rst>; + ls-en-pin = <&usb_c0_hb_retimer_ls_en>; + }; + + usb_c1_hb_retimer: jhl8040r-c1@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + reset-pin = <&usb_c1_hb_retimer_rst>; + ls-en-pin = <&usb_c1_hb_retimer_ls_en>; + }; }; &i2c_ctrl0 { @@ -150,14 +227,39 @@ }; /* typec_aic2 */ -&i2c2_0 { +&i2c1_0 { + label = "I2C_USB_C2_C3_TCPC"; status = "okay"; clock-frequency = <I2C_BITRATE_FAST>; - pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; pinctrl-names = "default"; + + tcpc_port2: ccgxxf@b { + compatible = "cypress,ccgxxf"; + reg = <0xb>; + }; + + tcpc_port3: ccgxxf@1b { + compatible = "cypress,ccgxxf"; + reg = <0x1b>; + }; + + usb_c2_hb_retimer: jhl8040r-c2@58 { + compatible = "intel,jhl8040r"; + reg = <0x58>; + reset-pin = <&usb_c2_hb_retimer_rst>; + ls-en-pin = <&usb_c2_hb_retimer_ls_en>; + }; + + usb_c3_hb_retimer: jhl8040r-c3@59 { + compatible = "intel,jhl8040r"; + reg = <0x59>; + reset-pin = <&usb_c3_hb_retimer_rst>; + ls-en-pin = <&usb_c3_hb_retimer_ls_en>; + }; }; -&i2c_ctrl2 { +&i2c_ctrl1 { status = "okay"; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts index 57b41bd9d2..42745d328b 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -98,15 +98,27 @@ * Because the power signals directly reference the GPIOs, * the correspinding named-gpios need to have no-auto-init set. */ -&sys_pwrok_ec { +&en_pp3300_a { no-auto-init; }; &rsmrst_pwrgd { no-auto-init; }; -&all_sys_pwrgd { +&ec_pch_rsmrst_l { no-auto-init; }; &pch_slp_s0_n { no-auto-init; }; +&ec_pch_pwrok_od { + no-auto-init; +}; +&sys_pwrok_ec { + no-auto-init; +}; +&sys_rst_odl { + no-auto-init; +}; +&all_sys_pwrgd { + no-auto-init; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf index 9a90e99a38..45b101a7ac 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf index 607bf3a9d1..5781a274c5 100644 --- a/zephyr/projects/intelrvp/mtlrvp/prj.conf +++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf @@ -1,30 +1,40 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # Power Sequencing CONFIG_AP_X86_INTEL_MTL=y +CONFIG_X86_NON_DSX_PWRSEQ_MTL=y CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n -CONFIG_PLATFORM_EC_POWERSEQ_METEORLAKE=y # Battery CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y +CONFIG_PLATFORM_EC_BATTERY_V2=y # CBI CONFIG_EEPROM=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_SHELL=n CONFIG_PLATFORM_EC_CBI_EEPROM=y +CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y -# USB-C and charging -# Below config are disabled to successfully compile battery conf -# This will be enabled in upcoming CL -CONFIG_PLATFORM_EC_USBC=n -CONFIG_PLATFORM_EC_CHARGER=n +# Disable BC1.2 +CONFIG_PLATFORM_EC_USB_CHARGER=n + +# Charger +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10 +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=n +CONFIG_PLATFORM_EC_CHARGER_ISL9241=y +CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y # IOEX CONFIG_PLATFORM_EC_IOEX_CROS_DRV=y +CONFIG_PLATFORM_EC_IOEX_CCGXXF=y CONFIG_GPIO_PCA95XX=y CONFIG_GPIO_NCT38XX=y CONFIG_PLATFORM_EC_IOEX_IT8801=y @@ -39,8 +49,31 @@ CONFIG_PLATFORM_EC_THERMISTOR=y CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y # USB CONFIG +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_MUX_TASK=y +CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y +CONFIG_PLATFORM_EC_USBC_PPC=y +CONFIG_PLATFORM_EC_USB_PD_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_CCGXXF=y CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y +CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y +CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y +CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y +CONFIG_PLATFORM_EC_USBC_VCONN=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y +CONFIG_PLATFORM_EC_USB_PD_USB4=y +CONFIG_PLATFORM_EC_USB_PD_INT_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED=y # 7-Segment Display CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y diff --git a/zephyr/projects/intelrvp/mtlrvp/src/board_power.c b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c index 6e5253ac55..301402bf0f 100644 --- a/zephyr/projects/intelrvp/mtlrvp/src/board_power.c +++ b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -47,8 +47,9 @@ void board_ap_power_action_g3_s5(void) /* Turn on the PP3300_PRIM rail. */ power_signal_set(PWR_EN_PP3300_A, 1); - if (!power_wait_signals_timeout(IN_PGOOD_ALL_CORE, - AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) { + if (!power_wait_signals_timeout( + IN_PGOOD_ALL_CORE, + AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) { ap_power_ev_send_callbacks(AP_POWER_PRE_INIT); } } diff --git a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c index 0839f453b5..9d96a08712 100644 --- a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c +++ b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c @@ -1,19 +1,172 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "battery.h" +#include "battery_fuel_gauge.h" +#include "charger.h" #include "common.h" #include "console.h" +#include "driver/retimer/bb_retimer_public.h" +#include "driver/tcpm/ccgxxf.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/tcpm/tcpci.h" +#include "extpower.h" #include "gpio.h" +#include "gpio/gpio_int.h" +#include "hooks.h" #include "i2c.h" #include "intelrvp.h" #include "intel_rvp_board_id.h" +#include "ioexpander.h" +#include "isl9241.h" #include "keyboard_raw.h" #include "power/meteorlake.h" +#include "sn5s330.h" +#include "system.h" +#include "task.h" +#include "tusb1064.h" +#include "usb_mux.h" +#include "usbc_ppc.h" +#include "util.h" -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) + +/*******************************************************************/ +/* USB-C Configuration Start */ + +/* PPC */ +#define I2C_ADDR_SN5S330_P0 0x40 +#define I2C_ADDR_SN5S330_P1 0x41 + +/* IOEX ports */ +enum ioex_port { + IOEX_KBD = 0, +#if defined(HAS_TASK_PD_C2) + IOEX_C2_CCGXXF, +#endif + IOEX_COUNT +}; + +/* USB-C ports */ +enum usbc_port { + USBC_PORT_C0 = 0, + USBC_PORT_C1, +#if defined(HAS_TASK_PD_C2) + USBC_PORT_C2, + USBC_PORT_C3, +#endif + USBC_PORT_COUNT +}; +BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB-C PPC configuration */ +struct ppc_config_t ppc_chips[] = { + [USBC_PORT_C0] = { + .i2c_port = I2C_PORT_TYPEC_AIC_1, + .i2c_addr_flags = I2C_ADDR_SN5S330_P0, + .drv = &sn5s330_drv, + }, + [USBC_PORT_C1] = { + .i2c_port = I2C_PORT_TYPEC_AIC_1, + .i2c_addr_flags = I2C_ADDR_SN5S330_P1, + .drv = &sn5s330_drv, + }, +}; +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +/* TCPC AIC GPIO Configuration */ +const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { + [USBC_PORT_C0] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p0)), + .ppc_intr_handler = sn5s330_interrupt, + }, + [USBC_PORT_C1] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)), + .ppc_intr_handler = sn5s330_interrupt, + }, +#if defined(HAS_TASK_PD_C2) + [USBC_PORT_C2] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p2)), + /* No PPC alert for CCGXXF */ + }, + [USBC_PORT_C3] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p3)), + /* No PPC alert for CCGXXF */ + }, +#endif +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); + +static void board_connect_c0_sbu_deferred(void) +{ + enum pd_power_role prole; + + if (gpio_get_level(GPIO_CCD_MODE_ODL)) { + CPRINTS("Default AUX line connected"); + /* Default set the SBU lines to AUX mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1); + } else { + prole = pd_get_power_role(USBC_PORT_C0); + CPRINTS("%s debug device is attached", + prole == PD_ROLE_SINK ? "Servo V4C/SuzyQ" : "Intel"); + + if (prole == PD_ROLE_SINK) { + /* Set the SBU lines to Google CCD mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 1); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1); + } else { + /* Set the SBU lines to Intel CCD mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 0); + } + } +} +DECLARE_DEFERRED(board_connect_c0_sbu_deferred); + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* + * TODO: Meteorlake PCH does not use Physical GPIO for over current + * error, hence Send 'Over Current Virtual Wire' eSPI signal. + */ +} + +void board_reset_pd_mcu(void) +{ + /* Reset NCT38XX TCPC */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 0); + msleep(NCT38XX_RESET_HOLD_DELAY_MS); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 1); + nct38xx_reset_notify(0); + nct38xx_reset_notify(1); + + if (NCT3807_RESET_POST_DELAY_MS != 0) { + msleep(NCT3807_RESET_POST_DELAY_MS); + } + + /* NCT38XX chip uses gpio ioex */ + gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c0))); + gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c1))); + +#if defined(HAS_TASK_PD_C2) + /* Reset the ccgxxf ports only resetting 1 is required */ + ccgxxf_reset(USBC_PORT_C2); + + /* CCGXXF has ioex on port 2 */ + ioex_init(IOEX_C2_CCGXXF); +#endif +} + +void board_connect_c0_sbu(enum gpio_signal signal) +{ + hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0); +} /******************************************************************************/ /* KSO mapping for discrete keyboard */ @@ -65,8 +218,7 @@ __override int board_get_version(void) * This loop retries to ensure rail is settled and read is successful */ for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { - - rv = gpio_pin_get_dt(&bom_id_config[0]); + rv = gpio_pin_get_dt(&bom_id_config[0]); if (rv >= 0) break; @@ -82,20 +234,20 @@ __override int board_get_version(void) * BOM ID [2] : IOEX[0] * BOM ID [1:0] : IOEX[15:14] */ - bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; + bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1; bom_id |= gpio_pin_get_dt(&bom_id_config[2]); /* * FAB ID [1:0] : IOEX[2:1] + 1 */ - fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; + fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; fab_id |= gpio_pin_get_dt(&fab_id_config[1]); fab_id += 1; /* * BOARD ID[5:0] : IOEX[13:8] */ - board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; + board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4; board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3; board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2; @@ -107,3 +259,73 @@ __override int board_get_version(void) mtlrvp_board_id = board_id | (fab_id << 8); return mtlrvp_board_id; } + +static void board_int_init(void) +{ + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); + + /* Enable TCPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_c1_tcpc)); +#if defined(HAS_TASK_PD_C2) + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c2_tcpc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c3_tcpc)); +#endif + + /* Enable CCD Mode interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode)); +} + +static int board_pre_task_peripheral_init(const struct device *unused) +{ + ARG_UNUSED(unused); + + /* Only reset tcpc/pd if not sysjump */ + if (!system_jumped_late()) { + /* Initialize tcpc and all ioex */ + board_reset_pd_mcu(); + } + + /* Initialize all interrupts */ + board_int_init(); + + /* Make sure SBU are routed to CCD or AUX based on CCD status at init */ + board_connect_c0_sbu_deferred(); + + return 0; +} +SYS_INIT(board_pre_task_peripheral_init, APPLICATION, + CONFIG_APPLICATION_INIT_PRIORITY); + +/* + * Since MTLRVP has both PPC and TCPC ports override to check if the port + * is a PPC or non PPC port + */ +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + if (!board_port_has_ppc(port)) { + return tcpm_check_vbus_level(port, level); + } else if (level == VBUS_PRESENT) { + return pd_snk_is_vbus_provided(port); + } else { + return !pd_snk_is_vbus_provided(port); + } +} + +__override bool board_port_has_ppc(int port) +{ + bool ppc_port; + + switch (port) { + case USBC_PORT_C0: + case USBC_PORT_C1: + ppc_port = true; + break; + default: + ppc_port = false; + break; + } + + return ppc_port; +} diff --git a/zephyr/projects/intelrvp/mtlrvp/usbc.dts b/zephyr/projects/intelrvp/mtlrvp/usbc.dts new file mode 100644 index 0000000000..e4f3bdc465 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/usbc.dts @@ -0,0 +1,76 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + usbc_port0: port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_hb_retimer + &virtual_mux_c0>; + }; + }; + port0-muxes { + virtual_mux_c0: virtual-mux-c0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port1: port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c1_hb_retimer + &virtual_mux_c1>; + }; + }; + port1-muxes { + virtual_mux_c1: virtual-mux-c1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port2: port2@2 { + compatible = "named-usbc-port"; + reg = <2>; + tcpc = <&tcpc_port2>; + usb-mux-chain-2 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c2_hb_retimer + &virtual_mux_c2>; + }; + }; + port2-muxes { + virtual_mux_c2: virtual-mux-c2 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port3: port3@3 { + compatible = "named-usbc-port"; + reg = <3>; + tcpc = <&tcpc_port3>; + usb-mux-chain-3 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c3_hb_retimer + &virtual_mux_c3>; + }; + }; + port3-muxes { + virtual_mux_c3: virtual-mux-c3 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/prj.conf b/zephyr/projects/intelrvp/prj.conf index 51b9245200..a7dcdc77dd 100644 --- a/zephyr/projects/intelrvp/prj.conf +++ b/zephyr/projects/intelrvp/prj.conf @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -22,6 +22,9 @@ CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000 CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001 +#Power Sequencing +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y + # Host command CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y @@ -34,9 +37,9 @@ CONFIG_I2C=y # eSPI CONFIG_ESPI=y -CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3=y -CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y -CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y # Keyboard CONFIG_PLATFORM_EC_KEYBOARD=y @@ -50,6 +53,17 @@ CONFIG_PLATFORM_EC_CMD_BUTTON=n CONFIG_SENSOR=y CONFIG_SENSOR_SHELL=n +# Shell Commands +CONFIG_SHELL_HELP=y +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y +CONFIG_KERNEL_SHELL=y + +# Logging +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y + # TODO # Below conf are disabled to compile successfully # These will be enabled in upcoming CLs diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd.c b/zephyr/projects/intelrvp/src/chg_usb_pd.c new file mode 100644 index 0000000000..63a1853b4d --- /dev/null +++ b/zephyr/projects/intelrvp/src/chg_usb_pd.c @@ -0,0 +1,129 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Common USB PD charge configuration */ + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "gpio.h" +#include "hooks.h" +#include "intelrvp.h" +#include "tcpm/tcpci.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +bool is_typec_port(int port) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE); +#else + return !(port == CHARGE_PORT_NONE); +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +static inline int board_dc_jack_present(void) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + return gpio_get_level(GPIO_DC_JACK_PRESENT); +#else + return 0; +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +static void board_dc_jack_handle(void) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + struct charge_port_info charge_dc_jack; + + /* System is booted from DC Jack */ + if (board_dc_jack_present()) { + charge_dc_jack.current = + (PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV; + charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV; + } else { + charge_dc_jack.current = 0; + charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV; + } + + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + DEDICATED_CHARGE_PORT, &charge_dc_jack); +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +void board_dc_jack_interrupt(enum gpio_signal signal) +{ + board_dc_jack_handle(); +} + +static void board_charge_init(void) +{ + int port, supplier; + struct charge_port_info charge_init = { + .current = 0, + .voltage = USB_CHARGER_VOLTAGE_MV, + }; + + /* Initialize all charge suppliers to seed the charge manager */ + for (port = 0; port < CHARGE_PORT_COUNT; port++) { + for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; + supplier++) { + charge_manager_update_charge(supplier, port, + &charge_init); + } + } + + board_dc_jack_handle(); +} +DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT); + +int board_set_active_charge_port(int port) +{ + int i; + /* charge port is a realy physical port */ + int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT); + /* check if we are source vbus on that port */ + int source = board_vbus_source_enabled(port); + + if (is_real_port && source) { + CPRINTS("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + /* + * Do not enable Type-C port if the DC Jack is present. + * When the Type-C is active port, hardware circuit will + * block DC jack from enabling +VADP_OUT. + */ + if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) { + CPRINTS("DC Jack present, Skip enable p%d", port); + return EC_ERROR_INVAL; + } +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */ + + /* Make sure non-charging ports are disabled */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i != port) { + board_charging_enable(i, 0); + } + } + + /* Enable charging port */ + if (is_typec_port(port)) { + board_charging_enable(port, 1); + } + + CPRINTS("New chg p%d", port); + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c new file mode 100644 index 0000000000..45fbbc6f65 --- /dev/null +++ b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c @@ -0,0 +1,92 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel-RVP family-specific configuration */ + +#include "console.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "include/gpio.h" +#include "intelrvp.h" +#include "ioexpander.h" +#include "system.h" +#include "tcpm/tcpci.h" +#include "usbc_ppc.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +void tcpc_alert_event(enum gpio_signal signal) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* No alerts for embedded TCPC */ + if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) { + continue; + } + + if (signal == tcpc_aic_gpios[i].tcpc_alert) { + schedule_deferred_pd_interrupt(i); + break; + } + } +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int i; + + /* Check which port has the ALERT line set */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* No alerts for embdeded TCPC */ + if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) { + continue; + } + + if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert)) { + status |= PD_STATUS_TCPC_ALERT_0 << i; + } + } + + return status; +} + +int ppc_get_alert_status(int port) +{ + return tcpc_aic_gpios[port].ppc_intr_handler && + !gpio_get_level(tcpc_aic_gpios[port].ppc_alert); +} + +/* PPC support routines */ +void ppc_interrupt(enum gpio_signal signal) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (tcpc_aic_gpios[i].ppc_intr_handler && + signal == tcpc_aic_gpios[i].ppc_alert) { + tcpc_aic_gpios[i].ppc_intr_handler(i); + break; + } + } +} + +void board_charging_enable(int port, int enable) +{ + int rv; + + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_sink_enable(port, enable); + } else { + rv = tcpc_config[port].drv->set_snk_ctrl(port, enable); + } + + if (rv) { + CPRINTS("C%d: sink path %s failed", port, + enable ? "en" : "dis"); + } +} diff --git a/zephyr/projects/intelrvp/src/intel_rvp_board_id.c b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c index d4172a468e..77d4e93afd 100644 --- a/zephyr/projects/intelrvp/src/intel_rvp_board_id.c +++ b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,25 +9,22 @@ #define DT_DRV_COMPAT intel_rvp_board_id BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1, - "Unsupported RVP Board ID instance"); + "Unsupported RVP Board ID instance"); #define RVP_ID_GPIO_DT_SPEC_GET(idx, node_id, prop) \ GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx), -#define RVP_ID_CONFIG_LIST(node_id, prop) \ - LISTIFY(DT_PROP_LEN(node_id, prop), \ - RVP_ID_GPIO_DT_SPEC_GET, (), node_id, prop) +#define RVP_ID_CONFIG_LIST(node_id, prop) \ + LISTIFY(DT_PROP_LEN(node_id, prop), RVP_ID_GPIO_DT_SPEC_GET, (), \ + node_id, prop) #if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) -const struct gpio_dt_spec bom_id_config[] = { - RVP_ID_CONFIG_LIST(DT_DRV_INST(0), bom_gpios) -}; +const struct gpio_dt_spec bom_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0), + bom_gpios) }; -const struct gpio_dt_spec fab_id_config[] = { - RVP_ID_CONFIG_LIST(DT_DRV_INST(0), fab_gpios) -}; +const struct gpio_dt_spec fab_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0), + fab_gpios) }; -const struct gpio_dt_spec board_id_config[] = { - RVP_ID_CONFIG_LIST(DT_DRV_INST(0), board_gpios) -}; +const struct gpio_dt_spec board_id_config[] = { RVP_ID_CONFIG_LIST( + DT_DRV_INST(0), board_gpios) }; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ diff --git a/zephyr/projects/intelrvp/src/intel_rvp_led.c b/zephyr/projects/intelrvp/src/intel_rvp_led.c index b382dcc485..0e4d872963 100644 --- a/zephyr/projects/intelrvp/src/intel_rvp_led.c +++ b/zephyr/projects/intelrvp/src/intel_rvp_led.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,8 +26,8 @@ #define LED_PULSE_TICK (125 * MSEC) -#define LED_FAST_PULSE_PERIOD (250 / 125) /* 250 ms */ -#define LED_SLOW_PULSE_PERIOD ((2 * MSEC) / 125) /* 2 sec */ +#define LED_FAST_PULSE_PERIOD (250 / 125) /* 250 ms */ +#define LED_SLOW_PULSE_PERIOD ((2 * MSEC) / 125) /* 2 sec */ struct led_pulse_data { bool led_is_pulsing; @@ -56,13 +56,13 @@ static void pulse_led_deferred(void) * and in OFF state in second half of the pulse period. */ if (rvp_led[i].led_tick_count < - (rvp_led[i].led_pulse_period >> 1)) + (rvp_led[i].led_pulse_period >> 1)) set_pwm_led_color(i, EC_LED_COLOR_GREEN); else set_pwm_led_color(i, LED_OFF); rvp_led[i].led_tick_count = (rvp_led[i].led_tick_count + 1) % - rvp_led[i].led_pulse_period; + rvp_led[i].led_pulse_period; call_deferred = true; } @@ -73,7 +73,7 @@ static void pulse_led_deferred(void) static void pulse_leds(enum pwm_led_id id, int period) { rvp_led[id].led_pulse_period = period; - rvp_led[id].led_is_pulsing = true; + rvp_led[id].led_is_pulsing = true; pulse_led_deferred(); } @@ -96,7 +96,7 @@ static void update_charger_led(enum pwm_led_id id) rvp_led[id].led_is_pulsing = false; set_pwm_led_color(id, EC_LED_COLOR_GREEN); } else if (chg_st == PWR_STATE_DISCHARGE || - chg_st == PWR_STATE_DISCHARGE_FULL) { + chg_st == PWR_STATE_DISCHARGE_FULL) { if (extpower_is_present()) { /* Discharging: * Flash slower (2 second period, 100% duty cycle) diff --git a/zephyr/projects/intelrvp/src/intelrvp.c b/zephyr/projects/intelrvp/src/intelrvp.c index fd0514f438..7098f26cbf 100644 --- a/zephyr/projects/intelrvp/src/intelrvp.c +++ b/zephyr/projects/intelrvp/src/intelrvp.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c new file mode 100644 index 0000000000..a194b358f1 --- /dev/null +++ b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c @@ -0,0 +1,106 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "console.h" +#include "gpio.h" +#include "intelrvp.h" +#include "usb_mux.h" +#include "usbc_ppc.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +static inline void board_pd_set_vbus_discharge(int port, bool enable) +{ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + ppc_discharge_vbus(port, enable); + } else { + tcpc_discharge_vbus(port, enable); + } +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_sink_enable(port, 0); + } else { + rv = tcpc_config[port].drv->set_snk_ctrl(port, 0); + } + + if (rv) { + return rv; + } + + board_pd_set_vbus_discharge(port, false); + + /* Provide Vbus. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_source_enable(port, 1); + } else { + tcpc_config[port].drv->set_src_ctrl(port, 1); + } + + if (rv) { + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = board_vbus_source_enabled(port); + + /* Disable VBUS. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + ppc_vbus_source_enable(port, 0); + } else { + tcpc_config[port].drv->set_src_ctrl(port, 0); + } + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) { + board_pd_set_vbus_discharge(port, true); + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_check_vconn_swap(int port) +{ + /* Only allow vconn swap if PP3300 rail is enabled */ + return gpio_get_level(GPIO_EN_PP3300_A); +} + +int pd_snk_is_vbus_provided(int port) +{ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + return ppc_is_vbus_present(port); + } else { + return tcpc_config[port].drv->check_vbus_level(port, + VBUS_PRESENT); + } +} + +int board_vbus_source_enabled(int port) +{ + if (is_typec_port(port)) { + if (tcpc_aic_gpios[port].ppc_intr_handler) { + return ppc_is_sourcing_vbus(port); + } else { + return tcpc_config[port].drv->get_src_ctrl(port); + } + } + return 0; +} diff --git a/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf new file mode 100644 index 0000000000..1ef365a8fa --- /dev/null +++ b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf @@ -0,0 +1,9 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zephyr Inbuilt AP Power Sequencing Config +CONFIG_AP_PWRSEQ=y +CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y +CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y +CONFIG_AP_PWRSEQ_S0IX=y |