diff options
Diffstat (limited to 'zephyr/projects/nissa/gpio_nivviks.dts')
| -rw-r--r-- | zephyr/projects/nissa/gpio_nivviks.dts | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/zephyr/projects/nissa/gpio_nivviks.dts b/zephyr/projects/nissa/gpio_nivviks.dts new file mode 100644 index 0000000000..7f4af90de5 --- /dev/null +++ b/zephyr/projects/nissa/gpio_nivviks.dts @@ -0,0 +1,144 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-gpios { + compatible = "named-gpios"; + + lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + label = "LID_OPEN"; + }; + + gsc_ec_pwr_btn_odl: power_btn { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + label = "GSC_EC_PWR_BTN_ODL"; + }; + + wp_l { + gpios = <&gpioa 1 GPIO_INPUT>; + enum-name = "GPIO_WP_L"; + label = "EC_WP_ODL"; + }; + + ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + label = "EC_ENTERING_RW"; + }; + + packet_mode_en { + gpios = <&gpio7 5 GPIO_OUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + label = "EC_GSC_PACKET_MODE"; + }; + ec_kso_02_inv { + gpios = <&gpio1 7 GPIO_OUT_LOW>; + enum-name = "GPIO_KBD_KSO2"; + label = "EC_KSO_02_INV"; + }; + pg_ec_dsw_pwrok { + gpios = <&gpio6 1 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_DSW_PWROK"; + label = "EC_SOC_DSW_PWROK"; + }; + sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_SYS_RESET_L"; + label = "SYS_RST_ODL"; + }; + pg_ec_rsmrst_odl { + gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_RSMRST_ODL"; + label = "RSMRST_PWRGD_L"; + }; + ec_pch_rsmrst_odl { + gpios = <&gpioa 6 GPIO_OUT_LOW>; + enum-name = "GPIO_PCH_RSMRST_L"; + label = "RSMRST_PWRGD_L"; + }; + pg_ec_all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; + label = "ALL_SYS_PWRGD"; + }; + pch_wake_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_PCH_WAKE_ODL"; + label = "EC_PCH_WAKE_R_ODL"; + }; + slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S0_L"; + label = "SLP_S0_L"; + }; + slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S3_L"; + label = "SLP_S3_L"; + }; + vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_LOW>; + enum-name = "GPIO_VCCST_PWRGD_OD"; + label = "EC_SOC_VCCST_PWRGD_OD"; + }; + ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_CPU_PROCHOT"; + label = "EC_PROCHOT_ODL"; + }; + ec_pch_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + label = "EC_SOC_PWR_BTN_ODL"; + }; + slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + enum-name = "GPIO_SLP_SUS_L"; + label = "SLP_SUS_L"; + }; + pch_pwrok { + gpios = <&gpio3 7 GPIO_OUT_LOW>; + enum-name = "GPIO_PCH_PWROK"; + label = "EC_SOC_SYS_PWROK"; + }; + ec_pch_sys_pwrok { + gpios = <&gpio7 2 GPIO_ODR_LOW>; + enum-name = "GPIO_EC_PCH_SYS_PWROK"; + label = "EC_SOC_PCH_PWROK_OD"; + }; + ec_edp_bl_en { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + label = "EC_EDP_BL_EN"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-pins = < + &gsc_ec_pwr_btn_odl + &lid_open + >; + }; +}; + +/* Power switch logic input pads */ +/* LID_OPEN_OD */ +&psl_in1 { + flag = <NPCX_PSL_RISING_EDGE>; +}; + +/* ACOK_EC_OD */ +&psl_in2 { + flag = <NPCX_PSL_RISING_EDGE>; +}; + +/* GSC_EC_PWR_BTN_ODL */ +&psl_in3 { + flag = <NPCX_PSL_FALLING_EDGE>; +}; |