diff options
Diffstat (limited to 'zephyr/projects')
65 files changed, 2352 insertions, 306 deletions
diff --git a/zephyr/projects/brya/keyboard.dts b/zephyr/projects/brya/keyboard.dts index 88b8ba8c65..4f06764810 100644 --- a/zephyr/projects/brya/keyboard.dts +++ b/zephyr/projects/brya/keyboard.dts @@ -16,3 +16,31 @@ pinctrl-0 = <&pwm3_gp80>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/brya/prj.conf b/zephyr/projects/brya/prj.conf index 931053c5f2..7ce897ae5f 100644 --- a/zephyr/projects/brya/prj.conf +++ b/zephyr/projects/brya/prj.conf @@ -92,7 +92,7 @@ CONFIG_PLATFORM_EC_HIBERNATE_PSL=y # MKBP event CONFIG_PLATFORM_EC_MKBP_EVENT=y CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y -CONFIG_PLATFORM_EC_MKBP_USE_HOST_EVENT=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y # PMIC CONFIG_PLATFORM_EC_PMIC=y diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index c75418f294..83ad865cb1 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -58,6 +58,7 @@ register_corsola_project( here / "interrupts_kingler.dts", here / "cbi_eeprom.dts", here / "gpio_kingler.dts", + here / "npcx_keyboard.dts", here / "led_kingler.dts", here / "motionsense_kingler.dts", here / "usbc_kingler.dts", @@ -77,8 +78,10 @@ register_corsola_project( here / "interrupts_kingler.dts", here / "cbi_eeprom.dts", here / "gpio_steelix.dts", + here / "npcx_keyboard.dts", here / "led_steelix.dts", here / "motionsense_kingler.dts", + here / "motionsense_steelix.dts", here / "usba_steelix.dts", here / "usbc_kingler.dts", here / "default_gpio_pinctrl_kingler.dts", diff --git a/zephyr/projects/corsola/gpio_kingler.dts b/zephyr/projects/corsola/gpio_kingler.dts index 6ef6f02e03..0199f985fa 100644 --- a/zephyr/projects/corsola/gpio_kingler.dts +++ b/zephyr/projects/corsola/gpio_kingler.dts @@ -91,7 +91,7 @@ lid_accel_int_l { gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; - tablet_mode_l { + gpio_tablet_mode_l: tablet_mode_l { gpios = <&gpiob 2 GPIO_INPUT>; enum-name = "GPIO_TABLET_MODE_L"; }; diff --git a/zephyr/projects/corsola/gpio_steelix.dts b/zephyr/projects/corsola/gpio_steelix.dts index 29c1bbe75a..3e0375564f 100644 --- a/zephyr/projects/corsola/gpio_steelix.dts +++ b/zephyr/projects/corsola/gpio_steelix.dts @@ -98,7 +98,7 @@ lid_accel_int_l { gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; - tablet_mode_l { + gpio_tablet_mode_l: tablet_mode_l { gpios = <&gpiob 2 GPIO_INPUT>; enum-name = "GPIO_TABLET_MODE_L"; }; diff --git a/zephyr/projects/corsola/i2c_kingler.dts b/zephyr/projects/corsola/i2c_kingler.dts index 843367668e..c832e55d2e 100644 --- a/zephyr/projects/corsola/i2c_kingler.dts +++ b/zephyr/projects/corsola/i2c_kingler.dts @@ -17,6 +17,7 @@ }; i2c_usb_c0: usb-c0 { i2c-port = <&i2c1_0>; + remote-port = <7>; enum-name = "I2C_PORT_USB_C0"; }; i2c_usb_c1: usb-c1 { diff --git a/zephyr/projects/corsola/interrupts_kingler.dts b/zephyr/projects/corsola/interrupts_kingler.dts index ac7da13e75..b33251624d 100644 --- a/zephyr/projects/corsola/interrupts_kingler.dts +++ b/zephyr/projects/corsola/interrupts_kingler.dts @@ -100,5 +100,10 @@ flags = <GPIO_INT_EDGE_FALLING>; handler = "bmi3xx_interrupt"; }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; }; }; diff --git a/zephyr/projects/corsola/interrupts_krabby.dts b/zephyr/projects/corsola/interrupts_krabby.dts index ddc9639d2b..900ce1611e 100644 --- a/zephyr/projects/corsola/interrupts_krabby.dts +++ b/zephyr/projects/corsola/interrupts_krabby.dts @@ -61,7 +61,7 @@ flags = <GPIO_INT_EDGE_FALLING>; handler = "icm42607_interrupt"; }; - int_accel: accel { + int_lid_imu: lid_imu { irq-pin = <&lid_accel_int_l>; flags = <GPIO_INT_EDGE_FALLING>; handler = "lis2dw12_interrupt"; @@ -91,11 +91,6 @@ flags = <GPIO_INT_EDGE_BOTH>; handler = "x_ec_interrupt"; }; - int_base_imu: base_imu { - irq-pin = <&base_imu_int_l>; - flags = <GPIO_INT_EDGE_FALLING>; - handler = "icm42607_interrupt"; - }; int_usb_c0_ppc_bc12: usb_c0_ppc_bc12 { irq-pin = <&usb_c0_ppc_bc12_int_odl>; flags = <GPIO_INT_EDGE_FALLING>; diff --git a/zephyr/projects/corsola/led_steelix.dts b/zephyr/projects/corsola/led_steelix.dts index 56a54862e6..31d17958d4 100644 --- a/zephyr/projects/corsola/led_steelix.dts +++ b/zephyr/projects/corsola/led_steelix.dts @@ -6,31 +6,14 @@ / { pwmleds { compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED - &pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED - &pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + led_battery_red: ec_led1_odl { + pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <100>; - - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-amber = <100 20 0>; - - brightness-range = <255 255 0 0 0 255>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; + led_battery_green: ec_led2_odl { + pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + led_power_white: ec_led3_odl { + pwms = <&pwm4 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; }; }; }; @@ -59,14 +42,14 @@ pinctrl-names = "default"; }; -/* Blue LED */ -&pwm2_gpc4 { +/* White LED */ +&pwm4_gpb6 { drive-open-drain; }; -&pwm2 { +&pwm4 { status = "okay"; clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm2_gpc4>; + pinctrl-0 = <&pwm4_gpb6>; pinctrl-names = "default"; }; diff --git a/zephyr/projects/corsola/motionsense_krabby.dts b/zephyr/projects/corsola/motionsense_krabby.dts index 730f1a938e..d369db460a 100644 --- a/zephyr/projects/corsola/motionsense_krabby.dts +++ b/zephyr/projects/corsola/motionsense_krabby.dts @@ -150,8 +150,6 @@ * list of GPIO interrupts that have to * be enabled at initial stage */ - sensor-irqs = <&int_base_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; + sensor-irqs = <&int_base_imu &int_lid_imu>; }; }; diff --git a/zephyr/projects/corsola/motionsense_steelix.dts b/zephyr/projects/corsola/motionsense_steelix.dts new file mode 100644 index 0000000000..70aa3679fb --- /dev/null +++ b/zephyr/projects/corsola/motionsense_steelix.dts @@ -0,0 +1,17 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&lid_rot_ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; +}; + +&base_rot_ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; +}; + diff --git a/zephyr/projects/corsola/npcx_keyboard.dts b/zephyr/projects/corsola/npcx_keyboard.dts new file mode 100644 index 0000000000..d3fd354b8f --- /dev/null +++ b/zephyr/projects/corsola/npcx_keyboard.dts @@ -0,0 +1,32 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf index b9d07a7227..b26c01461e 100644 --- a/zephyr/projects/corsola/prj.conf +++ b/zephyr/projects/corsola/prj.conf @@ -15,7 +15,6 @@ CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y # MKBP -CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y CONFIG_PLATFORM_EC_MKBP_EVENT=y CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y @@ -30,6 +29,7 @@ CONFIG_PLATFORM_EC_USB_PD_USB4=n CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK=n # Power Seq +CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y diff --git a/zephyr/projects/corsola/prj_kingler.conf b/zephyr/projects/corsola/prj_kingler.conf index 191a104cde..525d94a886 100644 --- a/zephyr/projects/corsola/prj_kingler.conf +++ b/zephyr/projects/corsola/prj_kingler.conf @@ -74,9 +74,6 @@ CONFIG_PLATFORM_EC_MATH_UTIL=y CONFIG_AP=y CONFIG_AP_ARM_MTK_MT8186=y CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y - -# Treat 2nd reset from H1 as Power-On -CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y CONFIG_PLATFORM_EC_POWERSEQ=y CONFIG_PLATFORM_EC_POWERSEQ_S4=n CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n @@ -93,11 +90,14 @@ CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y CONFIG_PLATFORM_EC_ACCEL_FIFO=y CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y CONFIG_PLATFORM_EC_LID_ANGLE=y CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y CONFIG_PLATFORM_EC_LID_SWITCH=y CONFIG_PLATFORM_EC_MOTIONSENSE=y CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y # USBA CONFIG_PLATFORM_EC_USBA=y @@ -122,6 +122,7 @@ CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2 CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y diff --git a/zephyr/projects/corsola/prj_steelix.conf b/zephyr/projects/corsola/prj_steelix.conf index 5354381f9b..48971c9ed4 100644 --- a/zephyr/projects/corsola/prj_steelix.conf +++ b/zephyr/projects/corsola/prj_steelix.conf @@ -4,4 +4,10 @@ # Variant config CONFIG_BOARD_KINGLER=n -CONFIG_BOARD_STEELIX=y
\ No newline at end of file +CONFIG_BOARD_STEELIX=y + +# steelix only use D2, drop the workaround config for H1 +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n + +# LED +CONFIG_PLATFORM_EC_LED_PWM=n diff --git a/zephyr/projects/corsola/src/kingler/led_steelix.c b/zephyr/projects/corsola/src/kingler/led_steelix.c index a44f961441..2d2e1431a1 100644 --- a/zephyr/projects/corsola/src/kingler/led_steelix.c +++ b/zephyr/projects/corsola/src/kingler/led_steelix.c @@ -4,11 +4,26 @@ * * Battery LED control for Steelix */ + +#include <zephyr/drivers/pwm.h> +#include <zephyr/logging/log.h> + +#include "board_led.h" #include "common.h" -#include "ec_commands.h" #include "led_common.h" #include "led_onoff_states.h" -#include "led_pwm.h" +#include "util.h" + +LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR); + +#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(100) + +static const struct board_led_pwm_dt_channel board_led_battery_red = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_red)); +static const struct board_led_pwm_dt_channel board_led_battery_green = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_green)); +static const struct board_led_pwm_dt_channel board_led_power_white = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white)); __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; @@ -18,6 +33,7 @@ __override struct led_descriptor [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, @@ -26,20 +42,110 @@ __override struct led_descriptor {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, }; +__override const struct led_descriptor + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, + [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, + {LED_OFF, 0.5 * LED_ONE_SEC} }, + [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, + {LED_OFF, 0.5 * LED_ONE_SEC} }, + [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, +}; + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED, +}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, + int percent) +{ + uint32_t pulse_ns; + int rv; + + if (!device_is_ready(ch->dev)) { + LOG_ERR("PWM device %s not ready", ch->dev->name); + return; + } + + pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); + + LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", + ch->dev->name, percent, pulse_ns); + + rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, + ch->flags); + if (rv) { + LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv); + } +} + __override void led_set_color_battery(enum ec_led_colors color) { switch (color) { case EC_LED_COLOR_RED: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); + board_led_pwm_set_duty(&board_led_battery_red, 100); + board_led_pwm_set_duty(&board_led_battery_green, 0); break; case EC_LED_COLOR_GREEN: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_GREEN); + board_led_pwm_set_duty(&board_led_battery_red, 0); + board_led_pwm_set_duty(&board_led_battery_green, 100); break; case EC_LED_COLOR_AMBER: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + board_led_pwm_set_duty(&board_led_battery_red, 100); + board_led_pwm_set_duty(&board_led_battery_green, 20); break; default: /* LED_OFF and other unsupported colors */ - set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + board_led_pwm_set_duty(&board_led_battery_red, 0); + board_led_pwm_set_duty(&board_led_battery_green, 0); break; } } + +__override void led_set_color_power(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_WHITE: + board_led_pwm_set_duty(&board_led_power_white, 100); + break; + default: + board_led_pwm_set_duty(&board_led_power_white, 0); + break; + } +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + brightness_range[EC_LED_COLOR_RED] = 1; + brightness_range[EC_LED_COLOR_GREEN] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + } else if (led_id == EC_LED_ID_POWER_LED) { + brightness_range[EC_LED_COLOR_WHITE] = 1; + } +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + if (brightness[EC_LED_COLOR_RED] != 0) { + led_set_color_battery(EC_LED_COLOR_RED); + } else if (brightness[EC_LED_COLOR_GREEN] != 0) { + led_set_color_battery(EC_LED_COLOR_GREEN); + } else if (brightness[EC_LED_COLOR_AMBER] != 0) { + led_set_color_battery(EC_LED_COLOR_AMBER); + } else { + led_set_color_battery(LED_OFF); + } + } else if (led_id == EC_LED_ID_POWER_LED) { + if (brightness[EC_LED_COLOR_WHITE] != 0) { + led_set_color_power(EC_LED_COLOR_WHITE); + } else { + led_set_color_power(LED_OFF); + } + } + + return EC_SUCCESS; +} diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c index d710e36187..42aa0a31d6 100644 --- a/zephyr/projects/corsola/src/kingler/usbc_config.c +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -192,12 +192,6 @@ __override int board_rt1718s_init(int port) RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL, RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); - /* Turn on SBU switch */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, - RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | - RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN | - RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN, - 0xFF)); /* Trigger GPIO 1/2 change when FRS signal received */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3, RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | diff --git a/zephyr/projects/corsola/src/usb_pd_policy.c b/zephyr/projects/corsola/src/usb_pd_policy.c index cdcb49ff2e..c9015de776 100644 --- a/zephyr/projects/corsola/src/usb_pd_policy.c +++ b/zephyr/projects/corsola/src/usb_pd_policy.c @@ -8,6 +8,7 @@ #include "chipset.h" #include "hooks.h" #include "timer.h" +#include "typec_control.h" #include "usb_dp_alt_mode.h" #include "usb_mux.h" #include "usb_pd.h" @@ -112,6 +113,8 @@ __override void svdm_dp_post_config(int port) { mux_state_t mux_mode = svdm_dp_get_mux_mode(port); + typec_set_sbu(port, true); + /* * Prior to post-config, the mux will be reset to safe mode, and this * will break mux config and aux path config we did in the first DP diff --git a/zephyr/projects/herobrine/BUILD.py b/zephyr/projects/herobrine/BUILD.py index dd3eed1562..2a15441c55 100644 --- a/zephyr/projects/herobrine/BUILD.py +++ b/zephyr/projects/herobrine/BUILD.py @@ -51,6 +51,8 @@ register_variant( extra_dts_overlays=[ here / "battery_hoglin.dts", here / "gpio_hoglin.dts", + here / "led_pins_hoglin.dts", + here / "led_policy_hoglin.dts", here / "motionsense_hoglin.dts", here / "switchcap_hoglin.dts", here / "usbc_hoglin.dts", @@ -64,8 +66,8 @@ register_variant( extra_dts_overlays=[ here / "battery_villager.dts", here / "gpio_villager.dts", - here / "gpio_led_villager.dts", - here / "led_villager.dts", + here / "led_pins_villager.dts", + here / "led_policy_villager.dts", here / "motionsense_villager.dts", here / "switchcap.dts", here / "usbc_villager.dts", diff --git a/zephyr/projects/herobrine/CMakeLists.txt b/zephyr/projects/herobrine/CMakeLists.txt index 64102e951c..537fa5ef68 100644 --- a/zephyr/projects/herobrine/CMakeLists.txt +++ b/zephyr/projects/herobrine/CMakeLists.txt @@ -12,8 +12,6 @@ cros_ec_library_include_directories(include) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c" "src/usb_pd_policy.c") -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON - "src/led.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/i2c.c") diff --git a/zephyr/projects/herobrine/gpio_hoglin.dts b/zephyr/projects/herobrine/gpio_hoglin.dts index 6f2f05eacf..f0b8a43586 100644 --- a/zephyr/projects/herobrine/gpio_hoglin.dts +++ b/zephyr/projects/herobrine/gpio_hoglin.dts @@ -174,16 +174,18 @@ gpios = <&gpioc 1 GPIO_OUTPUT_LOW>; enum-name = "GPIO_USB_C1_FRS_EN"; }; - gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 { + gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 { + #led-pin-cells = <1>; gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; }; - gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 { + gpio_ec_chg_led_r_c0: ec_chg_led_r_c0 { + #led-pin-cells = <1>; gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; }; - gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 { + gpio_ec_chg_led_y_c1: ec_chg_led_b_c1 { gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; }; - gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 { + gpio_ec_chg_led_w_c1: ec_chg_led_r_c1 { gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; }; ap_ec_spi_mosi { diff --git a/zephyr/projects/herobrine/keyboard.dts b/zephyr/projects/herobrine/keyboard.dts index 8c5f306192..202b61bb4f 100644 --- a/zephyr/projects/herobrine/keyboard.dts +++ b/zephyr/projects/herobrine/keyboard.dts @@ -17,3 +17,31 @@ pinctrl-0 = <&pwm3_gp80>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/herobrine/led_pins_hoglin.dts b/zephyr/projects/herobrine/led_pins_hoglin.dts new file mode 100644 index 0000000000..8603b4e61d --- /dev/null +++ b/zephyr/projects/herobrine/led_pins_hoglin.dts @@ -0,0 +1,33 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_b_c0 0>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_blue: color-blue { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_b_c0 1>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_red: color-red { + led-color = "LED_RED"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_RED"; + led-pins = <&gpio_ec_chg_led_b_c0 0>, + <&gpio_ec_chg_led_r_c0 1>; + }; + }; +}; diff --git a/zephyr/projects/herobrine/gpio_led_villager.dts b/zephyr/projects/herobrine/led_pins_villager.dts index 67a1d1926c..67a1d1926c 100644 --- a/zephyr/projects/herobrine/gpio_led_villager.dts +++ b/zephyr/projects/herobrine/led_pins_villager.dts diff --git a/zephyr/projects/herobrine/led_policy_hoglin.dts b/zephyr/projects/herobrine/led_policy_hoglin.dts new file mode 100644 index 0000000000..80ee9f7829 --- /dev/null +++ b/zephyr/projects/herobrine/led_policy_hoglin.dts @@ -0,0 +1,97 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + led-colors { + compatible = "cros-ec,led-colors"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* Blue 1 sec, off 3 sec */ + color-0 { + led-color = <&color_blue>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Red 1 sec, off 1 sec */ + color-0 { + led-color = <&color_red>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_red>; + }; + }; + + power-state-idle-forced { + charge-state = "PWR_STATE_IDLE"; + extra-flag = "LED_CHFLAG_FORCE_IDLE"; + + /* Red 2 sec, Blue 2 sec */ + color-0 { + led-color = <&color_red>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_blue>; + period-ms = <2000>; + }; + }; + + power-state-idle-default { + charge-state = "PWR_STATE_IDLE"; + extra-flag = "LED_CHFLAG_DEFAULT"; + + color-0 { + led-color = <&color_red>; + }; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_villager.dts b/zephyr/projects/herobrine/led_policy_villager.dts index 3bdf0147d7..46b0193e61 100644 --- a/zephyr/projects/herobrine/led_villager.dts +++ b/zephyr/projects/herobrine/led_policy_villager.dts @@ -1,3 +1,8 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + / { led-colors { compatible = "cros-ec,led-colors"; diff --git a/zephyr/projects/herobrine/prj.conf b/zephyr/projects/herobrine/prj.conf index 679c5c2424..e16d5c7899 100644 --- a/zephyr/projects/herobrine/prj.conf +++ b/zephyr/projects/herobrine/prj.conf @@ -30,7 +30,8 @@ CONFIG_SHELL_TAB_AUTOCOMPLETION=y CONFIG_PLATFORM_EC_HIBERNATE_PSL=y # LED -CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_DT=y # PWM CONFIG_PWM=y @@ -88,7 +89,7 @@ CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2 -CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=12500 CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y CONFIG_PLATFORM_EC_CHARGER_PSYS=y CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y @@ -148,6 +149,7 @@ CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y CONFIG_PLATFORM_EC_TABLET_MODE=y CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 # Sensor Drivers CONFIG_PLATFORM_EC_ACCEL_BMA255=y diff --git a/zephyr/projects/herobrine/prj_herobrine.conf b/zephyr/projects/herobrine/prj_herobrine.conf index c91071d844..3c7eddbae6 100644 --- a/zephyr/projects/herobrine/prj_herobrine.conf +++ b/zephyr/projects/herobrine/prj_herobrine.conf @@ -5,10 +5,6 @@ # Herobrine-NPCX9 reference-board-specific Kconfig settings. CONFIG_BOARD_HEROBRINE=y -# LED -CONFIG_PLATFORM_EC_LED_COMMON=n -CONFIG_PLATFORM_EC_LED_DT=y - # Sensors CONFIG_PLATFORM_EC_ALS=y diff --git a/zephyr/projects/herobrine/prj_hoglin.conf b/zephyr/projects/herobrine/prj_hoglin.conf index f68d139b78..370e942f45 100644 --- a/zephyr/projects/herobrine/prj_hoglin.conf +++ b/zephyr/projects/herobrine/prj_hoglin.conf @@ -13,4 +13,3 @@ CONFIG_PLATFORM_EC_ALS=y # Sensor Drivers CONFIG_PLATFORM_EC_ALS_TCS3400=y CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y - diff --git a/zephyr/projects/herobrine/prj_villager.conf b/zephyr/projects/herobrine/prj_villager.conf index a63e003788..34c366a36f 100644 --- a/zephyr/projects/herobrine/prj_villager.conf +++ b/zephyr/projects/herobrine/prj_villager.conf @@ -5,7 +5,4 @@ # Villager board-specific Kconfig settings. CONFIG_BOARD_VILLAGER=y -# LED -CONFIG_PLATFORM_EC_LED_DT=y -CONFIG_PLATFORM_EC_LED_COMMON=n CONFIG_PLATFORM_EC_ACCEL_KX022=y diff --git a/zephyr/projects/herobrine/src/led.c b/zephyr/projects/herobrine/src/led.c deleted file mode 100644 index ac6092884d..0000000000 --- a/zephyr/projects/herobrine/src/led.c +++ /dev/null @@ -1,175 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Power and battery LED control. - */ - -#include <zephyr/drivers/gpio.h> - -#include "battery.h" -#include "charge_manager.h" -#include "charge_state.h" -#include "chipset.h" -#include "ec_commands.h" -#include "hooks.h" -#include "host_command.h" -#include "led_common.h" -#include "system.h" -#include "util.h" - -#define BAT_LED_ON 1 -#define BAT_LED_OFF 0 - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_RIGHT_LED, -#ifndef CONFIG_BOARD_HOGLIN - EC_LED_ID_LEFT_LED, -#endif -}; - -const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); - -enum led_color { - LED_OFF = 0, - LED_AMBER, - LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ -}; - -static void side_led_set_color(int port, enum led_color color) -{ - gpio_pin_set_dt(port ? - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_y_c1) : - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_y_c0), - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); - gpio_pin_set_dt(port ? - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_w_c1) : - GPIO_DT_FROM_NODELABEL(gpio_ec_chg_led_w_c0), - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); -} - -void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -{ -#ifndef CONFIG_BOARD_HOGLIN - brightness_range[EC_LED_COLOR_AMBER] = 1; - brightness_range[EC_LED_COLOR_WHITE] = 1; -#else - brightness_range[EC_LED_COLOR_RED] = 1; - brightness_range[EC_LED_COLOR_BLUE] = 1; -#endif -} - -int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) -{ - int port; - - switch (led_id) { - case EC_LED_ID_RIGHT_LED: - port = 0; - break; - case EC_LED_ID_LEFT_LED: - port = 1; - break; - default: - return EC_ERROR_PARAM1; - } - - if (brightness[EC_LED_COLOR_WHITE] != 0) - side_led_set_color(port, LED_WHITE); - else if (brightness[EC_LED_COLOR_AMBER] != 0) - side_led_set_color(port, LED_AMBER); - else - side_led_set_color(port, LED_OFF); - - return EC_SUCCESS; -} - -/* - * Set active charge port color to the parameter, turn off all others. - * If no port is active (-1), turn off all LEDs. - */ -static void set_active_port_color(enum led_color color) -{ - int port = charge_manager_get_active_charge_port(); - - if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) - side_led_set_color(0, (port == 0) ? color : LED_OFF); - if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) - side_led_set_color(1, (port == 1) ? color : LED_OFF); -} - -static void board_led_set_battery(void) -{ - static int battery_ticks; - uint32_t chflags = charge_get_flags(); - - battery_ticks++; - - switch (charge_get_state()) { - case PWR_STATE_CHARGE: - /* Always indicate when charging, even in suspend. */ - set_active_port_color(LED_AMBER); - break; - case PWR_STATE_DISCHARGE: - if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { - if (charge_get_percent() <= 10) - side_led_set_color(0, - (battery_ticks & 0x4) ? LED_WHITE : LED_OFF); - else - side_led_set_color(0, LED_OFF); - } - - if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) - side_led_set_color(1, LED_OFF); - break; - case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); - break; - case PWR_STATE_CHARGE_NEAR_FULL: - set_active_port_color(LED_WHITE); - break; - case PWR_STATE_IDLE: /* External power connected in IDLE */ - if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks & 0x4) ? - LED_AMBER : LED_OFF); - else - set_active_port_color(LED_WHITE); - break; - default: - /* Other states don't alter LED behavior */ - break; - } -} - -/* Called by hook task every TICK */ -static void led_tick(void) -{ - board_led_set_battery(); -} -DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT); - -void led_control(enum ec_led_id led_id, enum ec_led_state state) -{ - enum led_color color; - - if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) && - (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) - return; - - if (state == LED_STATE_RESET) { - led_auto_control(EC_LED_ID_LEFT_LED, 1); - led_auto_control(EC_LED_ID_RIGHT_LED, 1); - board_led_set_battery(); - return; - } - - color = state ? LED_WHITE : LED_OFF; - - led_auto_control(EC_LED_ID_LEFT_LED, 0); - led_auto_control(EC_LED_ID_RIGHT_LED, 0); - - side_led_set_color(0, color); - side_led_set_color(1, color); -} diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py index 7b8bf9cb42..755b6479a6 100644 --- a/zephyr/projects/intelrvp/BUILD.py +++ b/zephyr/projects/intelrvp/BUILD.py @@ -26,7 +26,7 @@ def register_intelrvp_project( dts_overlays.append(here / "adlrvp/ioex.dts") if project_name.startswith("mtlrvp"): kconfig_files.append(here / "mtlrvp/prj.conf") - dts_overlays.append(here / "mtlrvp/battery.dts") + dts_overlays.append(here / "adlrvp/battery.dts") kconfig_files.extend(extra_kconfig_files) dts_overlays.extend(extra_dts_overlays) @@ -65,6 +65,7 @@ register_intelrvp_project( here / "adlrvp/adlrvp_npcx/cbi_eeprom.dts", here / "mtlrvp/mtlrvpp_npcx/fan.dts", here / "mtlrvp/mtlrvpp_npcx/gpio.dts", + here / "mtlrvp/mtlrvpp_npcx/keyboard.dts", here / "mtlrvp/mtlrvpp_npcx/interrupts.dts", here / "mtlrvp/ioex.dts", here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts", diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts index e001827d69..e735234128 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts @@ -29,3 +29,31 @@ >; }; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/battery.dts b/zephyr/projects/intelrvp/mtlrvp/battery.dts deleted file mode 100644 index 505e5878d2..0000000000 --- a/zephyr/projects/intelrvp/mtlrvp/battery.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - batteries { - default_battery: getac_smp_hhp_408_3s { - compatible = "getac,bq40z50-R3-S3", "battery-smart"; - }; - getac_smp_hhp_408_2s { - compatible = "getac,bq40z50-R3-S2", "battery-smart"; - }; - }; -}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts new file mode 100644 index 0000000000..e735234128 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts @@ -0,0 +1,59 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + output-settle = <35>; + debounce-down = <5000>; + debounce-up = <40000>; + poll-timeout = <100000>; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xfe /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xca /* C12 */ + >; + }; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts index 81219636f0..57b41bd9d2 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts @@ -43,11 +43,18 @@ gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; interrupt-flags = <GPIO_INT_EDGE_BOTH>; }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 3 GPIO_OPEN_DRAIN>; + output; + }; pwr-ec-pch-sys-pwrok { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "SYS_PWROK output to PCH"; enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpiof 5 0>; + gpios = <&gpiof 5 GPIO_OPEN_DRAIN>; output; }; pwr-sys-rst-l { diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py index c490471bcb..a620e7b9ae 100644 --- a/zephyr/projects/nissa/BUILD.py +++ b/zephyr/projects/nissa/BUILD.py @@ -4,7 +4,7 @@ """Define zmake projects for nissa.""" -# Nivviks and Craask has NPCX993F, Nereid has ITE81302 +# Nivviks and Craask, Pujjo has NPCX993F, Nereid has ITE81302 def register_nissa_project( @@ -18,7 +18,7 @@ def register_nissa_project( if chip.startswith("npcx"): register_func = register_npcx_project - register_func( + return register_func( project_name=project_name, zephyr_board=chip, dts_overlays=["cbi.dts", *extra_dts_overlays], @@ -26,7 +26,7 @@ def register_nissa_project( ) -register_nissa_project( +nivviks = register_nissa_project( project_name="nivviks", chip="npcx9m3f", extra_dts_overlays=[ @@ -41,7 +41,7 @@ register_nissa_project( extra_kconfig_files=[here / "prj_nivviks.conf"], ) -register_nissa_project( +nereid = register_nissa_project( project_name="nereid", chip="it8xxx2", extra_dts_overlays=[ @@ -55,15 +55,30 @@ register_nissa_project( extra_kconfig_files=[here / "prj_nereid.conf"], ) -register_nissa_project( +craask = register_nissa_project( project_name="craask", chip="npcx9m3f", extra_dts_overlays=[ here / "craask_generated.dts", here / "craask_overlay.dts", here / "craask_motionsense.dts", + here / "craask_keyboard.dts", here / "craask_power_signals.dts", here / "craask_pwm_leds.dts", ], extra_kconfig_files=[here / "prj_craask.conf"], ) + +pujjo = register_nissa_project( + project_name="pujjo", + chip="npcx9m3f", + extra_dts_overlays=[ + here / "pujjo_generated.dts", + here / "pujjo_overlay.dts", + here / "pujjo_motionsense.dts", + here / "pujjo_keyboard.dts", + here / "pujjo_power_signals.dts", + here / "pujjo_pwm_leds.dts", + ], + extra_kconfig_files=[here / "prj_pujjo.conf"], +) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index 18a82b9def..afc96e924f 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -35,7 +35,17 @@ if(DEFINED CONFIG_BOARD_CRAASK) zephyr_library_sources( "src/craask/led.c" ) - project(nivviks) + project(craask) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/craask/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/craask/charger.c") endif() +if(DEFINED CONFIG_BOARD_PUJJO) + project(pujjo) + zephyr_library_sources( + "src/led.c" + "src/pujjo/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/pujjo/fan.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/pujjo/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c") +endif() diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig index 3f0ef5954a..87d7bca977 100644 --- a/zephyr/projects/nissa/Kconfig +++ b/zephyr/projects/nissa/Kconfig @@ -20,6 +20,12 @@ config BOARD_CRAASK Build Google Craask board. Craask has Intel ADL-N SoC with NPCX993FA0BX EC. +config BOARD_PUJJO + bool "Google Pujjo Board" + help + Build Google Pujjo board. Pujjo has Intel ADL-N SoC + with NPCX993FA0BX EC. + module = NISSA module-str = Nissa board-specific code source "subsys/logging/Kconfig.template.log_config" diff --git a/zephyr/projects/nissa/craask_keyboard.dts b/zephyr/projects/nissa/craask_keyboard.dts new file mode 100644 index 0000000000..d3fd354b8f --- /dev/null +++ b/zephyr/projects/nissa/craask_keyboard.dts @@ -0,0 +1,32 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks_keyboard.dts b/zephyr/projects/nissa/nivviks_keyboard.dts index 72c573b796..71cb49ce65 100644 --- a/zephyr/projects/nissa/nivviks_keyboard.dts +++ b/zephyr/projects/nissa/nivviks_keyboard.dts @@ -16,3 +16,33 @@ pinctrl-0 = <&pwm6_gpc0>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks_overlay.dts index 926dc46129..bc10f510a5 100644 --- a/zephyr/projects/nissa/nivviks_overlay.dts +++ b/zephyr/projects/nissa/nivviks_overlay.dts @@ -261,7 +261,14 @@ */ def-lvol-io-list { compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = <&lvol_iof5 &lvol_iof4>; + lvol-io-pads = < + &lvol_iof5 + &lvol_iof4 + &lvol_io90 /* EC_I2C_SENSOR_SCL */ + &lvol_io87 /* EC_I2C_SENSOR_SDA */ + &lvol_ioe3 /* VCCIN_AUX_VID1 */ + &lvol_io92 /* VCCIN_AUX_VID0 */ + >; }; /* * Declare unused GPIOs so that they are shut down diff --git a/zephyr/projects/nissa/prj.conf b/zephyr/projects/nissa/prj.conf index 621355bf6a..df988de149 100644 --- a/zephyr/projects/nissa/prj.conf +++ b/zephyr/projects/nissa/prj.conf @@ -8,7 +8,6 @@ CONFIG_CROS_EC=y CONFIG_PLATFORM_EC=y CONFIG_SHIMMED_TASKS=y CONFIG_LTO=y -CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y # Debug options and features; can be disabled to save memory or once bringup # is complete. diff --git a/zephyr/projects/nissa/prj_nereid.conf b/zephyr/projects/nissa/prj_nereid.conf index 2508f5b13b..4b0db30556 100644 --- a/zephyr/projects/nissa/prj_nereid.conf +++ b/zephyr/projects/nissa/prj_nereid.conf @@ -8,10 +8,6 @@ CONFIG_CROS_FLASH_IT8XXX2=y CONFIG_CROS_SYSTEM_IT8XXX2=y CONFIG_ESPI_IT8XXX2=y -# Permit more detailed debugging of chargers -# TODO(b:230712704) disable when behavior is better understood -CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y - # Allow more time for the charger to stabilise CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 diff --git a/zephyr/projects/nissa/prj_pujjo.conf b/zephyr/projects/nissa/prj_pujjo.conf new file mode 100644 index 0000000000..e7e9cbd357 --- /dev/null +++ b/zephyr/projects/nissa/prj_pujjo.conf @@ -0,0 +1,40 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_BOARD_PUJJO=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=y +CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/pujjo_generated.dts b/zephyr/projects/nissa/pujjo_generated.dts new file mode 100644 index 0000000000..1c429ae32c --- /dev/null +++ b/zephyr/projects/nissa/pujjo_generated.dts @@ -0,0 +1,290 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + label = "EC_VSENSE_PP1050_PROC"; + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + label = "EC_VSENSE_PP3300_S5"; + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + label = "TEMP_SENSOR_1"; + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + label = "TEMP_SENSOR_2"; + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-name = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34>; + pinctrl-names = "default"; +}; + + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/pujjo_keyboard.dts b/zephyr/projects/nissa/pujjo_keyboard.dts new file mode 100644 index 0000000000..71cb49ce65 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_keyboard.dts @@ -0,0 +1,48 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + frequency = <10000>; + }; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/pujjo_motionsense.dts new file mode 100644 index 0000000000..69ebf04c59 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_motionsense.dts @@ -0,0 +1,163 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + label = "LID_MUTEX"; + }; + + base_mutex: base-mutex { + label = "BASE_MUTEX"; + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rot-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_data: lsm6dso-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The label "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO:(b/229577857) The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + label = "Lid Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + label = "Base Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + /* + * May be replaced by alternate depending + * on board config. + */ + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + label = "Base Gyro"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo_overlay.dts new file mode 100644 index 0000000000..c185d46e11 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_overlay.dts @@ -0,0 +1,347 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb_1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpiof 5 GPIO_INPUT>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpio6 3 GPIO_OUTPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "DDR and SOC"; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "Charger"; + enum-name = "TEMP_SENSOR_2"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + anx7483_mux_1: anx7483-mux-1 { + compatible = "analogix,anx7483"; + port = <&i2c_ec_i2c_sub_usb_c1>; + i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; + }; + }; + }; + + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + pwm-frequency = <1000>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach2>; + enable_gpio = <&gpio_fan_enable>; + }; + }; + + /* + * Declare unused GPIOs so that they are shut down + * and use minimal power + */ + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 3 0>, + <&gpio3 6 0>, + <&gpiod 7 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; + +/* Tachometer for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_1_in_gp73>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo_power_signals.dts b/zephyr/projects/nissa/pujjo_power_signals.dts new file mode 100644 index 0000000000..91876f0402 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_power_signals.dts @@ -0,0 +1,220 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/pujjo_pwm_leds.dts b/zephyr/projects/nissa/pujjo_pwm_leds.dts new file mode 100644 index 0000000000..b6f657fb03 --- /dev/null +++ b/zephyr/projects/nissa/pujjo_pwm_leds.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <324>; + + /*<red green blue>*/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 20 100>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/src/craask/led.c b/zephyr/projects/nissa/src/craask/led.c index 53274f6c44..a0c0447419 100644 --- a/zephyr/projects/nissa/src/craask/led.c +++ b/zephyr/projects/nissa/src/craask/led.c @@ -18,6 +18,7 @@ __override struct led_descriptor [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, {LED_OFF, 3 * LED_ONE_SEC} }, [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, diff --git a/zephyr/projects/nissa/src/craask/usbc.c b/zephyr/projects/nissa/src/craask/usbc.c index 0604411be0..32a390e502 100644 --- a/zephyr/projects/nissa/src/craask/usbc.c +++ b/zephyr/projects/nissa/src/craask/usbc.c @@ -10,6 +10,7 @@ #include "hooks.h" #include "usb_mux.h" #include "system.h" +#include "driver/charger/isl923x_public.h" #include "driver/retimer/anx7483_public.h" #include "driver/tcpm/tcpci.h" #include "driver/tcpm/raa489000.h" @@ -67,9 +68,11 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } return EC_SUCCESS; } @@ -91,6 +94,7 @@ int board_set_active_charge_port(int port) if (tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW)) LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); } /* @@ -101,7 +105,8 @@ int board_set_active_charge_port(int port) charger_discharge_on_ac(1); /* Enable requested charge port. */ - if (tcpc_write(port, TCPC_REG_COMMAND, + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { LOG_WRN("p%d: sink path enable failed.", port); charger_discharge_on_ac(0); @@ -188,6 +193,10 @@ int pd_set_power_supply_ready(int port) if (rv) return rv; + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + /* Notify host of power info change. */ pd_send_host_event(PD_EVENT_POWER_CHANGE); diff --git a/zephyr/projects/nissa/src/led.c b/zephyr/projects/nissa/src/led.c index fa28ccc179..27c78f8051 100644 --- a/zephyr/projects/nissa/src/led.c +++ b/zephyr/projects/nissa/src/led.c @@ -18,6 +18,8 @@ __override struct led_descriptor [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, + {LED_OFF, 3 * LED_ONE_SEC} }, [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, diff --git a/zephyr/projects/nissa/src/nereid/usbc.c b/zephyr/projects/nissa/src/nereid/usbc.c index e731b73a76..eeab449c32 100644 --- a/zephyr/projects/nissa/src/nereid/usbc.c +++ b/zephyr/projects/nissa/src/nereid/usbc.c @@ -63,22 +63,19 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) __override bool pd_check_vbus_level(int port, enum vbus_level level) { - /* - * While the charger can differentiate SAFE0V from REMOVED, doing so - * requires doing a I2C read of the VBUS analog level. Because this - * function can be polled by the USB state machines and doing the I2C - * read is relatively costly, we only check the cached VBUS presence - * (for which interrupts record transitions). - */ - switch (level) { - case VBUS_PRESENT: - return sm5803_is_vbus_present(port); - case VBUS_SAFE0V: /* Less than vSafe0V */ - case VBUS_REMOVED: /* Less than vSinkDisconnect */ - return !sm5803_is_vbus_present(port); + int vbus_voltage; + + /* If we're unable to speak to the charger, best to guess false */ + if (charger_get_vbus_voltage(port, &vbus_voltage)) { + return false; } - LOG_WRN("Unrecognized vbus_level value: %d", level); - return false; + + if (level == VBUS_SAFE0V) + return vbus_voltage < PD_V_SAFE0V_MAX; + else if (level == VBUS_PRESENT) + return vbus_voltage > PD_V_SAFE5V_MIN; + else + return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; } /* diff --git a/zephyr/projects/nissa/src/nivviks/usbc.c b/zephyr/projects/nissa/src/nivviks/usbc.c index 0b061d2bd5..c068eba6f4 100644 --- a/zephyr/projects/nissa/src/nivviks/usbc.c +++ b/zephyr/projects/nissa/src/nivviks/usbc.c @@ -10,6 +10,7 @@ #include "hooks.h" #include "usb_mux.h" #include "system.h" +#include "driver/charger/isl923x_public.h" #include "driver/retimer/anx7483_public.h" #include "driver/tcpm/tcpci.h" #include "driver/tcpm/raa489000.h" @@ -67,9 +68,11 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } return EC_SUCCESS; } @@ -91,6 +94,7 @@ int board_set_active_charge_port(int port) if (tcpc_write(i, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW)) LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); } /* @@ -101,7 +105,8 @@ int board_set_active_charge_port(int port) charger_discharge_on_ac(1); /* Enable requested charge port. */ - if (tcpc_write(port, TCPC_REG_COMMAND, + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { LOG_WRN("p%d: sink path enable failed.", port); charger_discharge_on_ac(0); @@ -188,6 +193,10 @@ int pd_set_power_supply_ready(int port) if (rv) return rv; + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + /* Notify host of power info change. */ pd_send_host_event(PD_EVENT_POWER_CHANGE); diff --git a/zephyr/projects/nissa/src/pujjo/charger.c b/zephyr/projects/nissa/src/pujjo/charger.c new file mode 100644 index 0000000000..c6209bdf75 --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Pujjo does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/src/pujjo/fan.c b/zephyr/projects/nissa/src/pujjo/fan.c new file mode 100644 index 0000000000..8914774452 --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/fan.c @@ -0,0 +1,45 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Pujjo fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt( + GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/src/pujjo/keyboard.c b/zephyr/projects/nissa/src/pujjo/keyboard.c new file mode 100644 index 0000000000..e6d819e348 --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config pujjo_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config +*board_vivaldi_keybd_config(void) +{ + return &pujjo_kb; +} diff --git a/zephyr/projects/nissa/src/pujjo/usbc.c b/zephyr/projects/nissa/src/pujjo/usbc.c new file mode 100644 index 0000000000..020f78dbdd --- /dev/null +++ b/zephyr/projects/nissa/src/pujjo/usbc.c @@ -0,0 +1,281 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && + port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, + const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int (void) +{ + poll_usb_gpio(0, + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int (void) +{ + poll_usb_gpio(1, + GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/npcx_evb/npcx9/keyboard.dts b/zephyr/projects/npcx_evb/npcx9/keyboard.dts index e2a5010952..e3ce1b1e20 100644 --- a/zephyr/projects/npcx_evb/npcx9/keyboard.dts +++ b/zephyr/projects/npcx_evb/npcx9/keyboard.dts @@ -41,3 +41,31 @@ pinctrl-0 = <&pwm2_gpc4>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h index 969549bc5d..ca1272a9ed 100644 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ b/zephyr/projects/skyrim/include/gpio_map.h @@ -23,5 +23,6 @@ enum power_signal { #define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S3_L #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/skyrim/keyboard.dts b/zephyr/projects/skyrim/keyboard.dts index 792e6074d1..216ea97045 100644 --- a/zephyr/projects/skyrim/keyboard.dts +++ b/zephyr/projects/skyrim/keyboard.dts @@ -17,3 +17,31 @@ pinctrl-0 = <&pwm1_gpc2>; pinctrl-names = "default"; }; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf index aea666c234..47e9c1d096 100644 --- a/zephyr/projects/skyrim/prj.conf +++ b/zephyr/projects/skyrim/prj.conf @@ -19,7 +19,9 @@ CONFIG_AP=y CONFIG_AP_X86_AMD=y CONFIG_PLATFORM_EC_POWERSEQ=y CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM=y +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y +CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y CONFIG_PLATFORM_EC_PORT80=y # Power button diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/usbc_config.c index 7e3b6ba486..fe60db2a69 100644 --- a/zephyr/projects/skyrim/usbc_config.c +++ b/zephyr/projects/skyrim/usbc_config.c @@ -3,7 +3,7 @@ * found in the LICENSE file. */ -/* Guybrush family-specific USB-C configuration */ +/* Skyrim family-specific USB-C configuration */ #include <zephyr/drivers/gpio.h> @@ -110,18 +110,69 @@ struct usb_mux usbc1_sbu_mux = { .driver = &ioex_sbu_mux_driver, }; -int baseboard_anx7483_mux_set(const struct usb_mux *me, +int baseboard_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) { return anx7483_set_default_tuning(me, mux_state); } +int baseboard_anx7483_c1_mux_set(const struct usb_mux *me, + mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + struct usb_mux usbc0_anx7483 = { .usb_port = USBC_PORT_C0, .i2c_port = I2C_PORT_TCPC0, .i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS, .driver = &anx7483_usb_retimer_driver, - .board_set = &baseboard_anx7483_mux_set, + .board_set = &baseboard_anx7483_c0_mux_set, .next_mux = &usbc0_sbu_mux, }; @@ -129,6 +180,13 @@ __overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) { CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + return 0; } @@ -146,7 +204,7 @@ struct usb_mux usbc1_anx7483 = { .i2c_port = I2C_PORT_TCPC1, .i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS, .driver = &anx7483_usb_retimer_driver, - .board_set = &baseboard_anx7483_mux_set, + .board_set = &baseboard_anx7483_c1_mux_set, .next_mux = &usbc1_sbu_mux, }; @@ -168,8 +226,6 @@ struct usb_mux usb_muxes[] = { }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); -/* TODO: HPD signal on PS8818 DB */ - /* * USB C0 (general) and C1 (just ANX DB) use IOEX pins to * indicate flipped polarity to a protection switch. @@ -350,10 +406,10 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, /* TODO: sbu_fault_interrupt from io expander */ /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ -#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 +#define SKYRIM_AC_PROCHOT_CURRENT_MA 3328 static void set_ac_prochot(void) { - isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA); + isl9241_set_ac_prochot(CHARGER_SOLO, SKYRIM_AC_PROCHOT_CURRENT_MA); } DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); |