diff options
Diffstat (limited to 'zephyr/shim/chip')
| -rw-r--r-- | zephyr/shim/chip/npcx/clock.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c index d70ac43e0f..24ae45d107 100644 --- a/zephyr/shim/chip/npcx/clock.c +++ b/zephyr/shim/chip/npcx/clock.c @@ -12,9 +12,14 @@ #include <zephyr.h> #include "clock_chip.h" +#include "module_id.h" LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); +#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc) +#define HAL_CDCG_REG_BASE_ADDR \ + ((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1)) + int clock_get_freq(void) { const struct device *clk_dev = device_get_binding(NPCX_CLK_CTRL_NAME); @@ -34,4 +39,31 @@ int clock_get_freq(void) void clock_turbo(void) { + struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; + + /* For NPCX7: + * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since + * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1. + */ + cdcg_base->HFCGP = 0x01; + cdcg_base->HFCBCD = BIT(4); +} + +void clock_normal(void) +{ + struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; + + cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL); + cdcg_base->HFCBCD = (FIUDIV_VAL << 4); +} + +void clock_enable_module(enum module_id module, int enable) +{ + /* Assume we have a single task using MODULE_FAST_CPU */ + if (module == MODULE_FAST_CPU) { + if (enable) + clock_turbo(); + else + clock_normal(); + } } |