diff options
Diffstat (limited to 'zephyr/shim/chip')
| -rw-r--r-- | zephyr/shim/chip/it8xxx2/include/flash_chip.h | 38 | ||||
| -rw-r--r-- | zephyr/shim/chip/npcx/include/flash_chip.h | 28 |
2 files changed, 66 insertions, 0 deletions
diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h new file mode 100644 index 0000000000..ff975ac439 --- /dev/null +++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h @@ -0,0 +1,38 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_FLASH_CHIP_H +#define __CROS_EC_FLASH_CHIP_H + +/* Flash size */ +#define CONFIG_FLASH_SIZE_BYTES DT_REG_SIZE(DT_NODELABEL(flash0)) +/* Program is run directly from storage */ +#define CONFIG_MAPPED_STORAGE_BASE DT_REG_ADDR(DT_NODELABEL(flash0)) +/* + * One page program instruction allows maximum 256 bytes (a page) of data + * to be programmed. + */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 +/* Minimum write size */ +#define CONFIG_FLASH_WRITE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ + write_block_size) +/* Erase bank size */ +#define CONFIG_FLASH_ERASE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ + erase_block_size) +/* Protect bank size */ +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE + +#define CONFIG_RO_STORAGE_OFF 0x0 +#define CONFIG_RW_STORAGE_OFF 0x0 + +/* + * The EC uses the one bank of flash to emulate a SPI-like write protect + * register with persistent state. + */ +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_FLASH_SIZE_BYTES / 2 - \ + CONFIG_FW_PSTATE_SIZE) + +#endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h new file mode 100644 index 0000000000..c8b3426e69 --- /dev/null +++ b/zephyr/shim/chip/npcx/include/flash_chip.h @@ -0,0 +1,28 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_FLASH_CHIP_H +#define __CROS_EC_FLASH_CHIP_H + +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ +#ifdef CONFIG_FLASH_SIZE +#define CONFIG_FLASH_SIZE_BYTES (CONFIG_FLASH_SIZE * 1024) +#else +#define CONFIG_FLASH_SIZE_BYTES 0x0 +#endif + +/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */ +#define CONFIG_MAPPED_STORAGE_BASE 0x64000000 +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE + +/* RO image resides at start of protected region, right after header */ +#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE + +#define CONFIG_RW_STORAGE_OFF 0 + +#endif /* __CROS_EC_FLASH_CHIP_H */ |