1 files changed, 23 insertions, 19 deletions

diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
index 97268e8fe6..e4ce364cb1 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,39 +14,41 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
  */
 enum power_states_ndsx chipset_pwr_seq_get_state(void)
 {
+	power_signal_mask_t sig = power_get_signals();
+
 	/*
-	 * Chip is shut down.
+	 * Chip is shut down, G3 state.
 	 */
-	if ((power_get_signals() & MASK_ALL_POWER_GOOD) == 0) {
-		LOG_DBG("Power rails off, G3 state");
+	if ((sig & MASK_ALL_POWER_GOOD) == 0) {
+		LOG_DBG("All power rails off, G3 state");
 		return SYS_POWER_STATE_G3;
 	}
 	/*
-	 * If not all the power rails are available,
-	 * then force shutdown to G3 to get to known state.
+	 * Not enough power rails up to read VW signals.
+	 * Force a shutdown.
 	 */
-	if ((power_get_signals() & MASK_ALL_POWER_GOOD)
-			!= MASK_ALL_POWER_GOOD) {
+	if ((sig & MASK_VW_POWER) != VALUE_VW_POWER) {
+		LOG_ERR("Not enough power signals on (%#x), forcing shutdown",
+			sig);
 		ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
-		LOG_INF("Not all power rails up, forcing shutdown");
 		return SYS_POWER_STATE_G3;
 	}
 
 	/*
-	 * All the power rails are good, so
+	 * Enough power signals are up, so
 	 * wait for virtual wire signals to become available.
 	 * Not sure how long to wait? 5 seconds total.
 	 */
 	for (int delay = 0; delay < 500; k_msleep(10), delay++) {
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3)
 		if (power_signal_get(PWR_SLP_S3) < 0)
 			continue;
 #endif
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4)
 		if (power_signal_get(PWR_SLP_S4) < 0)
 			continue;
 #endif
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5)
 		if (power_signal_get(PWR_SLP_S5) < 0)
 			continue;
 #endif
@@ -56,32 +58,34 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void)
 		LOG_DBG("All VW signals valid after %d ms", delay * 10);
 		break;
 	}
+	/* Re-read the power signals */
+	sig = power_get_signals();
+
 	/*
 	 * S0, all power OK, no suspend or sleep on.
 	 */
-	if ((power_get_signals() & MASK_S0) == MASK_ALL_POWER_GOOD) {
+	if ((sig & MASK_S0) == VALUE_S0) {
 		LOG_DBG("CPU in S0 state");
 		return SYS_POWER_STATE_S0;
 	}
 	/*
 	 * S3, all power OK, PWR_SLP_S3 on.
 	 */
-	if ((power_get_signals() & MASK_S0) ==
-		(MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))) {
+	if ((sig & MASK_S3) == VALUE_S3) {
 		LOG_DBG("CPU in S3 state");
 		return SYS_POWER_STATE_S3;
 	}
 	/*
-	 * S5, all power OK, PWR_SLP_S5 on.
+	 * S5, some power signals on, PWR_SLP_S5 on.
 	 */
-	if ((power_get_signals() & MASK_S5) == MASK_S5) {
+	if ((sig & MASK_S5) == VALUE_S5) {
 		LOG_DBG("CPU in S5 state");
 		return SYS_POWER_STATE_S5;
 	}
 	/*
 	 * Unable to determine state, force to G3.
 	 */
+	LOG_INF("Unable to determine CPU state (%#x), forcing shutdown", sig);
 	ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
-	LOG_INF("Unable to determine CPU state, forcing shutdown");
 	return SYS_POWER_STATE_G3;
 }