1 files changed, 0 insertions, 125 deletions

diff --git a/zephyr/test/ap_power/boards/native_posix.overlay b/zephyr/test/ap_power/boards/native_posix.overlay
index c6cd8c3790..b30240a094 100644
--- a/zephyr/test/ap_power/boards/native_posix.overlay
+++ b/zephyr/test/ap_power/boards/native_posix.overlay
@@ -52,131 +52,6 @@
 		};
 	};
 
-	common-pwrseq {
-		compatible = "intel,ap-pwrseq";
-	};
-
-	pwr-en-pp5000-s5 {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "PP5000_S5 enable output to regulator";
-		enum-name = "PWR_EN_PP5000_A";
-		gpios = <&gpio0 10 0>;
-		output;
-	};
-	pwr-en-pp3300-s5 {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "PP3300_S5 enable output to LS";
-		enum-name = "PWR_EN_PP3300_A";
-		gpios = <&gpio0 11 0>;
-		output;
-	};
-	pwr-pg-ec-rsmrst-odl {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "RSMRST power good from regulator";
-		enum-name = "PWR_RSMRST";
-		gpios = <&gpio0 12 0>;
-		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
-	};
-	pwr-ec-pch-rsmrst-odl {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "RSMRST output to PCH";
-		enum-name = "PWR_EC_PCH_RSMRST";
-		gpios = <&gpio0 13 0>;
-		output;
-	};
-	pwr-slp-s0-l {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SLP_S0_L input from PCH";
-		enum-name = "PWR_SLP_S0";
-		gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
-		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
-		no-enable;
-	};
-	pwr-slp-s3-l {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SLP_S3_L input from PCH";
-		enum-name = "PWR_SLP_S3";
-		gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
-	};
-	pwr-slp-sus-l {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SLP_SUS_L input from PCH";
-		enum-name = "PWR_SLP_SUS";
-		gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
-		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
-	};
-	pwr-ec-soc-dsw-pwrok {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "DSW_PWROK output to PCH";
-		enum-name = "PWR_EC_SOC_DSW_PWROK";
-		gpios = <&gpio0 17 0>;
-		output;
-	};
-	pwr-vccst-pwrgd-od {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "VCCST_PWRGD output to PCH";
-		enum-name = "PWR_VCCST_PWRGD";
-		gpios = <&gpio0 18 0>;
-		output;
-	};
-	pwr-imvp9-vrrdy-od {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "VRRDY input from IMVP9";
-		enum-name = "PWR_IMVP9_VRRDY";
-		gpios = <&gpio0 19 0>;
-	};
-	pwr-pch-pwrok {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "PCH_PWROK output to PCH";
-		enum-name = "PWR_PCH_PWROK";
-		gpios = <&gpio0 20 0>;
-		output;
-	};
-	pwr-ec-pch-sys-pwrok {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SYS_PWROK output to PCH";
-		enum-name = "PWR_EC_PCH_SYS_PWROK";
-		gpios = <&gpio0 21 0>;
-		output;
-	};
-	pwr-sys-rst-l {
-		compatible = "intel,ap-pwrseq-gpio";
-		dbg-label = "SYS_RESET# output to PCH";
-		enum-name = "PWR_SYS_RST";
-		gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
-		output;
-	};
-	pwr-slp-s4 {
-		compatible = "intel,ap-pwrseq-vw";
-		dbg-label = "SLP_S4 virtual wire input from PCH";
-		enum-name = "PWR_SLP_S4";
-		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
-		vw-invert;
-	};
-	pwr-slp-s5 {
-		compatible = "intel,ap-pwrseq-vw";
-		dbg-label = "SLP_S5 virtual wire input from PCH";
-		enum-name = "PWR_SLP_S5";
-		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
-		vw-invert;
-	};
-	pwr-all-sys-pwrgd {
-		compatible = "intel,ap-pwrseq-external";
-		dbg-label = "Combined all power good";
-		enum-name = "PWR_ALL_SYS_PWRGD";
-	};
-	pwr-pp3300-pwrok {
-		compatible = "intel,ap-pwrseq-external";
-		dbg-label = "PP3300 PWROK";
-		enum-name = "PWR_DSW_PWROK";
-	};
-	pwr-pp1p05-pwrok {
-		compatible = "intel,ap-pwrseq-external";
-		dbg-label = "PP1P05 PWROK";
-		enum-name = "PWR_PG_PP1P05";
-	};
-
 	clock: clock {
 		compatible = "cros,clock-control-emul";
 		clock-frequency = <DT_FREQ_M(100)>; /* 100 MHz */