diff options
Diffstat (limited to 'zephyr/test')
| -rw-r--r-- | zephyr/test/drivers/Kconfig | 16 | ||||
| -rw-r--r-- | zephyr/test/drivers/boards/native_posix.overlay | 5 | ||||
| -rw-r--r-- | zephyr/test/drivers/testcase.yaml | 6 | ||||
| -rw-r--r-- | zephyr/test/drivers/usbc_retimer/CMakeLists.txt | 3 | ||||
| -rw-r--r-- | zephyr/test/drivers/usbc_retimer/src/anx7483.c | 1287 |
5 files changed, 1312 insertions, 5 deletions
diff --git a/zephyr/test/drivers/Kconfig b/zephyr/test/drivers/Kconfig index cf24966beb..7ac5a297c0 100644 --- a/zephyr/test/drivers/Kconfig +++ b/zephyr/test/drivers/Kconfig @@ -162,9 +162,21 @@ config LINK_TEST_SUITE_USBC_SVDM_DFP_ONLY bool "Link and test the usbc_svdm_dfp_only tests" config LINK_TEST_SUITE_USBC_RETIMER - bool "Link and test the usbc_retimer tests" + bool "Link the USBC retimer tests" + +config LINK_TEST_SUITE_USBC_RETIMER_ANX7483 + bool "Link and test the ANX7484 tests" + select LINK_TEST_SUITE_USBC_RETIMER + select PLATFORM_EC_USBC_RETIMER_ANX7483 + help + Include the ANX7483 test suite in the binary. + +config LINK_TEST_SUITE_USBC_RETIMER_PS8811 + bool "Link and test the PS8811 tests" + select LINK_TEST_SUITE_USBC_RETIMER + select PLATFORM_EC_USBC_RETIMER_PS8811 help - Include the usbc_retimer test suite in the binary. + Include the PS8811 test suite in the binary. config LINK_TEST_SUITE_USBC_TBT_MODE bool "Link and test the usbc_tbt_mode tests" diff --git a/zephyr/test/drivers/boards/native_posix.overlay b/zephyr/test/drivers/boards/native_posix.overlay index 561f2cd311..442a07e5dc 100644 --- a/zephyr/test/drivers/boards/native_posix.overlay +++ b/zephyr/test/drivers/boards/native_posix.overlay @@ -897,6 +897,11 @@ ls-en-pin = <&usb_c1_ls_en>; }; + anx7483_emul: anx7483_emul@3e { + compatible = "cros,anx7483-emul", "analogix,anx7483"; + reg = <0x3e>; + }; + ps8811_emul: ps8811_emul@72 { compatible = "cros,ps8811-emul"; reg = <0x72>; diff --git a/zephyr/test/drivers/testcase.yaml b/zephyr/test/drivers/testcase.yaml index 164ca61801..7f1d71fca2 100644 --- a/zephyr/test/drivers/testcase.yaml +++ b/zephyr/test/drivers/testcase.yaml @@ -320,10 +320,12 @@ tests: drivers.usbc_ppc: extra_configs: - CONFIG_LINK_TEST_SUITE_USBC_PPC=y + drivers.usbc_retimer.anx7483: + extra_configs: + - CONFIG_LINK_TEST_SUITE_USBC_RETIMER_ANX7483=y drivers.usbc_retimer.ps8811: extra_configs: - - CONFIG_LINK_TEST_SUITE_USBC_RETIMER=y - - CONFIG_PLATFORM_EC_USBC_RETIMER_PS8811=y + - CONFIG_LINK_TEST_SUITE_USBC_RETIMER_PS8811=y drivers.usbc_svdm_dfp_only: extra_args: CONF_FILE="prj.conf;usbc_svdm_dfp_only/prj.conf" DTC_OVERLAY_FILE="usbc_svdm_dfp_only/boards/native_posix.overlay" diff --git a/zephyr/test/drivers/usbc_retimer/CMakeLists.txt b/zephyr/test/drivers/usbc_retimer/CMakeLists.txt index b67b309400..5c3253328d 100644 --- a/zephyr/test/drivers/usbc_retimer/CMakeLists.txt +++ b/zephyr/test/drivers/usbc_retimer/CMakeLists.txt @@ -2,4 +2,5 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -target_sources_ifdef(CONFIG_EMUL_PS8811 app PRIVATE src/ps8811.c) +target_sources_ifdef(CONFIG_LINK_TEST_SUITE_USBC_RETIMER_ANX7483 app PRIVATE src/anx7483.c) +target_sources_ifdef(CONFIG_LINK_TEST_SUITE_USBC_RETIMER_PS8811 app PRIVATE src/ps8811.c) diff --git a/zephyr/test/drivers/usbc_retimer/src/anx7483.c b/zephyr/test/drivers/usbc_retimer/src/anx7483.c new file mode 100644 index 0000000000..727bc3d435 --- /dev/null +++ b/zephyr/test/drivers/usbc_retimer/src/anx7483.c @@ -0,0 +1,1287 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "driver/retimer/anx7483.h" +#include "driver/retimer/anx7483_public.h" +#include "emul/retimer/emul_anx7483.h" +#include "i2c.h" +#include "power.h" +#include "usb_mux.h" + +#include <zephyr/drivers/emul.h> +#include <zephyr/ztest.h> + +#define ANX7483_EMUL EMUL_DT_GET(DT_NODELABEL(anx7483_emul)) + +int anx7483_init(const struct usb_mux *me); +int anx7483_set(const struct usb_mux *me, mux_state_t mux_state, + bool *ack_required); +int anx7483_get(const struct usb_mux *me, mux_state_t *mux_state); +int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val); +int anx7483_write(const struct usb_mux *me, uint8_t reg, uint8_t val); + +static struct usb_mux mux = { + .i2c_port = I2C_PORT_NODELABEL(i2c3), + .i2c_addr_flags = 0x3e, +}; + +/* Helper functions to make tests clearer. */ +static int anx7483_emul_test_get_reg(int reg, uint8_t *val) +{ + return anx7483_emul_get_reg(ANX7483_EMUL, reg, val); +} + +static int anx7483_emul_test_set_reg(int reg, uint8_t val) +{ + return anx7483_emul_set_reg(ANX7483_EMUL, reg, val); +} + +static int anx7483_i2c_read(int reg, int *data) +{ + return anx7483_read(&mux, reg, data); +} + +static int anx7483_i2c_write(int reg, int data) +{ + return anx7483_write(&mux, reg, data); +} + +static void anx7483_before(void *fixture) +{ + ARG_UNUSED(fixture); + + /* Ensure the ANX7483 is on. */ + power_set_state(POWER_S0); +} + +ZTEST_SUITE(anx7483, NULL, NULL, anx7483_before, NULL, NULL); + +/* Verify that the reset values for all registers are correct. */ +ZTEST(anx7483, test_emul_reset) +{ + uint8_t val; + int rv; + + rv = anx7483_emul_test_get_reg(ANX7483_LFPS_TIMER_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_LFPS_TIMER_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_ENABLE_EQ_FLAT_SWING_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_AUX_SNOOPING_CTRL_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT); + + /* CFG0 */ + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX1_PORT_CFG0_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX2_PORT_CFG0_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX1_PORT_CFG0_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX2_PORT_CFG0_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX1_PORT_CFG0_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX2_PORT_CFG0_REG_DEFAULT); + + /* CFG1 */ + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX1_PORT_CFG1_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX2_PORT_CFG1_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX1_PORT_CFG1_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX2_PORT_CFG1_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX1_PORT_CFG1_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX2_PORT_CFG1_REG_DEFAULT); + + /* CFG2 */ + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX1_PORT_CFG2_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX2_PORT_CFG2_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX1_PORT_CFG2_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX2_PORT_CFG2_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX1_PORT_CFG2_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX2_PORT_CFG2_REG_DEFAULT); + + /* CFG3 */ + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX1_PORT_CFG3_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX2_PORT_CFG3_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX1_PORT_CFG3_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX2_PORT_CFG3_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX1_PORT_CFG3_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX2_PORT_CFG3_REG_DEFAULT); + + /* CFG4 */ + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX1_PORT_CFG4_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_UTX2_PORT_CFG4_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX1_PORT_CFG4_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_URX2_PORT_CFG4_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX1_PORT_CFG4_REG_DEFAULT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_DRX2_PORT_CFG4_REG_DEFAULT); +} + +/* Test the ANX7483 driver's initialization function. */ +ZTEST(anx7483, test_init) +{ + int rv; + uint8_t val; + + rv = anx7483_init(&mux); + zexpect_ok(rv); + + rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val); + zexpect_ok(rv); + zexpect_true(val & ANX7483_CTRL_REG_EN); +} + +/* + * Test the ANX7483 driver's anx7483_set_eq, function which sets the + * equalization for a pin. + */ + +ZTEST(anx7483, test_set_eq) +{ + int rv; + uint8_t val; + + rv = anx7483_set_eq(&mux, ANX7483_PIN_UTX1, ANX7483_EQ_SETTING_12_5DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf, + ANX7483_EQ_SETTING_12_5DB); + + rv = anx7483_set_eq(&mux, ANX7483_PIN_UTX2, ANX7483_EQ_SETTING_12_5DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf, + ANX7483_EQ_SETTING_12_5DB); + + rv = anx7483_set_eq(&mux, ANX7483_PIN_URX1, ANX7483_EQ_SETTING_12_5DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf, + ANX7483_EQ_SETTING_12_5DB); + + rv = anx7483_set_eq(&mux, ANX7483_PIN_URX2, ANX7483_EQ_SETTING_12_5DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf, + ANX7483_EQ_SETTING_12_5DB); + + rv = anx7483_set_eq(&mux, ANX7483_PIN_DRX1, ANX7483_EQ_SETTING_12_5DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf, + ANX7483_EQ_SETTING_12_5DB); + + rv = anx7483_set_eq(&mux, ANX7483_PIN_DRX2, ANX7483_EQ_SETTING_12_5DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf, + ANX7483_EQ_SETTING_12_5DB); + + /* Test invalid pin. */ + rv = anx7483_set_eq(&mux, 0xff, ANX7483_EQ_SETTING_12_5DB); + zexpect_not_equal(rv, 0); +} + +/* + * Test the ANX7483 driver's anx7483_set_fg, function which sets the flat gain + * for a pin. + */ +ZTEST(anx7483, test_set_fg) +{ + int rv; + uint8_t val; + + rv = anx7483_set_fg(&mux, ANX7483_PIN_UTX1, ANX7483_FG_SETTING_1_2DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3, + ANX7483_FG_SETTING_1_2DB); + + rv = anx7483_set_fg(&mux, ANX7483_PIN_UTX2, ANX7483_FG_SETTING_1_2DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3, + ANX7483_FG_SETTING_1_2DB); + + rv = anx7483_set_fg(&mux, ANX7483_PIN_URX1, ANX7483_FG_SETTING_1_2DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3, + ANX7483_FG_SETTING_1_2DB); + + rv = anx7483_set_fg(&mux, ANX7483_PIN_URX2, ANX7483_FG_SETTING_1_2DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3, + ANX7483_FG_SETTING_1_2DB); + + rv = anx7483_set_fg(&mux, ANX7483_PIN_DRX1, ANX7483_FG_SETTING_1_2DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3, + ANX7483_FG_SETTING_1_2DB); + + rv = anx7483_set_fg(&mux, ANX7483_PIN_DRX2, ANX7483_FG_SETTING_1_2DB); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3, + ANX7483_FG_SETTING_1_2DB); + + /* Test invalid pin. */ + rv = anx7483_set_fg(&mux, 0xff, ANX7483_FG_SETTING_1_2DB); + zexpect_not_equal(rv, 0); +} + +/* Validate that accessing the emulator's registers through I2C works. */ +ZTEST(anx7483, test_emul_registers_rw) +{ + int rv; + uint8_t expected; + int val; + + expected = (uint8_t)(ANX7483_LFPS_TIMER_REG_RESERVED_MASK & + ANX7483_LFPS_TIMER_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_LFPS_TIMER_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_LFPS_TIMER_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_LFPS_TIMER_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK & + ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_ANALOG_STATUS_CTRL_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_ANALOG_STATUS_CTRL_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK & + ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_ENABLE_EQ_FLAT_SWING_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_ENABLE_EQ_FLAT_SWING_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK & + ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_AUX_SNOOPING_CTRL_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_AUX_SNOOPING_CTRL_REG, &val); + zexpect_equal(val, expected); + + /* CFG0 */ + expected = (uint8_t)(ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK & + ANX7483_UTX1_PORT_CFG0_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG0_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG0_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK & + ANX7483_UTX2_PORT_CFG0_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG0_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG0_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK & + ANX7483_URX1_PORT_CFG0_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG0_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK & + ANX7483_URX1_PORT_CFG0_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG0_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK & + ANX7483_DRX1_PORT_CFG0_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG0_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG0_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK & + ANX7483_DRX2_PORT_CFG0_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG0_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG0_REG, &val); + zexpect_equal(val, expected); + + /* CFG1 */ + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG1_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG1_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG1_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG1_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG1_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG1_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG1_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG1_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG1_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG1_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG1_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG1_REG, &val); + zexpect_equal(val, expected); + + /* CFG2 */ + expected = (uint8_t)(ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK & + ANX7483_UTX1_PORT_CFG2_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG2_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG2_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK & + ANX7483_UTX2_PORT_CFG2_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG2_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG2_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK & + ANX7483_URX1_PORT_CFG2_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG2_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK & + ANX7483_URX1_PORT_CFG2_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG2_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK & + ANX7483_DRX1_PORT_CFG2_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG2_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG2_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK & + ANX7483_DRX2_PORT_CFG2_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG2_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG2_REG, &val); + zexpect_equal(val, expected); + + /* CFG3 */ + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG3_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG3_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG3_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG3_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG3_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG3_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG3_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG3_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG3_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG3_REG, &val); + zexpect_equal(val, expected); + + expected = 0xff; + rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG3_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG3_REG, &val); + zexpect_equal(val, expected); + + /* CFG4 */ + expected = (uint8_t)(ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK & + ANX7483_UTX1_PORT_CFG4_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG4_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG4_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK & + ANX7483_UTX2_PORT_CFG4_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG4_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG4_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK & + ANX7483_URX1_PORT_CFG4_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG4_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG4_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK & + ANX7483_URX1_PORT_CFG4_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG4_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG4_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK & + ANX7483_DRX1_PORT_CFG4_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG4_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG4_REG, &val); + zexpect_equal(val, expected); + + expected = (uint8_t)(ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK & + ANX7483_DRX2_PORT_CFG4_REG_DEFAULT); + expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK); + rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG4_REG, expected); + zexpect_ok(rv); + rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG4_REG, &val); + zexpect_equal(val, expected); + + /* Ensure that reading/writing a non-existent register fails. */ + rv = anx7483_i2c_read(0xff, &val); + zexpect_not_equal(rv, 0); + rv = anx7483_i2c_write(0xff, 0xff); + zexpect_not_equal(rv, 0); +} + +/* Test that the ANX7483 driver correctly reports its state. */ +ZTEST(anx7483, test_mux_state_get) +{ + int rv; + uint8_t val; + mux_state_t state; + + rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val); + zexpect_ok(rv); + val |= ANX7483_CTRL_USB_EN; + val |= ANX7483_CTRL_DP_EN; + val |= ANX7483_CTRL_FLIP_EN; + rv = anx7483_emul_test_set_reg(ANX7483_ANALOG_STATUS_CTRL_REG, val); + zexpect_ok(rv); + + rv = anx7483_get(&mux, &state); + zexpect_ok(rv); + zexpect_true(val & USB_PD_MUX_USB_ENABLED); + zexpect_true(val & USB_PD_MUX_DP_ENABLED); + zexpect_true(val & USB_PD_MUX_POLARITY_INVERTED); +} + +/* Test that the ANX7483 driver correctly sets the mux state. */ +ZTEST(anx7483, test_mux_state_set) +{ + int rv; + uint8_t val; + bool ack_required; + + rv = anx7483_set(&mux, + USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | + USB_PD_MUX_POLARITY_INVERTED, + &ack_required); + zexpect_ok(rv); + rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val); + zexpect_ok(rv); + zexpect_true(val & ANX7483_CTRL_REG_EN); + zexpect_true(val & ANX7483_CTRL_USB_EN); + zexpect_true(val & ANX7483_CTRL_DP_EN); + zexpect_true(val & ANX7483_CTRL_FLIP_EN); +} + +/* Validates that writing to a reserved register returns an error. */ +ZTEST(anx7483, test_emul_reserved) +{ + int rv; + + rv = anx7483_emul_test_set_reg(ANX7483_LFPS_TIMER_REG, + ANX7483_LFPS_TIMER_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_ANALOG_STATUS_CTRL_REG, + ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_ENABLE_EQ_FLAT_SWING_REG, + ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_AUX_SNOOPING_CTRL_REG, + ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + /* CFG0 */ + rv = anx7483_emul_test_set_reg( + ANX7483_UTX1_PORT_CFG0_REG, + ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_UTX2_PORT_CFG0_REG, + ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_URX1_PORT_CFG0_REG, + ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_URX2_PORT_CFG0_REG, + ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_DRX1_PORT_CFG0_REG, + ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_DRX2_PORT_CFG0_REG, + ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + /* CFG2 */ + rv = anx7483_emul_test_set_reg( + ANX7483_UTX1_PORT_CFG2_REG, + ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_UTX2_PORT_CFG2_REG, + ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_URX1_PORT_CFG2_REG, + ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_URX2_PORT_CFG2_REG, + ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_DRX1_PORT_CFG2_REG, + ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_DRX2_PORT_CFG2_REG, + ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + /* CFG4 */ + rv = anx7483_emul_test_set_reg( + ANX7483_UTX1_PORT_CFG4_REG, + ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_UTX2_PORT_CFG4_REG, + ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_URX1_PORT_CFG4_REG, + ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_URX2_PORT_CFG4_REG, + ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_DRX1_PORT_CFG4_REG, + ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); + + rv = anx7483_emul_test_set_reg( + ANX7483_DRX2_PORT_CFG4_REG, + ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK); + zexpect_not_equal(rv, 0); +} + +/* + * Tests that the ANX7483 driver correctly configures the default tuning for + * USB. The register values should match those in the anx7483_usb_enabled struct + * within the driver. + */ +ZTEST(anx7483, test_tuning_usb) +{ + int rv; + uint8_t val; + + rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_USB_ENABLED); + zexpect_ok(rv); + + /* CFG0 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + /* CFG1 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + /* CFG2 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + /* CFG3 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + /* CFG4 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); +} + +/* + * Tests that the ANX7483 driver correctly configures the default tuning for + * DisplayPort. The register values should match those in the anx7483_dp_enabled + * struct within the driver. + */ +ZTEST(anx7483, test_tuning_dp) +{ + int rv; + uint8_t val; + + rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DP_ENABLED); + zexpect_ok(rv); + + /* CFG0 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + /* CFG1 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + /* CFG2 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + /* CFG3 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + /* CFG4 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); +} + +/* + * Tests that the ANX7483 driver correctly configures the default tuning for + * dock mode in a non-flipped state. The register values should match those in + * the anx7483_dock_noflip struct within the driver. + */ +ZTEST(anx7483, test_tuning_dock_noflip) +{ + int rv; + uint8_t val; + + rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DOCK); + zexpect_ok(rv); + + /* Corresponds to anx7483_dock_noflip. */ + /* CFG0 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + /* CFG1 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + /* CFG2 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + /* CFG3 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + /* CFG4 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); +} + +/* + * Tests that the ANX7483 driver correctly configures the default tuning for + * dock mode in a flipped state. The register values should match those in + * the anx7483_dock_flip struct within the driver. + */ +ZTEST(anx7483, test_tuning_dock_flip) +{ + int rv; + uint8_t val; + + rv = anx7483_set_default_tuning( + &mux, USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED); + zexpect_ok(rv); + + /* CFG0 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG0_DEF); + + /* CFG1 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG1_DEF); + + /* CFG2 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG2_DEF); + + /* CFG3 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_100Ohm_IN); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG3_90Ohm_IN); + + /* CFG4 */ + rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); + + rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val); + zexpect_ok(rv); + zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE); +} |