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* Clear OWNERS for factory/firmware branchfactory-4128.BBrian Norris2021-09-101-0/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155031 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* Bus fault handler doesn't need to be nakedRandall Spangler2013-05-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When it was a naked call, if it doesn't jump somewhere, it just falls through to whatever code happens to be next. Which happened to re-enable bus faults - meaning that only the first fault was being ignored. That's a problem for flash protection on STM32, where writes to potentially-locked key registers come in pairs. BUG=chrome-os-partner:19564 BRANCH=spring TEST=manual, on pit: 1. Hack in a igbusfault console command to call ignore_bus_fault() 2. igbusfault 1 3. ww 0x40023c0c 0xdeadbeef -> no fault 4. ww 0x40023c0c 0xdeadbeef -> still no fault 5. igbusfault 0 6. ww 0x40023c0c 0xdeadbeef -> exception and reboot Change-Id: I5cf74b06a76ebf0176a2905924be87b3d1c825ce Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55572 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit c2933c122a10c8a1e0850672ed878b39c9c67be1) Reviewed-on: https://gerrit.chromium.org/gerrit/56322 Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* Support write protect GPIO on pitRandall Spangler2013-05-223-8/+9
| | | | | | | | | | | | | | | | | | | | | Daisy doesn't have a write protect signal, so emulate it as a fake signal which is always low; this maintains the current behavior on daisy. BUG=chrome-os-partner:15613 BRANCH=none TEST=flashinfo shows gpio not asserted then short across the WP screw and flashinfo shows it asserted Change-Id: I329424efe1c3b065976e17395e2bf9588cdce88c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51500 Reviewed-by: Vic Yang <victoryang@chromium.org> (cherry picked from commit 7d207c98e2a99accbd1ab1353d0a802f9a8be3de) Reviewed-on: https://gerrit.chromium.org/gerrit/56321 Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* Fix detecting inconsistent flash stateRandall Spangler2013-05-222-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the last bank of flash in a region was protected and the rest of the region was unprotected, flash_get_protect() shoud return the INCONSISTENT flag, but this wasn't being properly detected. Port the existing fix from STM32F. BUG=chrome-os-partner:19529 BRANCH=none (not likely worth porting to link) TEST=protect just the last bank of RW firmware, then flashinfo > flashinfo Physical: 128 KB Usable: 128 KB Write: 64 B Erase: 256 B Protect: 4096 B Flags: all_now INCONSISTENT Protected now: ........ ........ ........ .......Y Should have the inconsistent flag set. Change-Id: I407737cef42748da6b3ec40d84968c76ee07972c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51498 Reviewed-by: Bill Richardson <wfrichar@chromium.org> (cherry picked from commit 6ff01d910a17900c58179809d49f30f921e72d8c) Reviewed-on: https://gerrit.chromium.org/gerrit/56320 Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* Set SPI lines to inputs when AP is offRandall Spangler2013-05-223-10/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When AP is off, turn off pullup on NSS, and set MISO to an input so the SPI module won't drive it high if the last sent bit was a 1. This reduces leakage when the AP is off. This patch also fixes a bug where gpio_set_alternate_function() set the wrong pins to normal-mode when func=-1; that didn't hit anything else because that functionality wasn't used on STM32 until now. BUG=chrome-os-partner:19304 BRANCH=none TEST=boot pit On EC console, with AP on, 'rw 0x40020000' returns read 0x40020000 = 0x6569aa20 <- must have 0x____aa__ Then 'apshutdown' and 'rw 0x40020000' returns read 0x40020000 = 0x65690020 <- must have 0x____00__ The 'power on' and AP turns back on. At u-boot prompt, 'sspi 2:0 256 9f00000000' returns FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEEC010001 (some number of 0xFD's followed by FEEC...) This shows SPI functionality is restored when AP is powered back on, and not just at init time. Change-Id: Ia3cd3e0bc222dc663d635509918fa3d383fd7971 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51182 Reviewed-by: Simon Glass <sjg@chromium.org> (cherry picked from commit 3c2c1398ec993cc597903a4d4ba38546182b7053) Reviewed-on: https://gerrit.chromium.org/gerrit/56319 Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* pit: Add more delay for proper power_on sequenceWonjoon Lee2013-05-221-3/+4
| | | | | | | | | | | | | | | | | | | | It makes delay between 3.3V_EN and PMIC_ON So we are now 5V EN -> 2ms Delay -> 3.3V EN -> 2ms Delay -> PMC3_ACOK BUG=chrome-os-partner:19305 BRANCH=none TEST=Using osiloscope, See until PMC3_ACOK is far from P3.3V_AUX as 5ms Change-Id: I65bfece28f55edf4f5640fe411bd57caaaaa5e1d Reviewed-on: https://gerrit.chromium.org/gerrit/50449 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 23ece32e08cb188c36eb3162b7519b4713275d6b) Reviewed-on: https://gerrit.chromium.org/gerrit/56318 Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* Add console command to force enable consoleVic Yang2013-05-225-49/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | When system is locked, the console is disabled. However, we need console for debugging and testing. This CL uses a bit from back-up register to indicate if the console should always be enabled. (This bit is currently used by fake WP, which is removed in this CL.) With this, we can set this bit with console command 'forceen 1' to ensure console is never disabled. To prevent device shipped in this state, the chip name is postfixed with '-unsafe' so that the device is not able to pass HWID check. BUG=chrome-os-partner:19293 TEST=Manual BRANCH=spring Change-Id: I88556e973ca542c1bdc27ba64988718291e01a26 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51086 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit c8b7b430fe5e4aa3d5f27fbd160dfee31254e36d) Reviewed-on: https://gerrit.chromium.org/gerrit/56317 Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* do not store the keyboard state on the stackVincent Palatin2013-05-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | As our stack for the keyboard scanning task might be small (256 bytes on STM32), we store the full keyboard state in a global instead of the stack to avoid consuming 16 bytes there. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:19389 TEST=run on Spring with CONFIG_OVERFLOW_DETECT and see that the KEYSCAN task is now consuming 248 bytes of stack instead of 264. Change-Id: I2dd7815f36e6807e7b9e88d59f8fd8a14b1988ab Reviewed-on: https://gerrit.chromium.org/gerrit/51028 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 24beb9976a482c40cf5ad8302dcb2032dd5307d1) Reviewed-on: https://gerrit.chromium.org/gerrit/56316 Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
* spring: Pull more current from video dongleVic Yang2013-05-131-6/+10
| | | | | | | | | | | | | | | | | | We cannot know how much current we can pull from video dongle, so let's just try to pull as much as possible up to 2A. BUG=chrome-os-partner:19324 TEST=Plug in video dongle and see 3.3V output. TEST=Plug in video dongle with supplied charger, and see 50% PWM duty cycle. TEST=Plug in video dongle with normal charger, and see 70~80% PWM duty cycle. BRANCH=spring Change-Id: I8b503f886fcafaa11e6757a5059ce673a8ed53cc Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50963 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* slippy: Enable internal pullup for recovery pinDuncan Laurie2013-05-131-1/+1
| | | | | | | | | | | | | | | | The recovery pin input from servo is open drain and needs an internal pullup enabled so it is not always low. BUG=chrome-os-partner:19398 BRANCH=none TEST=manual: ensure rec_mode can be turned off $ dut-control rec_mode:off rec_mode rec_mode:off Change-Id: I387a53eb5b64bb0bf3a87fc47b5cca9b2063f6a9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50993
* Clarify help text for dumb USB port power controlDuncan Laurie2013-05-131-5/+5
| | | | | | | | | | | | | | | | | | The help text says to pass 0 or 1 for the mode but the code only accepts "on" or "off". Fix up the help text to match and have the display output for the port status also use on/off so it is consistent with the input. BUG=chrome-os-partner:18825 BRANCH=none TEST=manual: verify "usbchargemode 0 on" works as it is explained in the help text. Change-Id: Ib32dc68af93989d277aa84a1cb53ae9b66a8b595 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50838
* LM4: Support configurable host UART interfaceDuncan Laurie2013-05-134-59/+71
| | | | | | | | | | | | | | | | | | | | | | | Slippy uses UART2 instead of UART1 and so the EC needs to be able to tolerate having the host use a different interface. There are of course many ways to accomplish that but this approach adds two config variables to specify the host uart and the host uart irq. The UART port setup is split out to allow them to be configured separately rather than needing to be adjacent in a for loop. The interrupt functions were renamed (to ec and host) in order to indicate which interface they are responsible for. BUG=chrome-os-partner:19356 BRANCH=none TEST=boot slippy and see host serial output Change-Id: I1913ff3d650f329224c9654eee7bb7412fae5402 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50837
* Clean up SPI GPIOsRandall Spangler2013-05-133-20/+2
| | | | | | | | | | | | | | | | | | | SPI is always enabled on pit, so remove #ifdefs SPI1_CLK was aliased to AC_STATUS, which is left over from snow and doesn't exist on pit. That caused it to be driven high briefly during EC boot. Also set SPI pins for 40MHz speed so we can try faster SPI clock. BUG=chrome-os-partner:19304 BRANCH=none TEST=boot system; sspi 2:0 256 9f prints a bunch of FDs then FEEC010001 Change-Id: I10352cff3669d6a087939d9d8e302d70708e9ee3 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51023 Reviewed-by: Doug Anderson <dianders@chromium.org>
* Tidy comments for I2C passthru messageRandall Spangler2013-05-131-3/+3
| | | | | | | | | | | | | No code changes; just fix a few comments. BUG=chrome-os-partner:18778 BRANCH=none TEST=build code Change-Id: I7ed32b5af01a6dbd401334175b5a1b5b4786cac7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51017 Reviewed-by: Doug Anderson <dianders@chromium.org>
* slippy: Make EC_RCIN_L pin output and high by defaultDuncan Laurie2013-05-131-1/+1
| | | | | | | | | | | | | | This is causing the host to reset because this pin is going low when it is left as open drain, despite having a 3.3V pullup. BUG=chrome-os-partner:19355 BRANCH=none TEST=manual: boot on slippy without RCIN# causing reset Change-Id: I59e9316e85ce618edc84c7dd988d70ea4de1e71a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50836
* Slippy: Changes needed to boot EC without bricking.Bill Richardson2013-05-107-6/+64
| | | | | | | | | | | | | | | | This commits the hacks made during board bringup. Bugs can be filed and fixed based on this starting point. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Try it and see. Change-Id: Ia663eaf9a357633873b1b5d5cc6dbdda63513082 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50875 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Implement I2C passthru commandRandall Spangler2013-05-094-2/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a revised version of passthru which more closely resembles the kernel interface. It allows multiple read/write messages in a single transaction, and sends back one accumulated result. BUG=chrome-os-partner:18778 BRANCH=none TEST=On link, from root shell: ectool i2cxfer 0 0xb 6 0x21 Read bytes: 0x05 0x41 0x52 0x52 0x4f 0x57 (I did not actually run this with the updated code) On pit, in U-Boot: Read i2c values: Peach # crosec i2c md 48 0 0000: 00 00 3e 00 12 20 4b bf ff ff 20 00 1e 1e 1e 1f ..>.. K... ..... Peach # crosec i2c md 48 0 20 0000: 00 00 3e 00 12 20 4b bf ff ff 20 00 1e 1e 1e 1f ..>.. K... ..... 0010: 1f 1f 1f 1f 1f 1f 20 00 00 07 00 00 00 00 00 00 ...... ......... Update value at offset 10: Peach # crosec i2c mw 48 10 4 Peach # crosec i2c md 48 0 20 0000: 00 00 3e 00 12 00 0b 1f 1f ff 20 00 1e 1e 1e 1f ..>....... ..... 0010: 04 1f 1f 1f 1f 1f 20 00 00 07 00 00 00 00 00 00 ...... ......... Peach # On pit, in kernel: localhost ~ # i2cdetect -y -a -r 20 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- UU -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- localhost ~ # i2cdump -f -y 20 0x48 No size specified (using byte-data access) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: 00 00 3e 00 12 00 0b 1f 1f ff 20 00 1e 1e 1e 1f ..>.?.???. .???? 10: 1f 1f 0e 1f 1f 0e 20 00 00 07 00 00 00 00 00 00 ?????? ..?...... 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ localhost ~ # i2cset -f -y 20 0x48 0x10 0 localhost ~ # i2cdump -f -y 20 0x48 No size specified (using byte-data access) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: 00 00 3e 00 12 00 0b 1f 1f ff 20 00 1e 1e 1e 1f ..>.?.???. .???? 10: 00 1f 0e 1f 1f 0e 20 00 00 07 00 00 00 00 00 00 .????? ..?...... 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ localhost ~ # i2cset -f -y 20 0x48 0x10 0x1f localhost ~ # i2cdump -f -y 20 0x48 No size specified (using byte-data access) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: 00 00 3e 00 12 00 0b 1f 1f ff 20 00 1e 1e 1e 1f ..>.?.???. .???? 10: 1f 1f 0e 1f 1f 0e 20 00 00 07 00 00 00 00 00 00 ?????? ..?...... Change-Id: I14d47e1712828f726ac5caddc4beede251570ad3 Signed-off-by: Randall Spangler <rspangler@chromium.org> Updated to simplify protocol: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49958 Commit-Queue: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
* Add power button testVic Yang2013-05-085-169/+111
| | | | | | | | | | | | | This tests power button notification and debouncing. BUG=chrome-os-partner:19236 TEST=Pass all tests BRANCH=None Change-Id: Ief8bc24a8725e01734d84e76ab4b6ae0506b811f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50524 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Put test utility macros in headerVic Yang2013-05-0814-223/+126
| | | | | | | | | | | | | | Several test utility macros have been duplicated across tests. Let's put them in a single place. BUG=chrome-os-partner:19236 TEST='make runtests', 'BOARD=spring make tests' BRANCH=None Change-Id: Ib0c9f829715425cc23e33b8ef456b17dfadab13c Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50513 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Speed up mutex and kb_scan testVic Yang2013-05-082-3/+3
| | | | | | | | | | | | | The current delay is unnecessarily long. This CL shortens the delay. BUG=chrome-os-partner:19236 TEST='make runtests' BRANCH=None Change-Id: Ica07458e7ae15cf28c3482b6df96df66c0d45182 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50487 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* spring: Hard-limit DCP current at 1.5AVic Yang2013-05-081-3/+12
| | | | | | | | | | | | | | The spec suggests we cannot reliably go over 1.5A and gracefully recover. Let's avoid going over that limit. BUG=chrome-os-partner:19267 TEST=Build spring BRANCH=spring Change-Id: I07411ff3ce4107e0289c5af5365ef5a23fd23e4e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50321 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* i2c: Allow for i2c "ping" that's a write of 0 bytesDoug Anderson2013-05-081-1/+3
| | | | | | | | | | | | | | | | | | | The i2cdetect command on Linux likes to probe by doing a write of 0 bytes. Rather than always returning success because there was nothing to write, let's actually implement this command. At the moment we only implement for the stm32l. We also don't try to implement the "read of 0" bytes since I don't think anyone uses that. BUG=chrome-os-partner:18778 BRANCH=none TEST=i2cdetect -y -a 20 now detects the right devices Change-Id: Ia159ce9b8c957d5cd11f187f1a179ca5967bf96f Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50009 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* i2c: stm32l: Fix i2c reads of sizes other than 1Doug Anderson2013-05-082-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | The STM32L manual has a whole section on i2c master reads and describes the correct method for receiving exactly 2 bytes and more than 2 bytes. We weren't following those instructions and thus larger transfers weren't working. BUG=chrome-os-partner:19265 BRANCH=none TEST=i2cxfer r16 0x90 0 ...doesn't fail TEST=i2cxfer r 0x90 0 ...doesn't fail TEST=Use pydevi2c and test some commands: >>> tps = I2CDevice(20, 0x48) >>> [hex(x) for x in tps.Get(0, 20)] ['0x1e', '0x0', '0x3e', '0x0', '0x12', '0x20', '0x4b', '0xbf', '0xff', '0xff', '0x20', '0x12', '0x1e', '0x1e', '0x1e', '0x1f', '0x1f', '0x1f', '0x1f', '0x1f'] Change-Id: Ifaab6d8b700e099bcd9c374c70fca0983858ed3f Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50229 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Fix host command in 64-bit executableVic Yang2013-05-082-6/+6
| | | | | | | | | | | | | | On 64-bit platform, arrays should be aligned to 8 bytes. Also, change the order of host_command fields so that it's packed on both 32-bit and 64-bit platforms. BUG=chrome-os-partner:19257 TEST=Pass all tests. Print out and check the content of host commands. BRANCH=None Change-Id: I350a903bc11562d6d205c402548942f8967b75a5 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50467
* Add lid switch test and enable kb_mkbp testVic Yang2013-05-089-6/+163
| | | | | | | | | | | BUG=chrome-os-partner:19236 TEST=Pass both tests BRANCH=None CQ-DEPEND=CL:50467 Change-Id: I59cc407c2d1bf7f549ff9c46226cf7fa60fe7157 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50466
* spring: Improve charging current controlVic Yang2013-05-071-20/+37
| | | | | | | | | | | | | | | | | This includes: - Increase overcurrent retry count from 1 to 2. - Mark overcurrent event regardless of what current PWM duty cycle is. - PWM duty cycle settles faster. - PWM duty cycle starts from ~100%. BUG=chrome-os-partner:19001, chrome-os-partner:19037 TEST=Manual BRANCH=spring Change-Id: Idf007fb589fde3baef6c8975dfa1f2fc1ec6e95d Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50262 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Use uintptr_t when converting integer from/to pointerVic Yang2013-05-0711-25/+24
| | | | | | | | | | | | | | | Perviously we use uint32_t for this, but this doesn't compile for 64-bit environment (and likely doesn't for 16-bit either.) Use uintptr_t so that we don't get size mismatch errors. BUG=chrome-os-partner:19257 TEST=Run host emulated tests BRANCH=None Change-Id: I3cd66a745fa171c41a5f142514284ec106586acb Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50358 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f: Set ADC single read timeoutVic Yang2013-05-071-4/+13
| | | | | | | | | | | | | | | If an ADC read fails and EOC bit is somehow never set, we will be stuck in the read function holding mutex lock forever, which is really bad. Let's set a timeout for this. BUG=chrome-os-partner:18997 TEST=Boot Spring. Check ADC works. BRANCH=spring Change-Id: I19b108326f34f380497606fe92eabfaf0a778bb4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50338 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* spi: Fix OOBE in bounds-checking the replyDoug Anderson2013-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | There was an off-by-one error in bounds checking the reply. You could trigger it with pydevi2c with: >>> tps = I2CDevice(20, 0x48, force=True) >>> tps.Get(0, 249) The EC would show: ASSERTION FAILURE 'msg_len < sizeof(out_msg)' in reply() at chip/stm32/spi.c:184 BUG=chrome-os-partner:18778 BRANCH=none TEST=Run the above commands and see no error. Change-Id: I9789405a9d70c5dc3fa237504fea8f46a139386c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50254 Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix and enable SPI for pitRandall Spangler2013-05-075-79/+69
| | | | | | | | | | | | | | | | | | | | | | | | | I've simplified the SPI module, since we only ever use SPI1 (and there were already a number of places which assumed this was true). Somewhere along the way I fixed a number of problems keeping the code from compiling and working on STM32L. The code isn't currently used anywhere else, but should still work there (that is, I don't think I broke it working on STM32F if you re-enable it on some STM32F platform). BUG=chrome-os-partner:19073 BRANCH=none TEST=from u-boot console, sspi 2:0 64 9f0000 u-boot prints: FDFDFDFDFDFDFDFD ec prints: [193.740912 HC 0x9f][193.741141 HC err 1] [sjg: gpio optimization back in for now] [dianders: add comment as rspangler requested; update SOBs] Change-Id: Ib9419403e4e44dadc1f17681e48401882cb49175 Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49684
* Add persistent storage for emulatorVic Yang2013-05-075-1/+99
| | | | | | | | | | | | | | This is needed for non-volatile register emulation. Also, this can be used to implement system jump or reset flags. BUG=chrome-os-partner:19235 TEST=Run utils test. Check persistent storage file exists. BRANCH=None Change-Id: I699f95718ef6f5de6c3bbb4e37619ee015fb6c4a Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50313 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Pthread-based emulator for unit testingstabilize-4100.38.BVic Yang2013-05-0734-22/+964
| | | | | | | | | | | | | | This is the first version of pthread-based RTOS emulator. With this, we will be able to test high-level modules entirely on the host machine. BUG=chrome-os-partner:19325 TEST='make runtests' and see tests passing. BRANCH=None Change-Id: I1f5fcd76aa84bdb46c7d35c5e60ae5d92fd3a319 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49954 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add test for keyboard MKBP protocolVic Yang2013-05-063-0/+265
| | | | | | | | | | | | | A test that check keyboard MKBP module using keyboard scanning module and host commands. BUG=chrome-os-partner:19236 TEST=Pass the test BRANCH=None Change-Id: Ic22a2c8f3069d8e72c1222882073d428b733bca3 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50132
* spring: Fix S3 USB charging bugVic Yang2013-05-061-1/+1
| | | | | | | | | | | | | | | | The EC currently assumes the AP only provides USB power during S0, which is incorrect. This CL adds S3 so that it behaves when the device is suspended. BUG=chrome-os-partner:19190 TEST=Suspend and unplug power. Doesn't hear clicking sound. BRANCH=Spring Change-Id: Ice1421bda55b2fee408ba062ed3de7a697ccd0c8 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50093 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Define slippy GPIOs, make power sequencing task do nothing.Bill Richardson2013-05-023-730/+123
| | | | | | | | | | | | | | | | | | | This specifies the Slippy GPIOs. Because the power controls are completely different from Link, we have to gut the power sequencing task to do nothing. For bringup and test, we'll just manually set and get the GPIOs until we know exactly what we need to do. This is where the fun starts... BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Built everything, Link still works. Change-Id: Ic1ce1d4085298f49dd98d99e81e04835eca5f11c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50004
* Slippy uses dumb USB ports, not smart ones.Bill Richardson2013-05-023-106/+69
| | | | | | | | | | | BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Change-Id: I87459c177b8ae41b68e7157f26843eaf5ed93c60 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49975 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Remove Link peripherals from Slippy boardBill Richardson2013-05-022-84/+31
| | | | | | | | | | | | | | | | | Temp sensors, I2C devices, ADC inputs, and keyboard GPIOs are all different. This removes the things we don't need, connecting some of the things we will. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=none Doesn't break Link. Change-Id: Ifb9775d921f6e9952497bffa98d405353ed4df71 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49964 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Disable the charger task for Slippy bringupBill Richardson2013-05-022-8/+4
| | | | | | | | | | BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Change-Id: Idbcd297e3f77c02539dcb215bf8c60b1bcfb2d92 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49933
* Add some ifdefs to distinguish between Link and SlippyBill Richardson2013-05-026-6/+21
| | | | | | | | | | | | | | | I'll still need to decide what to do differently for Slippy, but for now let's just identify the places where there will likely be a difference. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Link still works. Change-Id: I950f0e5356ccf9838f2140d853122235f884e34f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49931
* Support power button on slippy, make it compile again.Bill Richardson2013-05-022-0/+3
| | | | | | | | | | BUG=chrome-os-partner:18825 BRANCH=slippy TEST=none Change-Id: If20ebaf8e718bc24d61a976026586445ccb6685e Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49914
* Fix I2C port configuration on pitRandall Spangler2013-05-022-16/+20
| | | | | | | | | | | | | | | | | | 1) Port needs to be open-drain. Missed this when porting from STM32F because open-drain and alternate function are set in the same register on STM32F and are different regs on STM32L. 2) Queue a stop condition if a transaction failed, so the clock goes back high. BUG=chrome-os-partner:18969 BRANCH=none TEST=i2cscan finds both the PMU at 0x90 and the battery at 0x16 Change-Id: I708b925e4e30da9d5864b74641b1cbe90c9313fe Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49898 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Split the USB port power control into smart and dumb versions.Bill Richardson2013-05-015-5/+208
| | | | | | | | | | | | | | | Also renaming to avoid confusion as to what's being charged. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Build everything, Link still works. Change-Id: I4205a1210c7dfe57cfbbdd740970ef57e6a011b8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49775 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Disable i2c for mccroskey. It's busted, but we don't care.Bill Richardson2013-05-011-1/+0
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=manual make BOARD=mccroskey Change-Id: Ide8d84d262a658d5c7fd33dec73353bc6ec797da Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49771 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* spring: Implement battery cut-off commandVic Yang2013-05-013-1/+23
| | | | | | | | | | | BUG=chrome-os-partner:18818 TEST='ectool batterycutoff' on Spring. BRANCH=spring Change-Id: Idf315562930744ae1e7425d6e15915b0477c2343 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49651 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Re-enable charging task on pitRandall Spangler2013-05-011-1/+1
| | | | | | | | | | | | | Now that I2C works, we can re-enable the charging task to debug battery charging. BUG=chrome-os-partner:18657 BRANCH=none TEST=in EC log, should see battery state messages Change-Id: I600d0152ba416c13420ce853b55206afba9f6cec Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49649
* Rename REINIT to IDLE0 in TPS65090 charge state machineVic Yang2013-05-013-26/+33
| | | | | | | | | | | | | | | | The state REINIT in TPS65090 charge state machine is more like IDLE0 state in charge_state.h. Rename it so that it's less confusing and easier to merge the two state machines in the future. Also move the state name definition to the header file. BUG=chrome-os-partner:18914 TEST=Boot Spring BRANCH=None Change-Id: I116438fedc46ff188dfb6a3964795715b5af4d1f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49732 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Monitor video detachment with ADC watchdogVic Yang2013-04-301-41/+72
| | | | | | | | | | | | | | | | | | This eliminates a per-second hook and removes a duplicated ADC read per second. Also, TSU6721 is now reset after every detachment. This way, we don't suffer from TSU6721 dirty state (most commonly seen after OTG dongle detached.) BUG=chrome-os-partner:17928 TEST=1. Test plugging/unplugging video dongle. 2. Test Toad cable mode switching. 3. Test charging with 200K charger. BRANCH=spring Change-Id: Ic035b7332e07ca385d766c735ce39efd31e46034 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49578 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Fix ADC watchdog bug and extend sample timeVic Yang2013-04-301-4/+6
| | | | | | | | | | | | | | | This fixes a bug in ADC watchdog that sample sequence is not set before enabling ADC watchdog. Also, current sample time isn't long enough for some weakly driven net. This extends ADC sample time to 13.5 cycles. BUG=chrome-os-partner:17928 TEST=Test with Toad cable and video dongle on Spring BRANCH=spring Change-Id: Iecdfd4aada4e974225a41144e213e92897f4797b Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49680 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Split x86_power.c into Ivybridge and Haswell variantsBill Richardson2013-04-306-9/+773
| | | | | | | | | | | | | | | | The voltage rails, inputs, and sequencing is completely different. Easiest to just handle it separately for each chipset. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Built Link, still works. Change-Id: Ibf26ef47cdf2284b7bfb3a2e5ccfb6841aba5ac6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49559 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Put a copy of test binaries under build/${BOARD}Vic Yang2013-04-301-1/+2
| | | | | | | | | | | | | | This puts a copy of test binaries at build/${BOARD}/test-*.bin. This way it is easier for us to get all test binaries. BUG=chrome-os-partner:19057 TEST='make tests' and check build/${BOARD}/test-*.bin BRANCH=None Change-Id: I8394cea6bee95f00fc01d725d2494ca5e222f47d Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49608 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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