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* Makefiles.rules: Add rule to create static libraries (.a)factory-atlas-11907.11.BNicolas Boichat2019-03-101-0/+6
| | | | | | | | | | | | | This will be useful for some targets (which will still need to fixup the dependencies themselves). BRANCH=none BUG=b:124804731 TEST=With follow-up TEST CLs, libprivate.a can be created Change-Id: I5a1f4726794b308824275530b08f327e679eb904 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1475108
* thermistor: Consolidate thermistor_get_temperature() functionsVijay Hiremath2019-03-092-52/+33
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I30064163b1af1090e75fbd4927ef25f77ddc043a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1510516 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* PD: Set Rp consistently on initial connection, increasing laterDiana Z2019-03-082-19/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This change ensures that the charge_manager always selects CONFIG_USB_PD_PULLUP on inactive ports. This should prevent us from presenting Rp 3.0A on an initial source connection, which can trigger CCD mode detection. This change also sets the correct Rp to represent our current capabilities after Vconn is sourced, when we should be able to set Rp 3.0A without triggering CCD. BRANCH=octopus BUG=b:123063171, b:124531988 TEST=on orbatrix with an HDMI dongle, added debug prints into the tcpci set_role_ctrl function to ensure that any Rp values set before the partner was attached were to 1.5 A and Rp was set to 3.0 A after the connection was stable, regardless of whether the dongle had been plugged into port 1 previously Change-Id: Iba38f9c07d85c1eb03ae1b8b3e476197a9841121 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1487116 Tested-by: Matt Wang <matt_wang@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* flash_ec: remove board-to-nrf51 conversion logicNamyoon Woo2019-03-081-8/+0
| | | | | | | | | | | | | Servod already knows ec_chip of hadoken is 'nrf51'. CQ-DEPEND=CL:1493037, CL:1491936 BUG=b:125837387 BRANCH=none TEST=none Change-Id: I96de6d1b98f6e13b99552c7c7aaf0b072371ccaf Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496196
* bq25710: Report VBUS as 0 when VBUS is too low to measurePhilip Chen2019-03-081-3/+7
| | | | | | | | | | | | BUG=b:124968142 BRANCH=none TEST=verify VBUS measurement via 'ectool usbpdpower' Change-Id: I1966537f394016706f96e975c7b54008ea8bfa33 Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1509176 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cortex-m: fix vecttable.c when compiling with clangTom Hughes2019-03-081-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Text section name is adding ",\"a\" @" to the section name. arm-none-eabi-objdump --disassemble-all \ ./build/nocturne_fp/RO/core/cortex-m/vecttable.o Before: Disassembly of section .text.vecttable,"a" @: 00000000 <vectors>: ... After: Disassembly of section .text.vecttable: 00000000 <vectors>: ... Comparing the text.vecttable elf section headers for gcc before and after this change, there is no difference to flags: arm-none-eabi-objdump -h \ ./build/nocturne_fp/RO/core/cortex-m/vecttable.o .text.vecttable 00000298 00000000 00000000 00000050 2**2 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE One difference when compiling with clang is that it sets the DATA attribute in the header, while gcc sets CODE. Since this is an array of addresses, not executable code, I think clang is actually correct: .text.vecttable 00000298 00000000 00000000 00000060 2**2 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA BRANCH=nocturne,nami BUG=chromium:931797 TEST=make buildall -j Change-Id: I16e57ccd988a8644ed179bed057647c16e96e134 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1470779 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* cbi: Add a new API for cbi_set_stringFurquan Shaikh2019-03-083-8/+26
| | | | | | | | | | | | | | | | | | | | This change introduces cbi_set_string that can be used by callers to add string data to CBI. Internally, this function ensures that the data is not NULL and call cbi_set_data for the string with a size of strlen + 1. It is added so that callers don't have to repeat the same operations for string data. BUG=b:124282048 BRANCH=None TEST=None Change-Id: Iad9da206c5e87735eac3adee6fce151fd1f0a53a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1506440 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cbi: Do not add tags if data size is zeroFurquan Shaikh2019-03-081-2/+11
| | | | | | | | | | | | | | | | | | | This change skips adding a tag to CBI if the size of its data is zero. Thus, callers of optional tags do not need to worry about checking if a tag should be added. It is taken care of within cbi_set_data. BUG=b:124282048 BRANCH=None TEST=Verified that MODEL_ID no longer shows up in cbi data. Change-Id: Id0c3da87a1479f5c52bd7b4f06840e5b4476b3d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1506439 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* arcada_ish: Add the gyro to the motion sensor arrayMathew King2019-03-082-8/+28
| | | | | | | | | | | | | The gyro for the LSM6DS3 is needed to get the ACCEL_FIFO working BUG=b:123634700 TEST=built and deployed to arcada device BRANCH=none Change-Id: I164e39dec6e2b9c10e7864fbcdcae41b1bfb8eb2 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1503799 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Nami: Make Vayne cutoff battery on critical chargestabilize-11895.95.Bstabilize-11895.89.Bstabilize-11895.72.Bstabilize-11895.118.Bstabilize-11895.109.Bstabilize-11895.108.Brelease-R74-11895.BDaisuke Nojiri2019-03-071-0/+10
| | | | | | | | | | | | | | | | | | | | Currently, Vayne and all other Nami's hibernate when battery is at critical level for 30 seconds. This patch makes Vayne cutoff the battery at critical charge. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/123727148 BRANCH=nami TEST=Verify Vayne shuts down on critical battery then battery is cutoff in 30 seconds. Verify AC plugin boot DUT on both ports. Change-Id: I1da572669c7fbe00753668810692d73ffe9f4bf8 Reviewed-on: https://chromium-review.googlesource.com/1487114 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_pd: Get current CC stateAyushee2019-03-073-10/+58
| | | | | | | | | | | | | | | | | CC state has the information of type of device attached and it is needed to configure the Intel virtual muxes hence returning the current CC state in USB_PD_CONTROL host command. BUG=None BRANCH=None TEST=Verified on Dragonegg, able to get correct CC state Change-Id: I917321b599a17381e2ffbe5e813e676df03abd47 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1468049 Commit-Ready: Ayushee Shah <ayushee.shah@intel.com> Tested-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* flash_ec: enable i2c_mux before it uses I2C interfaceNamyoon Woo2019-03-071-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is for it83xx EC. i2c_mux should be enabled before it does dut-control jtag_buf_on_flex_en , which uses i2c interface. Also during cleanup, servo setting should be restored after ftdii2c initialization and i2c_mux enabling. BUG=b:127696997 BRANCH=none TEST=ran flash_ec on Ampel with servo_v2 or Suzy-Q - servo_v2: http://gpaste/4877399499997184 - Suzy-Q: http://gpaste/5150426007601152 Tested with a fake board name for servod, and flash_ec without --board and --chip. $ ./util/flash_ec --image /tmp/a --verbose ERROR: Please check that servod is running or \ manually specify either --board or --chip. Tested without launching servod: ./util/flash_ec --board=coral --image /tmp/a --verbose Connection refused dut-control --port=9999 servo_type Connection refused ERROR: board 'coral' not supported. Please check \ that servod is running, or manually specify --chip. Change-Id: I8106c2f08fd74c8d86c985562cd4e1771df65287 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1506446 Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* i2c: fix style violations introduced by ab40ba67cVadim Bendebury2019-03-072-23/+21
| | | | | | | | | | | | | | | The patch in question was uploaded with numerous coding style violations. Fixing them to avoid warnings when cherry-picking the patch into different branches. BRANCH=cr50, cr50-mp BUG=none TEST=repo upload does not complain any more. Change-Id: I01e2786a509819ed914370b0ab276bb58e420365 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1500993 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* build: Fix print configs when _tsk_cfg_rw is not emptyPi-Hsun Shih2019-03-071-1/+1
| | | | | | | | | | | | | | | | | | | The _tsk_cfg_rw is a series of flags like HAS_TASK_MOTIONSENSE, which doesn't make sense to be used as a command. BRANCH=none BUG=b:126308353 TEST=make BOARD=kukui print-configs works TEST=print-configs on all boards, and check that output is not changed except for boards that RW Config can't be printed due to this bug. Change-Id: I513e88032abb8a418b22179d9e9c92a1dd8fbf3a Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1498954 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: Runtime configure GPIO settings between rev1 and rev2.Yilun Lin2019-03-075-67/+31
| | | | | | | | | | | | | | | | | | Considering we have more space on flash now, we would like to share one image between two board revisions to ease the development. This CL also removes unused powerrails in P1. TEST=flash image on P1 and P2, and check both boards boots. BUG=b:126315091 BRANCH=None Change-Id: Ifd0242396013e18e7e1cbc29048a5fc508626e5b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1505214 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* battery/max17055: Report 5 sec average currentTing Shen2019-03-071-2/+2
| | | | | | | | | | | | | | | | Revert CL:982334 since we might want a smoother battery life prediction curve. BUG=b:125946757 TEST=Run a full battery cycle and observe the values reported by ec. BRANCH=none Change-Id: I32d0f05377580df5dc4ff4bce97b6214e5698c2f Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1485041 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Reland "npcx: pwm: Use DCRn greater than CTRn to present its duty cycle is ↵Mulin Chao2019-03-074-26/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | zero." This is a reland of 93d7bcea8121869520b0d02bf94f95eb261bee05 with a fix for fan_is_stalled. Original change's description: > npcx: pwm: Use DCRn greater than CTRn to present its duty cycle is zero. > > In npcx pwm driver, it turns off pwm module directly when its duty cycle > is set to zero. But we saw pwm signal isn't turned off by the following > sequence: > 1. pwm_set_raw_duty(ch, 0); > 2. pwm_enable(ch, 1); > > Please notice setting zero in DCRn doesn't mean duty cycle is zero. > (NPCX duty cycle: ( (DCRn+1) / (CTRn+1) ) x 100). Hence in step 2, we > can observe a very low duty cycle once the driver enables pwm module. > > According to figure. 24 in npcx5's datasheet, setting DCRn greater than > CTRn means that the result of 16-bits comparator is always false. It > equals the duty cycle is zero. This CL adopts this method to present it > and removes the dependency between pwm_enable()/ pwm_get_enabled() and > pwm_set_raw_duty()/pwm_get_duty(). > > In order to make sure DCRn can be greater than CTRn, we also defined > the PWN maximum duty cycle is (0xFFFF -1) since both DCR and CTR are > 16-bits registers. > > BRANCH=none > BUG=b:123552920 > TEST=No build errors for npcx5/7 series. > > Test pwm console command on npcx5/7 evbs by the following sequence. > 1. pwm_set_raw_duty(ch, 0); > 2. pwm_enable(ch, 1); > And no symptoms are observed. PWM_CONFIG_ACTIVE_LOW flag is tested also > and no symptom occurred. > > Test fan control by faninfo & fanset console commands. Connect Sunon > 4-pins PWM fan and evb by following steps: > 1. Connect PWM0 to PWM pin of fan. > 2. Connect TA1_TACH1 and 3.3 PU on Tacho pin of fan. > 3. Connect 5V and GND pins of fan to power supply. > No symptoms are observed. > > Change-Id: I92517ff0bf3e027ae191be00112cd71ec4b55a2b > Signed-off-by: Mulin Chao <mlchao@nuvoton.com> > Reviewed-on: https://chromium-review.googlesource.com/1475096 > Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> > Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Bug: b:123552920 Change-Id: I4ea76c51811507ee4a35e5c0edfb70e9fb6c4c8b Reviewed-on: https://chromium-review.googlesource.com/1506115 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* kukui_scp/ipi: Clarify ipi_send() signature.Yilun Lin2019-03-072-2/+2
| | | | | | | | | | | | | | | | ipi_send() shuold not modify the buffer argument. This CL changes argument type from 'void *' to 'const void *'. TEST=make BOARD=kukui_scp -j BUG=b:120808999 BRANCH=None Change-Id: I1e629c7d6ba6902df1e8e2a21b7ac29bf3dffebf Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1490796 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Pi-Hsun Shih <pihsun@chromium.org>
* mkbp_event,include/config.h: Clarify MKBP delivery method.Yilun Lin2019-03-0721-26/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have two MKBP delivery methods: 1. define CONFIG_MKBP_USE_HOST_EVENT to notify via host event 2. undef CONFIG_MKBP_USE_HOST_EVENT to notify via GPIO interrupt It may become more complicated if new notification methods introduced. e.g.: mt_scp uses IPI, rather than host event and GPIO interrupt. This CL does: 1. add CONFIG_MKBP_USE_GPIO to explicilty declare that MKBP event are sent via GPIO interrupt. 2. CONFIG_MKBP_USE_CUSTOM for boards which have custmized methods. 3. Remove weak attribute in mkbp_set_host_active (which can be done with CONFIG_MKBP_USE_CUSTOM now. 4. Removes mkbp_set_host_active function in board Nocturne. It only deliver MKBP events through GPIO interrupt now. BRANCH=None BUG=b:120808999 TEST=grep -rn "CONFIG_MKBP_USE_GPIO\|EC_INT_L" board/ baseboard/ and see the result is reasonable: 1. EC_INT_L must be 1-to-1 mapped to define CONFIG_MKBP_USE_GPIO in every board, except that meep, yorp, ampton which are defined in baseboard octopus. 2. undef CONFIG_MKBP_USE_GPIO in bip and casta, which use host event, but also have baseboard octopus. Change-Id: I4af6110e4fd3c009968075c3623ef2d91cbd770b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1490794 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* flash_ec: remove board-to-npcx_(int_spi|uut) conversion logicNamyoon Woo2019-03-061-75/+20
| | | | | | | | | | | | | | | | | | Servod already knows ec_chip for atlas, cheza, hatch, octopus_npcx, grunt, and nocturne. CQ-DEPEND=CL:1493037, CL:1487322 BUG=b:125837387 BRANCH=none TEST=manually ran flash_ec on fleex and liara, careena with suzy-q and servo_micro. Change-Id: Iacdd61cf94231093714463ae46f8d670c1bad6ea Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1495476 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* hatch : Add volume buttons functionalityKashyap Nanavati2019-03-063-6/+10
| | | | | | | | | | | | | | | | | | | Enable config and gpio changes for volume buttons BUG=b:122799547 BRANCH=none TEST=gpioget shows volume UP/DOWN gpios and while pressing/releasing the button observed log messages on EC console ('Volume Up' was released/pressed) Also, we need to do the rework(volume down should be reroute to gpio93 from gpio57) on proto boards before testing. still no change in audio volume Change-Id: I8fae622550508eb3ab92f8c3b8a11d10d5ecbcee Signed-off-by: Kashyap Nanavati <kashyap.nanavati@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1504122 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* driver: lsm6dso: Add support to LSM6DSO IMUMario Tesi2019-03-067-0/+743
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support to LSM6DSO IMU sensor. Features included in this driver are: - Basic Sensor Read acc/gyro data - ODR and FS runtime configuration - FIFO water mark interrupt - Shared commons function with ST MEMs devices BUG=none BRANCH=master TEST=Tested on discovery target BOARD with LSM6DSO connected to EC i2c master bus and motion sense task running. Commands used to test LSM6DSO device are: - accelinit - accelrange - accelinfo All basic features tested, including: 1) ODR change: - accelrate 0 [13000:208000] - accelrate 1 [13000:208000] 2) FS Range change: - accelrange 0 [2:16] - accelrange 1 [250:2000] 3) Interrupt on FIFO water mark Signed-off-by: Mario Tesi <mario.tesi@st.com> Change-Id: If2984f7d0d30b0ef475e0525aca2bc365aa4fe21 Signed-off-by: Mario Tesi <mario.tesi@st.com> Reviewed-on: https://chromium-review.googlesource.com/1371364 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org>
* chip: stm32: Fix GPIO base addresses for STM32F4/LMoritz Fischer2019-03-061-3/+12
| | | | | | | | | | | | | | | | | | The CHIP_FAMILY_STM32L has the base addresses for the GPIO F, G and H banks swapped w.r.t CHIP_FAMILY_STM32F4 and the alphabetic order vs the base addresses. Break out the CHIP_FAMILY_STM32F4 case in the registers file, such that GPIOH bank works for both cases. BUG=none BRANCH=none TEST=Use pin PH0 on STM32F412/11, observe it actually toggling Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Change-Id: I9a639c4872f6e4c5b384cdab9e3da2f626e32227 Reviewed-on: https://chromium-review.googlesource.com/1481650 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chgstv2: Make board_critical_shutdown_check specify action on critical socDaisuke Nojiri2019-03-066-28/+53
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, board_critical_shutdown_check is used only in the context of CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF. It returns true to cutoff the battery or false to take no action. This patch extends board_critical_shutdown_check to allow it to control what actions to take on critical battery condition. With this change, each board can also customize critical battery actions with more granularity (per OEM, BOARD_VERSION, etc.). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/123727148 BRANCH=nami TEST=Verify a battery is cutoff at critical low charge on Scarlet and DUT wakes up by AC plugin on cros/firmware-scarlet-10388.B. Change-Id: Id49e860b05e21c3bfa4d75f27c48b55c2a3ad95f Reviewed-on: https://chromium-review.googlesource.com/1487113 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "npcx: pwm: Use DCRn greater than CTRn to present its duty cycle is ↵Daisuke Nojiri2019-03-063-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | zero." This reverts commit 93d7bcea8121869520b0d02bf94f95eb261bee05. Reason for revert: fan_is_stalled is broken Original change's description: > npcx: pwm: Use DCRn greater than CTRn to present its duty cycle is zero. > > In npcx pwm driver, it turns off pwm module directly when its duty cycle > is set to zero. But we saw pwm signal isn't turned off by the following > sequence: > 1. pwm_set_raw_duty(ch, 0); > 2. pwm_enable(ch, 1); > > Please notice setting zero in DCRn doesn't mean duty cycle is zero. > (NPCX duty cycle: ( (DCRn+1) / (CTRn+1) ) x 100). Hence in step 2, we > can observe a very low duty cycle once the driver enables pwm module. > > According to figure. 24 in npcx5's datasheet, setting DCRn greater than > CTRn means that the result of 16-bits comparator is always false. It > equals the duty cycle is zero. This CL adopts this method to present it > and removes the dependency between pwm_enable()/ pwm_get_enabled() and > pwm_set_raw_duty()/pwm_get_duty(). > > In order to make sure DCRn can be greater than CTRn, we also defined > the PWN maximum duty cycle is (0xFFFF -1) since both DCR and CTR are > 16-bits registers. > > BRANCH=none > BUG=b:123552920 > TEST=No build errors for npcx5/7 series. > > Test pwm console command on npcx5/7 evbs by the following sequence. > 1. pwm_set_raw_duty(ch, 0); > 2. pwm_enable(ch, 1); > And no symptoms are observed. PWM_CONFIG_ACTIVE_LOW flag is tested also > and no symptom occurred. > > Test fan control by faninfo & fanset console commands. Connect Sunon > 4-pins PWM fan and evb by following steps: > 1. Connect PWM0 to PWM pin of fan. > 2. Connect TA1_TACH1 and 3.3 PU on Tacho pin of fan. > 3. Connect 5V and GND pins of fan to power supply. > No symptoms are observed. > > Change-Id: I92517ff0bf3e027ae191be00112cd71ec4b55a2b > Signed-off-by: Mulin Chao <mlchao@nuvoton.com> > Reviewed-on: https://chromium-review.googlesource.com/1475096 > Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> > Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Bug: b:123552920 Change-Id: Iece29c665d3a7518159514291f3c17a7b58c3284 Reviewed-on: https://chromium-review.googlesource.com/1505014 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* bq25710: Disable VDPM-triggered PROCHOT by defaultPhilip Chen2019-03-062-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | PROCHOT_VDPM is triggered in every AC detach when VBUS drops. Ideally we may want to check the battery voltage when PROCHOT_VDPM is triggered. If battery voltage is not too low, we clear the flag and release PROCHOT pin. However, this PROCHOT profile isn't very useful for the case of AC detach, because EC already knows AC detach event from GPIO_AC_PRESENT pin and can check battery voltage then. PROCHOT_VDPM does provide finer-grained monitoring for VBUS, but before we come up with a good use of this profile, we may want to just disable this profile to prevent PROCHOT pin from being asserted in every AC detach. So let's disable PROCHOT_VDPM at charger initialization. BUG=b:123931545 BRANCH=none TEST=boot hatch and then unplug AC, verify bq25710 doesn't assert PROCHOT Change-Id: Icbbbb5572f26a450d0df92890d99fc216564a981 Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1479872 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* kukui: Update virtual usb mux info.Yilun Lin2019-03-061-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Update the mux info which would be used by AP. TEST=1. Modify dts, and enable extcon-usbc-cros-ec kernel module 2. cat /sys/devices/platform/*/extcon/extcon0/state, and see when DP plugged: USB=0 USB-HOST=1 DP=1 when DP unplugged: USB=0 USB-HOST=1 DP=0 BUG=b:124345449 BRANCH=None Change-Id: Id1f2259c6ae18a70f68634477282cb396ab1a0ed Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1472413 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "Servo v4: reduce RO flash size"Todd Broch2019-03-062-8/+2
| | | | | | | | | | | | | | | | | | | | | This reverts commit 590a45db85507787af77cf6bfc8ae63499cbf1cc. BRANCH=none BUG=b:124465253 TEST=manual, Running sudo servo_updater -b servo_v4 --force -f build/servo_v4/ec.bin sudo servo_updater -b servo_v4 --force -f build/servo_v4/ec.bin passes without failure, servo_updater.ServoUpdaterException: usb_updater2 exit with res = 3 Change-Id: Ied9939192c30342bb6314e6dccfcd56d950659ab Signed-off-by: Todd Broch <tbroch@google.com> Reviewed-on: https://chromium-review.googlesource.com/1497438 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* cr50: CCD flags not read correctly on first factory bootKeith Short2019-03-061-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | During the first factory boot flow, the CCD flags are not read correctly. In this boot path, the ccd_config_loaded flag is not set until after the first calls to HOOK_CCD_CHANGE. Changed ccd_load_config() to always call HOOK_CCD_CHANGE after setting ccd_config_loaded flag. Changed ccd_save_config() so that it doesn't call HOOK_CCD_CHANGE if the ccd_config_loaded flag is not set. BUG=b:126971514 BRANCH=cr50 TEST=Erase the board ID, peform rollback to 0.0.22, and then upgrade to 4.14 firmware. On Wilco, confirmed that GPIO_FACTORY_MODE(GPIO_I2C_SCL_INA) is driven high during first factory boot flow. Change-Id: Ib6764085d2911abe330c7e580fd6b31bbfe6f89d Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496679 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* scratch_reg: reorganize BOARD_ALL_PROPERTIESMary Ruthven2019-03-061-5/+11
| | | | | | | | | | | | | | | | List one board property per line and alphabetize the list, so the BOARD_ALL_PROPERTIES definition is more readable. BUG=none BRANCH=cr50 TEST=none Change-Id: Ic0a8d83b380c4f61c89c54535a1c350daf4ae39f Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1481656 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use closed loop reset based on board propertyMary Ruthven2019-03-063-10/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the closed loop reset when cr50 needs to reset the device. Cr50 expects the board to reset in three places: board_reboot_ap, board_reboot_ec, or during init after any cr50 reset other than deep sleep. This change modifies these to use the closed loop reset if the board property is set. In board_reboot_ap and board_reboot_ec it calls board_closed_loop_reset instead of doing the normal reset steps if the board property is set. In init_ap_detect call board_closed_loop_reset if cr50 just resumed from any reset other than hibernate. Don't trigger the tpm_rst_isr manually. BUG=b:123544145 BRANCH=cr50 TEST=manual Flash firmware that supports resetting the AP when EC_RST_L is asserted. Reboot cr50 and verify deferred_tpm_rst_isr is only called after tpm_rst_asserted. Open Cr50. Verify the AP is reset Flash old Mistral firmware which seems to take around 12 seconds for the warm reset to happen. Boot the AP. Reboot cr50 while the AP is up. The AP wont reset for a while. While the AP is still up, verify Cr50 keeps EC_RST_L asserted, the AP state is Unknown, and tpm commands fail while the AP is in this state. Eventually the AP resets. Make sure the TPM becomes usable again and the AP state is on. Change-Id: I6f0e8728717f1ed35c96b2669f1796078ebf93f7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1447001 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add closed loop reset property to mistralMary Ruthven2019-03-061-1/+2
| | | | | | | | | | | | | BUG=b:123544145 BRANCH=cr50 TEST=make buildall -j Change-Id: I39309c73957f0698b573342880a083d14077519f Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1480712 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* cr50: add no ina support board propertyMary Ruthven2019-03-064-11/+24
| | | | | | | | | | | | | | | | | | Mistral also uses the ina pins as gpios. Add a board property for no ina support. Use that instead of the closed source set board property for the usb_i2c_enable code. BUG=b:124949444 BRANCH=cr50 TEST=flash on mistral. Make sure EN_PP3300_INA_L isn't asserted when ccd is enabled. Change-Id: If06a65bc4a1ef7b374a44fc53d65ea5daed336df Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1480711 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* cr50: set ap state to unknown while waiting for resetMary Ruthven2019-03-061-0/+3
| | | | | | | | | | | | | | | While cr50 is waiting to see the AP reset, set the state to unknown. BUG=b:123544145 BRANCH=cr50 TEST=firmware_Cr50DeviceState Change-Id: I33f5758a6e3c41bd1c9d0c69ced8685365005a28 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1447000 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tpm_registers: check if_stop has been initialized before calling itMary Ruthven2019-03-061-1/+3
| | | | | | | | | | | | | | | | | It's possible tpm_stop will be called before the interface has been registered. Don't call if_stop unless it has been initialized. BUG=none BRANCH=cr50 TEST=none Change-Id: I45b6d11553ce0eda5b097184a5be81f8b79726aa Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1480710 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* cr50: add a closed loop reset functionMary Ruthven2019-03-063-5/+37
| | | | | | | | | | | | | | | | | | | Add a function that asserts EC_RST_L until TPM_RST_L gets asserted. Disable sleep using SLEEP_MASK_AP_RUN while waiting for the AP reset. Disable tpm communications using tpm_stop until the AP is reset. BUG=b:123544145 BRANCH=cr50 TEST=run 'ecrst cl' on mistral, scarlet, and soraka. Make sure the sleepmask is cleared correctly and the TPM works after the reset is complete. Change-Id: I5971b45b7a69fd24887a7c22ee7984972b7828ae Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1444411 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* cr50: use interrupts for ap_stateMary Ruthven2019-03-064-67/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ap_state machine as is is pretty hard to modify as it's implemented now. The state machine has to have certain states set at certain points to handle AP detection properly and it is very slow to detect AP off. It takes a second and it will only detect AP off if TPM_RST_L stays asserted for 1 second. This change modifies ap_state.c to use interrupts instead of polling, so it can detect when the AP is off immediately and wont miss any resets. This is required for the new closed loop reset feature. Cr50 has to be able to detect all AP resets and it can't take 1 second for cr50 to determine the AP is off. We used polling because we had to use APTX_CR50RX to detect AP state for a while. The UART level changes a lot. Processing all of the interrupts really impacted CCD uart, so we couldn't use interrupts to detect the state. We had to poll. AP UART isn't used to detect AP state anymore on any platforms, so it's ok to switch to interrupts now. APTX_CR50RX is still used for ap uart detection in ap_uart_state.c. This change doesn't modify that at all. BUG=b:123544145 BRANCH=cr50 TEST=Make sure suspend and reboot stress tests still work on a bob and a soraka. Check that Cr50 detects the AP state correctly. Change-Id: I80eb97aecffe460b7857e66e7204a55b72c9dd47 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1446999 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* gsctool: make sure programmed image size is properly alignedVadim Bendebury2019-03-061-0/+6
| | | | | | | | | | | | | | | | | Flash driver of the g chip requires that the size of the programmed area is evenly divisible by 4. This patch makes sure that gsctool complies with this requirement. BRANCH=none BUG=b:127295653 TEST=without this patch attempts to update Cr50 to an image built from ToT fails, with this patch the same image programs just fine. Change-Id: I064d22130a56e9e703f728bc898fd5de82d365d4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1499657 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: use board prop to mask straps if config is ambiguousMary Ruthven2019-03-051-6/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cr50 tries to determine SPI vs I2C by checking that there are pullups on only the I2C or SPI straps. If there are pullups on both, it can't use the straps to determine SPI vs I2C, so it just defaults to the default board properties (I2C and PLT_RST_L). This change uses last board properties to determine I2C vs SPI if the straps can't be used to make this determination. The actual strap pins are only connected to the pullup or pulldown being used for the straps. It's pretty likely these strap readings are correct. The unused straps are connected to the AP which can interfere with these readings if it has a pullup on any of these signals. This change uses the last board property configuration to determine I2C vs SPI and mask unused straps to try and remove signals the AP is interfering with. If this masked config isn't valid, then cr50 will still fall back to using I2C and PLT_RST_L. BUG=b:124777847 BRANCH=cr50 TEST=manual flash mistral. Reboot cr50. Make sure it doesn't switch to I2C config # Verify cr50 selects spi Ambiguous strap config. Use spi based on old brdprop. Use DBG image to set invalid I2C and SPI board property settings rollback to the image that checks if I2C and SPI brdprop settings are invalid. Verify Mistral can't find a valid strap and uses I2C. Use DBG image to select SPI and I2C board properties. Make sure this is rejected as invalid. # enable writing to long life scratch 1 rw 0x40000128 2 # write old board properties with i2c and spi rw 0x40000130 (OLD_BRDPROP | 3) for mistral - rw 0x40000130 0x811143 # rollback to image that checks old board properties if # straps are ambiguous rollback # Verify Mistral doesn't use old AP bus setting and # defaults to the default properties. Invalid strap pins! Default properties = 0x42 Use DBG image to select neither the SPI or I2C board property. Make sure this is rejected as invalid. # enable writing to long life scratch 1 rw 0x40000128 2 # write old board properties without i2c or spi rw 0x40000130 (OLD_BRDPROP & ~3) for mistral - rw 0x40000130 0x811140 # rollback to image that checks old board properties if # straps are ambiguous rollback # Verify Mistral doesn't use old AP bus setting and # defaults to the default properties. Invalid strap pins! Default properties = 0x42 Use dbg image to modify board properties to select I2C. rollback and make sure Cr50 continues using I2C. # enable writing to long life scratch 1 rw 0x40000128 2 # write old board properties with i2c for mistral - rw 0x40000130 0x811142 # write old board properties with i2c rollback # Verify cr50 selects i2c Ambiguous strap config. Use i2c based on old brdprop. Change-Id: I409e2f3ab1339aafe450b35259adc3c4c5d870ae Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1483816 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* flash_ec: do not mark NEED_SERVO 'no' for it83xxNamyoon Woo2019-03-051-1/+1
| | | | | | | | | | | | | | | | Servod is required to flash it83xx chip. BUG=b:124388894 BRANCH=none TEST=manually ran flash_ec. $ ./util/flash_ec --board=dragonegg --image ${IMG} Change-Id: I50e8599e8fedce6dd51bc217128dd8142557269b Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1500892 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* i2c:xfer i2cwrite invalid in ec consoleTony Zou2019-03-051-16/+16
| | | | | | | | | | | | | | | | | | | In command xfer i2cwrite port addr offset value 16bit offset and 8bit offset call the wrong i2c write interfacefix it. BRANCH=none BUG=b:126820386 TEST=1:) Build flapjack EC and flash to DUT , in ec console can read/write i2c device correctly. 2:) Build kukui EC , build pass. Change-Id: Ib3aa058ae0917fe62f38bc500a8227d6e36dbab1 Reviewed-on: https://chromium-review.googlesource.com/1496676 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Tony Zou <zoutao@huaqin.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: pwm: Use DCRn greater than CTRn to present its duty cycle is zero.Mulin Chao2019-03-053-21/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx pwm driver, it turns off pwm module directly when its duty cycle is set to zero. But we saw pwm signal isn't turned off by the following sequence: 1. pwm_set_raw_duty(ch, 0); 2. pwm_enable(ch, 1); Please notice setting zero in DCRn doesn't mean duty cycle is zero. (NPCX duty cycle: ( (DCRn+1) / (CTRn+1) ) x 100). Hence in step 2, we can observe a very low duty cycle once the driver enables pwm module. According to figure. 24 in npcx5's datasheet, setting DCRn greater than CTRn means that the result of 16-bits comparator is always false. It equals the duty cycle is zero. This CL adopts this method to present it and removes the dependency between pwm_enable()/ pwm_get_enabled() and pwm_set_raw_duty()/pwm_get_duty(). In order to make sure DCRn can be greater than CTRn, we also defined the PWN maximum duty cycle is (0xFFFF -1) since both DCR and CTR are 16-bits registers. BRANCH=none BUG=b:123552920 TEST=No build errors for npcx5/7 series. Test pwm console command on npcx5/7 evbs by the following sequence. 1. pwm_set_raw_duty(ch, 0); 2. pwm_enable(ch, 1); And no symptoms are observed. PWM_CONFIG_ACTIVE_LOW flag is tested also and no symptom occurred. Test fan control by faninfo & fanset console commands. Connect Sunon 4-pins PWM fan and evb by following steps: 1. Connect PWM0 to PWM pin of fan. 2. Connect TA1_TACH1 and 3.3 PU on Tacho pin of fan. 3. Connect 5V and GND pins of fan to power supply. No symptoms are observed. Change-Id: I92517ff0bf3e027ae191be00112cd71ec4b55a2b Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1475096 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/minute-ia: Add __ram_free to link scriptNicolas Boichat2019-03-051-4/+2
| | | | | | | | | | | | | | | | | | Use __ram_free instead of defining a fake FLASH region in the linker script. This reverts commit 6fd1d521e48 ("core/minute-ia: Add FLASH memory configuration"). BRANCH=none BUG=b:123327630 TEST=make BOARD=atlas_ish -j shows *** 592328 bytes in RAM still available on atlas_ish **** Change-Id: Iacce7924dd867024e5381e31f1afb12d13305f3a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496686 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* Makefiles.rules: Fix free space message on boards with no flashNicolas Boichat2019-03-051-3/+7
| | | | | | | | | | | | | | | | | | | | | | kukui_scp has no flash, so let's just print the leftover space in RAM instead. BRANCH=none BUG=b:123327630 TEST=make buildall -j 2>&1 | grep "still available" | sort > avail before and after this change, only this line changes: *** -29956 bytes in flash and 468976 bytes in RAM still available on kukui_scp **** *** 468976 bytes in RAM still available on kukui_scp **** TEST=kukui_scp does not appear in "Tightest boards' RW flash" summary. TEST=make savesizes/newsizes still reports changes in RAM space on kukui_scp Change-Id: I4e17a142777ae20bb8e8c66b5402edf2838250a3 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496685 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* kukui_scp: Add rpmsg name service.Peter Shih2019-03-044-0/+31
| | | | | | | | | | | | | | | | rpmsg name service provide a way for firmware to announce available rpmsg channels and its IPI id to AP, without AP having to hard-code all the IPI ids. BUG=b:120953723 TEST=manually BRANCH=none Change-Id: I8ec539a45b58f20e70a798ede4abaad5a7bb4360 Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389986 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* makefile: add manifest header supportJett Rink2019-03-042-1/+66
| | | | | | | | | | | | | | | | | | The ISH FW image needs to have a static manifest header prepended to built ISH image before it can be loaded on to hardware. The header we prepend is static and is the bare minimum to make the corresponding shim loader work correctly. BRANCH=none BUG=b:122371717,b:124788278 TEST=ec.bin output will chain load properly when sent to the kernel driver. Change-Id: I5458782d70308c99e297b823fd085a74480d252e Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1490671 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* flash_ec: remove some boards from BOARDS_IT83XXNamyoon Woo2019-03-021-3/+0
| | | | | | | | | | | | | | | | | | Servod already knows ec_chip of ampton, bip and dragonegg is 'it83xx'. CQ-DEPEND=CL:1493037 BUG=b:125837387 BRANCH=none TEST=manually ran flash_ec on bit, dragonegg with servo_v2 $ ./util/flash_ec --board=bip --image ${IMG} $ ./util/flash_ec --board=dragonegg --image ${IMG} Change-Id: Ibd2faa5cffdacf30b89935203f4343e3a064a408 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496198 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* flash_ec: remove board-to-mec1322 conversion logicNamyoon Woo2019-03-021-10/+0
| | | | | | | | | | | | | | Servod already knows ec_chip of chell, glados and strago is 'mec1322'. CQ-DEPEND=CL:1493037 BUG=b:125837387 BRANCH=none TEST=none Change-Id: I49dba2b33aaab40b9e86354cca5b7c5f22ab59a6 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496162 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* flash_ec: remove board-to-LM4 conversion logicNamyoon Woo2019-03-021-8/+0
| | | | | | | | | | | | | | | | | Servod already knows ec_chip of Samus is 'lm4'. CQ-DEPEND=CL:1493037 BUG=b:125837387 BRANCH=none TEST=manually ran flash_ec on samus with servo_v2. $ ./util/flash_ec --board=samus --image ${IMG} Change-Id: Ib87a4231d5c19bf2da0e3e115ab9ce9b76cc8517 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1495475 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* flash_ec: remove some boards from BOARDS_STM32.Namyoon Woo2019-03-021-9/+0
| | | | | | | | | | | | | | | | | | Servod already knows ec_chip of big, blaze, elm, flapjack, hammer, kitty, kukui, oak, and scarlet is 'stm32'. CQ-DEPEND=CL:1493037, CL:1491936 BUG=b:125837387 BRANCH=none TEST=manually ran flash_ec on scarlet with suzy_Q. $ ./util/flash_ec --board=scarlet --image ${IMG} Change-Id: I1f7a2b3aa6e63c5b22d22de3d23cf9cbb0585910 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496382 Reviewed-by: Wai-Hong Tam <waihong@google.com>
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