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* Convert panic() to C codeSimon Glass2012-06-084-110/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the implementation of panic into C code. Only a very small part needs to be in assembler, and the reset is easier to maintain as C. As part of this, define panic_putc() and panic_puts() which directly wite to the UART. To make things more convenience for the future, add a simple printf() implementation in the panic path. This is not reliant on the uart buffering system being in a happy state. However, we do call the emergency flush so that our panic message will appear after previous output rather that surpressing it (which would be extremely confusing). Code/data size for panic.o grows by about 200 bytes, but this is mostly due to the increased flexibility. text data bss dec hex filename 292 272 0 564 234 old panic.S 692 3 48 743 2e7 new panic.c BUG=chrome-os-partner:10146 TEST=manual: build and boot on snow: > rw 0x06000000 === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :00000047 r2 :06000000 r3 :200013dd r4 :00000000 r5 :080052cc r6 :200013d0 r7 :00000002 r8 :00000000 r9 :200013de r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002a5d pc :08003962 Rebooting... Change-Id: If3e3f572e0f32af780b6ebda235b1b3cde4de5e4 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24503 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* qemu: allow to boot link EC firmwareVincent Palatin2012-06-081-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | Add the minimal amount of stubs (namely MOSCCTL, UARTCC and FLASH_FMPPEx registers) to the emulation to be able to boot link EC firmware and pass OS tests. the QEMU binary is generated from the chromeos-ec-0.15.1 sandbox of the chromium.org qemu.git repository at hash 1a48940. I will add next better GPIO control and default states to ensure we are booting the proper mode. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:10240 TEST=make qemu-tests BOARD=link ./util/run_qemu_test -b link Change-Id: I3d7b9247628133289e0ef04bb7d85c7438b6ed81 Reviewed-on: https://gerrit.chromium.org/gerrit/24880 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* EC: alphabetize command list in help messageLuigi Semenzato2012-06-081-20/+20
| | | | | | | | | | BUG=none TEST=none Change-Id: I00ac033d36a8472007ea66a4aebde003970cd1a2 Signed-off-by: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24878 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fix typo in ectool help.Bill Richardson2012-06-081-4/+2
| | | | | | | | | | BUG=none TEST=none Change-Id: I54f24672dd8294b17bae1de4eae2f2791c73998d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24855 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add option to adjust delay for indiviual temperature sensorVic Yang2012-06-083-14/+18
| | | | | | | | | | | | | | | | | | | | | | Perviously we have a 10-second delay for all temperature sensor. This is not suitable for CPU temperature. Let's change that to have an option to set the delay length for each temperature sensor. And also shorten the delay of TMP006 sensor to 7 seconds, that of EC internal temperature to 4 seconds, and that of PECI CPU temperature to 0 second. Signed-off-by: Vic Yang <victoryang@chromium.org> BUG=chrome-os-partner:10233 TEST=Check EC issued warning as soon as CPU temperature reached the threshold. (cherry picked from commit cf24df7f3ee24eaa5dbeae3b304d11ddada9a914) Change-Id: Id2cc4a437bde15697afe4020b6153e5d13466759 Reviewed-on: https://gerrit.chromium.org/gerrit/24694 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Ready: Vic Yang <victoryang@chromium.org>
* Refactor the i8042 module to be thread-safe.Louis Yung-Chieh Lo2012-06-074-58/+182
| | | | | | | | | | | | | | | | | | Any command/data coming from host will be placed in from_host queue, and the interrupt handler returns immediately. The i8042_command_task() will handle them later. Data reply to the host will be protected by the mutex. BUG=chrome-os-partner:10090 TEST=randomly play around on the link board. Change-Id: Ic19d5abd1abf8dc261ddaad4224cd9305c2f36a4 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24299 Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Reviewed-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
* fix QEMU OS testsVincent Palatin2012-06-073-5/+5
| | | | | | | | | | | | | | | | | | - update strings which were modified by the message text "compression" - updated QEMU which supports a couple of additional registers for LM4F (getting internal oscillator calibration status and writing timer counter through TAV) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:10008 TEST=make qemu-tests Change-Id: Idf0ee13f354b4e14405e949861d426f3e4c3022b Reviewed-on: https://gerrit.chromium.org/gerrit/24827 Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Don't echo the NV recovery requests back to the BIOS. It knows.Bill Richardson2012-06-071-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | When recovery is required, it will be because there's either a hardware pin pulled somewhere, or because the recovery_reason is set in NVRAM. Coreboot and U-Boot can see both of those, so the EC shouldn't make up a new reason. If it does, it changes the original cause. BUG=chrome-os-partner:9706 TEST=manual Reset the EC using ESC+Power (Refresh+Power on EVT). At a root shell, run crossystem recovery_request=11 reboot When you see the Recovery screen, press TAB. It should say recovery_reason: 0x0b We have no idea what this means Prior to this fix, you'd see recovery_reason 2 instead, which is wrong. Change-Id: Ie54185471927e7e829962d30bba9d142d593088f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24152 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix printing hex numbersRandall Spangler2012-06-071-2/+2
| | | | | | | | | | | | | | | | Off-by-one is not my friend. BUG=chrome-os-partner:10206 TEST=manual 1. rw 0x20000000 2. ww back the same number printed 3. rw 0x20000000. should match Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: I61e0d26cf4cb274a88326d4e7d24ff1c82d6e515 Reviewed-on: https://gerrit.chromium.org/gerrit/24756 Reviewed-by: Simon Glass <sjg@chromium.org>
* EC: snow: keyboard: fix incorrect index calculation with empty fifoLuigi Semenzato2012-06-071-2/+2
| | | | | | | | | | | | | | | | | | | When kb_fifo_start is 0, the index calculation yields -1 because C got the mod (%) operation arguably wrong. By adding KB_FIFO_DEPTH to the index before computing the mod with respect to KB_FIFO_DEPTH, we avoid the negative case and (obviously) produce the same result in all other cases. BUG=chrome-os-partner:10247 TEST=saw incorrect state from kernel log before fix: could not repro after. Signed-off-by: Luigi Semenzato <semenzato@chromium.org> Change-Id: I3a30c229dc9f762dd45203e842128811a24cf53f Reviewed-on: https://gerrit.chromium.org/gerrit/24730 Tested-by: Luigi Semenzato <semenzato@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Luigi Semenzato <semenzato@google.com>
* console: Support delete as well as backspaceSimon Glass2012-06-071-2/+2
| | | | | | | | | | | | | | | | Some terminals do not generate backspace correctly, so accept delete as a substitute. BUG=chrome-os-partner:10147 TEST=manual: ssh into workstation, then telnet to serial port (with ser2net running) See that the backspace key now works correctly, instead of injecting strange characters into the terminal. Change-Id: Ief6f2bcab9b8e82cb5720d18c596326b49ffc336 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24715 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Stay in G3 when power appliedRandall Spangler2012-06-072-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We were going straight to S5. When the PCH first goes into S5 after power-loss, it decides to boot for some reason. So, stay in G3. Still exit G3 if waking from hibernate or if the power button is pressed when the EC boots on a power-on reset. BUG=chrome-os-partner:10239 TEST=manual 1) Unplug battery and AC power. Plug in AC power. System does not boot. 2) Press power button. System boots now. 3) From console, 'hibernate 10'. Close and open lid. System boots. 4) From console, 'hibernate 10'. Press power button. System boots. 5) Hold power+esc+refresh. System boots into recovery. 6) Hold power+esc. EC reboots. Release esc. System stays off. 7) Unplug battery and AC power. Plug in AC power while holding power button. System boots. Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: I7612a40ab5ebe41d356ac3a6b89cedf1174125f4 Reviewed-on: https://gerrit.chromium.org/gerrit/24729 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix detecting boot keys on EVTRandall Spangler2012-06-071-3/+6
| | | | | | | | | | | | | | | | | EVT uses power+refresh as the Silego combination not power+esc, so holding down power+esc+D wouldn't turn on the fake dev switch, and holding down power+refresh+D wouldn't either because on a short enough tap the EC would measure refresh as still held down. BUG=chrome-os-partner:10210 TEST=manual 1) hold down reset combo + D -> turns on fake dev mode 2) hold down reset combo + F -> turns off fake dev mode Change-Id: I85b51d3684500ae821513e71a2cd01aa4fcf5e8f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24646
* Misc keyboard module cleanupRandall Spangler2012-06-075-123/+46
| | | | | | | | | | | Should be no functional changes; this is just rearranging code. BUG=none TEST=boot system and type on console; should still work Change-Id: I1c0d44db2d32048b1aaf458728b887b4a008c8cd Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24644
* Switch keyboard outputs to open-drainRandall Spangler2012-06-071-21/+13
| | | | | | | | | BUG=chrome-os-partner:10209 TEST=boot system and type on console; should still work Change-Id: I9f89420acd59947baee445fc2a655857809f8fb9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24636
* Put correct RO_FRID, RW_FWID_A, RW_FWID_B entries in FMAPBill Richardson2012-06-073-6/+16
| | | | | | | | | | | | BUG=chrome-os-partner:9495 TEST=manual Build image, run dump_fmap. Look for those entries. Change-Id: I6dfc38e00ce1e11ea24c8392d1691fab32a59d1f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24696 Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* Move printf() formatting to its own file to enable re-useRandall Spangler2012-06-078-210/+350
| | | | | | | | | | | | | Also add snprintf(), and %X format code. BUG=chrome-os-partner:10206 TEST=timerinfo; should print correctly. 'ectool battery' on host side should print same serial as 'battery' on EC console. Change-Id: I5c9f69d1a20ee5d0a59440c122655adbf62c9aea Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24635 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* Flash host command functions should be staticRandall Spangler2012-06-061-9/+9
| | | | | | | | | | | | Since they're not used outside of this source file. BUG=none TEST=if it builds, it worked Change-Id: I92c13c7d58e0e6977c2696746c9d95cbdcb6dbd5 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24638 Reviewed-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
* Fix setting PROCHOT levelRandall Spangler2012-06-061-2/+2
| | | | | | | | | | BUG=chrome-os-partner:10205 TEST=boot system; still works Change-Id: I05808068954af40ef8d259e5dc5c94324e8e256d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24621 Reviewed-by: Simon Glass <sjg@chromium.org>
* Add powerinfo command to display CPU stateBill Richardson2012-06-061-0/+11
| | | | | | | | | | | | BUG=chrome-os-partner:10194 TEST=manual Run "powerinfo" at the EC console. Change-Id: I4c8fe8bc32ae6600bd8f0729e81bd239198c73fc Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24578 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add a common watchdog fileSimon Glass2012-06-054-22/+20
| | | | | | | | | | | | | | Some things about watchdogs are common across Cortex-M3, so create a common watchdog file to hold these. Put the watchdog task in there as the first customer. BUG=chrome-os-partner:10145 TEST=build for all boards Change-Id: Id55f71a807ee12bae3758afc213c30c731eadc07 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24395 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Unify the watchdog API over stm32 and lm4Simon Glass2012-06-054-9/+15
| | | | | | | | | | | | | | | | Use the same prototype for watchdog_init() everywhere. One version takes a parameters and one doesn't. We don't need the parameter since we have a #define. Tidy this up. Also move watchdog defines into watchdog.h. BUG=chrome-os-partner:10145 TEST=build for all boards Change-Id: I38ae63d7cc137b93017c850e767703d5f90f56ad Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24394 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Drop LED blinking from watchdog taskSimon Glass2012-06-051-8/+0
| | | | | | | | | | | | | We don't really need this, and want to free up the LED for other debugging uses, so drop it. BUG=chrome-os-partner:10145 TEST=build and boot on snow (for want of a better test) Change-Id: I62aad38e9b29556dde0a3bf8e10a85df577a8e73 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24392 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Release keyboard recovery button on next power-onRandall Spangler2012-06-045-25/+51
| | | | | | | | | | | | | | | | | | | | | | | | Keyboard recovery used to persist until the next time the EC was reset. It should release the next time the user turns on the system via the lid or power button. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:10034 TEST=manual 1. power system on normally. not in recovery. 2. press Power+Esc+Refresh. System turns on into recovery. 3. shut system down 4. power system on with lid-open. System boots normally. 5. repeat steps 2-3, then power system on with power button. System boots normally. Change-Id: I455c7191d128614629c50ba27d7ef977e414fe90 Reviewed-on: https://gerrit.chromium.org/gerrit/24409 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Disable default I2C register dumpRong Chang2012-06-031-2/+4
| | | | | | | | | | | | | | Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:10132 TEST=manual Connect uart console to Daisy, boot and remove the battery. The I2C debug trace should not show up by default. Change-Id: I911923138cb233cf2897983997c4a4764a62981b Reviewed-on: https://gerrit.chromium.org/gerrit/24363 Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* Send success code when rebooting EC using I2C host commandsDavid Hendricks2012-06-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This causes the reboot command to respond to the host via I2C with EC_RES_SUCCESS. Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=none TEST=tested on Snow and Link using ectool and flashrom Both machines were able to reboot the EC and go thru an EC update via Flashrom successfully: localhost ~ # ectool reboot_ec RO ; echo $? done. 0 Flashrom is also able to do a fully automatic update, without the user specifying a layout: Reading old contents from flash chip... done. Found 'RO_SECTION' in image. Found 'RW_SECTION_A' in image. GEC is jumping to [RO_SECTION] GEC has jumped to [RO_SECTION] Erasing and writing flash chip... ... GEC is jumping to [RW_SECTION_A] GEC has jumped to [RW_SECTION_A] GEC needs 2nd pass. ... Change-Id: Id723c26caa8f352a7ddc6ebfae664448c38300f0 Reviewed-on: https://gerrit.chromium.org/gerrit/24290 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org>
* stm32mon: more robust serial communicationVincent Palatin2012-06-011-11/+24
| | | | | | | | | | | | | | | | | | | | | | | - throw away all the incoming garbage after a NACK to be protect against unexpected behavior on the embedded monitor. - increase the command timeout : on STM32F100, I have measured up to 1.4s to execute the erase 64kB command. With the current 2s timeout, it was failing when you are unlucky (since it's using a integer second timestamp to measure the timeout). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=with a Snow, flash the board using stm32mon -w ec.bin from various states. Change-Id: I260b3b1311eac9be7c43f835eeac68051befd24a Reviewed-on: https://gerrit.chromium.org/gerrit/24314 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Add host command to switch LCD backlight and WLAN/BluetoothVic Yang2012-06-014-0/+110
| | | | | | | | | | | | | | We need to be able to toggle these signals to increase test coverage. BUG=chrome-os-partner:9967 TEST=Toggle 'ectool wireless' and see GPIO signal changes. 'ectool backlight 0' and see LCD backlight turn off. Change-Id: Ic96fe26aa82c33b0e51e1f973280a0edc322f158 Reviewed-on: https://gerrit.chromium.org/gerrit/23625 Commit-Ready: Vic Yang <victoryang@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* simple and self-contained EC flashing toolVincent Palatin2012-05-314-4/+155
| | | | | | | | | | | | | | | | | | | | | | | | | This produces a host binary running on the application processor and which is able to re-flash th EC firmware over the AP-to-EC link (either LPC or I2C). The payload (ie the EC firmware) to use is embedded inside the flasher binary. This is just aimed at testing and developer upgrade. The auto-update flow is using flashrom. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=build for link/daisy/snow/bds and tests On Snow, run burn_my_ec from the serial console and see that the EC was correctly re-flashed. Change-Id: I7f90e773678a7ef3d8dc6dbacf54e80f3294607b Reviewed-on: https://gerrit.chromium.org/gerrit/24236 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Assorted keyboard module cleanupRandall Spangler2012-05-313-12/+17
| | | | | | | | | | | | | | | Const- and static-ifying data and pointers. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=kblog on, then boot system, then kblog; should print log Change-Id: I2e1da8e3d614b66dad8749b18c43bd77dc75928d Reviewed-on: https://gerrit.chromium.org/gerrit/24233 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fix alignment of task scratchpad and system stackRandall Spangler2012-05-313-6/+14
| | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:10042 TEST=boot system, ctrl+alt+F2, type on console; shouldn't crash Change-Id: I935bc141fbbc1e7d0d073f1754104808a24fe869 Reviewed-on: https://gerrit.chromium.org/gerrit/24232 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fix a typo in thermal engine temperature settingVic Yang2012-05-311-1/+1
| | | | | | | | | Signed-off-by: Vic Yang <victoryang@chromium.org> BUG=none TEST=none Change-Id: I369522c00724c959d1eac18ca9c3ce57bd55aeff
* PMU tps65090 driverRong Chang2012-05-314-0/+170
| | | | | | | | | | | | | | This is an initial commit of tps65090 pmu driver. An empty charging task added. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:9756 TEST=manual When connected to a battery, the EC uart console will display battery status on value change. Check pmu register with 'i2c r 0x90 4'. Output should be '0x03'. Change-Id: I99e243d203c438751af0c3647556cbf9a94e928f
* Add stm32 I2C master driverRong Chang2012-05-314-2/+475
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A polling mode I2C master driver. Interfaces for read/write byte and word are implemented. i2c_read_string() is currently an empty function. CONFIG_SMART_BATTERY added to daisy board for testing. Move smart_battery.o back to CONFIG_SMART_BATTERY since it is not depended on charging state machine. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:9724 TEST=manual/host commands > battery Temp: 0x0bad = 298.9 K (25.8 C) Manuf: Device: Chem: Serial: 0x0001 V: 0x1cb7 = 7351 mV V-desired: 0x20d0 = 8400 mV V-design: 0x1c20 = 7200 mV I: 0x0000 = 0 mA I-desired: 0x0bb8 = 3000 mA Mode: 0x6001 Charge: 49 % Abs: 47 % Remaining: 2705 mAh Cap-full: 5575 mAh Design: 5800 mAh Time-full: 0h:0 Empty: 0h:0 Change-Id: I9f4e9e8819955ad1b107fb3b70ac2559d9b02b55
* Detect recovery key combinationVincent Palatin2012-05-313-22/+79
| | | | | | | | | | | | | | | | Check if ESC+Power+Refresh is pressed at startup, if the recovery combination is detected, record it to allow U-Boot to go into recovery. The status of the keyboard recovery can be read from the response of the EC_CMD_MKBP_INFO command. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9916 TEST=On Snow, do a recovery reset by pressing ESC+Refresh+Power and see the trace, try other resets and don't see it. Change-Id: I0e1a8214781a6e74bd90bf8313887a9dcf4df56d
* Merge "stm32: assert/de-assert GPIO_PMIC_PWRON_L with keyboard power event"Gerrit2012-05-301-0/+3
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| * stm32: assert/de-assert GPIO_PMIC_PWRON_L with keyboard power eventDavid Hendricks2012-05-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sets the PMIC_PWRON_L signal to correspond with the keyboard power button state. BUG=chrome-os-partner:9821 TEST=Tested on Lucas (see notes below) Signed-off-by: David Hendricks <dhendrix@chromium.org> 1. AC power plugged in, AP off, EC booted > gpioget PMIC_PWRON_L 1* PMIC_PWRON_L 2. AP running, press and release power button (should see screen zoom out and then back in, but I don't have a monitor...) 2a. AP running, power button not pressed > gpioget PMIC_PWRON_L 1 PMIC_PWRON_L 2b. Press power button > Waiting for long power press 280507864 > gpioget PMIC_PWRON_L 0* PMIC_PWRON_L 2c. release power button before 8s > Cancel power off > gpioget PMIC_PWRON_L 1* PMIC_PWRON_L 3. From AP off state, press and hold keyboard power button > gpioget PMIC_PWRON_L 0* PMIC_PWRON_L After 8s, we see: Timeout waiting for GPIO 0/KB_PWR_ON_L Power button was not released in time Shutdown complete. 4. AP on, press and hold keyboard power button > gpioget PMIC_PWRON_L 1 PMIC_PWRON_L > Waiting for long power press 654024769 > gpioget PMIC_PWRON_L 0* PMIC_PWRON_L > Power off after long press now=654025073, 0 ending loop 2 Shutdown complete. <-- Note: This message comes from power_off() which also de-asserts PMIC_PWRON_L > gpioget PMIC_PWRON_L 1* PMIC_PWRON_L Change-Id: I6955771707ecea2926570be0e8bd77ebddbca4d4
* | Merge "stm32: use level interrupt instead of edge"Vincent Palatin2012-05-305-11/+11
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| * | stm32: use level interrupt instead of edgeVincent Palatin2012-05-305-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using low level trigger interrupt rather than falling edge is more robust since we avoid detecting glitches or missing interrupts. This is backward compatible with the AP software expecting falling edge. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8869 TEST=On Daisy, check we can still enter text in U-Boot console and Chrome browser (and check interrupt count increase as expected). Change-Id: Ide2b27f9129173530d137b5d70d998ebd8f8e669
* | | Merge "Add basic SPI support to link"Gerrit2012-05-308-0/+221
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| * | Add basic SPI support to linkRandall Spangler2012-05-308-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds SPI transaction support, and a debug command to read a few values from the SPI EEPROM. Note that the SPI controller is normally *disabled* with all its I/Os high-Z, so this will not interfere with main processor or Servo on the SPI bus. The bus is only enabled during the SPIROM command itself. BUG=chrome-os-partner:7844 TEST=manual 1) Reboot system 2) on EC console, 'spirom'. Should print Man/Dev ID : 0xef 0x16 JEDEC ID : 0xef 0x40 0x17 Unique ID : 0xd1 0x61 0x44 0xb0 0x63 0x5d 0x40 0x32 Status reg 1: 0x00 Status reg 2: 0x00 Note that unique ID is, well, unique, so it won't match my value. But it should still be something not all 0xff's. 3) Power on the system. x86 should still boot normally, indicating that the EC isn't interfering with the SPI bus. Change-Id: I53bf5fdbbe7a37949375d0463e30e408cc6fb6a8
* | | Merge "stm32f: update flash write size"Gerrit2012-05-301-2/+2
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| * | stm32f: update flash write sizeDavid Hendricks2012-05-291-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL updates the constant FLASH_WRITE_BYTES to 64 and modifies the decrement value in the flash_physical_write() loop. The constant value was changed so that it would agree with EC_FLASH_SIZE_MAX which is the size of the data payload. FLASH_WRITE_BYTES is provided as part of EC_CMD_FLASH_INFO, so programs which query size this way will can take advantage of 64-byte writes. The decrement value in the loop did not actually change in value, but instead uses the size of the half-word. Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=none TEST=Tested on Lucas Change-Id: If335bd8e11db0acc6464dcdef819d91f61ae0890
* | ec: Remove *.dis from default target.Hung-Te Lin2012-05-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | *.dis files can always be generated by *.elf files, so we can remove it from default build targets, and only generate that on demand (make dis). This also speeds up building time from 6.637s to 4.9s. BUG=chromium-os:31379 TEST=emerge-link chromeos-ec make # no *.dis make dis # get *.dis Change-Id: Ibc5305501ae72a0733f401863ea1d4c1f17aa34f Signed-off-by: Hung-Te Lin <hungte@chromium.org>
* | Improve the timeout when running on non-Google EC boards.Louis Yung-Chieh Lo2012-05-301-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The udelay() has big overhead so that repeating calling leads big errors (expect 1 sec of timeout, but actually 12 secs of timeout). So, the improvement is to double the udelay count when BUSY bit is set. Even better, if we can check the I/O port content before really running the EC command, it can save more time. BUG=chrome-os-partner:10003 TEST=tested on link, alex, zgb, lumpy, stumpy and mario. Only mario takes 1 second to timeout. Others stop when checking ports (takes around 0.01 second). Change-Id: I96c6d8cbe6226d05428a2ab126815e934942f5a9 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
* | Merge "Add host command to simulate key press"Gerrit2012-05-293-0/+66
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| * | Add host command to simulate key pressVic Yang2012-05-293-0/+66
| |/ | | | | | | | | | | | | | | | | | | | | In order to enable automatic keyboard testing, let's add key press simulating command to ectool. BUG=chrome-os-partner:9188 TEST='ectool kbpress 4 6 1' and see 'j' pressed. 'ectool kbpress 4 6 0' and see 'j' released. Change-Id: I5a445e13aad2bd09aa6e9a1d62995cf34b782aeb
* | Merge "Jump to RAM before entering hibernate"Gerrit2012-05-291-7/+18
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| * | Jump to RAM before entering hibernateRandall Spangler2012-05-291-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Works around LM4 errata where EEPROM access is unstable while powering down. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9996 TEST=hibernate 1 Change-Id: I99d21ec8ab5a06fb0972edebec3cc58ca9f60fa9
* | | Merge "Use correct EEPROM timeout"Gerrit2012-05-291-7/+18
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