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* Clear OWNERS for factory/firmware branchfactory-excelsior-12812.B-cr50_stabBrian Norris2021-09-101-9/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155051 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* SQA images should allow support rollback to 0.0.22Vadim Bendebury2019-12-192-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rolling back to 0.0.22 requires erasing the INFO1 rollback protection space, as current RW level is at two, and 0.0.22 is at one. The only way to erase INFO1 is to run a node locked prod signed 0.3.22 image. But 0.3.22 will destroy board ID along with the rollback spaces AND it is not capable of rollback, so to roll back to a lower than 0.3.22 version one still needs to run the SQA image. 0.3.22 will not allow to restore the Board ID either. Another problem is that SQA image would update the rollback INFO1 space, thus again preventing 0.0.22 from running. This patch alleviates the situation by allowing the SQA images to write Board ID fields and preventing SQA images from updating rollback space in INFO1. BRANCH=cr50 BUG=b:146522336 TEST=with the new image was able to downgrade a device from 0.4.24 to 0.0.22 Change-Id: I8babf15ae32036dc612ae9c808c773a2b3355762 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1975092 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: do not waste time looking for legacy NVMEM spaceVadim Bendebury2019-12-134-2/+22
| | | | | | | | | | | | | | | | | | | | It takes 14.5 ms to decrypt two 12K flash spaces into SRAM, then calculate their hash to see if either one is is a valid NVMEM space. There is no need for this check when the 'other' Cr50 image is newer than {3,4}.18. BRANCH=Cr50, Cr50-mp BUG=b:132665283 TEST=with added instrumentation verified that in case the other slot is occupied by 0.0.22 image, the check takes 14.5 ms, when the other slot is occupied by 0.4.23 image the check takes 8 us. Change-Id: I0414ca3d7e90d343589a21e91319f35479632eff Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1967543 Reviewed-by: Keith Short <keithshort@chromium.org>
* cr50: change OWNERS to cr50 team membersMary Ruthven2019-12-109-30/+6
| | | | | | | | | | | | | | Change the OWNERS to cr50 team members and remove OWNERS files from all subdirectories. BUG=none BRANCH=none TEST=none Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: narrow the condition for custom TPM command codesNamyoon Woo2019-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | CR50 used to detects the custom TPM command code if the vendor specific bit field is set. This patch enfornces this condition by comparing the command code to 0x20000000 value. It is planned to support extended TPM commands, which are not yet standard, and those commands shall have 0x20000000|x as their command code. This patch will pass those commands to tpm2 library directly by calling ExecuteCommand(). BUG=b:140527213 BRANCH=cr50 TEST=ran gsctools with -m, -o, -i options. Cq-Depend: chromium:1892419 Change-Id: I43ce52bee96f6b6def8e4bf3a14f092b3235740a Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891523 Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 939160b5b82424e57457a3d07dccfe7127681787) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958419
* chip/host: Avoid concurrent recipes of libcryptoc.astabilize-12748.B-cr50_stabYicheng Li2019-12-064-28/+4
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50. CONFIG_LIBCRYPTOC does similar things for other boards that configures it, including host. This resulted in cr50_fuzz having concurrent recipes for libcryptoc, as it has both configs. This change separates CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc. Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC. BRANCH=none BUG=b:144811298 TEST=make -j buildall > /dev/null Observed no more "warning: overriding recipe for target 'build/host/cr50_fuzz/cryptoc/libcryptoc.a' " Change-Id: I2186cbead773629456da254df5f82b96e9646fc2 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit a018043265ecb3466863ff9020ab25d552105c61) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956404 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* g: update rollback info map for both RO and RW sectionsVadim Bendebury2019-12-061-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both RO and RW sections have their respective rollback spaces in INFO1, but until now Cr50 code did not honor the RO binaries' headers rollback maps and did not update the appropriate iNFO1 space. With this patch both RO and RW info maps are updated to the lowest level of the two images found in the flash when invoked during board_init() or to match the currently active RO/RW when invoked through vendor command indicating successful OS startup. BRANCH=cr50, cr50-mp BUG=b:136284186 TEST=tried the new image on a chip with freshly erased INFO1 space: first running a DBG image, which does not touch INFO1 maps: > vers ... RO_A: * 0.0.11/bc74f7dc RO_B: 0.0.11/4d655eab RW_A: * 0.4.24/DBG/cr50_v2.0.2744-d79516a9d RW_B: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d .. > sysinfo ... Rollback: 0/1/1 0/128/128 ... Then running an image with debug extensions disabled: > vers ... RO_A: * 0.0.11/bc74f7dc RO_B: 0.0.11/4d655eab RW_A: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d RW_B: * 0.4.24/cr50_v2.0.2744-d79516a9d ... > sysinfo ... Rollback: 1/1/1 2/128/2 ... Change-Id: I259a3f46c03199633ca85389872449d667f172fb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949548 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit 94cfd7cee548047d8e0f5dee2995c4c03fba665d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954342
* g: display both RO and RW info map statusVadim Bendebury2019-12-062-27/+38
| | | | | | | | | | | | | | | | | | | | | | | Cr50 firmware is required to update the rollback prevention map in INFO1 for both RO and RW images. This patch adds code to display the state of the RO map and both RO_A and RO_B headers in addition to previously reported RW information. BRANCH=cr50, cr50-mp BUG=b:136284186 TEST=loaded the new image and observed reported rollback state: > sysinfo ... Rollback: 0/1/1 0/128/128 ... Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546 Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit 565c54c270bd93ee30e8f8560d3d1691d128e762) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954341
* cr50: add support for FIPS mode flag in FWMPVadim Sukhomlinov2019-12-062-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | Added definition of FWMP_DEV_FIPS_MODE matching same definition in vboot. Support function board_fwmp_fips_mode_enabled() introduced to read it's status. It's not currently used, but will be consumed by FIPS code. BUG=b:138577491 BRANCH=cr50 TEST=make BOARD=cr50 Change-Id: Iebf672cfebfeb18ae62892097fbf1fa30a770338 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1950813 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> (cherry picked from commit bf8241699ba35984887e3f1a71d29ea1e92b21fe) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954340 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* g: Add support for 192 and 256 bit AES-GCM in DCRYPTO_gcm_initVadim Sukhomlinov2019-12-063-7/+9
| | | | | | | | | | | | | | | | | | | DCRYPTO_gcm_init hardcoded key length to 128 bit causing preventing testing of 192 and 256 bit functionality for AES-GCM. BUG=b:135623371 BRANCH=cr50 TEST=compile, specific test for issue as described in bug Change-Id: I4fc41f6155661709115c57aa944c8976e17bffac Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766098 Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 24f7511e41c1f8140b19d69d9440a3ea6f91bd89) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954339 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use new conventions to determine key ladder modeVadim Bendebury2019-12-063-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The new RW dev key does not follow the existing convention of bit 0x4 set in prod Key ID and unset in dev key ID. The suggested approach is to check values of some key manager registers to determine if the device is running in fully configured prod mode or not. BRANCH=cr50, cr50-mp BUG=b:144455990 TEST=tried running this patch on a node locked image: > sysinfo ... RO keyid: 0xaa66150f RW keyid: 0x334f70df ... Key Ladder: dev Change-Id: I73088ce44a8b8bf8e11a0d240d07152b49a3225b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1915504 Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 74237689eb277bf1fe0e682cb256825508fa511f) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954338
* Fix smart erase.Barry Twycross2019-11-271-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smart erase is used by the haven private-CR51 firmware, I don't know if other projects use it. Smart erase attempts to speed up erase by checking if the block to be erased is all ff's, and only erasing it if there is content (not ff's). The bug is that after erasing a block, the code does not wait for completion of the erase before reading ahead to see if the next block is already erased (all ff's). This is contrary to the spec where the only valid operation is a check of the status after issuing the erase. On some eeproms, with some timings, this causes the smart erase to give a flase positive erased block detection. Ie, the eeprom reads back al ff's while it's busy doing the erase. The upshot is that only the first non erased block is erased, and the rest of the eeprom is left untouched. The code before smart erase looked like: do wait for not busy erase block until all erased wait for not busy Smart erase was added by inserting the check for erased at the top of the loop. If instead, it's moved down below the wait for not busy, everything works fine. (Or, the wait for not busy is moved back to top of the loop.) This is the fix used here. TEST= Run without and with patch on a Starcard. Without patch not all of the targeted flash is erased. With patch, all of the targeted flash is erased. BUG=b:144868388 BRANCH=barryt/smart Signed-off-by: barryt@google.com Change-Id: I679ad4d21c3c353252646394f5631abc42782ded Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931466 Reviewed-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Barry Twycross <barryt@google.com> Commit-Queue: Barry Twycross <barryt@google.com> Tested-by: Barry Twycross <barryt@google.com> Auto-Submit: Barry Twycross <barryt@google.com>
* clang-format: reflow commentsJett Rink2019-11-261-1/+1
| | | | | | | | | | | | | | | | | | The formatter should try and reflow comments to fit within the 80 character column limit BRANCH=none BUG=none TEST=verified that long comments get formatted to wrap within the 80 column limit within VScode Change-Id: I219e8e4d55ebbb7931d1b0e9fb41c7f48744d2aa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1937887 Tested-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* usb_mux: cleanup the usb_mux_get() functionVijay Hiremath2019-11-266-41/+22
| | | | | | | | | | | | | | Simplified the usb_mux_get() function and made the MUX info prints same as in ectool. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Iefb16e1dbd323afbe248b06fe9c53abc63be9a67 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931284 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec: use symbolic names instead of magic numbersPaul Fagerburg2019-11-261-2/+20
| | | | | | | | | | | | | | | | | | | PD_DP_PIN_CAPS used a lot of magic numbers, which made it difficult to work out what it's doing. Added a comment about using the "receptacle type" field to deterimine whether the UFP_D or DFP_D pin assignments should be used, and replaced magic numbers with #define'd constants. BUG=None BRANCH=None TEST=`make -j buildall && ./util/flash_ec --board=kohaku` (or whatever board you're testing with), then verify that a USB-C dock with HDMI or DisplayPort still works. Change-Id: I1b5cf6d6cf7d0e1698bd7c727226f10f804ed5e9 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1935088 Reviewed-by: Jett Rink <jettrink@chromium.org>
* host_command: clear any leftover dataJett Rink2019-11-263-2/+153
| | | | | | | | | | | | | | | We want to ensure that the entire buffer we may be sending back to the host from the EC does not contain any data from previous host command responses. Clear the data in common code so all chips do not have to implement this functionality. BRANCH=none BUG=b:144878983,chromium:1026994 TEST=new unit test shows cleared data Change-Id: I93ad4d36923ba1bf171f740e94830640d3fde3b0 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930931
* cortex-m/m0: Reformat linkers script with tabsCraig Hesling2019-11-262-604/+635
| | | | | | | | | | | | | | This is just a cleanup of the linker scripts for cortex-m chips. This brings no functional change. BRANCH=none BUG=none TEST=make buildall Change-Id: If9fa43157e8955fed7c7426b910c6af957794b0b Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930392 Reviewed-by: Jett Rink <jettrink@chromium.org>
* puff: update PP3300_SNS dividerPeter Marheine2019-11-261-3/+9
| | | | | | | | | | | | | | The schematic has changed to 9.31k / 47k resistors on this input. BUG=b:1829597655 TEST=still builds BRANCH=None Change-Id: I2856df05b2611edd30d497a35bb871b8f5b173e9 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1935467 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* treeya : Add new battery informationxiaoqiang.zhu2019-11-262-1/+94
| | | | | | | | | | | | | | | | | | | | | | | treeya need support three new batteries --SMP:L19M3PG1 --LGC:L19L3PG1 --Celxpert:L19C3PG1 The same manufacturer(SMP) has two kinds of batteries, manuf_name can't specify the unique battery, so need to check device_name. BUG=none BRANCH=none TEST=boot treeya board with new batteries, charging/discharging/cutoff work as expected. Change-Id: I09e2a68961e5df92c6b6d639963ac8894eb7ec20 Signed-off-by: xiaoqiang.zhu <xiaoqiang.zhu@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1933788 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Tested-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* flash_ec: Fix accidental dut-control invocationFei Shao2019-11-261-1/+1
| | | | | | | | | | | | | | | | There's a typo when calling dut_control in CL:1884252, which causes "--port" argument is missing when executing flash_ec. BUG=b:145103343 BRANCH=kukui TEST="util/flash_ec --image ${IMG} --board ${BOARD} --port 9998" works Change-Id: I8c79797be4a665bd9ab8c3770c5199f2f798c6c4 Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1932869 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* trembyle: tcpc fault needs to be clearedDenis Brockus2019-11-251-0/+22
| | | | | | | | | | | | | | | | | We currently do not use the TCPCI fault for anything but need to clear any faults to stop an alert storm. Added debug output so we can see what is coming out in times of fault, just as an FYI. BUG=b:144126745 BRANCH=none TEST=insert-extract charger from USB-C0 and verify AC on/off Change-Id: Ifc5ffc4e18790e6fc9763bbeb334cbdff901ad43 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1934045 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: make BB virtual mux retimer compatible with non-virtualDenis Brockus2019-11-259-109/+49
| | | | | | | | | | | | | | | | Changed the driver interface for BB virtual mux retimer to stop using global functions and use the usb_retimers array instead. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I56befaca1720eb2f4e0599a983629b4df45dc76b Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928121 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* zork: make product ID project levelDenis Brockus2019-11-252-8/+8
| | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: I7cd71e246708dd4423b7fc3021a644e2988e2771 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930868 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Reland "smart_battery: add smbus error checking support"Ting Shen2019-11-255-44/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of daccb3adea9394116d7ab2c807e4a360cb5a93a1 Original change's description: > smart_battery: add smbus error checking support > > Jacuzzi/Kodama has a unstable software controlled i2c bus, its data > transmission may be interrupted by other higher priority tasks and > causes device timeout. > > If timeout happens when ec is reading data, it has no knowledge about > what's happening on slave, and keep receiving bad data (0xFF's) until > end. The standard i2c/smbus error handling mechanism can not handle this > case, so we need the error checking feature from smbus 1.1 to ensure our > received data is correct. > > This CL adds the error checking (PEC) functions to i2c and smart battery > module. > > BUG=b:138415463 > TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, > no failure after 100k read/writes. > test code at CL:1865054 > BRANCH=master > > Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 > Signed-off-by: Ting Shen <phoenixshen@google.com> > Reviewed-on: http://crrev.com/c/1827138 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Tested-by: Ting Shen <phoenixshen@chromium.org> > Commit-Queue: Ting Shen <phoenixshen@chromium.org> BUG=b:138415463 TEST=in addition to the TESTs above, verified this CL boots on hatch(npcx chips), and reef_it8320(it83xx chips). BRANCH=master Change-Id: I67975eee677cfd6e383742d48103662372cac061 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1913940 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* battery : differentiate overtemperature conditionYongBeum.Ha2019-11-251-2/+13
| | | | | | | | | | | | | | | | Battery charging is stopped over 55'C during charging and started below 45'C. BUG=b:140596424 BRANCH=hatch TEST=make -j BOARD=kohaku && ./util/flash_ec --board=kohaku check charging status & led on chamber Change-Id: Ib4a8ba5236d107397db904ca7075f0d0f29dd724 Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928539 Tested-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* TCPMv2: Keep message transmission and reception synchronizedSam Hurst2019-11-242-52/+114
| | | | | | | | | | | | | | | | | | | | | If a message is expected after a transmit, hold off on checking for that until the sender response timer is set. BUG=chromium:1022715 BRANCH=none TEST=make -j buildall manual tests: Connect StarTech CDP2DP USB-C to DP dongle Observe REQUEST send less than 1ms after SRC_CAP Look for ACCEPT message sent by PE and PD Change-Id: I1d155ead698ac39172c604cc3f656631565855d5 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907807 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* jinlon: add FAN2 supportDevin Lu2019-11-243-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:141259174 BRANCH=hatch TEST=faninfo can see the 2nd fan works with console. 2019-11-22 14:23:55 Fan 0 Actual: 3309 rpm 2019-11-22 14:23:55 Fan 0 Target: 3291 rpm 2019-11-22 14:23:55 Fan 0 Duty: 42% 2019-11-22 14:23:55 Fan 0 Status: 2 (locked) 2019-11-22 14:23:55 Fan 0 Mode: rpm 2019-11-22 14:23:55 Fan 0 Auto: yes 2019-11-22 14:23:55 Fan 0 Enable: yes 2019-11-22 14:23:55 Fan 0 Power: yes 2019-11-22 14:23:55 2019-11-22 14:23:55 Fan 1 Actual: 3101 rpm 2019-11-22 14:23:55 Fan 1 Target: 3291 rpm 2019-11-22 14:23:55 Fan 1 Duty: 37% 2019-11-22 14:23:55 Fan 1 Status: 2 (locked) 2019-11-22 14:23:55 Fan 1 Mode: rpm 2019-11-22 14:23:55 Fan 1 Auto: yes 2019-11-22 14:23:55 Fan 1 Enable: yes Change-Id: I88aa8efcbb55d8a64ae51c68b5a142e5a4997f46 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928542 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* TCPMv2: PD: Separately track each SOP and SOP' and SOP''Sam Hurst2019-11-246-94/+177
| | | | | | | | | | | | | | | | | | Tracked PD header spec. version for each port partner type. BUG=chromium:1023025 BRANCH=none TEST=make -j buildall Manual Testing: Connected PD2.0 source charger and made sure we talked PD2.0 Connected PD3.0 source charger and made sure we talked PD3.0 Connected apple 2019 PD2.0 dock with charger and made sure we downgraded from PD3.0 to PD2.0 Change-Id: I3b49d9630acf6c19101ac71334445890c78c4077 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907430 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: ServoV4 is not recognized appropriatelySam Hurst2019-11-223-95/+347
| | | | | | | | | | | | | | | | | | Configure the port as a SNK with PD in DebugAccessory.SNK state BUG=chromium:1020752 BRANCH=none TEST=make -j buildall Manual Test: 1: Connect Servo v4 with NeckTek charger pluged in DUT power port The DUT negotiates to 20V, and starts charging. Change-Id: Id44d566024b5016965f996435d11befdc1c53e98 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906993 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: fix storm tracker overflow issueJett Rink2019-11-226-6/+145
| | | | | | | | | | | | | | | | | | | If there is no USB-C interrupt activity for 2^31 microseconds, then there are more than ALERT_STORM_MAX_COUNT events within 2^31 microsecond (instead of ALERT_STORM_INTERVAL), then the interrupt storm would incorrectly detect a storm and disable the port due to incorrect math regarding 32-bit overflow. BRANCH=octopus and all branches with original storm detection (CL:1650484) BUG=b:144369187 TEST=unit test in CL Change-Id: I90b888ac092f81d151538d6018771fb32f8e9c39 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925668 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* cr50: prepare to release 0.{3,4}.24Vadim Bendebury2019-11-222-2/+2
| | | | | | | | | | | BRANCH=cr50, cr50-mp BUG=none TEST=none Change-Id: I2bef8173536cdf4d584b93169d22c6120daed7f2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930141 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* krane: Use the PWM mode to adjust brightness as lowestLeo Zhou2019-11-221-4/+22
| | | | | | | | | | | | | | | | | | Adjust current=4ma, pwm=1/32, and change the state as: charging is blue charged full is green low battery is red BUG=b:137618886 BRANCH=kukui TEST=Do a full charging test, notice LED indicator status under different charge state Change-Id: Ic1b7a99ab3edaee5c92a5cae56bc6d9a321e9c23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918995 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Tested-by: Kook Zhang <zhangbinbin@huaqin.corp-partner.google.com> Commit-Queue: Leo Zhou <zhoubo@huaqin.corp-partner.google.com>
* npcx7: i2c: enable FIFO mode to transmit and receive dataCHLin2019-11-223-80/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx7, all I2C modules have separate 32-byte transmit FIFO and 32-byte receive FIFO buffers. In this CL, we add the FIFO mode support to the I2C driver. This will help to reduce the firmware overhead (i.e. the occurrence of I2C interrupt) during long I2C transactions by allowing the EC to write/read more than one byte of data at one time to I2C module and hence improve the I2C performance. The FIFO mode is enabled by default on all npcx7 series chips. BUG=none BRANCH=none TEST=No error for "make buildall" TEST=Connect npcx7 EVB to the I2C slave emulator, do stress test: 1. iterate ~2000 times of single i2c_xfer_unlocked API call. i.e. i2c_xfer_unlocked(.., I2C_XFER_SINGLE) 2. iterate ~2000 times of multiple i2c_xfer_unlocked API calls: i.e. i2c_xfer_unlocked(.., I2C_XFER_START) i2c_xfer_unlocked(.., 0) . . i2c_xfer_unlocked(.., I2C_XFER_STOP) 3. Issue 6 I2C transactions by 6 tasks at the same time. iterates ~2000 times. TEST=with this CL; build and upload an image (with/without FIFO mode enabled.) to yorp; no symptom occurs. Change-Id: I387e8ef6e619acef670273f08ab4150e3d2b75f2 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827137 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* it83xx/config_chip: remove configurationtim2019-11-221-1/+0
| | | | | | | | | | | | | | | | The CONFIG_HOSTCMD_X86 will get automatically defined if either CONFIG_HOSTCMD_LPC or CONFIG_HOSTCMD_ESPI are defined. So this definition is redundant in config_chip.h BUG=none BRANCH=none TEST=make buildall -j Change-Id: I3cb9b61d4b006becba5eb75e0dabe61bd9e3c999 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868134 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/spi_master: correct the module IDtim2019-11-222-6/+6
| | | | | | | | | | | | | | The module ID in alternate function setting for spi master should be corrected as MODULE_SPI_MASTER. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ib52b09a5f1e0c496374d4ed2f3a222dab9af2eb0 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868133 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/nds32 and riscv-rv32i/ec.lds.S: no assert if section is not presenttim2019-11-222-2/+4
| | | | | | | | | | | | | | | When the h2ram section is not present, we don't need the assert to check the space whether enough or not. BUG=none BRANCH=none TEST=No error when we don't define configration of CONFIG_HOSTCMD_x86 or CONFIG_H2RAM_SIZE. Change-Id: Id5d0e674f65cfdb220bc996c597740390000d861 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868132 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/it8xxx1, chip/it8xxx2: GPIO, WUC and IRQ for chip it83201/it83202Ruibin Chang2019-11-223-39/+282
| | | | | | | | | | | | | | | | | | | | GPIO, WUC and IRQ changes for chip it83201/it83202. BRANCH=None BUG=b:133460224 TEST=test GPIO group O, P, Q, R 1.Input: external input 3.3v, GPDR of corresponding pin is 1. (GCR31, GCR32 select 1.8v, validate again for O and P group) 2.Output: GPDR of corresponding pin set 1, measure 3.3v. 3.INT: GPIO_INT input trigger => WU INT (select high, low, rising, falling, both edge trigger mode) => INT => CPU INT 4.Test power-up and down with this CL on ampton. Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704 Reviewed-by: Jett Rink <jettrink@chromium.org>
* all hatch variants: Make sure EC_RST_ODL is GPIO_LOCKEDShelley Chen2019-11-225-0/+55
| | | | | | | | | | | | | BUG=b:144886704 BRANCH=hatch TEST=make buildall Change-Id: I0d520a5c375a2b47c55a335da91f556ccfd59c29 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928422 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* all hatch variants: Assign SYS_RST_ODL to GPIOC5Shelley Chen2019-11-225-4/+5
| | | | | | | | | | | | | | | | | There is an error where SYS_RST_ODL is assigned to GPIO02 where it is actually assigned to GPIOC5 in the schematics. This should cause AP reset to fail from the ec console. BUG=b:141476349 BRANCH=hatch TEST=None (I don't have a hatch board to test this out on) Change-Id: I855a65489ce974ee92be4bf51a83d5af40e4e2da Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928421 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* Ensure CEC bus pin is not driven lowFelix Ekblom2019-11-221-0/+3
| | | | | | | | | | | | | | | | | | We have seen cases where after a cold EC reboot the pin is low until the first CEC message is sent by AP (after which the bus is left in a well defined state again) This is a follow up to https://crrev.com/c/1346990 which initializes the pull up in case not done by the RO FW. BRANCH=none BUG=b:144548408 TEST=CEC pin only goes low for ~40ms instead of 30s. Signed-off-by: Felix Ekblom <felixe@chromium.org> Change-Id: I3c98f8858f407279ad1bd086210969d69df2230b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928993 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* gsctool: delay RO update for old cr50 imagesMary Ruthven2019-11-221-0/+35
| | | | | | | | | | | | | | | | If Cr50 is running older than 0.3.20, delay the RO update 1 minute after the RW update, so Cr50 doesn't reject the RO blocks because their offsets are less than the RW offsets. BUG=b:144873413 BRANCH=none TEST=update board running RO 0.0.10 RW 0.3.18 to the RO 0.0.11 RW 0.3.22 image. Change-Id: I0179cc235c692133b08cd3430d71069b2f94bf69 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1929481 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Dratini/Jinlon: Add support for TEMP_SENSOR3Devin Lu2019-11-226-10/+28
| | | | | | | | | | | | | | A new temperature sensor is added to Dratini/Jinlon boards, close to the CPU. It is used to support the fan control. BUG=none BRANCH=hatch TEST=temp command in EC console Change-Id: Icd5974133da5e1aec81f2201f87e1b83b79c6169 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925802 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* battery : Define CONFIG_BATTERY_DEAD_UNTIL_VALUEYongBeum Ha2019-11-223-0/+15
| | | | | | | | | | | | | | | | It takes 850ms~950ms to get valid RSOC after battery wake-up. Sometimes battery FG returns garbage data(1%) as RSOC and 0 value of desired current / voltage. Add CONFIG_BATTERY_DEAD_UNTIL_VALUE to continue charging. BUG=b:138413964 BRANCH=None TEST=build & flash, check battery charging with dead battery Change-Id: I0cbe30aa973499b0c27faf9b6da03a0344ad1065 Signed-off-by: YongBeum Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918985 Reviewed-by: Jett Rink <jettrink@chromium.org>
* jinlon: change TCPC port 0 from ANX7447 to PS8751Devin Lu2019-11-223-9/+8
| | | | | | | | | | | | | | | | | This patch chagnes TCPC port 0 from ANX7447 to PS8751, It includes the gpio name, function name and reset signal. BUG=none BRANCH=hatch TEST=make sure tcpc port 0 is workable. Change-Id: I698d70750727080f46cffdc136ffd8a54967ca89 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918984 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
* Trogdor: Initial board commitWai-Hong Tam2019-11-2211-0/+2530
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is an initial commit for Trogdor. Use Cheza as a baseline. Make the change according to the schematic, e.g. * Reflect the GPIO change * Reflect the TCPC/PPC part change * Update the USB topology, e.g. no device mode support * Remove the detachable related code * Add keyboard support * Support keyboard backlight * Update the battery characteristic * Add initial support of muxing DP path * Support a single USB-A port * Change sensors from lid to base * Minor code style improvement BRANCH=None BUG=b:143616352 TEST=BOARD=trogdor make Change-Id: Ia9bb0adfcb8d347e6335fd3ae1e565b0f9d1a025 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1847204 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cleanup: Segregate ioexpander related drivers in ioexpander folderVijay Hiremath2019-11-2216-12/+12
| | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I7fe9ab23254dbd8515936d10ad6782305e76236c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925173 Reviewed-by: Jett Rink <jettrink@chromium.org>
* doc: document USB_PID strategyJett Rink2019-11-221-1/+8
| | | | | | | | | | | | | | | | We want to have a single USB VID/PID per platform. If we need further granularity within a platform, then we can use the HW version field within the AMA VDO. BRANCH=none BUG=none TEST=none Change-Id: Ia32f8c2b41efc04e570c8f6d92b3e1307948863a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1910451 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* flash_ec: Fix servo micro boot0 for fpmcu/usbpdCraig Hesling2019-11-221-0/+4
| | | | | | | | | | | | | | | | | This CL fixes servo micro flashing for fpmcu and usbpd. This broke after crrev.com/c/1884252. The error seen was the following: ./util/flash_ec: line 496: servo_micro_usbpd_boot0: command not found BRANCH=nocturne,hatch BUG=none TEST=./util/flash_ec --board=dartmonkey --image=./build/nocturne_fp/ec.bin Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Ic98fb31e29ee25d5397d38d5e742727a909994e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924990 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: Enable TCPC low power when port is looking for a connectionSam Hurst2019-11-219-256/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port is in a state where it is looking for a connection, to save power, we should put the TCPC in its low power mode and enable auto toggling. Low power mode can happen when DRP auto toggling, acting as a SNK only, or acting as a SRC only. BUG=chromium:1022217 BRANCH=none TEST=make -j buildall manual tests: 1: (S0) Nothing plugged in, port is drp and low power mode 2: (S5/S3/S0ix) Port is SNK only, and low power with nothing plugged in 3: (S3/S0ix) If TypeC sink was previously plugged in, port remains powered 4: (S5/S3/S0ix) TypeC source is recognized 5: (S3->S0) TypeC sink plugged in, port is powered when S0 is reached Low power exit test: Using this command from the AP console: ectool i2cread 8 2 0x16 0x0d Transfer failed with status=0x1 # This means the TCPC was asleep. On the EC console: 2019-11-21 09:50:24 [315.235538 TCPC p1 init ready] 2019-11-21 09:50:24 [315.236048 TCPC p1 Exit Low Power Mode] 2019-11-21 09:50:24 [315.242837 TCPC p1 init ready] 2019-11-21 09:50:24 [315.243229 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.246471 C1: Unattached.SNK] 2019-11-21 09:50:24 [315.252504 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.362878 C1: LowPowerMode] 2019-11-21 09:50:24 [315.363314 TCPC p1 Enter Low Power Mode] Change-Id: I7e853d05e0ece1f6b3031f17a18fcbf0d9a15a51 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904974 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: add enter_low_power_mode for retimer muxDenis Brockus2019-11-213-6/+62
| | | | | | | | | | BUG=b:139428185 BRANCH=none TEST=verify mode is set correctly when switching devices Change-Id: I3e40e0321cb1026180b7edc0bfe99439c13acafb Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1922062
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