| Commit message (Collapse) | Author | Age | Files | Lines |
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BUG=none
TEST=none
Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155064
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Owners-Override: Jora Jacobi <jora@google.com>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
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Herobrine uses the Vivaldi keyboard. The Refresh key is at T2
(col:2, row:3), instead of T3 (col:2, row:2). The code filters out
the Refresh key and check any boot key remaining, like the Esc key.
Misconfiguring it fails the recovery boot, as EC detects a redundant
key pressed.
BRANCH=None
BUG=b:196885613
TEST=Pressed Refresh (T2) + Esc and booted EC. Checked the message:
[0.005749 KB boot key mask 1]
which showed the Esc key was recognized.
Without this CL, the message won't show up, as a redundant key
(T2 not recognized as Refresh) is pressed.
Both EC-OS and Zephyr images behave the same.
Change-Id: Iee82d7d4d6b3301ac342abc384488842a9858b7e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102287
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Add Kconfig option for CONFIG_KEYBOARD_REFRESH_ROW3.
BRANCH=None
BUG=b:196885613
TEST=zmake testall
Change-Id: Idd55e5bc3af4aab95aa9577b49eb3d8eb5e90630
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102286
Reviewed-by: Keith Short <keithshort@chromium.org>
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BMI160 is going to EOL, so we intend to import ICM42607
to make 2 sources compatible for Mrbland.
BUG=b:196287196
BRANCH=trogdor
TEST=1.make BOARD=mrbland
2.ectool motionsense can get the sensor data
Change-Id: Ie1b4c6722b460339a38ef48aeae1018f6c008949
Signed-off-by: Siyu Qin <qinsiyu@huaqin.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3089082
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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When import the second source sensor ICM42607,
the on-body detection and gesture detection functions will course
proccess going to null pointer. Mrbland does not require these features,
so just remove the related macro.
BUG=b:196287196
BRANCH=trogdor
TEST=make BOARD=mrbland
Signed-off-by: Siyu Qin <qinsiyu@huaqin.corp-partner.google.com>
Change-Id: I7a6be7efe0c57c73ebdad0fb462eea0eb516ad61
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088969
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Switching config option to route buttons and switches over MKBP
instead of 8042 driver
BRANCH=main,dedede
BUG=b:170966461
TEST=manual tested on Madoo
Cq-Depend: chromium:3094530
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I5c82ee09a64b1971e63547220ca20c1226cb5ba3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069163
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Nick Vaccaro <nvaccaro@google.com>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
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modify LED behavior for driblee
Power LED:
System S0: White
System S0ix: Blinking white (1 sec on, 1 sec off)
System S5/G3: Off.
Battery LED:
DC mode:
System S0: off.
System S5/G3: Off.
System battery low: Blinking Amber (1 sec on, 1 sec off).
AC mode:
Charging: Amber.
Full charged: White.
Battery low or AC only: Blinking Amber (1 sec on, 1 sec off).
BUG=b:196910961
BRANCH=keeby
TEST=make BOARD=driblee
Signed-off-by: Matt_Wang <Matt_Wang@compal.corp-partner.google.com>
Change-Id: Iddd6d74a8073d8b409340a2585c45776e10388aa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102331
Tested-by: Matt Wang <matt_wang@compal.corp-partner.google.com>
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Setup battery parameter for driblee.
BUG=b:196910958
BRANCH=keeby
TEST=make BOARD=driblee
Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com>
Change-Id: I6196138c5546beb2a724921c2c1add03a7cd4ce9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3099426
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Driblee only 180 SKU so remove the motionsensor code.
BUG=b:196929676
BRANCH=keeby
TEST=make BOARD=driblee
Signed-off-by: Matt_Wang <Matt_Wang@compal.corp-partner.google.com>
Change-Id: I76fff7ad4f15ec3fb74268ae91c15e495e7ce4a9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102686
Tested-by: Matt Wang <matt_wang@compal.corp-partner.google.com>
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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With all four PD tasks enabled, ADLRVP board was rebooting
with WDT errors. On increasing the frequency from 48MHZ
to 96MHZ, the issue got resolved.
BUG=b:195406641
BRANCH=None
TEST=ADL P RVP booting fine without any WDT errors
Signed-off-by: poornima tom <poornima.tom@intel.com>
Change-Id: I7f8ea030c2a9837f4468e2bcdd9fc6de00c33eb4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3067290
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: caveh jalali <caveh@chromium.org>
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For KX022 is recommended I2C CLK timing minimum to 2.5us, set
IT83XX_I2C_CH_B to 400kbps. Fill min and max frequency in
motion_sensors for KX022.
BUG=b:196998259
BRANCH=icarus
TEST=I2C timing meets the spec.
Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com>
Change-Id: I74e1bd6e59963dc86fd5f8725a5ee0d5aeda1d59
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102329
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@chromium.org>
Commit-Queue: Shou-Chieh Hsu <shouchieh@chromium.org>
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ADLRVP does not have standard overlays to program EC hence
added adlrvpp_npcx board to NPCX internal SPI array.
BUG=b:196998258
BRANCH=none
TEST=Below command flashes NPCX MECC on ADLRVP
./util/flash_ec --board=adlrvpp_npcx
Change-Id: I132aa21a0bed533c61cc8f2edf159c95774cad0b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102298
Reviewed-by: caveh jalali <caveh@chromium.org>
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Created array for the NPCX internal SPI for the boards which
do not use standard overlays.
BUG=none
BRANCH=none
TEST=Able to flash npcx9m3f using MECC AIC on ADLRVP
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Change-Id: I57e4909f0b487b0efa4a3fa26f8b3d5465267dd7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3101842
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
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Remove als tcs4300 function.
BUG=b:192370253
BRANCH=brya
TEST=make buildall -j succeeded.
Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com>
Change-Id: I8e5f5145da807449ff90d9400072161516c35fa9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3098117
Reviewed-by: caveh jalali <caveh@chromium.org>
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Update usb3 signal setting
BUG=b:194985848
BRANCH=volteer
TEST=make BOARD=chronicler
Signed-off-by: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com>
Change-Id: I929ca1af7105b53f92c80c7e478e1815965daa00
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060351
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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Add pins definitions in device tree file used to build zephyr
BRANCH=main
BUG=b:194136536
TEST=Build zephyr for herobrine npcx9 and verify if sku id and
board version in EC console are correct.
Change-Id: Ib5d36d0089e79b9202af0ecdd173490caf443e0d
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3077543
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
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Add pins definitions in device tree file used to build zephyr
BRANCH=main
BUG=b:194136536
TEST=Build zephyr for herobrine npcx7 and verify if sku id and
board version in EC console are correct.
Change-Id: Ib47a4cafcd74c816ae26f884f811898eb2d46b89
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3077542
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
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Add pins definitions in device tree file used to build zephyr
BRANCH=main
BUG=b:194136536
TEST=Build zephyr for lazor and verify if sku id and board version
in EC console are correct.
Change-Id: Ibdc1dcb456b5cecd48ddafeafff0f765ffa45081
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3077541
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
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Previously, functions for reading board version and sku id were defined
in board.c files which are not compiled in Zephyr builds.
Logic from board.c files should be moved to the DeviceTree files.
This commit adds support for defining board version and sku id
pins and numeral system used to decode them.
BRANCH=main
BUG=b:194136536
TEST=Call system_get_sku_id and system_get_board_version
on CrOS EC and Zephyr, values should be correct and
the same on both versions
Change-Id: I61b5e205cb2a2299ad86c5dff38c05a9659eb2d3
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3048102
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
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Disabling accelspoof and battfake EC console commands
BRANCH=main,dedede
BUG=none
TEST=make -j BOARD=buggzy
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Iea64aa822a103500d39d6d1045e8fc9fbe9e8c93
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3101840
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Rob Barnes <robbarnes@google.com>
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BUG=b:185084342
BRANCH=none
TEST=make -j BOARD=primus
TEST=check lock key works
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I0f08cf8a71efda77ae9ca130a0ba32ea5e0f6902
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3099285
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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Enable -Werror compile options so that code warnings cause build
failures.
BUG=b:174871569
BRANCH=none
TEST=zmake testall
TEST=Introduce unused variable warning, verify build fails
Change-Id: Ifecfc391dc936a56ba9c02d70f089e058f0453d2
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3101832
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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The ps8815 can take up to 50ms to fully wake up from sleep/low power
mode. When the chip is asleep, the 1st I2C transaction will fail but the
chip will begin to wake up within 10ms. After this delay, I2C
transactions succeed, but the firmware is still not fully
operational. The way to check if the firmware is ready, is to poll the
firmware register for a non-zero value.
BRANCH=none
BUG=b:195087071,b:186189039
TEST=buildall passes
Change-Id: If047fc122d7f61ed5fc361f97b47180e5cf08970
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3084331
Reviewed-by: Keith Short <keithshort@chromium.org>
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Per the schematics, bugzzy is actually using the NPCX797FC and not the
NPCX796FC. This variant has more SRAM and will provide some more space
to be used for the image.
BUG=b:192521391,b:194554146
BRANCH=dedede
TEST=`make -j BOARD=bugzzy` and verify that it compiles and is not out
of space.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I8c0c8510d614cbaf07e53632676036bdb9284a79
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3101348
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
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When PCHG isn't enabled in RO, a keyboard is disabled until another
USB device is plugged.
This patch restores PCHG in RO but disables it by assigning an
invalid value to the IRQ signal (GPIO_IH_COUNT). A PCHG task
will be started but will not run because there will be no event.
BUG=b:193223400, b:173235954
BRANCH=trogdor
TEST=On CoachZ, stylus charges in normal mode and doesn't charge in
recovery mode.
Change-Id: Icb5702474ac5ef74119455ab4879447cb7a963e4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3100491
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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To avoid unnecessary waking of USBC task changed code to
Trigger TCPC interrupts on falling edge only.
BUG=none
BRANCH=none
TEST=Added print statements in ISR and observed, Type-C
interrupts are triggered only on falling edge only.
Change-Id: I91ea8a23fe9736fbd28ab302b4ccc44447470386
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060258
Reviewed-by: caveh jalali <caveh@chromium.org>
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BUG=b:195406641
BRANCH=none
TEST=ADLRVP type-C ports can enter low power mode
Change-Id: I0b457758ba67328c139c85dce977603e305715d0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088162
Reviewed-by: caveh jalali <caveh@chromium.org>
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If the "dual role" is enabled and the TCPC chip does not support
"Dual role auto toggle mode" then the PD state remains in
PD_DRP_TOGGLE_ON state in active state of the AP. Hence check for CC
line open state to decide to enter low power mode for such devices.
BUG=b:195406641
BRANCH=none
TEST=Tested on ADL RVP, FUSB302 & IT83XX can enter LPM
> pd 0 state
Port C0 CC1, Disable - Role: SRC-UFP TC State: LowPowerMode,
Flags: 0x0010 PE State: , Flags: 0x0001
Change-Id: Ic70c6bfcd2ffd0721fdcaf6e61c68736971e037b
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088161
Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Vijay Hiremath <vijay.p.hiremath@intel.com>
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Add six battery type for cret.
And add device name to identify.
BUG=b:196943911
BRANCH=dedede
TEST=make BOARD=cret,battery can be found via EC log check and
battery can be cutoff by ectool command.Charge and discharge
normally.
Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com>
Change-Id: I32a73783f13627d2e8b0e0f3e3f778340dc1cb38
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3099287
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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The Type-C PDO "PD_MAX_POWER_MW" change to 45w from 60w
BUG=b:196325467
BRANCH=firmware-volteer-13672.B
TEST=manual
Check PDO using command "ectool usbpdpower".
Signed-off-by: Michael5 Chen1 <michael5_chen1@pegatron.corp-partner.google.com>
Change-Id: Ie9d892eb22f9b486ceabfa2824819a6689b4046c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3093350
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Create the initial EC image for the bugzzy variant by copying the
waddledoo reference board EC files into a new directory named for
the variant.
(Auto-Generated by create_initial_ec_image.sh version 1.5.0).
BUG=b:192521391
BRANCH=None
TEST=make BOARD=bugzzy
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I71b44d40a11a477f6fa81a75795dd972e44435f0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3067291
Reviewed-by: Henry Sun <henrysun@google.com>
Commit-Queue: Henry Sun <henrysun@google.com>
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The position of SLEEP_KEY_MASK bit is not in its intended
position because TK_* enum is 1-indexed. Fix this bug by
shift the mask by 1.
BUG=b:196934919
TEST=evtest
BRANCH=trogdor
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I900636f032786510f7870948d1856d0bc4374800
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097478
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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We have keyboard backlight at T6, brightness_down at T7,
brightness_up at T8, play_pause at T9, micmute at T10.
BUG=b:194146863
BRANCH=none
TEST=make -j BOARD=gimble
Signed-off-by: Will Tsai <will_tsai@wistron.corp-partner.google.com>
Change-Id: Ibd0362a4e668867b0f8307ca1baad8c1b8198871
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3099386
Reviewed-by: caveh jalali <caveh@chromium.org>
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This fixes an issue where we sometimes time out waiting for the
HVSNK_STS bit to get set after enabling sink mode using the EN_SINK
GPIO. Checking for HV_SNK mode in the device status register is more
robust as it appears to reflect the state of the EN_SINK pin as
expected.
I'm still not sure why the HVSNK_STS bit isn't set as expected
sometimes. I suspect that it only gets set when there is actual voltage
presented by the connected device.
BRANCH=none
BUG=b:194833460
TEST=with additional debug code, verified that we detect HV_SNK mode
even when HV sink switch is off.N
Change-Id: Ifa5b9ebaedfc03755306ecb4e3e6e1fa654418d0
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058079
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This saved about 3 seconds erasing time while running software sync.
This also pull configurations of flash/memory layout to chip level.
BRANCH=none
BUG=b:195954913
TEST=software sync successfully.
(without erase timeout patch of depthcharge)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ia7fa08fdf6bdde4c47ca8d852f8eeaa83f39dae5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097250
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Create the initial EC image for the driblee variant by copying
the lalala reference board EC files into a new directory named for
the variant.
(Auto-Generated by create_initial_ec_image.sh version 1.5.0).
BUG=b:191732473
BRANCH=None
TEST=make BOARD=driblee
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id6cffcdb7aad6c9cb7ac065fb377c6e7dfa9e574
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3070401
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Add PSL_IN1/PSL_IN2/PSL_IN3 as the hibernate wakeup pins. Also map the
non-PSL (low power RAM) hibernate wakeup source to the same pads.
(i.e. GPIOD2/GPIO00/GPIO01.) Then we can use either PSL hibernate mode
(CONFIG_PLATFORM_EC_HIBERNATE_PSL=y) or non-PSL hibernate mode
(CONFIG_PLATFORM_EC_HIBERNATE_PSL=n) on the EVB.
BUG=none
BRANCH=none
TEST=pass "zmake testall"
TEST='hibernate' & wake-up ec by those wakeup pins.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I4175bdabee138c7bac25f8b43774268ae336d989
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3089083
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
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BUG=b:196476916
BRANCH=none
TEST=No error with bb retimer initial.
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Change-Id: Iccf5bde3029ddcc2e0a83c7e5ea9f4d3da835973
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3068490
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Zick Wei <zick.wei@quanta.corp-partner.google.com>
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Create the initial EC image for the corori variant by copying the
lalala reference board EC files into a new directory named for
the variant.
(Auto-Generated by create_initial_ec_image.sh version 1.5.0).
BUG=b:194356176
BRANCH=None
TEST=make BOARD=corori
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3aa0c1317b926c6f39e1d5a669f57c75151861aa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3070319
Reviewed-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Add a driver for writing Skin Temperature Tracking (STT) sensor
readings to the SB-RMI interface. STT readings are used to maximize
the SOc performance while keeping the skin temperature within
specification.
BUG=b:176994331
TEST=Build and run on guybrush
BRANCH=None
Change-Id: If655545158e7dc05946bc67686b1b0b40a40a713
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078050
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
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Add Side-Band Remote Management Interface driver. SB-RMI can be used to
manage power limits of the SOC. SB-RMI uses a soft mail box for
executing transactions.
BUG=b:176994331
TEST=Build
BRANCH=None
Change-Id: Ie185985e4c8d2c2d915b2ae2447709ddc16adda6
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078049
Tested-by: Rob Barnes <robcb85@gmail.com>
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Fanli Zhou <fanliccc@gmail.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
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This patch assign gpio EC_CBI_WP to GPH5.
BUG=b:188368049
BRANCH=keeby
TEST=make BOARD=haboki
Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com>
Change-Id: Iab3a49c53019fc053e2500ea1c8f7a37cfd20936
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097246
Reviewed-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Some muxes may need to be re-set after they've power cycled, and many
muxes are tied to the S5 power rails. Introduce a flag which can be
used to indicate a mux needs to re-run init and is no longer in LPM
after the G3 state has been hit.
BRANCH=None
BUG=b:195045790
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I8bd4184dbea629edf106dbee32f811620ebda0dd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3093086
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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This adds error checking to ps8815_disable_rp_detect_workaround_check.
BRANCH=none
BUG=none
TEST=buildall passes
Change-Id: I6c901893e0f5f8ea02fbcb0e6dc082671f13a172
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3087984
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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The latest app note indicates the ps8815 firmware may take up to 50ms to
be ready.
BRANCH=none
BUG=b:186189039
TEST=buildall passes
Change-Id: Ibc5ee2e6030d19b91d6c0b8a493aa05dd31c77e4
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3087983
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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This patch removes custom switchcap logic and uses
device tree implementation instead.
BRANCH=main
BUG=b:194211207
TEST=Compile and flash Zephyr's EC for herobrine_npcx9
Powering on and off should work correctly
Change-Id: Ice51e097c2126e78c6dbfb933a10724cf0374f67
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3089119
Reviewed-by: Keith Short <keithshort@chromium.org>
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This commit adds support for switchcap definition in device tree.
It will allow to remove board specific files which implemented
the switchcap functionalities. This will unify the logic between
different board in zephyr.
BRANCH=main
BUG=b:194211207
TEST=Use linked TEST commits to see example of definitions for lazor
Use GPIO or LN9310 version, build and flash to lazor.
Board should be able to boot correctly.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Change-Id: Ib80a73dcb2db95e2dcf48e33f876a39246fd506a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3085670
Reviewed-by: Keith Short <keithshort@chromium.org>
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This CL enables RTC for npcx7/9_evb.
BUG=none
BRANCH=none
TEST='rtc' console command
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Icc5d79d16ba2e4073ce39d38f0942a050d128e82
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088961
Reviewed-by: Keith Short <keithshort@chromium.org>
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If DUTs enter mode in S5->S3, and the mux would be re-configured
after in S3 and make the DP alt mode not correctly function.
BUG=b:194031794
TEST=plug DP dongle in S5/G3 on Asurada, boot to S0, and see display
BRANCH=asurada
Change-Id: Iee0ea2549e68ca7effc8cc538c22f4d388f10943
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3093347
Reviewed-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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This refactors how we deal with ps8xxx_role_control_delay. An array of
booelans is replaced with an array of delay values with default of 0ms.
Instead of checking the array to determine whether a 1ms delay should be
performed, the array unconditionally specifes the delay to be performed.
The default 0ms delay is equivalent to the previous "false" entry.
BRANCH=none
BUG=b:186189039
TEST=buildall passes
Change-Id: Ie351c58442eb206f38cea7a1f30dd1789a8c8025
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3084330
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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