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* Clear OWNERS for factory/firmware branchfactory-oak-8141.BBrian Norris2021-09-102-10/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155073 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* ectool: Support keyboard factory scanningDevn Lu2016-04-018-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | This is keyboard test mechanism request for "multiple key press test", we can thru the testing to scan out kso ksi pins shortting or keyboard has multiple key pressing, below was the testing steps: 1. Turn off internal keyboard scan function. 2. Set all scan & sense pins to input and internal push up. 3. Set start one pin to output low. 4. check other pins status if any sense low level. 5. repeat step 3~4 for all keyboard KSO/KSI pins. 6. Turn on internal keyboard scan function. BUG=chrome-os-partner:49235 BRANCH=ToT TEST=manual Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed. if no pins short together, it shows passed. Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/332322 Reviewed-by: Shawn N <shawnn@chromium.org>
* apollolake: initial chipset codeKevin K Wong2016-03-313-0/+462
| | | | | | | | | | | | | | used chipset skylake as the initial code base for apollolake BUG=none BRANCH=none TEST=make buildall Change-Id: If82f9bcd53ff44714f4b277637ff9f3c115ccc4d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331651 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* sensor: update sensor driver to use I2C port from motion_sensor_tKevin K Wong2016-03-3117-197/+251
| | | | | | | | | | | | | this allow motion sensor devices to be locate on different I2C port BUG=none BRANCH=none TEST=make buildall Change-Id: Ia7ba2f5729ebb19561768ec87fdb267e79aafb6a Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334269 Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: enable use of multiple UARTsMary Ruthven2016-03-316-62/+244
| | | | | | | | | | | | | | | | cr50 has three UARTs that it will be using. This change modifies the uart api to specify which uart to use. BUG=chrome-os-partner:50702 BRANCH=none TEST=change the interrupts and CONFIG_UART_CONSOLE to see that the different UARTs can be used. Change-Id: I754a69159103b48bc3f2f8ab1b9c8b86cea6bea5 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333402 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: First attempt at USB suspend with deep sleepBill Richardson2016-03-313-57/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is still in testing mode, so you have to take special steps to enable it (keep reading). But if you do the right dance, it does go into deep sleep for USB suspend, and resumes correctly. However, it doesn't yet wake for any other reason. That's coming next. Normal sleep is not yet supported, either. BUG=chrome-os-partner:49955, chrome-os-partner:50721 BRANCH=none TEST=make buildall; extensive tests on Cr50 Testing is a pain. First, you can't print anything in the idle task, because that just makes it stop being idle, so the only way to detect when it's triggered is by wiring up a GPIO and instrumenting things. Second, you have to manually reenable USB suspend on the host every time the Cr50 boots with echo auto > /sys/bus/usb/devices/<BLEH>/power/control where <BLEH> is the correct device. Third, for reasons probably related to the mysteries of HID devices combined with crbug.com/431886, you have to build the firmware without CONFIG_USB_HID (and the related items in board.h) Finally, because it's still a work in progress, you have to type idle d at the serial console after every boot (or resume) to reenable deep sleep in the idle task. If you do all that, then you'll see that it does go into deep sleep. Ping it again with "lsusb -v -d 18d1:5014" or ./test/usb_test/device_configuration, and it wakes up and responds! If you disconnect the USB while it's in deep sleep, it stays asleep. When you plug it in again, it wakes up, but it correctly recognizes that it shouldn't resume and does a normal reset instead. Change-Id: I3cc66e48ce671142a4d12edbe0eb9fdacecea0d9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336279 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* kevin: Add battery and charger supportShawn Nematbakhsh2016-03-317-14/+168
| | | | | | | | | | | | | | | | Add support for bd99955 charger and battery. BUG=chrome-os-partner:51722 TEST=Verify kevin charges at 3A input current when zinger is inserted, and verify battery actually charges. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iccd8185585fe39440681f5830cf58acafe6291b8 Reviewed-on: https://chromium-review.googlesource.com/335538 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* charger: bd99955: Add support for extended featuresShawn Nematbakhsh2016-03-312-13/+157
| | | | | | | | | | | | | | | | | | | | | | Add support for charge port switching and extpower detection, which are not part of the standard charger API. In addition, add a console command for dumping all regs, which is helpful for debug. BUG=chrome-os-partner:51722 TEST=Manual with subsequent commit. Verify kevin charges at 3A input current when zinger is inserted, and verify battery actually charges. BRANCH=None Change-Id: I98a0c0142d26facc0e0b9ef7f1dcd003ebffd9c1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335537 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* CR50: add NULL padding support for RSA encrypt/decryptnagendra modadugu2016-03-314-5/+42
| | | | | | | | | | | | | | | | | NULL padding (aka vanilla RSA) support is required by the TPM2 test suite (referred to as TPM_ALG_NULL in the tpm2 source). BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9848fad3b44add05a04810ecd178fbad20ae92cc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328830 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Cr50: Include low-power exit triggers in reset causesBill Richardson2016-03-303-3/+18
| | | | | | | | | | | | | | | | | | | | | | | Some of the reset causes are found in another register when resuming from a low-power state. We know we'll need to distinguish among them eventually, so we might as well decode them now. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 I forced the system into deep sleep and observed that the reset cause is accurately recorded on resume. Doing that requires a fair amount of hacks and manual effort, and can't happen by accident. Future CLs will make use of this. The current, normal behavior is completely unaffected. Change-Id: I5a7b19dee8bff1ff1703fbbcc84cff4e374cf872 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336314 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Handle possible resume from deep sleepBill Richardson2016-03-302-2/+26
| | | | | | | | | | | | | | | | | | | | | | | A resume from deep sleep looks a lot like a cold boot, but there are some registers that need updating quickly. We need to disable the settings that triggered deep sleep so that it isn't accidentally invoked again, and we need to unfreeze any modules or pins that were frozen during the deep sleep. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 Since we aren't yet triggering deep sleep, this doesn't do anything noticeable, which is the point. It shouldn't have any effect unless we are entering deep sleep and DON'T do this when it resumes. FWIW, I have tested that too, but it's coming in a later CL. Change-Id: I4b32fd2e24fe089d3f659154df26d275b41b4c1b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336450 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Add stubs to support low-power idleBill Richardson2016-03-303-0/+81
| | | | | | | | | | | | | | | | | | | This just adds the framework to use for implementing sleep and deep-sleep. This provides a custom idle task, and a new "idle" console command to control what that task should do (nothing, yet). BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 Other than the new idle command which does nothing, there is no visible change. This is just a stub. Change-Id: I8a9b82ca68dd6d1e3e7275f4f6753a23a7448f1d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336420 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: add support for RSA PKCS1-PSS paddingnagendra modadugu2016-03-304-6/+124
| | | | | | | | | | | | | | | Add support for PSS padding as per RFC 3447. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under tpm2 pass Change-Id: I14c58394f742daa5de4ec2fbeb7e7f14e54c9fcc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328778 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Cr50: Support USB SETCFG/GETCFG control transfersBill Richardson2016-03-304-6/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds USB support to Set and Get the Device Configuration. These control transfers are standard device requests that need to be added in order to behave properly for USB suspend/resume (and in general). Before this CL, the Get command always failed and the Set command had no effect internally. With this CL it works. Note that this particular change only supports ONE configuration for the Cr50. If/when we add additional configuration descriptors, we'll need to update it again. BUG=chrome-os-partner:50721 BRANCH=none TEST=make buildall; manual tests on Cr50 This CL includes a test program. Connect the Cr50 to the build host, and use that program to read and change the configuration. cd test/usb_test make ./device_configuration ./device_configuration 0 ./device_configuration 1 ./device_configuration 2 You may need to use sudo if your device permissions aren't sufficient. Change-Id: Id65e70265f0760b1b374005dfcddc88e66a933f6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335878 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* spi_flash: print spi flash size in proper unitNaresh G Solanki2016-03-301-1/+1
| | | | | | | | | | | | | Spi flash size is calculated in the units of kB but is printed as MB. correcting it to kB unit. Change-Id: If71681fc868a5974b44d135055c01f9184c71602 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332732 Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Tested-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
* Fan: enable fan after system resumeKeith Tzeng2016-03-301-1/+1
| | | | | | | | | | | | | | | | | | Fan will disable when S3 and S5 by pwm_fan_s3_s5, which call set_enabled(fan, 0) to disable it. But the pwn_fan_resume called fan_set_enabled() which not setting GPIO_FAN_PWR_DIF_L to 1, we should use set_enabled() instead. BUG=chrome-os-partner:50372 BRANCH=master TEST=check fan enable after system resume Signed-off-by: Keith Tzeng <Keith.Tzeng@quantatw.com> Change-Id: Id0bd4dd0afc7e02bcfa6e20401d6e9dfe8a81423 Reviewed-on: https://chromium-review.googlesource.com/335693 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cr50: update GPIOsMary Ruthven2016-03-291-8/+8
| | | | | | | | | | | | | | Update the GPIO mapping based on the Kevin P0 schematic and drive the EC and AP select signals low. BUG=chrome-os-partner:50728 BRANCH=none TEST=test that DIOB2 and B3 default to low, but can be set high or low. Change-Id: If574436913ad0271540bcce2939fe1f4574dae97 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335381 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: gpio: Configure pin attributes before setting as outputShawn Nematbakhsh2016-03-291-8/+10
| | | | | | | | | | | | | | | | | | | | When a pin power-on default is input, it is necessary to configure output level, pull up, etc. before setting the pin to output. Otherwise, the pin may be set to an undesired logic level for a short time. BUG=chrome-os-partner:51722 TEST=Power-up kevin, verify that CR50_RESET_L (default input, configured as high + open drain output by default) does not go low for a short period at boot. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ieaa08e14e6ea15a908f3ff4ee9188e14b17583cf Reviewed-on: https://chromium-review.googlesource.com/335344 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* kevin: Change battery i2c frequency to 100 KHzShawn Nematbakhsh2016-03-291-1/+1
| | | | | | | | | | | | | | | Battery does not support frequency higher than 100 KHz. BUG=chrome-os-partner:51722 TEST=Verify `battery` on kevin shows battery stats. BRANCH=None Change-Id: Ia75e0ffec9344dfc432205acce0ad31ca6d3fb3e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335374 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* power: rk3399: Add power down sequencingShawn Nematbakhsh2016-03-292-10/+35
| | | | | | | | | | | | | | | | Add simple power down control for rk3399. BUG=chrome-os-partner:51722 TEST=Verify power button powers up SOC. Verify next power button press powers down SOC. BRANCH=None Change-Id: Ibf4c9c3cb155b59ca7f2b6feb4f51ff173f407c7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335531 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* flash_ec: Add support for kevinShawn Nematbakhsh2016-03-281-2/+14
| | | | | | | | | | | | | | | | Add support for kevin, which uses external 1.8V SPI. BUG=chrome-os-partner:51722 TEST=Verify kevin EC is flashable. Verify wheatley still uses pp3300 SPI voltage. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I13e45e829cdc7b2298715812f5714d5dd806df06 Reviewed-on: https://chromium-review.googlesource.com/335396 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: pwm: Fix PWM moduleShawn Nematbakhsh2016-03-282-5/+8
| | | | | | | | | | | | | | | | | - Fix incorrect use of pwm functions which take a channel number. - Set power-down register according to PWMs that are actually enabled. BUG=chrome-os-partner:51722 TEST=Run 'pwm 1 50` on kevin and verify that LED lights up. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If7bcc812b55d3b72f215cf41c264d34827db7e29 Reviewed-on: https://chromium-review.googlesource.com/335372 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* spi_flash: Reload watchdog before writing a flash pageShamile Khan2016-03-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When EC receives many flash write requests from host and PDCMD, CHARGE and USB_CHG_P0 tasks are all ready to run, the HOOK task may not get scheduled in time to pet the watchdog resulting in an EC reset. BUG=chrome-os-partner:51438 BRANCH=None TEST=Manual on lars, determine two EC versions that have enough differences so that replacing one image with the other will require all or most of the flash pages to be updated. Alternate between flashing the two images with flashrom using a script. Atleast 1000 iterations should pass. Change-Id: I8b5c8b680a2935b945f3740e371dee2d218ec4c5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334457 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit a537d1ac44c40e7f6e1131e8cc852b030ccdba52) Reviewed-on: https://chromium-review.googlesource.com/334903 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* Cr50: Fix subtle USB error in clearing global NAKsBill Richardson2016-03-251-2/+2
| | | | | | | | | | | | | | | | | | | | | We clear global NAKs by writing bits in the USB_DCTL register. However, prior to this CL we were overwriting the entire register, not just touching individual bits. Since we've never actually set any global NAKs, this mistake didn't have any noticeable effects. But we should still do the right thing in case we need it later. BUG=chrome-os-partner:50721 BRANCH=none TEST=make buildall; test on Cr50 No visible change; everything continues to work. Change-Id: Ia25d95dc6211e5460132622ac005723f43b00e24 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335190 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Fix console message on unexpected USB eventBill Richardson2016-03-251-6/+6
| | | | | | | | | | | | | | | | We were referring to unhandled USB control messages as errors, but they aren't necessarily. Sometimes they're optional things that aren't fatal. We should still address them, but we don't have to freak out. BUG=none BRANCH=none TEST=make buildall; test on Cr50 Change-Id: I892acec2d89b8ec95353cdc09f3e49aa78b1704d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335200 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Cleanup check_reset_cause() codeBill Richardson2016-03-251-10/+18
| | | | | | | | | | | | | | There were some unnecessary shifts and conditionals. This just makes the code a little more readable. BUG=none BRANCH=none TEST=make buildall; test on Cr50 hw Change-Id: I084f191675d1b51101e9dc55c2e5a12b0b345d33 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334870 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Cr50: cleanup: Clarify a few commentsBill Richardson2016-03-242-7/+18
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall; try on Cr50 No code changes, just comments. Change-Id: I3eccccb024b4a319920a8252cd7d5d3829bf21da Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334820 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Cr50: Remove CONFIG_HOSTCMD_SPS supportBill Richardson2016-03-243-311/+1
| | | | | | | | | | | | | | | | This config option allowed us to disable the TPM protocol on the SPI slave bus and replace it with our EC-style host command protocol. We only used this for early testing and don't need it anymore, so we can get rid of it completely for this SoC. BUG=none BRANCH=none TEST=make buildall; test on cr50 Change-Id: I2126537e8bcc78e583cf426a3a83962c9ff1a121 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334762 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* it8380dev: util: Enable Host Global ResetDonald Huang2016-03-241-1/+1
| | | | | | | | | | | | | | BRANCH=none BUG=none TEST=Test OK on ITE8390CX. You can run "make -j BOARD=it8380dev" to build ec.bin and flash the ec.bin via "sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin" Change-Id: I2077012114bdbd5a8cc8f7dc29e43cdcb77d65b6 Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/334176 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb_port_power_smart: Support variable port countchris wang2016-03-242-25/+35
| | | | | | | | | | | | | | | | | | | | Use CONFIG_USB_PORT_POWER_SMART_PORT_COUNT to support more usb ports (default 2). BUG=None BRANCH=firmware-strago-7287.B TEST=build&flash ec,verify on wizpig,usb function work Signed-off-by: Chris Wang <chriswang@ami.com.tw> Change-Id: I2460d4a5755ef457249d728169c27fc6d00625d2 Reviewed-on: https://chromium-review.googlesource.com/333232 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: lehai deng <denglehai@ithaier.com> Commit-Queue: Chris Wang <chriswang@ami.com.tw> Tested-by: Chris Wang <chriswang@ami.com.tw> (cherry picked from commit 1e7d3554f1bedbb839a0f4800286c9db0d27e4f1) Reviewed-on: https://chromium-review.googlesource.com/334510 Commit-Ready: Chris Wang <chriswang@ami.com.tw>
* oak: allow charging of dead battery requesting nilstabilize-8104.BYH Huang2016-03-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | On oak battery, when the battery is dead it reports 0 for desired voltage, current, and state of charge. In this case we should allow charging. Added a CONFIG option for this that should be removed as soon as the battery side is fixed. With this CL, when a dead oak battery is used and a charger is connected, we attempt to charge it. BUG=chrome-os-partner:51454 BRANCH=none TEST=test on an oak with a dead battery. w/o this CL, the battery never charges because the charging not allowed flag is set. With this CL, the battery charges. Change-Id: If9f1250cd41aec265838e1d109f53c1bcd58c111 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/334471 Reviewed-by: Rong Chang <rongchang@chromium.org>
* it83xx: keyboard: remove "CONFIG_IT83XX_KEYBOARD_KSI_WUC_INT" and fix ISRDino Li2016-03-225-34/+3
| | | | | | | | | | | | | | | | | | | | | | 1. Always use wake-up control interrupt for keyboard KSI. This can also wake-up EC from deep doze / sleep mode. 2. In keyboard ISR, we just clear interrupt status to prevent keyboard interrupt can't be re-enabled. (for example, a KSI interrupt wakes up keyboard scan task, but keyboard_raw_read_rows() got 0.) Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=keyboard function is normally. Change-Id: If8c292189c6133b179a63dedcb7a18abbc091312 Reviewed-on: https://chromium-review.googlesource.com/333865 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip: it83xx: remove "CHIP_FAMILY_IT839X"Dino Li2016-03-223-8/+0
| | | | | | | | | | | | | | | | | The new IC is backward compatible with it839x, so we removed it. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make -j buildall Change-Id: I8de3d3c13b0f07f50ffffffc80723e44a923c7c8 Reviewed-on: https://chromium-review.googlesource.com/333864 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Console: Fix channel enum valuesAnton Staaf2016-03-223-96/+62
| | | | | | | | | | | | | | | | | | | The channel enum and string name array were out of sync (when CONFIG_EXTENSION_COMMAND is defined). This was caused by the two lists being specified separately. I argue that this is a good reason to merge the lists into a separate X-Macro include file. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I81d143f550a0fe6ef0c64e3c8357ed18aee4bfdc Reviewed-on: https://chromium-review.googlesource.com/334381 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Driver: bd99955: Add ROHM bd99955 initial charger driverVijay Hiremath2016-03-224-0/+402
| | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=Manually tested on Amenia prototype. Used 'charger' console command to check the charger properties. Used 'battery' console command to check the battery charging. Change-Id: Ic8787bfa3e0e3a615542b9cf72e6404fccc96e18 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334021 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* charger: isl9237: Report nominal current limit as ramp currentShawn Nematbakhsh2016-03-221-2/+9
| | | | | | | | | | | | | | | | | | | | | | isl9237 uses HW ramping but has no way to monitor the ramp current. Zero is not a good estimate of the ramp current and scares users into thinking their device isn't charging, so use the nominal current limit instead. BUG=chrome-os-partner:51286 BRANCH=Glados TEST=Verify "ectool usbpdpower" on chell reports "14xxxmV / 2668mA" rather than "... / 0mA" with stock charger attached. Change-Id: I0a29c8092b4994fda68dc3db8e02be2e0f234fd9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334237 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit cef36e872f72db9e060dd0cc7e5bced3062fbfd1) Reviewed-on: https://chromium-review.googlesource.com/334395 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: ectool: Ensure LED-related strings are defined for all typesShawn Nematbakhsh2016-03-221-2/+4
| | | | | | | | | | | | | | | | Use asserts to ensure that new strings are added when new ec_led_colors / ec_led_id enum types are defined. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4bcd6ad6de15b96a1c6a3fb70dbcc74f4d7f2857 Reviewed-on: https://chromium-review.googlesource.com/334382 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* smbus: Re-write smbus driverShawn Nematbakhsh2016-03-211-168/+108
| | | | | | | | | | | | | | | | | Re-write smbus driver to fix arbitrary length read and improve code organization. BUG=chromium:576911 BRANCH=None TEST=Manual on sentry. Verify that smbus communication with battery is functional. Change-Id: I63c4bc3df40755cd41b3d9956af0ab9d2145a253 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333787 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* GPIO: Rename and move board_set_gpio_hibernate_stateAnton Staaf2016-03-216-14/+16
| | | | | | | | | | | | | | | | | This function is no longer GPIO specific and fits better as part of the system API, so this moves it there and renames it board_hibernate_late. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I39d3ecedadaaa22142cc82c79f5d25c891f3f38c Reviewed-on: https://chromium-review.googlesource.com/330124 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* crc8: Support crc calculation across non-contiguous dataShawn Nematbakhsh2016-03-182-3/+20
| | | | | | | | | | | | | | | | | Building a single buffer for crc calculation is often inefficient, so add a new function that calculates crc8 from an existing crc8. BUG=chromium:576911 BRANCH=None TEST=Manual on sentry with subsequent commit. Verify that smbus communication with battery is functional. Change-Id: I05ffedb81ffcf0c126acda5f6212b3147b1580a1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333786 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ectool: Eliminate needless stderr output from `tempsinfo`Shawn Nematbakhsh2016-03-181-0/+3
| | | | | | | | | | | | | | | | | | `tempsinfo all` will probe all 24 sensor IDs, which will produce stderr output due to host command failure if a given sensor does not exist. Therefore, check memmap data for presence before probing a given ID. BUG=chrome-os-partner:51026 BRANCH=None TEST=Manual on Sentry. Verify "ectool tempsinfo all" dumps info on 4 temperature sensors and prints nothing to stderr. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14d65c1ad03eafafc21db41781c434b3ed74cb7e Reviewed-on: https://chromium-review.googlesource.com/333779 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Do not shutdown LPC in deepsleep.Divya Jyothi2016-03-172-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | During the resume sequence of S0ix EC can receive host commands early in the resume path when LPC is still disabled in EC. Host messages will be lost if the LPC interface with the kernel is down. Clock control was programed to 2 which means ring oscillator is shut down after completion of everty LPC transaction.To restart the oscillator EC should enable a wake interrupt on LPC LFRAME number and this mode can cause an increase in the time to respond to the LPC transactions. Keeping LPC always on shows minimal power impact as per datasheet Pg.390. The impact is < 0.45mW. BUG=chrome-os-partner:50627 TEST=Enter into S0ix and exit reliably. BRANCH=firmware-glados-7820.B Change-Id: I670b9b45c3a85c9bca249312a73a25dca52b313a Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332333 Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c03fd6e0eaa6ecd3205214f901facb9896a798b4) Reviewed-on: https://chromium-review.googlesource.com/332791
* servo_micro: add initial servo_micro buildNick Sanders2016-03-168-1/+602
| | | | | | | | | | | | | | | | | | * Update flash_ec to allow flashing servo_micro * Add servo_micro build BUG=chromium:571477 BRANCH=None TEST=updated servod is able to control gpio, gpio extender, SPI flash, ec uart, ap uart on test yoshi Signed-off-by: Nick Sanders <nsanders@google.com> Change-Id: I4d69c83ae581cb41da928a27c39b7152475d7ca8 Reviewed-on: https://chromium-review.googlesource.com/327214 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* oak: make sure power button is stable when waiting for releaseYH Huang2016-03-161-33/+4
| | | | | | | | | | | | | | | | | | The debounce timer might be too slow to actually update the state of debounced_power_pressed by the time we do power_button_is_pressed in the S3->S5 state transition. Call power_button_wait_for_release() instead of wait_for_power_button_release() to make sure there are no deferred actions. BRANCH=none BUG=chrome-os-partner:50362, chrome-os-partner:51109 TEST=During dev mode screen, press power button, note the device stays off TEST=sudo test_that -b oak <DUT_IP> firmware_FwScreenPressPower Change-Id: Ic60c1847ba461ef874dea5bf7d03675622f24beb Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/332310 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: Clean up CONFIG_PMIC_FW_LONG_PRESS_TIMER related codesKoro Chen2016-03-162-15/+0
| | | | | | | | | | | | | | | | | | | | | CONFIG_PMIC_FW_LONG_PRESS_TIMER was ported long time ago from Tegra, but the codes are actually not used and erroneous. It might wrongly trigger set_pmic_pwron(0), and turn off PMIC power accidentally. This causes POWER_GOOD lost and power state will go back to S5 during boot up. Clean up the codes by referencing check_for_power_off_event() of Rockchip. BRANCH=none BUG=none TEST=bootup and press power button quickly right after we are in S0. Bootup should still complete normally. Change-Id: Ie034efa3575dbebae4debb1afc206fddd9116350 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/332724 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: Add delay before we turn off VBATKoro Chen2016-03-161-0/+7
| | | | | | | | | | | | | | | | After power good is lost, PMIC requires some time to turn off all its internal power before we can turn off VBAT by set_system_power(0). This ensures the power measurement is within PMIC spec when system is shut down. BRANCH=none BUG=none TEST=measure the power rails of PMIC after system is shut down Change-Id: I55d4d99ed0ef69b103a4e52e9f9eec1c9e6265b5 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/332409 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: rev5: increase cycle time for LED in SUSPENDWei-Ning Huang2016-03-161-2/+9
| | | | | | | | | | | | | | Increase LED blink cycle time to reduce power consumption on Oak rev5 with GlaDOS ID. BUG=chrome-os-partner:50317 TEST=`make EXTRA_CFLAGS=-DBOARD_REV=5 BOARD=oak -j` Change-Id: Ic00512434965471a82b94ef431e0ec88c9e4c0c3 Reviewed-on: https://chromium-review.googlesource.com/332346 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
* npcx: Add 256KB alignment of RO & RW regions for npcx5m6g.Mulin Chao2016-03-154-38/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since npcx5m6g has larger than 128 KB code ram for FW, the original alignment between RO & RW regions isn't suitable for new chip. Therefore, we add 256KB alignment of them for npcx5m6g. In order to program the flash used by npcx5m6g, we add new board array, BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g and flash_npcx5m6g to program flash with different layout. Modified sources: 1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for npcx5m6g. 2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to distinguish which flash layout ec used. 3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with different layout. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/331903 Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_micro: add USB I2C interfaceNick Sanders2016-03-155-1/+332
| | | | | | | | | | | | | | | | | | Add a usb endpoint and class for i2c control via USB. Used for servo micro and servo_v4 to export USB control through servod. BUG=chromium:571477 BRANCH=None TEST=updated servod is able to control gpio extender on servo_micro Signed-off-by: Nick Sanders <nsanders@google.com> Change-Id: Id44096f8c9e2da917c0574d28dfcbcc0adf31950 Reviewed-on: https://chromium-review.googlesource.com/329322 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chell: Indicate when charging in suspendDuncan Laurie2016-03-151-2/+7
| | | | | | | | | | | | | | | | | | | | Currently when in suspend the LED blinks white no matter what the state of the battery or charging is. This is very confusing for users who expect to be able to plug in a charger with the system in suspend and see that it starts to charge. Past platforms from this OEM have had two LEDs so this has not been an issue. BUG=chrome-os-partner:49151 BRANCH=glados TEST=put chell in suspend, plug in charger to see amber LED and then remove the charger and see that it blinks white again. Change-Id: I60e849d7b8b717fb568d7d5d64046621c1c34157 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/332625 Reviewed-by: Shawn N <shawnn@chromium.org>
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