| Commit message (Collapse) | Author | Age | Files | Lines |
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For the dual data role, when the state is UFP
assert the otg pins to activate the usb device controller.
This will enable usb gadget mode and the board will act as
usb device instead of host.
For DFP state, de-assert the otg pins to activate the host mode.
BUG=b:74339386
BRANCH=NONE
TEST=Connect two Eve boards with the usb type c cable.
On ec console, type the command usb pd 0 swap data.
pd 0 state should return UFP mode.
Verify that the otg pins are high (USB2_OTG_ID and USB2_OTG_VBUSSENSE).
Change-Id: I0efb08ae3946ff09ce9dfeb89cff049e551fe000
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/961381
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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BRANCH=none
BUG=b:74388692,b:75986973
TEST=build all
Change-Id: Ief74b3e1a18ca90cb8fbf76c51780f659e4caf61
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/974310
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Battery on nautilus requires a minimum bus free time of 5ms between
I2C transactions. Use I2C_XFER_CALLBACK mechanism to ensure that this
time is guaranteed before starting a new i2c transaction.
BUG=b:73147310
BRANCH=None
TEST=make -j BOARD=nautilus. Verified on nautilus that no issue is
observed while charging the battery.
Change-Id: Ieba168835190b5d1334e413dc4f74e0248bf5a15
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/957966
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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BUG=b:74841068
BRANCH=scarlet
TEST='/sys/class/power_supply/sbs-9-000b/status' shows
discharging/charging/full status correctly
Change-Id: I4216ba2d95ac82a9f600d8685d993cb5b37206d8
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969747
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This CL fills out the ppc_chips and config options required to support
the NX20P3483 PPC. On Yorp for port 0 SNK/SRC control is driven by the
TCPC, while on port 1 it's driven by the EC.
BUG=b:74206647,b:74127309
BRANCH=none
TEST=make -j BOARD=yorp and verify there are no errors.
Change-Id: I41920be0bf4d9232101d8e1840714ca0c70f1bc5
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966927
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The NX20P3483 is a USB PD and Type C high voltage sink/source combo
switch. This CL adds support for this PPC variant. Unlike the TI
SN5S330, the NX20P3483 does not support VCONN and does not need to be
informed of CC polarity by the TCPM. To account for these differences,
2 new PPC config options are added and the driver for the TI SN5S330
was modified to include these new options.
The SNK/SRC switch mode for the NX20P3483 is controlled by 2 GPIO
signals which may be connected the EC or directly to the TCPC. To
handle both cases, the ppc_chips structure was modified with a flags,
snk_gpio, and src_gpio elements.
BUG=b:74206647
BRANCH=none
TEST=make -j buildall and verified there are no build errors.
Change-Id: Ic4415ab7571b80e7661ea673434eaf4cf1f1fd2d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966926
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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i2c transaction
This change adds a new config option CONFIG_I2C_XFER_CALLBACK that
makes i2c_xfer callback into board-provided functions before the start
and after the end of every I2C transaction. This can be used by boards
to implement any I2C device-specific quirks e.g. requiring minimum
bus-free time between every I2C transaction when the slave device
cannot actually do clock stretching.
BUG=b:73147310
BRANCH=None
TEST=make -j buildall
Change-Id: I452de4f22a81ffd97ca4944e1b940a3537637df9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/956934
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This function enables variadic functions to take advantage
of functionality provided by snprintf.
Signed-off-by: Jeff Andersen <jeffandersen@google.com>
BRANCH=none
BUG=b:72360575
TEST=make buildall -j
Change-Id: I0095a96339b374ef8030b87b5184fa4678b439eb
Reviewed-on: https://chromium-review.googlesource.com/971761
Commit-Ready: Jeff Andersen <jeffandersen@google.com>
Tested-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Geminilake uses the same power sequencing code as Apollolake. Instead
of the board specifying the wrong chipset, we will make the correct
chipset reuse the existing power code.
This also gives us flexibility in the future if GLK needs to vary from
ALK in any of shared code.
BRANCH=none
BUG=b:74020444
TEST=build all
Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969613
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This helps us tell whether a monitor lost picture because the EC
exited the DisplayPort mode or other reason.
BUG=b:75288273
BRANCH=none
TEST=boot Fizz
Change-Id: I2da6a27c66f03ef780a0ed6f60a597a01f248942
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966993
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Add the state machine and the interfacing to the enrollment and matching
algorithm providing by the private driver part.
Implement the host commands interface for it (based on MKBP event) along
with the console debug commands to exercise it.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=On ZerbleBarn console, use 'fpenroll' then 'fpmatch' for several
fingers.
TEST=With ZerbleBarn and a servo-v2, retrieve and upload templates with
'ectool_servo fptemplate'.
TEST=On Meowth, exercise with the prototype of biod
CrosFpBiometricsManager.
CQ-DEPEND=CL:*555078
Change-Id: I10b0d76d3faa898a682cf9a2eb7fc7e212b0c20c
Reviewed-on: https://chromium-review.googlesource.com/886401
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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CQ-DEPEND=CL:*591042
BUG=b:75978856
BRANCH=poppy
TEST=No regressions observed.
Change-Id: I3c481ac46bd9005df05f7be13bee8799959fb282
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969786
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Meowth has two analog detection pins with which it monitors to determine
the base status: the attach, and detach pins. When the voltages cross a
certain threshold, after some debouncing, the base is deemed connected.
Meowth then applies the base power and monitors for power faults from
the eFuse as well as base disconnection. Similarly, once the voltages
cross a different threshold, after some debouncing, the base is deemed
disconnected. At this point, Meowth disables the base power.
BUG=b:69140200
BRANCH=None
TEST=Verify that we can detect a base attach and detach.
TEST=Verify that when base is attached, tablet mode goes to 0, and goes
to 1 when the base is detached.
TEST=Connect base, take a paper clip and short the attach pin to ground
to trigger a fault 4 times in a row. Verify that base power is disabled
yet base detect state machine still reports attached. Wait at least 1s,
physically detach and reattach base, verify that base power is
re-enabled.
Change-Id: I2a069fc450c2232c7eae02b8e7459d38a049668a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/923396
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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In most cases when Cr50 signer script is invoked, the input elf files
are stored in the same directory and named ec.RW.elf and ec.RW_B.elf,
the way they produced by the EC makefile.
Let's allow create_released_image.sh to accept a directory name
instead of two elf file names.
BRANCH=none
BUG=none
TEST=verified that the script properly handles both old and new
command line options (allows to pass individual elf files and a
directory name).
Change-Id: I40bb8983fd97e6cd82e235308622ba2f20119ce5
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/963618
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
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This creates a second pty for pty_driver to open, to prevent the
need for freezing the user pty. This also allows the user pty to
fully log and print all output.
BRANCH=None
BUG=b:74023102,b:73310923
TEST=servod is fast now, recovery works
CQ-DEPEND=CL:958127
Change-Id: Ib369a5e64838ded98719d76f8159d71a97fe08ad
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958128
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add LSM6DSL accel + gyro support to meowth.
FIFO and gesture support will be added later.
BUG=b:69140267,b:73546254
BRANCH=master
TEST=use accelinfo to get sensor data.
Change-Id: I4362fe5dd568fb5d696c460432b5c0a6a80be83e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924411
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Units must be reported in according to the range.
2g means 1<<15 should be returned when accel is 2g.
Actually accelerometer report units in mg.
BUG=b:73546254
BRANCH=master
TEST=Check with accelinfo with 2g gain Z ~= 1<<14.
Change-Id: I218210ca8305ecbe76a681b535f3d75f3a6bea52
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924408
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Accelerometer reports accelerating in mg. Fix gain to that full range
(2g, 4g or 8g) returns 2<<15.
BUG=b:73546254
BRANCH=master
TEST=compile
Change-Id: I2873a641985fa800709a2d30b031c2b6e3fcb39e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924407
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BUG=b:73546254
BRANCH=master
TEST=compile
Change-Id: If914dfbf7bb30e934b711d8f89c46af2787f917c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924406
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add support in ectool, expose min/max ODR.
BUG=b:73546254
BRANCH=master
TEST=compile
Change-Id: Ib09c06e17d7d73aaab91680672de4d5267299c7f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924405
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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LSM6DSM now use STM MEMs common functions already
used by LIS2DH12 device. Added st_raw_read_n_noinc
function to read i2c data not using auto increment
protocol.
BUG=b:73546254
BRANCH=master
TEST=Tested on discovery BOARD with LSM6DSM sensor connected on
I2C master bus interface of target board.
Using motion sense console commands is possible to enable, set data
rate, set full scale and show data from sensor (acc and gyro).
Commons function works properly for LSM6DSM.
Change-Id: I7a987306135a85abcfa9c1d3ba596fb70598fadc
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/465376
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This reflects version changes in Cr50 branches.
BRANCH=none
BUG=none
TEST=none
Change-Id: I121c65797a30595a58d0b55774e80147692bda38
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969340
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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CONFIG_VBOOT_HASH needs to be set in EC config
BUG=b:75276859
BRANCH=none
TEST=make -j BOARD=yorp and verify there are no errors.
Change-Id: Ief7adb8afe40fda02aa6b84a3f81971a3c64e455
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966934
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Kionix suggests that it is recommended to issue the Software Reset
command after the device was powered. This is effective against
dynamic or non-linear behavior of a power supply or unexpected
noise above normal on the power rail during a power up.
BRANCH=eve
BUG=b:62607555
TEST=kx022:
1. press power button 10 second to power off.
2. power on the DUT
3. refresh + power button to cold reboot the DUT
4. Check the g-sensor by 'ectool motionsense'
kxcj9:
eve: sensor kxcj9 found.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/536723
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
(cherry picked from commit 5a52614b8c87ab1de84c461b7bbd0b4a14dc7fdb)
Conflict in init routine in accel_kionix.c.
By moving WHOAMI after reset, we expect the test to work the first
time.)
Change-Id: I362f2af59253519aa35b72cfb6b666c49e425777
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/753969
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Add error code to indicate a piece of hardware is not working properly.
BUG=none
TEST=compile
BRANCH=none
Change-Id: I34eca8073a359aec1c559241654a1d0a7075cd44
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/753968
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This reverts commit 1d8fcd4fabfed67d8304b3c5ad418cf6f5ae1878.
It looks like KXCJ9 may not return proper WHOAMI after powerup
but before reset.
BUG=b:67865186
BRANCH=eve
TEST=compile
Change-Id: Iceaaf3b2a45d920e08db587e1308cec0379e68cf
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/753967
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Fix argument to adc_read_channel() to be enum adc_channel.
No change in behavior since this ends up being a different
name for the same value (0/1).
BUG=none
BRANCH=none
TEST=none
Change-Id: I0e8b3066122f3789d043b98aad98d8a32c2607bc
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967242
Reviewed-by: Simon Glass <sjg@chromium.org>
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On cros/firmware-poppy-10431.B, plus the patches on this branch:
make BOARD=nautilus SECTION=RW analyzestack | grep Task
Task: HOOKS, Max size: 728 (504 + 224), Allocated size: 800
Task: USB_CHG_P0, Max size: 672 (448 + 224), Allocated size: 720
Task: USB_CHG_P1, Max size: 672 (448 + 224), Allocated size: 720
Task: CHARGER, Max size: 712 (488 + 224), Allocated size: 800
Task: MOTIONSENSE, Max size: 720 (496 + 224), Allocated size: 768
Task: CHIPSET, Max size: 744 (520 + 224), Allocated size: 800
Task: KEYPROTO, Max size: 516 (292 + 224), Allocated size: 600
Task: PDCMD, Max size: 776 (552 + 224), Allocated size: 800
Task: HOSTCMD, Max size: 792 (568 + 224), Allocated size: 840
Task: CONSOLE, Max size: 840 (616 + 224), Allocated size: 880
Task: POWERBTN, Max size: 696 (472 + 224), Allocated size: 800
Task: KEYSCAN, Max size: 584 (360 + 224), Allocated size: 600
Task: PD_C0, Max size: 896 (672 + 224), Allocated size: 1000
Task: PD_C1, Max size: 896 (672 + 224), Allocated size: 1000
RO is identical
200c7720 D __shared_mem_buf
There is still 2272 bytes of shared memory.
BRANCH=poppy
BUG=b:75234825
TEST=See above, software sync still works
Change-Id: Ia98b27a924d0023a5fb3bfef5280e9365e6ddf4b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/965706
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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On cros/firmware-poppy-10431.B, plus the patches on this branch:
make BOARD=soraka SECTION=RO analyzestack | grep Task
Task: HOOKS, Max size: 776 (552 + 224), Allocated size: 800
Task: USB_CHG_P0, Max size: 696 (472 + 224), Allocated size: 800
Task: USB_CHG_P1, Max size: 696 (472 + 224), Allocated size: 800
Task: CHARGER, Max size: 776 (552 + 224), Allocated size: 800
Task: MOTIONSENSE, Max size: 664 (440 + 224), Allocated size: 768
Task: CHIPSET, Max size: 760 (536 + 224), Allocated size: 800
Task: PDCMD, Max size: 784 (560 + 224), Allocated size: 880
Task: HOSTCMD, Max size: 808 (584 + 224), Allocated size: 840
Task: CONSOLE, Max size: 856 (632 + 224), Allocated size: 960
Task: POWERBTN, Max size: 728 (504 + 224), Allocated size: 800
Task: PD_C0, Max size: 912 (688 + 224), Allocated size: 1000
Task: PD_C1, Max size: 912 (688 + 224), Allocated size: 1000
(RW returns identical values)
All tasks have a good amount of slack (some have even more, as
poppy board requires even more stack size than soraka).
Shared_mem_buf at:
200c7400 D __shared_mem_buf
(so there is still 3072 bytes of available RAM)
BRANCH=none
BUG=b:75234824
TEST=See line above, EC software sync still works
Change-Id: I60d8574c827c1102f0968766b1e6c4a50f56071a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966044
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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make BOARD=staff SECTION=RO analyzestack | grep Task
Task: RWSIG, Max size: 780 (716 + 64), Allocated size: 1280
Task: HOOKS, Max size: 960 (896 + 64), Allocated size: 2048
Task: CONSOLE, Max size: 840 (776 + 64), Allocated size: 1024
make BOARD=staff SECTION=RW analyzestack | grep Task
Task: HOOKS, Max size: 1216 (1152 + 64), Allocated size: 2048
Task: TOUCHPAD, Max size: 548 (484 + 64), Allocated size: 640
Task: CONSOLE, Max size: 468 (404 + 64), Allocated size: 1024
Task: KEYSCAN, Max size: 408 (344 + 64), Allocated size: 488
BRANCH=poppy
BUG=b:75234264
TEST=See results above. No more (or few) missing annotations in
full results. No task stack overflow.
Change-Id: Iaae99e0129f5eac3f0ed3bcacd89fffbceca7a7f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966043
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Makes it far simpler to support hooks, console commands, host
commands.
BRANCH=poppy,fizz
BUG=chromium:648840
TEST=Add new array annotation, run stack_analyzer
Change-Id: I8ed074ba5534661ed59f4f713bb4ba194e712f4e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966042
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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The temperature of test chamber is 55'C.
Battery temperature is over 60'c when system runs on test chamber.
The system turns off and enter hibernation
because discharging_max_c is set to 60'C.
BUG=b:74414822
BRANCH=none
TEST=Build, flash and check system in test chamber.
Change-Id: Ibfe05f0f31a0ebd9f72926ff7efa8faacca08153
Signed-off-by: YB.Ha <ybha@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/958802
Commit-Ready: YongBeum Ha <ybha@samsung.com>
Tested-by: YongBeum Ha <ybha@samsung.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
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Add 2 ADC channels for SKU ID. Each channel gives a 0-15 level,
these are combined to give a 0-255 SKU ID. The AP reads this
using EC_CMD_GET_SKU_ID.
BUG=b:75285661
BRANCH=none
TEST=EC_CMD_GET_SKU_ID (HC 0x0e) now succeeds
TEST=dmidecode | grep sku
Change-Id: I5b03e478518a1bb0ce7107451d71a82b7e48ec86
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967223
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This change brings the improvements to suspend EC power
on npcx by properly configuring unused GPIOs to INPUT | PULL_UP.
BOARDID pins are all reconfigured for low power since they get properly
configured on reading anyways.
Those are:
GPIO43 (BOARD_VERSION1)
GPIO44 (BOARD_VERSION2)
GPIO45 (BOARD_VERSION3)
GPIO57 (TP_EC_GPIO_57) is unused
GPIO01 (CHARGER_RST_ODL) is floating
GPIO02 (EC_HAVEN_RESET_ODL) is floating
BRANCH=eve
BUG=b:69816245
TEST=manual
with R67-10492.0.0, and ec: eve_v1.1.6585-859d2ea99
(powerd_dbus_suspend)
@@ NAME COUNT AVERAGE STDDEV MAX MIN
@@ pp3300_dsw_ec_mw 5053 19.57 6.12 39.14 9.59
with R67-10492.0.0, and ec: eve_v1.1.6620-f8301499 (this change)
(powerd_dbus_suspend)
@@ NAME COUNT AVERAGE STDDEV MAX MIN
@@ pp3300_dsw_ec_mw 5199 12.78 5.43 17.99 3.98
Change-Id: I83879be45c1aa74dc4746ea51db41e068e2284b4
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/965782
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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These print-outs are usually very deep in the call stack (rare
error cases that do not happen often), and therefore are the
longest branches on most tasks. Replacing cprints by
cputs/cprintf helps with that.
BRANCH=none
BUG=b:75234824
TEST=make BOARD=soraka SECTION=RW analyzestack | grep Task shrinks
significantly (more than 100 bytes on some tasks)
Change-Id: I7c5bb750f4aa624cd06736e0bb6b24d307fc0196
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966041
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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On Nami, the CPU will manage temperature control. The EC's role is
passive. It sends the CPU temperatures read from the sensors upon
request and to control the fan speed as instructed.
This patch removes thermal control.
BUG=b:72959743
BRANCH=none
TEST=Boot Nami
Change-Id: If4bb7b9774e417813190327c98232eca536ba9c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967145
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Modify battery smbus frequency to 100KHz.
Due to the max working frequency is
100KHz, so EC change for support it.
BUG=b:75077297
BRANCH=none
TEST=Verify TI gauge battery that can be
recognize via ec console.
Change-Id: Ibdafdadbc83faed5b40b5ba00b179867ce307151
Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/966048
Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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A few commands had help text of "[0 | 1]" but parse_bool()
doesn't recognize 0 and 1. Change help text to "[on | off]",
matching other commands.
BUG=b:75302458
BRANCH=none
TEST=none
Change-Id: I9b1e4a70e024d17ec8bccc015069e31d7fff08ca
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967248
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The number of interrupt events will increase with the ST sensors support.
BUG=b:73546254
BRANCH=none
TEST=compile
Change-Id: If375afa97ad664594f005a6b007aa7d9439e8ecb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/767611
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This patch removes flash WP check in the EFS main. It means even
if the SPI flash is not write protected, it performs EFS.
This allows dogfood devices to boot just like normal devices.
BUG=b:74983574
BRANCH=none
TEST=Boot Fizz. Verify EFS works as expected.
HW_WP=0, SW_WP=0: No EFS
HW_WP=0, SW_WP=1: No EFS
HW_WP=1, SW_WP=0: EFS is performed (Dogfood devices)
HW_WP=1, SW_WP=1: EFS is performed (Normal devices)
Change-Id: I33b39463d6bd16fe0fc398cd49f3c92c76fa5103
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/964740
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Define GPIOs for board versions 0 and 2. Read version in board_init()
and configure GPIOs correctly.
BUG=b:74538637
BRANCH=none
TEST=build + boot grunt (version 0)
Change-Id: I1ff23d5c114cb12e3a32ef069f5e5dff50640d3f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966591
Reviewed-by: Martin Roth <martinroth@chromium.org>
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If the fan is never enabled, temp_metrics itself has no code-path to
enable the fan. This fixes this by calling fanduty 0 in the beginning
of temp_metrics, since fanduty does explicitly enable the fan.
Note: This is a hack to avoid having to flash a new EC image. See
crrev.com/c/964037 for a more fundamental fix to the same issue.
BRANCH=link
BUG=chromium:808764
TEST=couldn't reproduce issue with this version of temp_metrics.
Change-Id: I8a9b258ba7b50cf5180497d318f8d94454dab434
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/964069
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Sameer Nanda <snanda@chromium.org>
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Configure the large arrays for the image frame and template in other
SRAM memory regions to free up space for the malloc heap in the 'main'
SRAM.
Note: the template buffer is only used in future CLs.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=on ZerbleBarn, run the 'shmem' console and see 500kB of heap
available for malloc.
Change-Id: I31a1b4fb0d5e124e3229d29386cc6500e402dac0
Reviewed-on: https://chromium-review.googlesource.com/946370
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Add fast compensation automatic calibration, like bmi160.
Use timestamp_expired for timeout measurement for both perform_calib
functions.
Remove driver offset field, remove private bma2x2 structure.
BUG=b:73205042
BRANCH=master
TEST=echo 1 > calibrate perform calibration.
Reading in_accel_*_calibbias is within range.
Check on Lami for both bma2x2 and bmi160.
Change-Id: I3472865287fa4769a05e6f872b92d7c3f933cb4e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/957872
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Save some space on kevin.
BUG=b:73205042
BRANCH=master
TEST=Can compile kevin with perform_calib addition.
Change-Id: If1526a90925ad20e4cc335e68de266cbc1ae6a42
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/961223
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The CLs supporting BC 1.2 with rt946x have been merged.
It's time to enable BC 1.2 on Scarlet!
BUG=b:65446459
BRANCH=none
TEST=Charge Scarlet rev4 with SDP (500mA), DCP (1500mA),
PD charger, and Type-C charger (3000mA).
Change-Id: Ia3c7a700586bc15d94c4ef104fbd5afc8be9b0af
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905934
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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set_resolution is only used for few sensors and is not exposed to the AP.
Remove definition when sensors have a fixed resolution.
BUG=none
BRANCH=master
TEST=compile, kevin has enough space for perform_calib.
Change-Id: I8482387e135356467edaee44da3a0e47cf1db524
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/961222
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Similar to eve, disable power button shutdown by PMIC on long press of
power button. Using Vup+Pwr is the still the best way to do a PMIC
reset.
BUG=b:74866345
BRANCH=poppy
TEST=Verified that holding power button for >80 seconds did not
trigger PMIC shutdown.
Change-Id: I6a844b1b5d68a9e28daaf0452e461233057e1869
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/964889
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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The same Chrome OS device could have not only several released
firmware images, but also several variations of the GBB contents. Any
permutation of these two sets is possible, but both areas must match,
as modified GBB is no smaller problem than modified code or RO data.
With this patch the verifier will continue looking for board sections
in the descriptors database until the entire database has been
scanned. Only finding exactly two sections, and each section providing
proper matches will qualify the check as 'pass'.
BRANCH=none
BUG=b:73668125
TEST=verified that both single and dual section descriptions are
processed properly, and that matching 1 and 3 sections triggers a
return error.
Change-Id: I181655192246ce245c43e6ce7ba4768ac5c9e51a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/951864
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Unify get_range/get_datarate by using accelgyro_saved_data_t
structure.
BUG=none
BRANCH=none
TEST=compile
Change-Id: I0bfa2f06c5dd2021a5af9e6499c97e65988167ce
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/961221
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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