summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* cr50: prepare to release 0.{5,6}.60firmware-cr50-9308.BMary Ruthven2021-10-192-2/+2
| | | | | | | | | | | | BUG=b:203205487 TEST=none Change-Id: I90ef2a52a40ceef6de930df2acb635cdc0b3d014 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3227259 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 69492c43e78abfb8647bab969526cd3e2d300707) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3232289
* usb_spi_v2: read full PDU into a bufferVadim Bendebury2021-10-194-35/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain test configurations present a problem for the raiden protocol V2 implementation on the Cr50 side, which result in random SPI read failures. While the issue is still being investigated this patch offers a workaround, where SPI and USB transactions are not overlaid, the driver first reads the entire requested number of bytes into a buffer, and then sends them to the host in multiple USB packets. Since buffer memory can not be permanently dedicated to the driver, it uses dynamic allocation to acquire the buffer. The allocation could fail, for instance when the flashrom operation is requested soon after startup and heap memory is used for NVMEM compaction. If the allocation fails, the driver sends an error packet to the host, and the host requests to restart the response. To be able to restart the response the driver now stores the request. With some instrumentation, measurements taken on reading of 200 2040 byte blocks have shown that memory was held by this driver for 94% of the duration. To address the case when flashrom session is interrupted mid PDU transfer, do not wait for the transmit queue to become available for more than 500 ms. In case the queue gets stuck return without waiting any more, this will make sure the allocated buffer is freed. BUG=b:196820680 TEST=successfully ran hundreds of cycles of read, and read and write on the setup which exhibits the problem without this patch on pretty much every read attempt. The slow down caused by this change is pretty small: average of five attempts to read 16MB of SPI flash on guybrush device take 50.560s before this change and 51.267s after this change, which is a 1.7% slowdown. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I82c98f912a8763b7e242dad48997a8d2ffbaf29a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3188568 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 30c8e6783a40a6f0969972f5b342b9db3588c5e0) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3232288 Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* i2cp: reduce the number of i2c flog errorsMary Ruthven2021-10-191-0/+8
| | | | | | | | | | | | | | | | | | | Cap the number of I2C flog errors at 2 per boot. The timestamps of the two events can indicate if the unwedge issues happen successively or if there is a large gap between events. Many events with a short gap are likely benign and due to i2c not being terminated correctly. Inidividual I2C errors are likely caused by some other issue. BUG=b:146067724 TEST=check the number of i2c log messages on coral in s0ix Change-Id: I3f04c85e6233bf0c790db0d40a85aab3c927b9b8 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3225996 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 2b702d8cc86ac5763a5181854caf2139b61b4e7c) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229796 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* i2cp: remove FE_TPM_I2C_ERROR logMary Ruthven2021-10-191-4/+0
| | | | | | | | | | | | | | | | | FE_TPM_I2C_ERROR events don't mean much and it's not a big deal if cr50 needs to recover the I2C bus. Remove FE_TPM_I2C_ERROR logging from chip/i2cp. BUG=b:146067724 TEST=make buildall -j Change-Id: I2bdce35fc794559c8236b1c14d87fa4372ffafa4 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219755 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 39e75e0a99061689620de3df9adc81bc1d810f66) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229795 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* ap_ro_status: report the button status if verification is unsupportedMary Ruthven2021-10-192-16/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Shimless RMA needs to know if the button combo triggered AP RO verification even if AP RO verification isn't supported. This change adds two new responses AP_RO_UNSUPPORTED_TRIGGERED(5) and AP_RO_UNSUPPORTED_NOT_TRIGGERED(4) to tell if the button combo was pressed on a board that doesn't support AP RO verification. The old AP_RO_UNSUPPORTED value, 3, isn't returned by cr50 anymore. AP_RO_PASS(1) and AP_RO_FAIL(2) are still used. They both mean the combo was triggered. AP_RO_NOT_RUN(0) is still used. It still means the combo wasn't triggered. Summary of the states - pressed - AP_RO_PASS(1), AP_RO_FAIL(2), AP_RO_UNSUPPORTED_TRIGGERED(5) - not pressed - AP_RO_NOT_RUN(0) and AP_RO_UNSUPPORTED_NOT_TRIGGERED(4) - unknown - AP_RO_UNSUPPORTED_UNKNOWN(3) The prepvt branch doesn't have AP RO verification v2, so there were merge conflicts. BUG=b:181000999 TEST=use gsctool to get the AP RO verification status on cr50 images with the new and old version of the get AP RO status vendor command. Change-Id: Ib2b33e69a4d4165fc2c13437a919b8f2a83c1bba Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213112 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 484f31b694f04a3b027e3129f5153044a296ee5c) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229794 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* ccdblock: move IGNORE_SERVO warning to the endMary Ruthven2021-10-191-4/+4
| | | | | | | | | | | | | | | | | | | | Move the IGNORE_SERVO warning to the end of ccdblock output, so it doesn't break up the ports blocked. BUG=none TEST=enable ccdblock EC_CR50_COMM and IGNORE_SERVO. Verify EC_CR50_COMM shows up in the port blocked field. > ccdblock CCD ports blocked: EC_CR50_COMM IGNORE_SERVO WARNING: enabling UART while servo is connected may damage hardware Change-Id: I423f05d3d4c097c2e2fc2fd6db83a8d1f6b410a0 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219761 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 27d99037218b794324d5731591dafa8ab5209c92) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229793 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* ccdblock: add option to tri-state the EC UARTMary Ruthven2021-10-191-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block EC UART output and EC COMM with 'ccdblock TRISTATE_EC enable'. This removes the EC UART output, prevents EC-EFS2, and removes the pulldown from the EC RX signal. This is used for flashing the EC with c2d2. It's only available when CCD is enabled. BUG=b:202464674 TEST=manual # Disconnect servo. Verify EC tx is disabled and there's no pull # down after tristating the EC > ccdblock TRISTATE_EC enable CCD ports blocked: EC IGNORE_SERVO WARNING: enabling UART while servo is connected may damage hardware EC_CR50_COMM TRISTATE_EC > pinmux ... 400600c8: DIOB5 0 IN 400600d0: DIOB6 16 IN GPIO0_GPIO15 ... > ccdstate ... State flags: UARTAP USBEC+TX CCD ports blocked: EC EC_CR50_COMM TRISTATE_EC ... # Check UART TX is re-enabled after disabling TRISTATE_EC > ccdblock TRISTATE_EC disable CCD ports blocked: (none) > ccdstate ... State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX CCD ports blocked: (none) ... > pinmux ... 400600c8: DIOB5 78 IN UART2_TX 400600d0: DIOB6 16 IN GPIO0_GPIO15 ... # Connect servo, so cr50 disables the EC UART on it's own. # Verify the pulldown is removed after tristating the EC. > ccdstate ... State flags: UARTAP UARTEC USBEC+TX CCD ports blocked: (none) > pinmux ... 400600c8: DIOB5 0 IN PD 400600d0: DIOB6 16 IN GPIO0_GPIO15 ... > ccdblock TRISTATE_EC enable CCD ports blocked: EC EC_CR50_COMM TRISTATE_EC > ccdstate ... State flags: UARTAP USBEC+TX CCD ports blocked: EC EC_CR50_COMM TRISTATE_EC # Check PD is removed from DIOB5 > pinmux ... 400600c8: DIOB5 0 IN 400600d0: DIOB6 16 IN GPIO0_GPIO15 ... # Check PD is re-enabled after disabling TRISTATE_EC > ccdblock TRISTATE_EC disable CCD ports blocked: (none) > ccdstate ... State flags: UARTAP UARTEC USBEC+TX CCD ports blocked: (none) > pinmux ... 400600c8: DIOB5 0 IN PD 400600d0: DIOB6 16 IN GPIO0_GPIO15 Change-Id: I7bde996be3914bd5d625ad99e418f9bd2c0f41d1 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219760 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 29c152bcf67e09d60d28f519458b7fd7a0e8a1cd) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229792 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* rdd: only enable AP UART if the AP is onMary Ruthven2021-10-191-1/+1
| | | | | | | | | | | | | | | | | | When the AP is off, cr50 doesn't need to enable the AP UART. Having it enabled could cause power leakage if the signals aren't terminated correctly. Check ap_is_on and ap_uart_is_on before enabling the AP UART. BUG=b:136602563 TEST=firmware_Cr50DeviceState Change-Id: I192bdc4caef8cfa0ce6d8a3ca181b16388e35cd4 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219756 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 39447a20c6e663d83b8581330378275530b3b2f3) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229791 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* Reland "usb_spi: move to Raiden V2 implementation"Vadim Bendebury2021-10-198-10/+740
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of 0972fa88f1c3f39020efff37784b58bbbdf41fe6 Original change's description: > usb_spi: move to Raiden V2 implementation > > This patch introduces an alternative USB SPI protocol implementation > to be used by Cr50: Raiden V2. The SPI USB endpoint descriptor is > modified to advertise the new version in the bInterfaceProtocol, which > allows the flashrom utility to use the new protocol version. > > Protocol version 2 implements segmentation and reassembly where longer > flash read and write PDUs can be transferred split into shorter fixed > size USB packets. The comment section in usb_spi_v2.c describes the > protocol in detail. > > Each time a USB packet is received from the host, the packet header is > examined to determine the command. The command could be a DUT > configuration query OR a request to read and or write some data > from/to the SPI flash chip, OR a request to retransmit the last PDU > from the beginning. > > This patch implementation does not process the retransmittion request > command yet, in case a packet is dropped flashrom would need to be > re-run. This is a pretty rare condition, but if deemed necessary > support can be added later. > > H1 SPI controller supports multibuffer transactions where the CS > signal is kept asserted while the controller clocks the bus when the > next portion of data to write becomes available or there is more room > to read data to send back to the host. This allows to support > arbitrary length read and write transactions. There is no need to > support write transactions longer than 256 bytes of data, as this is a > typical SPI flash chip page size. For read direction the size of 2040 > was chosen, which is close to 2K and takes full payload of 34 USB > packets on top of 2 byte headers. > > The protocol state machine on the device sideOB can be in one of > two states, IDLE or WRITING. Many of host requests do not require the > device to change state: configuration requests, or writes of short > blocks of data (fitting into one USB packet) can be executed > immediately. Requests to read long blocks of data can still be > executed without leaving the IDLE state, the device starts the SPI > transaction and then iterates reading one packet worth of data at a > time and sends it back to the host. Once the entire PDU is read, the > CS is deasserted. > > In case the host requests to write a block of data which does not fit > into a USB packet the device asserts the CS, sends the first received > block to the SPI flash chip and then enters the WRITING state, > expecting the controller to send the rest of the PDU in following > packets. > > Once the entire PDU is transferred the CS is deasserted and state is > changed back to IDLE. > > BUG=b:79492818 > TEST=performed numerous flash read/write operations with 16M SPI flash > chip on the Atlas device. Timing results comparison of various > operations: > Raiden V1 Raiden V2 > > Reading entire chip: 3m 16s 0m 52s > > Vanilla writing of new image: 16m 22s 5m 48s > > Writing of AP firmware into an > erased flash chip (no read > before or after writing) 4m 12s 1m 38s > > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> > Change-Id: I374f3caab7146fc84b62274e9e713430d7d31de0 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977965 > Reviewed-by: Brian Nemec <bnemec@chromium.org> > Reviewed-by: Andrey Pronin <apronin@chromium.org> > (cherry picked from commit 049538cb663e8d8f1f9fbeed94f7b823e0eafabe) > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078207 > Tested-by: Mary Ruthven <mruthven@chromium.org> > Commit-Queue: Mary Ruthven <mruthven@chromium.org> Bug: b:79492818 Change-Id: I4fe8ff3c18ae0cfa400fdc0a3cc3009c6fbca440 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229785 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* Reland "g: spi_controller: add the subtransaction capability"Vadim Bendebury2021-10-192-13/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of 87e229413d52a4c2b7cca7e1aede3a8dcb5532c1 Original change's description: > g: spi_controller: add the subtransaction capability > > It is necessary to be able to send SPI transactions with sizes > exceeding the SPI controller buffer size. This can be achieved by > asserting CS before sending the first batch (data block) in a > transaction and deasserting CS after the last batch. > > Let's add a SPI controller spi_sub_transaction() API, with an > additional parameter indicating when the last batch is submitted for > processing. > > The existing spi_transaction() API becomes a wrapper which always > calls spi_sub_transaction() to send a full single batch transaction. > > BUG=b:79492818 > TEST='flashrom --flash-name' still succeeds. > > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> > Change-Id: Ia0c5114edd5caf6c6d0e22cab3bfa3c4d86ac79a > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977964 > Reviewed-by: Mary Ruthven <mruthven@chromium.org> > (cherry picked from commit e2655cb43fdc938d467018ccd5c3df9fb907c400) > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004086 > Reviewed-by: Andrey Pronin <apronin@chromium.org> > Tested-by: Mary Ruthven <mruthven@chromium.org> > Commit-Queue: Mary Ruthven <mruthven@chromium.org> Bug: b:79492818 Change-Id: Ib04478faf626c26800235e27d77f13f41286f1fb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229784 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* Reland "cr50: switch SPI CS to GPIO mode"Vadim Bendebury2021-10-193-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of b3480c1ae2ef6dcc246cfa39c1d8daeee715da21 Original change's description: > cr50: switch SPI CS to GPIO mode > > To be able to send and receive multiple SPI buffer quantities in a > single SPI transaction it is necessary to control the SPI CS signal > directly, as opposed to connecting it to the SPI controller. > > Direct mode allows to keep CS asserted as long as necessary to > transfer the full data blob, size of which might exceed the the size > of the SPI controller buffer. > > BUG=b:79492818 > TEST=flashrom access still works fine: > > $ flashrom -p raiden_debug_spi:target=ap --flash-name > flashrom f10dff7b-dirty on Linux 5.4.0-71-generic (x86_64) > flashrom is free software, get the source code at https://flashrom.org > > Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). > Raiden target: 2 > Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, SPI) on... > vendor="GigaDevice" name="GD25Q127C/GD25Q128C" > > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> > Change-Id: Idecf019d3fd19675d7f78e4dc1140106a2112c6b > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973580 > Reviewed-by: Mary Ruthven <mruthven@chromium.org> > (cherry picked from commit c6095192742c9f59f72a6178ece5a2dd8cea4e43) > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004085 > Reviewed-by: Andrey Pronin <apronin@chromium.org> > Tested-by: Mary Ruthven <mruthven@chromium.org> > Commit-Queue: Mary Ruthven <mruthven@chromium.org> Bug: b:79492818 Change-Id: I9ba90258f381e41551ee5636c9712e90ef605ed7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229783 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* tpm_mode: do not proceed if nvmem commits can not be enabledVadim Bendebury2021-10-192-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NVMEM commits are disabled for a few seconds after every TPM reset. Setting TPM mode to 'disabled' requires the commits to be enabled first, so that the NVMEM updates would be saved immediately. Re-enabling the commits must be done by the same task which disables them, i.e. the TPM task. This patch moves the invocation of 'nvmem_enable_commits()' to the main processing thread of the TPM mode vendor command handler. When invoked through TPM it will be able to properly reenable NVMEM commits. When invoked through USB it will fail if TPM reset happened less than 3 seconds ago. BUG=b:187831914 TEST=verified that when the TPM disable command is sent immediately after TPM reset over USB it is rejected with error code 11, no lockup/watchdog reset is observed. Testing the AP sending the command will be done when debugging NBR. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I035cd5db2c55fe5c9dd3679153bf9a2ec49210b6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2998302 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit 1e68e66a387c91b63a7a79324f3c828f7f0fed4b) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229790 Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* CRYPTO_TEST: fix build ap_state build issueMary Ruthven2021-10-191-0/+2
| | | | | | | | | | | | | | BUG=none TEST=make -j BOARD=cr50 CRYPTO_TEST=1 Change-Id: Iad1c87d6ca3dfd798a6b63a0cffc087e1dd716a2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3002450 Reviewed-by: Andrey Pronin <apronin@chromium.org> Commit-Queue: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 0c2cec099fbaa330af54837232b0208addeff299) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229789 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add closed loop reset print statementsMary Ruthven2021-10-191-0/+2
| | | | | | | | | | | | | | | | | Add some print statements to closed loop reset, so it's easier to tell what cr50 is doing. BUG=none BRANCH=cr50 TEST=none Change-Id: I2b6b28d8eabcd8950fe7105b4382d8b8ed94afa6 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1716927 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 701f45f574cfcf9182e89267e5479af5eb709576) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229788 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: refactor pinmux state printing functionVadim Bendebury2021-10-191-10/+20
| | | | | | | | | | | | | | | | | | | | | | | This refactoring improves optional parameter alignment, includes virtual pads in the output and shaves 44 bytes from the image size. BRANCH=cr50, cr50-mp BUG=none TEST=saved pinmux command output in files pm.before and pm.after, then verified that the following command produced no output $ diff -w <(sort pm.before) <(sort pm.after) Change-Id: I81c2fad8c9e87e05dd39c588340a82f83e3ab488 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1731138 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit 77be418d68b6569133d45b040792e6aa34e20c82) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229787 Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* Mark reset and panic functions as noreturnPatrick Georgi2021-10-196-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | gcc 6.3 (as provided by coreboot-sdk) needs that to know which code paths end early. Also add a loop after the command that is "supposed" to reset the machine so that the compiler believes it (and in case that assumption fails). BRANCH=none BUG=b:65441143 TEST=none Change-Id: Idb87253ec7880d66ffec30d75f4d007f02f63aab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/742916 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 887e3962ca19cc7e8c3c474f8c82b4240eb63416) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229786 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* Revert "Clear OWNERS for factory/firmware branch"Mary Ruthven2021-10-011-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9d31b93251fc934309aa9c9a3ad29514b59d62f4. Reason for revert: keep cr50 team members in OWNERS Original change's description: > Clear OWNERS for factory/firmware branch > > BUG=none > TEST=none > > Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 > Signed-off-by: Brian Norris <briannorris@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155148 > Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> > Owners-Override: Jora Jacobi <jora@google.com> > Tested-by: Jack Rosenthal <jrosenth@chromium.org> Bug: none Change-Id: I48ffbed9f14ed9a066ae9dcab1663149329381b4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3200062 Auto-Submit: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* Clear OWNERS for factory/firmware branchBrian Norris2021-09-111-9/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155148 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* cr50: prepare to release 0.{5,6}.51Mary Ruthven2021-08-272-2/+2
| | | | | | | | | | | | | BUG=b:194901448 TEST=none Change-Id: Ia16d194f042ab44a36e00668f699dfab4df8a536 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114224 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit ea35354507745b5763bb85479a26409920ed37b0) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124572
* add BOARD_CCD_REC_LID_PIN_DIOA12 to Zork brdpropMary Ruthven2021-08-271-1/+2
| | | | | | | | | | | | | | | | | | Make DIOA12 an output on Zork, so it can be used for the ccd recovery or lid switch signals. BUG=b:197916691 TEST=setting CCD_REC_LID_PIN toggles lid_open on tomato Change-Id: I755498fd9bb9b764b0e0aa2bf0394c45b087c767 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124565 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 6b7b22bc5abf09c823451f12b50559c197ed6c32) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124571
* usb_spi: Remove stm32spi.py since no one uses itYilin Yang2021-08-271-140/+0
| | | | | | | | | | | | | | | | | | | | BUG=chromium:1031705 BRANCH=master TEST=None Signed-off-by: kerker <kerker@chromium.org> Change-Id: Idf4f5342da6b3f3307e1948c165d44b83031543a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2425983 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@chromium.org> (cherry picked from commit 24f03775900d085130f4d411da3bfdfe29afc7ef) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3067596 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit fe02aee774d97b87431de3407bedc8505f115c4e) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124570 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* tpm_mode: move s_tpm_mode to .bss.Tpm2_commonMary Ruthven2021-08-271-6/+12
| | | | | | | | | | | | | | | | | | Move tpm_mode_s to .bss.Tpm2_common, so TPM_MODE_ENABLED is cleared during tpm reset events. Cr50 still clears TPM_MODE_DISABLED by doing a hard reset instead of triggering a tpm reset event. BUG=b:191180387,b:196820239 TEST=run firmawre_Cr50TpmMode Change-Id: I5f5cedb7b5b6a03bf504583c378fae87896cef2b Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3105485 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 5db45a1e5e122ab1098eeb8cd61176e0837809f6) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124569
* Revert "cr50: switch SPI CS to GPIO mode"Mary Ruthven2021-08-273-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b3480c1ae2ef6dcc246cfa39c1d8daeee715da21. Reason for revert: Recent CCD changes cause flash ap issues on eve Original change's description: > cr50: switch SPI CS to GPIO mode > > To be able to send and receive multiple SPI buffer quantities in a > single SPI transaction it is necessary to control the SPI CS signal > directly, as opposed to connecting it to the SPI controller. > > Direct mode allows to keep CS asserted as long as necessary to > transfer the full data blob, size of which might exceed the the size > of the SPI controller buffer. > > BUG=b:79492818 > TEST=flashrom access still works fine: > > $ flashrom -p raiden_debug_spi:target=ap --flash-name > flashrom f10dff7b-dirty on Linux 5.4.0-71-generic (x86_64) > flashrom is free software, get the source code at https://flashrom.org > > Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). > Raiden target: 2 > Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, SPI) on... > vendor="GigaDevice" name="GD25Q127C/GD25Q128C" > > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> > Change-Id: Idecf019d3fd19675d7f78e4dc1140106a2112c6b > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973580 > Reviewed-by: Mary Ruthven <mruthven@chromium.org> > (cherry picked from commit c6095192742c9f59f72a6178ece5a2dd8cea4e43) > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004085 > Reviewed-by: Andrey Pronin <apronin@chromium.org> > Tested-by: Mary Ruthven <mruthven@chromium.org> > Commit-Queue: Mary Ruthven <mruthven@chromium.org> Bug: b:79492818 Change-Id: Icc1498ee7bc6ff6333b639d120dc8a7d4b6b6980 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124573 Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* Revert "g: spi_controller: add the subtransaction capability"Mary Ruthven2021-08-272-52/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 87e229413d52a4c2b7cca7e1aede3a8dcb5532c1. Reason for revert: Recent CCD changes cause flash ap issues on eve Original change's description: > g: spi_controller: add the subtransaction capability > > It is necessary to be able to send SPI transactions with sizes > exceeding the SPI controller buffer size. This can be achieved by > asserting CS before sending the first batch (data block) in a > transaction and deasserting CS after the last batch. > > Let's add a SPI controller spi_sub_transaction() API, with an > additional parameter indicating when the last batch is submitted for > processing. > > The existing spi_transaction() API becomes a wrapper which always > calls spi_sub_transaction() to send a full single batch transaction. > > BUG=b:79492818 > TEST='flashrom --flash-name' still succeeds. > > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> > Change-Id: Ia0c5114edd5caf6c6d0e22cab3bfa3c4d86ac79a > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977964 > Reviewed-by: Mary Ruthven <mruthven@chromium.org> > (cherry picked from commit e2655cb43fdc938d467018ccd5c3df9fb907c400) > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004086 > Reviewed-by: Andrey Pronin <apronin@chromium.org> > Tested-by: Mary Ruthven <mruthven@chromium.org> > Commit-Queue: Mary Ruthven <mruthven@chromium.org> Bug: b:79492818 Change-Id: Ibf6861e11a52dd74746fb8ff21bbae6e5af9d21a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125115 Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* Revert "usb_spi: move to Raiden V2 implementation"Mary Ruthven2021-08-278-740/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 0972fa88f1c3f39020efff37784b58bbbdf41fe6. Reason for revert: breaks flashing the ap on eve Original change's description: > usb_spi: move to Raiden V2 implementation > > This patch introduces an alternative USB SPI protocol implementation > to be used by Cr50: Raiden V2. The SPI USB endpoint descriptor is > modified to advertise the new version in the bInterfaceProtocol, which > allows the flashrom utility to use the new protocol version. > > Protocol version 2 implements segmentation and reassembly where longer > flash read and write PDUs can be transferred split into shorter fixed > size USB packets. The comment section in usb_spi_v2.c describes the > protocol in detail. > > Each time a USB packet is received from the host, the packet header is > examined to determine the command. The command could be a DUT > configuration query OR a request to read and or write some data > from/to the SPI flash chip, OR a request to retransmit the last PDU > from the beginning. > > This patch implementation does not process the retransmittion request > command yet, in case a packet is dropped flashrom would need to be > re-run. This is a pretty rare condition, but if deemed necessary > support can be added later. > > H1 SPI controller supports multibuffer transactions where the CS > signal is kept asserted while the controller clocks the bus when the > next portion of data to write becomes available or there is more room > to read data to send back to the host. This allows to support > arbitrary length read and write transactions. There is no need to > support write transactions longer than 256 bytes of data, as this is a > typical SPI flash chip page size. For read direction the size of 2040 > was chosen, which is close to 2K and takes full payload of 34 USB > packets on top of 2 byte headers. > > The protocol state machine on the device sideOB can be in one of > two states, IDLE or WRITING. Many of host requests do not require the > device to change state: configuration requests, or writes of short > blocks of data (fitting into one USB packet) can be executed > immediately. Requests to read long blocks of data can still be > executed without leaving the IDLE state, the device starts the SPI > transaction and then iterates reading one packet worth of data at a > time and sends it back to the host. Once the entire PDU is read, the > CS is deasserted. > > In case the host requests to write a block of data which does not fit > into a USB packet the device asserts the CS, sends the first received > block to the SPI flash chip and then enters the WRITING state, > expecting the controller to send the rest of the PDU in following > packets. > > Once the entire PDU is transferred the CS is deasserted and state is > changed back to IDLE. > > BUG=b:79492818 > TEST=performed numerous flash read/write operations with 16M SPI flash > chip on the Atlas device. Timing results comparison of various > operations: > Raiden V1 Raiden V2 > > Reading entire chip: 3m 16s 0m 52s > > Vanilla writing of new image: 16m 22s 5m 48s > > Writing of AP firmware into an > erased flash chip (no read > before or after writing) 4m 12s 1m 38s > > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> > Change-Id: I374f3caab7146fc84b62274e9e713430d7d31de0 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977965 > Reviewed-by: Brian Nemec <bnemec@chromium.org> > Reviewed-by: Andrey Pronin <apronin@chromium.org> > (cherry picked from commit 049538cb663e8d8f1f9fbeed94f7b823e0eafabe) > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078207 > Tested-by: Mary Ruthven <mruthven@chromium.org> > Commit-Queue: Mary Ruthven <mruthven@chromium.org> Bug: b:79492818 Change-Id: Ice31e77e296262cc13f6c533e2b59db0ae7e57ce Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125114 Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Brian J. Nemec <bnemec@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* cr50: prepare to release 0.{5,6}.50Mary Ruthven2021-08-062-2/+2
| | | | | | | | | | | | | BUG=b:194901448 TEST=none Change-Id: I9d4d5133d26ac528b2ecf5e1b0f4be20a47badb8 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3072819 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 04f5e125aa9bb9d8543828a1a285b52abd0929aa) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078208 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* usb_spi: move to Raiden V2 implementationVadim Bendebury2021-08-068-10/+740
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces an alternative USB SPI protocol implementation to be used by Cr50: Raiden V2. The SPI USB endpoint descriptor is modified to advertise the new version in the bInterfaceProtocol, which allows the flashrom utility to use the new protocol version. Protocol version 2 implements segmentation and reassembly where longer flash read and write PDUs can be transferred split into shorter fixed size USB packets. The comment section in usb_spi_v2.c describes the protocol in detail. Each time a USB packet is received from the host, the packet header is examined to determine the command. The command could be a DUT configuration query OR a request to read and or write some data from/to the SPI flash chip, OR a request to retransmit the last PDU from the beginning. This patch implementation does not process the retransmittion request command yet, in case a packet is dropped flashrom would need to be re-run. This is a pretty rare condition, but if deemed necessary support can be added later. H1 SPI controller supports multibuffer transactions where the CS signal is kept asserted while the controller clocks the bus when the next portion of data to write becomes available or there is more room to read data to send back to the host. This allows to support arbitrary length read and write transactions. There is no need to support write transactions longer than 256 bytes of data, as this is a typical SPI flash chip page size. For read direction the size of 2040 was chosen, which is close to 2K and takes full payload of 34 USB packets on top of 2 byte headers. The protocol state machine on the device sideOB can be in one of two states, IDLE or WRITING. Many of host requests do not require the device to change state: configuration requests, or writes of short blocks of data (fitting into one USB packet) can be executed immediately. Requests to read long blocks of data can still be executed without leaving the IDLE state, the device starts the SPI transaction and then iterates reading one packet worth of data at a time and sends it back to the host. Once the entire PDU is read, the CS is deasserted. In case the host requests to write a block of data which does not fit into a USB packet the device asserts the CS, sends the first received block to the SPI flash chip and then enters the WRITING state, expecting the controller to send the rest of the PDU in following packets. Once the entire PDU is transferred the CS is deasserted and state is changed back to IDLE. BUG=b:79492818 TEST=performed numerous flash read/write operations with 16M SPI flash chip on the Atlas device. Timing results comparison of various operations: Raiden V1 Raiden V2 Reading entire chip: 3m 16s 0m 52s Vanilla writing of new image: 16m 22s 5m 48s Writing of AP firmware into an erased flash chip (no read before or after writing) 4m 12s 1m 38s Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I374f3caab7146fc84b62274e9e713430d7d31de0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977965 Reviewed-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 049538cb663e8d8f1f9fbeed94f7b823e0eafabe) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078207 Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* tpm_mode: make available to all boards and restore on resetsVadim Bendebury2021-08-064-41/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the restriction of TPM_MODE vendor command, allowing any board's AP to disable TPM mode if required. In addition, TPM reset processing flow is being modified to always reboot the H1 in case TPM reset happens when TPM is disabled. BUG=b:191180387, b:191180208 TEST=on an Atlas device: localhost ~ # gsctool -a -f start target running protocol version 6 keyids: RO 0xaa66150f, RW 0x334f70df offsets: backup RO at 0, backup RW at 0x4000 Current versions: RO 0.0.11 RW 0.6.30 $ localhost ~ # gsctool -a -m disable TPM Mode: disabled (2) localhost ~ # gsctool -a -f start [WARNING:bus.cc(638)] Bus::SendWithReplyAndBlock took 1516ms to... Problems reading from TPM, got 10 bytes Failed to start transfer localhost ~ # reboot -- GSC reboots during device rebnoot localhost ~ # gsctool -a -f start target running protocol version 6 keyids: RO 0xaa66150f, RW 0x334f70df offsets: backup RO at 0, backup RW at 0x4000 Current versions: RO 0.0.11 RW 0.6.30 localhost ~ # reboot -- GSC does NOT reboot during device rebnoot Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I492bd2f201f3c5c7d1cd9b228ec6ab1cdcf8fa53 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987913 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit 8afa696aa05a02ee6a4015533a011a6b82716f05) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078206 Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* cr50: change OWNERS to cr50 team membersMary Ruthven2021-07-302-7/+6
| | | | | | | | | | | | | | | | | | | | | Change the OWNERS to cr50 team members and remove OWNERS files from all subdirectories. BUG=none BRANCH=none TEST=none Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 420abd92d8a437cde30115405a3fa883c7a7bccd) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059342 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit ec417486538167fcdb015191d91f987499037953) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060557 Commit-Queue: Randall Spangler <rspangler@chromium.org>
* cr50: prepare to release 0.{5,6}.40Mary Ruthven2021-07-082-2/+2
| | | | | | | | | | | | | | | | | | | BUG=b:192269002 TEST=none Change-Id: Ied092d9dd0a909aae116f440fa545ee43ec4c6ed Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3002844 Reviewed-by: Andrey Pronin <apronin@chromium.org> Commit-Queue: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 6c476e94fabae0c950a51a65264d8bab20ff2907) Change-Id: Ie4eac2854a902b8101858c783ca569baa58f5253 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004087 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* g: spi_controller: add the subtransaction capabilityVadim Bendebury2021-07-082-13/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is necessary to be able to send SPI transactions with sizes exceeding the SPI controller buffer size. This can be achieved by asserting CS before sending the first batch (data block) in a transaction and deasserting CS after the last batch. Let's add a SPI controller spi_sub_transaction() API, with an additional parameter indicating when the last batch is submitted for processing. The existing spi_transaction() API becomes a wrapper which always calls spi_sub_transaction() to send a full single batch transaction. BUG=b:79492818 TEST='flashrom --flash-name' still succeeds. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ia0c5114edd5caf6c6d0e22cab3bfa3c4d86ac79a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977964 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit e2655cb43fdc938d467018ccd5c3df9fb907c400) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004086 Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* cr50: switch SPI CS to GPIO modeVadim Bendebury2021-07-083-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be able to send and receive multiple SPI buffer quantities in a single SPI transaction it is necessary to control the SPI CS signal directly, as opposed to connecting it to the SPI controller. Direct mode allows to keep CS asserted as long as necessary to transfer the full data blob, size of which might exceed the the size of the SPI controller buffer. BUG=b:79492818 TEST=flashrom access still works fine: $ flashrom -p raiden_debug_spi:target=ap --flash-name flashrom f10dff7b-dirty on Linux 5.4.0-71-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Raiden target: 2 Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, SPI) on... vendor="GigaDevice" name="GD25Q127C/GD25Q128C" Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Idecf019d3fd19675d7f78e4dc1140106a2112c6b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973580 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit c6095192742c9f59f72a6178ece5a2dd8cea4e43) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004085 Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* usb_spi: prevent potential loss of upstream trafficVadim Bendebury2021-07-081-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code placing data on the upstream usb_spi queue does not check if there is enough room on the queue, which could result in silent dropping of data when the upstream queue is busy. This is not a big deal with Raiden protocol V1 where USB packets to the host are sent one at a time, but becomes a problem if the DUT sends multiple USB packets without waiting for the host. Adding a sleep in the loop waiting for the room in the queue to free up seems an appropriate solution, since the AP is held in reset at this point and there is no much activity happening on Cr50. Experiments have shown that with 2KB PDU size the total wait time while reading a 16M flash does not exceed 30 ms when this fix is deployed. BUG=b:79492818 TEST=with the rest of the patches applied observed successful flashrom operations running Raiden protocol version V2. Without this patch there were periodic drops of data sent by DUT. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I73fdfdda09837891dc1db2453098ec1d219c4553 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973573 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit a6e62a3020e1f6d53880d91760073c4f91a63bef) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004084 Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* ccd_config: remove UpdateNoTPMWipeMary Ruthven2021-07-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | UpdateNoTPMWipe did not do anything. Replace it with 'Unused' in the capabilities list. We can't completely remove the capability because of how cr50 uses the cap_info list. Every item from 0 to CCD_CAP_COUNT needs to have a name and a default value. Renaming it makes it clear the capability isn't used and keeps the relationship between capabilities and their value in the capabilities bitmask. BUG=b:182482706 TEST=none Change-Id: Ie1e6674f414789ae52508b89e6f95d0a122cbd6f Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2970990 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 90120a2e36936e9e857ee84e799657d5e54b7ba0) Change-Id: If7cb58a2e973726aafdaa64e5d857c6a4c4e904d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004083 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* ap_ro_integrity_check: handle invalid hash responses the same wayMary Ruthven2021-07-081-2/+0
| | | | | | | | | | | | | | | | Process FLASH_READ_FAILED the same as the rest of the errors. Put the actual code in response and return INTERNAL_ERROR. BUG=none TEST=none Change-Id: Iacbdc2db01c54da57cac28ccbdfd3210be95dc62 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954320 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 4547342e44b9e3e61dd9f52e532d831599e61ba9) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004082 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* ap_ro_integrity_check: Add vendor command to check statusMary Ruthven2021-07-087-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP RO verification has four outcomes. Shimless RMA needs to be able to check the status. This change adds a vendor command to check the AP RO verification status NOT_TRIGGERED: The last AP reboot was not triggered by RO verification key combination. PASS: The last AP reboot was triggered by RO verification key combination, and the verification passes FAIL: The last AP reboot was triggered by RO verification key combination, and it fails. In reality, the device should brick and the system will not see this response. UNSUPPORTED: The last AP reboot was triggered by RO verification key combination, but there is no data to perform it or the board doesn't support it. BUG=b:182594555 TEST=manual # Erase board id # Erase AP RO hash cr50 > ap_ro_info erase # Check status AP RO status = 3: unsupported # Set gbb flags /usr/share/vboot/bin/set_gbb_flags.sh 0x140 # Set AP RO hash ./util/ap_ro_hash.py -v True GBB # Check status AP RO status = 0: not run # Trigger verification # Check status AP RO status = 1: pass # Change gbb flags /usr/share/vboot/bin/set_gbb_flags.sh 0xa39 # Trigger verification # Check status AP RO status = 2: FAIL # Set board id to DUKI:0x10 # Check status AP RO status = 3: unsupported Change-Id: I354ccd6317cd36008a66ffd93afb3ee95f3c3561 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2950314 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 49a02d634caaa5db07653f1669ff9ae35268116d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004081 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* ap_ro_integrity_check: skip verify based on RLZMary Ruthven2021-07-084-3/+84
| | | | | | | | | | | | | | | | | | | | | | Some factories programmed hashes into devices that don't support reading from AP flash while EC_RST_L is asserted. Skip AP RO verification on these devices if the RLZ is blocked. BUG=b:185783841 TEST=manual Set board id to YVRQ:0x10 Verify AP RO verification can be triggered Set board id to VYRC:0x10 Verify AP RO verification is skipped even if the hash is stored. Change-Id: I7ef5ceafd55ae5e90b4a754d1e92317a9a745ef9 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2950313 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit b231b059c0947522e4a0c9815eab1a5c2601718f) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004080 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* ap_ro_integrity_check: unify ap ro hash checksMary Ruthven2021-07-082-25/+43
| | | | | | | | | | | | | | | Use one method to verify the AP RO hash is valid. BUG=b:182594555,b:185783841 TEST=run ap ro check on hatch Change-Id: I4a45e423180ee8494cefe1ca35685676b910efdf Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2950312 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 3e2b82328c52ea8f5f8f226997249b680bd527a8) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004079 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* brdprop: print tpm-board-cfgMary Ruthven2021-07-081-1/+1
| | | | | | | | | | | | | | BUG=b:186446598 TEST=none Change-Id: I0192cd85904fe162c38bbedd5321187bc24be8d9 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2970991 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit e89767b3bdea0c9dcbc1563fd9bf6c491e73b107) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004078 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: support EC-EFS 2.1Namyoon Woo2021-07-088-46/+341
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the codes that support EC-EFS 2.1. However, it is not enabled. EC-EFS 2.0 is still enabled as default. BUG=b:187953899 TEST=built cr50 image, and ran it on hatch with CONFIG_EC_EFS2_VERSION defined as 0 and 1 respectively. For both cases, CrOS booted good. Also checked CrOS recovery was done good with corrupted TPM secdata, and booted good at the end. > ec_comm corrupt > ecrst pulse Ran the unittest for both version as well. $ make run-ec_comm $ make run-ec_comm21 Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I7623fa56dd44a01002628685826105afe76e034f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2891925 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit 5fdf0294794606773b2403b708e3947a45e7b666) Change-Id: I03a337eeeab753ac5d9129e9d886723956243844 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3010312 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* add reserved `VIRTUAL_NV_INDEX_RMA_BYTES` in comment.Leo Lai2021-07-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | The index is added to cr50 repository while the usage is only for generic TPM2.0 case. In the future we don't want GSC to re-use the index number. BUG=b:187821960 BUG=b:191163997 TEST=make buildall -j Signed-off-by: cylai@chromium.org Change-Id: I6cfb12cf4558dd0bf2c99e045ef6e0b89698bbc7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2892151 Tested-by: Leo Lai <cylai@google.com> Commit-Queue: Andrey Pronin <apronin@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 98e4da99997a020f8aba11b2cfc7edaf67376677) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004077 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* ap_ro_integrity_check: allow setting hash in DBG imagesMary Ruthven2021-07-081-0/+2
| | | | | | | | | | | | | | | | | | | It's difficult to erase the board id. Skip the board id check for setting the hash with a DBG image. These images are only used by developers. BUG=none TEST=ap_ro_hash.py -v True GBB with and without the board id set with a DBG image. Change-Id: I3cb56323aac5d32c3552e91db8f05724ba04fe94 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2950311 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit b529376c7bc36d9627d0e1992fa470be76014674) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004076 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* hmac_drbg: increase output sizeMary Ruthven2021-07-081-1/+1
| | | | | | | | | | | | | | | | | Increase the size of the hmac output buffer to 512, so it's big enough to support the lab responses. BUG=b:189376694 TEST=drbg_test.py Change-Id: Id5ff4024079241d36a33f1c36f322a27c4b929d7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923240 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit ac722759f58c5a4956a9cdaaa206de1d8808e1d2) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004075 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* make: fix awk complaintVadim Bendebury2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | It has not always been like that but recently the following message started showing up on the console when building Cr50 image with CR50_DEV and H1_DEVID variables defined: awk: cmd. line:1: warning: regexp escape sequence "' is not a ... This patch fixes the problem. BUG=none TEST=running 'CR50_DEV=1 H1_DEVIDS="0 1" make BOARD=cr50 -j' succeeds and does not generate the above error message any more. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I3a34e1dc5dc3ca58928bfeac32df1ac7e1aa3c4c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931956 Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit 1458cfd6338e362dd0d95ace52fc7d0632a62ae3) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004074 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* cr50: move trng.c under CONFIG_DCRYPTO control in chip/g/build.mkVadim Sukhomlinov2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to dcrypto code refactoring as independent build unit for Cr50 U2F FIPS certifcation, need to enable disabling the use of crypto provided by chip/g/dcrypto and chip/g/trng.c. While use of chip/g/dcrypto is controlled by CONFIG_DCRYPTO, chip/g/trng.c is always linked in. Since all chip/g boards (cr50, cr52*, cr53*) enable CONFIG_DCRYPTO, and logically trng is cryptographic unit, move it under CONFIG_DCRYPTO control. BUG=b:134594373 TEST=make buildall -j Change-Id: I7be47abfe961c4a216a56e15c88254b60da10005 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2937383 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> (cherry picked from commit fa9bfd03289ff40dec869eb3f16f74937bb91cbd) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004073 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* host: fixing make runtestsVadim Sukhomlinov2021-07-084-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Changes in compiler resulted in multiple warnings treated as errors, failing host test builds. Addresing warnings by checking return values. BUG=none TEST=make runtests Change-Id: Idb2686370bf041791099b3e332ff25173338e994 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2936000 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org> (cherry picked from commit 47e7451821083879349df71d1c3a3d0f6c30979f) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004072 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* CRYPTO_TEST: open ccdMary Ruthven2021-07-081-1/+1
| | | | | | | | | | | | | | | | | CRYPTO_TEST images don't need to have restricted CCD. Open CCD for crypto test images like we do for DBG images. BUG=none TEST=ccd is automatically open in crypto test images Change-Id: I674ef9055e1a87caf9f8b2b28f9893e79ed9e7e5 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2916576 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit d06a3ef222f36d6c0e09cec7206d6b8ab6bebf80) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004071 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* H1_RED_BOARD: force rddkeepaliveMary Ruthven2021-07-081-0/+4
| | | | | | | | | | | | | | | | | Enable rddkeepalive on red boards, so nothing needs to be done to enable ccd. BUG=none TEST=build red board image. Make sure ccd is automatically enabled. Change-Id: If629ead1307d8d12cd36678bae792f1109a0839c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2916575 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 6460246a9a587b084582f092a0ebf96cfd1aaa56) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004070 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: debounce successive TPM reset pulses (take two)Mary Ruthven2021-07-081-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms generate more than one pulse when resetting, many Intel SOCs generate two pulses, some other chips could go even higher. TPM reset on Cr50 is processed asynchronously, repetitive pulses result in multiple reset processing cycles.In case pulses are coming too soon one after another this could cause some race conditions. Let's ignore repetitive reset pulses unless there has been an attempt by the host to read a register (which is usually the very first action of the AP when booting up). Clear reset_in_progress when the TPM is stopped to ensure they aren't set at the same time. TPM stop disables tpm communication until the TPM is reset. reset_in_progress blocks resetting the tpm until there's tpm communication. We need to ensure these aren't both set at the same time otherwise the system will get into a state where it rejects tpm resets and tpm communication forever. This fixes the ccd open issue from take one where the tpm would stay disabled after opening ccd because cr50 rejected the tpm resets that would clear if_stop. BUG=b:164130916 TEST=observed that only one reset is happening on an Octopus device, while there are two pulses present on the PLT_RST_L line. Verified proper reboot multiple times in a row. use rma_auth to open ccd. Verify subsequent tpm resets reset the TPM and don't say reset already in progress. Change-Id: I62717bf3f0e9bc6d9090122e5b15d13c8f4825e5 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2832434 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit f42ae66a8149e367f963db17e371122d4546bed4) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004069 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* CRYPTO_TEST_SETUP: enable dev featuresMary Ruthven2021-07-082-1/+4
| | | | | | | | | | | | | | | | | | | | Enable dev features in CRYPTO_TEST builds, so it's easier to update and rollback to MP images. Add the rollback command and disable update checks. BUG=b:186663661 TEST=make clobber ; make -j BOARD=cr50 make clobber ; make -j BOARD=cr50 CRYPTO_TEST=1 Change-Id: Id8929f67f206d3222c551532c91921bd646d2a50 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2875480 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit afdc6bf6cefd4afa83b68967d34a512ac02f6544) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004068 Reviewed-by: Andrey Pronin <apronin@chromium.org>
View Lorry Controller Status