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* mt_scp: Generate IPI tables with util gen_ipi_table.Yilun Lin2019-04-305-25/+78
| | | | | | | | | | | | | | | | | | | | IPI table is board-specific. This CL removes the original IPI table in chip layer, and uses gen_ipi_table to generate the table for each board to reduce the maintenance effort. TEST=make BOARD=kukui_scp, and see build/kukui_scp/ipi_table_gen.inc exists. Push to Kukui, and see SCP boots. TEST=modify IPI_COUNT in board.h and see it generates a new ipi_table_gen.inc BUG=b:130508869 BRANCH=None Change-Id: I0c05319447d15917e8833aa80d61166c4e396370 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1568890 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Flapjack: Disable charging from BC 1.2 charger as USB-C chargerDaisuke Nojiri2019-04-303-1/+10
| | | | | | | | | | | | | | | | | | | | | Currently, if a charger shows Rp=USB on USB-C port, the charge manager chooses it and sets the max current to 500 mA even if it can provide higher power as a BC 1.2 charger. This patch introduces CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF. When it's defined, a BC 1.2 charger won't be recognized as a USB-C charger. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/131353444 BRANCH=none TEST=Charge Flapjack from BC 1.2 charger on USB-C port. Change-Id: I50969973026185dd2aecdb768985cd116c1d32f7 Reviewed-on: https://chromium-review.googlesource.com/1586580 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Flapjack: Turn off LED when brightness == 0Daisuke Nojiri2019-04-301-7/+16
| | | | | | | | | | | | | | | | | | | | | | Currently, when the brightness passed to led_set_brightness is zero, the current is set to 4mA and the pwm duty is set to the brightness. Since duty == 0 means 1/32 (instead of 0/32), this doesn't turn off the LED. This patch makes the current explicitly set to 0mA if the brightness is zero. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/131205169 BRANCH=none TEST=buildall Change-Id: I7f581349713d30f10acb3797ab08b15aa2d50f00 Reviewed-on: https://chromium-review.googlesource.com/1584351 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org>
* Revert "CQ: disable broken cheza pre-cq"Eric Caruso2019-04-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c7ff23fb5e7057dfda351de004e70b862127a1d0. Reason for revert: upstream fix[1] is in ToT [1]https://chromium.googlesource.com/chromiumos/third_party/libqmi/+/a09764425d471c1b5c6c473af55252f4125972c4 Original change's description: > CQ: disable broken cheza pre-cq > > cheza is broken in ToT, removing it from the mandatory pre-CQ configs > for the EC until it's working again. > > BRANCH=None > BUG=chromium:957280 > TEST=None > > Change-Id: I7276ee1a5e7e903d0d0343b3a8b59d88df6ef791 > Signed-off-by: Nicolas Norvez <norvez@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1586732 > Reviewed-by: Mathew King <mathewk@chromium.org> > Reviewed-by: Jason Clinton <jclinton@chromium.org> > Reviewed-by: Sean Abraham <seanabraham@chromium.org> > Tested-by: Nicolas Boichat <drinkcat@chromium.org> Bug: chromium:957280 Change-Id: Ib51b50320ea46bea717446b47bb0a78881b59ad6 Reviewed-on: https://chromium-review.googlesource.com/1588296 Commit-Ready: Eric Caruso <ejcaruso@chromium.org> Tested-by: Eric Caruso <ejcaruso@chromium.org> Reviewed-by: Eric Caruso <ejcaruso@chromium.org> Reviewed-by: Sean Abraham <seanabraham@chromium.org>
* Flapjack: Fix bit size for LCM_IDDaisuke Nojiri2019-04-292-1/+2
| | | | | | | | | | | | | | | | | | LCM_ID's bit size is 4. Thus, PANEL_UNINITIALIZED should be 0xf. This fixes 'bitwise comparison always evaluates to false' error. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Cq-Depend: chromium:1586582 BUG=none BRANCH=none TEST=make BOARD=flapjack Change-Id: Ib9c43cb7b929f902cdced627e1d40669ae365775 Reviewed-on: https://chromium-review.googlesource.com/1585398 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Reland "flapjack: do not carry LCM_ID with old board"Daisuke Nojiri2019-04-292-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b9bf62a7aea6e71e3faec26894e9f75c3d435afa. Reason for revert: <INSERT REASONING HERE> Original change's description: > Revert "flapjack: do not carry LCM_ID with old board" > > This reverts commit 6549da39d519b4d07e8bca7bef0393549765412b. > > Reason for revert: this breaks building (run make buildall -j) > > Original change's description: > > flapjack: do not carry LCM_ID with old board > > > > With older boards there is no need to carry LCM_ID in SKU_ID > > since it's not available. In this way it can be compatible with > > the sku_id defined for older boards. > > > > BUG=b:129569858 > > TEST=build and verify the sku_id on older board. > > BRANCH=None > > > > Change-Id: I68d8c380660eed7633b9c38a21ccd5c6ca536587 > > Signed-off-by: YH Lin <yueherngl@chromium.org> > > Reviewed-on: https://chromium-review.googlesource.com/1584381 > > Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> > > Bug: b:129569858 > Change-Id: Iefd5df18f786dc4d3fb720c18545e9109cc54e0a > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1586185 > Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> > Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> > Tested-by: Mathew King <mathewk@chromium.org> Cq-Depend: chromium:1585398 Bug: b:129569858 Change-Id: Ic76e01ca07f32623c0de9f64f31e77cb331df5bf Reviewed-on: https://chromium-review.googlesource.com/1586582 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/(mec1322|mchp): Drop math expressions in MEMORY ORIGIN/LENGTHNicolas Boichat2019-04-292-4/+18
| | | | | | | | | | | | | | | | | binutils/ld 2.32 does not allow expressions in MEMORY regions (for some reason 2.31.1 was fine with that). Replace the expression with a constant, and add 2 assertions to check that the values are sane. BRANCH=none BUG=chromium:957361 TEST=make buildall -j with latest coreboot-sdk, no error Change-Id: I679f1a0ff24e96f215a52cdd6f2cde8540901b8e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1587256 Reviewed-by: Sean Abraham <seanabraham@chromium.org>
* CQ: disable broken cheza pre-cqNicolas Norvez2019-04-281-2/+1
| | | | | | | | | | | | | | | | | cheza is broken in ToT, removing it from the mandatory pre-CQ configs for the EC until it's working again. BRANCH=None BUG=chromium:957280 TEST=None Change-Id: I7276ee1a5e7e903d0d0343b3a8b59d88df6ef791 Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1586732 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jason Clinton <jclinton@chromium.org> Reviewed-by: Sean Abraham <seanabraham@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org>
* driver: bmi160: Check enable_fifo flags before processing FIFOGwendal Grignou2019-04-271-13/+13
| | | | | | | | | | | | | | | | | | | | If there is an interrupt pending after we suspend the BMI160, we will try to collect length from the FIFO, but the FIFO is suspended. Bring back enable_fifo flags check before processing the FIFO. It has been move after gathering the length in CL:1128555 BUG=b:127321764,b:131272795 BRANCH=master TEST=Using flip_flop.sh script at b/131272795#comment2 Check the messages "unexpected empty FIFO" disappear. Change-Id: Iaab1a7f3607b902acd92b75c926365d7eb09fd5e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1585420 Reviewed-by: Enrico Granata <egranata@chromium.org> (cherry picked from commit d17cd2add14f1f1e32bd58d51d60a2c93f17f055) Reviewed-on: https://chromium-review.googlesource.com/1585471
* npcx: disable the selection of JTAG0 signals due to strapCHLin2019-04-2710-196/+271
| | | | | | | | | | | | | | | | | | | | | | | | It was observed that pressing recovery key combination + the other keys, some keys on the keyboard become invalid after system reboots. (see b:129908668 for more detail.) It is because the hardware strap pin for JTAG0 signals is unintentionally triggered. This CL reverts the selection of JTAG signals and set them back to keyboard scan function at system initialization. The revert applies to all real platforms except npcx_evbs. BRANCH=none BUG=b:129908668 TEST=pass "make buildall" TEST=Press the specific key combination, after the system reboots, the keyboard function works normally. On npcx EVBs, the JTAG0 is still functional. Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1575887 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* motion sense: Calculate loop time based on sensor needsMathew King2019-04-278-90/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the motion sense loop bases its sleep time based on the fastest active sensor. This method has several flaws: 1. It does not take into account any task switching overhead 2. With a mix of interrupt driven and forced sensors the sleep time gets recalculated every time there is an interrupt causing the loop to oversleep 3. If multiple sensors do not have rates that are in sync the timing of the slower sensor will be off. For example if there was a sensor running at 50 Hz and one running at 20 Hz the slower sensor would end up being sampled at about 16 Hz instead of 20 Hz This change calculates an ideal read time for every forced mode sensor and calculates the sleep time based on the nearest read time. Every time a sensor is read the next read time is calculated based on the ideal read time not the actual read time so that reading does not drift because of system load or other overhead. BUG=b:129159505 TEST=Ran sensor CTS tests on arcada, without this change the magnetometer was failing 50 Hz tests at about 38 Hz with 30% jitter with this change in place 50 Hz was spot on with about 10% jitter BRANCH=none Change-Id: Ia4fccb083713b490518d45e7398eb3be3b957eae Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1574786 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ccd: delay sleep while opening ccdMary Ruthven2019-04-273-16/+26
| | | | | | | | | | | | | | | | | Cr50 may enter deep sleep while wiping the TPM. This change adds a sleep delay before opening ccd. BUG=b:130646257 BRANCH=cr50 TEST=manual dut-control cold_reset:on run ccd open make sure ccd is open even after entering deep sleep Change-Id: Id44b608702b664621bd2441f62a03ba6428135cf Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1585606 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* Revert "flapjack: do not carry LCM_ID with old board"Jack Rosenthal2019-04-262-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6549da39d519b4d07e8bca7bef0393549765412b. Reason for revert: this breaks building (run make buildall -j) Original change's description: > flapjack: do not carry LCM_ID with old board > > With older boards there is no need to carry LCM_ID in SKU_ID > since it's not available. In this way it can be compatible with > the sku_id defined for older boards. > > BUG=b:129569858 > TEST=build and verify the sku_id on older board. > BRANCH=None > > Change-Id: I68d8c380660eed7633b9c38a21ccd5c6ca536587 > Signed-off-by: YH Lin <yueherngl@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/1584381 > Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Bug: b:129569858 Change-Id: Iefd5df18f786dc4d3fb720c18545e9109cc54e0a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1586185 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Mathew King <mathewk@chromium.org>
* Revert "kukui: scp: calibrate ULPOSC1&2"Yilun Lin2019-04-262-183/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e08a71fd05bfc9e32dd64b7e15840e7232d72788. Reason for revert: SCP will hang with this CL. Original change's description: > kukui: scp: calibrate ULPOSC1&2 > > ULPOSC generates clock for SCP core and peripherals. The calibration > process adjust 2 values, div and cali. Both values are positive > correlated to OSC frequency. The frequency function is: > f(div, cali) = k1 * (div + k2) / R(cali) * C > Where: > R(cali) = k3 / (1 + k4 * (cali - k4)) > > The actual frequency is not linear to cali parameter. This change > selects the div that generates closest frequency when cali == 32. And > then adjust cali to get better output. > > BRANCH=none > BUG=b:120176040,b:120169529 > TEST=manual > check SCP console command: > > ulposc > ULPOSC1 frequency: 248 MHz > ULPOSC2 frequency: 330 MHz > > Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 > Signed-off-by: Rong Chang <rongchang@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/1520571 > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Bug: b:120176040, b:120169529, b:131273034 Change-Id: Ifaeb9a7835a35556587fac4c039b9fde6d66504d Reviewed-on: https://chromium-review.googlesource.com/1583481 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* ish: cleanup of UART-related functionalityJack Rosenthal2019-04-262-196/+164
| | | | | | | | | | | | | | | | | | | This commit cleans up UART-related ISH code: * Moving REG{8,16,32} macro usages into header files * Changing ifdef logic in code to use IS_ENABLED macro * Reduce repeated code in uart_defs.h * Change hexadecimal masks in uart_defs.h to use BIT(n) macros * Change disabling of UART2 to use common logic in uart_stop_hw BUG=b:130573158 BRANCH=none TEST=UART on arcada_ish is functioning as normal Change-Id: Ia05feea2de8c14e44e4d3f9dd7c790bcb81cd1c0 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1582457 Reviewed-by: Jett Rink <jettrink@chromium.org>
* atlas: let AP fully control display backlightCaveh Jalali2019-04-263-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | this change removes the EC from the display backlight control logic. previously, the EC would enable/disable the backlight master enable directly based on the lid switch. this turns out to be redundant and in some cases causes timing violations between backlight enable and the backlight PWM signal. the AP already controls the display power load switch (EN_PP3300_DX_EDP), so when the AP is off, display power (including the backlight) is also off. in addition, the AP correctly controls the backlight using PCH_EDP_BKLTEN. with this change, we're only removing the EC's master kill switch for the backlight. BRANCH=none BUG=b:129651119,b:128625720 TEST=verified no ill effects on atlas. EE scoped PWM vs. BL enable. Change-Id: Ibef9062ce66dfec1363626e674f144a1a3d55b5e Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1566482 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit e3c9e42a6475121e07fc5b9372e24af847fecf4b) Reviewed-on: https://chromium-review.googlesource.com/1585134 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* cr50: update version to .16Mary Ruthven2019-04-262-2/+2
| | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I873b50ebd73c0edd16c278b1fa825378e693d18d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1584589 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* hatch: Configure EC_INT pin as open-drainPhilip Chen2019-04-262-23/+1
| | | | | | | | | | | | | | | | | Without this change, during POR, PP3300_A/PP1800_A rises and then temporarily stays in a wrong voltage level before eventually reaching 3.3V/1.8V. BUG=b:129306003 BRANCH=None TEST=see PP3300_A step correctly during POR Change-Id: If5facf5b413d5936abe5a24785f408c7b112a2fa Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1564495 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ish: fix s/w generated interrupt requestHyungwoo Yang2019-04-267-132/+179
| | | | | | | | | | | | | | | | | Current s/w generated IRQ uses LAPIC's ICR but it causes pending interrupts for other IRQs in IOAPIC and leads LVT error with illegal vector. So instead of using ICR, we use "int" instruction. BRANCH=none BUG=b:129937881,b:124128140 TEST=Tested on Arcada platform Change-Id: I49c4120e7355f9a98d20d5ed259c4fdf6bad5196 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1568786 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* flapjack: do not carry LCM_ID with old boardYH Lin2019-04-262-7/+6
| | | | | | | | | | | | | | | With older boards there is no need to carry LCM_ID in SKU_ID since it's not available. In this way it can be compatible with the sku_id defined for older boards. BUG=b:129569858 TEST=build and verify the sku_id on older board. BRANCH=None Change-Id: I68d8c380660eed7633b9c38a21ccd5c6ca536587 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1584381 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* driver: TCPM: nct38xx: add support for NCT38XX series chipsCHLin2019-04-264-7/+378
| | | | | | | | | | | | | | | | | | | | This commit adds the driver to support for Nuvoton TCPC NCT38XX series chips. BRANCH=none BUG=none TEST=No error for "make buildall" TEST=Apply this and related CLs.Test on a reworked yorp platform with NCTT38XX AIC card. PD Functions including source, sink, and ALT DP mode work fine. Change-Id: Ibd4d3faf29afa55b150971e2aef2587686f523d5 Signed-off-by: Amit Maoz <Amit.Maoz@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1436658 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* flash_fp_mcu: use modalias to detect FP spiidTom Hughes2019-04-264-14/+28
| | | | | | | | | | | | | | | | | | During bringup there was a point where the spiid for the fingerprint sensor changed between devices (apparently due to broken TPM firmware since the TPM is usually the first SPI device)). This resulted in non-obvious failures when running flash_fp_mcu since many other things were also not working. BRANCH=none BUG=chromium:955117 TEST=emerge-nocturne ec-utils-test && cros deploy nocturne ec-utils-test flash_fp_mcu /opt/google/biod/fw/nocturne_fp_v2.2.110-b936c0a3c.bin Change-Id: I9161361e2c66de200f618c00074eeb42a9ecb29b Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1566653 Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* chip/g: prevent USB read queue overflowNamyoon Woo2019-04-263-2/+8
| | | | | | | | | | | | | | | | | | | | CR50 should check whether USB RX queue has enough space for host data. If not, it schedules to retry it in another deferred call. BUG=b:130908211 BRANCH=cr50 TEST=manually ran "echo 'help' > /dev/ttyUSB0" more than 30 times. Without this CL, it used to break cr50 console input, and it worked as if it is 'read-only'. After applying this CL, cr50 console input works normal even after excessive input stream. Change-Id: Ieace84b51c31800b52d2c4a9334e6ffe7888e592 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576326 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* uartupdatetool: retry opr_check_sync() if the first attept failsNamyoon Woo2019-04-261-0/+8
| | | | | | | | | | | | | | | | This is a workaround fix for grunt, where the first command after EC reset gets zero bytes as response. BUG=b:126795953 BRANCH=none TEST=manually ran flash_ec on grunt/careena, grunt/liara and octopus/fleex through servo_v4_with_ccd_cr50 or suzy-Qable. Change-Id: I5da3bd7889d9e4059a8f523352db4f3e5a7ce841 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1583128 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* makefile: fix image stats reporting problemsVadim Bendebury2019-04-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | Recently merged patch (34cc1f91c) introduced printing of free space stats for both RO and RW images, without actually describing which image the message applies to. This change adds this additional description. BRANCH=none BUG=none TEST=built a cr50 image: $ make BOARD=cr50 -j ... *** 8148 bytes in flash ... still available on cr50 RO **** *** 8880 bytes in flash ... still available on cr50 RW **** Change-Id: Ib7d5890c94ea93906d8f6a7a7c95819c47ffab8a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1582456 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* charger: Add basic driver code for ISL9241Vijay Hiremath2019-04-264-1/+471
| | | | | | | | | | | | | | | | | | The ISL9241 is a digitally configurable buck-boost battery charger that can support both Narrow Voltage Direct Charging (NVDC) and Hybrid Power Buck Boost (HPBB/Bypass) charging and switch between the modes using firmware control. BUG=b:131123775 BRANCH=none TEST=Able to boot intelrvp with charger & battery is charging Change-Id: If0736136778cbe7650ed7f03d04f4e011eedd1f6 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1579241 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* thermistor: Add STEINHART-HART lookup table for NCP15WB473F03RCVijay Hiremath2019-04-263-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lookup table is based off of a resistor divider circuit on 3.0V with a 22.6K resistor in series with a thermistor with nominal value of 47K (at 25C) and a B (25/100) value of 4050. Calculation: 1. Get the thermistor resistance for a given temperature from the datasheet. 2. Calculate the ADC input voltage. Vout = (Vdd * Rt) / (Rt + Rs) Where: Vdd - Source voltage (Constant) Vout - ADC value read on STEINHART-HART voltage divider circuit Rt - Resistance of thermistor at given temperature Rs - Series resistance value (constant) 3. Form a STEINHART-HART lookup table for 0 to 100 deg C 4. Add a scaling factor so that the STEINHART-HART lookup table data is 1-byte per pair. BUG=b:131060744 BRANCH=none TEST=Manually tested on ICLRVP, able to read correct temperature Change-Id: Ib0e7b1ab6d6d4c5bcb14ff4ab0e830881e9864e6 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1577741 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* util: Add tool to generate cros_ec_commands.hGwendal Grignou2019-04-264-4/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a rule to generate a new cros_ec_commands.h when ec_commands.h is modified. The rule is checked when buildall is invoked. At Presubmit stage, check a cros_ec_commands.h exists if ec_commands.h is modified. The CL author is responsible to upstream that file. BUG=chromium:945948 BRANCH=none Cq-Depend: chromium:1558853 TEST=Check manually cros_ec_commands.h is generated with make build_cros_ec_commands Check no bread crumbs are left-over when the rule fails. Check checkpatch triggers when it finds an invalid syntax in the output file. Check ../../repohooks/pre-upload.py returns a meaningful error when cros_ec_commands.h file is not present. Change-Id: Ibc8ed7165914d39b5f0bd41643932a8514768925 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1559380 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
* ec_commands: Move #ifdef to encompass more codeGwendal Grignou2019-04-261-1/+3
| | | | | | | | | | | | | | | To generate kernel ec_commands.h as lean as possible, include comments within #ifdef. BUG=chromium:945948 BRANCH=none TEST=compile Change-Id: I23e48aa68c456ac09e8418f80993e952043111f6 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1559379 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec_commands.h: Fix multi-line comments layoutGwendal Grignou2019-04-261-12/+17
| | | | | | | | | | | | | | | | | | | | checkpatch.pl found some comments that does not match the format: /* * line1 * line2 */ Fix some other minors errors in comments. BUG=chromium:945948 BRANCH=none TEST=Compile Change-Id: I34fddfc8db2a68431c114fd534278e80fa4b3b53 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1559378 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
* atlas: remove obsolete commentCaveh Jalali2019-04-251-1/+0
| | | | | | | | | | | | | | | | we're going to keep the ability to turn on the blue LED channel for testing the hardware, if nothing else. BUG=b:130447080 BRANCH=none TEST=no functional change Change-Id: Ibc30c0c39cbac4a539ea7fbd55d815f66d098a5a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570611 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: Support legacy U2F key handlesLouis Collard2019-04-252-5/+54
| | | | | | | | | | | | | | | | | | | | | | The new U2F functions make use of a new key derivation scheme. This adds a flag clients can specify that allows the new functions to also sign requests using a legacy key handle. This will allow continued support of legacy key handles in Chrome OS whilst allowing the legacy code to be removed from cr50. BUG=b:112603199, b:123161715 TEST=with new cr50 and u2fd patched to send new param: - register legacy key handle with Google - restart u2fd with user keys and no fallback - check login fails - restart u2fd with user keys and fallback - check login succeeds Signed-off-by: Louis Collard <louiscollard@chromium.org> Change-Id: Ib3164e9c0856d51b958fa8db181153b5b2227850 Reviewed-on: https://chromium-review.googlesource.com/1580622 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* kohaku: Make PP5000_A_PGOOD a power signal interruptScott Collyer2019-04-251-1/+1
| | | | | | | | | | | | | | | | | This signal is of the power signals, but it had been set as just a GPIO_INPPUT. This CL corrects and makes in a interrupt signal similar to the other power sequencing signals. BUG=b:129372306 BRANCH=none TEST=make -j BOARD=kohaku Change-Id: Icc2e35292ba397ae13c0dc3d578bb9ddb1c99035 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1579901 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* hatch: Make PP5000_A_PGOOD a power signal interruptScott Collyer2019-04-251-1/+1
| | | | | | | | | | | | | | | | | | This signal is of the power signals, but it had been set as just a GPIO_INPPUT. This CL corrects and makes in a interrupt signal similar to the other power sequencing signals. BUG=b:129372306 BRANCH=none TEST=Verify that Hatch system boots successfully. Change-Id: Id4434cbd41ad1cc8996f2759d5a0f5698e74918c Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1579900 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* board: arcada_ish: add lis2mdl magnetometerYuval Peress2019-04-242-5/+30
| | | | | | | | | | | | | | | | | | BRANCH=None BUG=b:128619310 TEST=Validated that iio:device4 is present TEST=Validate that cat **/iio:device4/in_magn_*_raw prints correct values TEST=Ran some CTS tests and verified magnetometer tests pass. TEST=Opened an android compass app and raw magnetometer reading app and verified that data is correct. Change-Id: I79ff5ba8de12686d61e7701ac83689924c4de6c4 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535428 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
* ish: refactor bit-mask constants to use BIT macroJack Rosenthal2019-04-245-97/+92
| | | | | | | | | | | | | | | We should be using the BIT(n) macro rather than (1 << n), as it prevents errors, and makes the intended purpose a little bit easier to read. BRANCH=none BUG=none TEST=make buildall -j Change-Id: Ia727ac2f8e5abfb852ba78d5cba19d7c8af72839 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1567688 Reviewed-by: Jett Rink <jettrink@chromium.org>
* minute-ia: hard reset if we panic while handling a panicJack Rosenthal2019-04-242-16/+28
| | | | | | | | | | | | | | | | | ish_pm_reset is a rather complex procedure, and encountering a panic while it is happening could lead to an infinte loop of handling panics. This will preform a reset of the Minute-IA core if a panic occurs and the system is already resetting from panic. BUG=b:130752748,b:130587334 BRANCH=none TEST=copied some invalid opcodes into switch_to_aontask procedure, observed the hard reset after forcing a panic Change-Id: I43459d78da9b67297f84e3a736d3f92da42a814c Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576835 Reviewed-by: Jett Rink <jettrink@chromium.org>
* minute-ia: remove divzero console commandJack Rosenthal2019-04-241-10/+0
| | | | | | | | | | | | | | I had forgotten to remove this from testing the panic handler. This is a duplicate command of "crash divzero" and should be removed. BUG=b:126691187 BRANCH=none TEST=divzero console command is gone on arcada Change-Id: Id37d3f3749bd4228045cca93a38315ee9c94b2e9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576837 Reviewed-by: Jett Rink <jettrink@chromium.org>
* util/stm32mon: Add cmdline option to display versionTom Hughes2019-04-242-2/+20
| | | | | | | | | | | | | | | | | | | Also display the version when running in order to make it easier to debug flashing issues in the field or factory. BRANCH=none BUG=chromium:952332 TEST=./util/flash_ec --board=hatch_fp --image=./build/hatch_fp/ec.bin => displays stm32mon version ./build/hatch_fp/util/stm32mon -v => displays version ./build/hatch_fp/util/stm32mon --version => displays version Change-Id: I43f622ed370938eeed31453d5b11806f02b47277 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1565462 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* grunt: Improve safe state when entering DP modeEdward Hill2019-04-241-31/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | When configuring DisplayPort alt mode, follow the spec more closely: Place the USB Type-C pins that are to be re-configured to DisplayPort Configuration into the Safe state before sending the configure command. Then switch the pins to DisplayPort after receiving the ack to the command. For TYPEC_MUX_DOCK, the superspeed signals can remain connected. For TYPEC_MUX_DP, disconnect the superspeed signals in svdm_dp_config, then re-configure the pins to DisplayPort in svdm_dp_post_config. This means we avoid an unnecessary disconnection in the TYPEC_MUX_DOCK case (CL:1553572) but still follow the spec and put the pins in safe state in the TYPEC_MUX_DP case. BUG=b:123310411 BRANCH=grunt TEST=External display works with both DOCK and DP pin modes. Change-Id: I7de990e7dae053d089027cdc62094e5f8cd5ec4b Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1575429 Tested-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* tests: make lighbar test easier to debugJett Rink2019-04-243-10/+15
| | | | | | | | | | | | | | | | | This test was failing and it is easier to comment out tests that are passing to debug. I needed to add a precondition so each test would pass on its own. I also needed to remove the static modifier to allow each test to be comment out. BRANCH=none BUG=none TEST=builds and passes Change-Id: Ib2a7c0948aee363e1552835222a9700225993e46 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570605 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-04-242-66/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 248 MHz ULPOSC2 frequency: 330 MHz Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520571 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* tasks: convert TASK_EVENT_CUSTOM macro to bitJett Rink2019-04-2423-58/+69
| | | | | | | | | | | | | | | | | | | | | We should ensure that all custom task definition are non-zero and fit with the globally defined events. Add compile time check and change semantics to specify bit number (instead of making all callers use the BIT macro). This also fixes an error with TASK_EVENT_PHY_TX_DONE for ITE being 0. The bug that made that happen hasn't landed on any firmware branches that use it though. BRANCH=none BUG=none TEST=builds Cq-Depend:chrome-internal:1178968,chrome-internal:1178952 Change-Id: I5e1d1312382d200280c548e9128e53f4eddd3e61 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570607 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* mkbp: take timestamp closer to hardware interruptJett Rink2019-04-249-33/+70
| | | | | | | | | | | | | | | | | We want to ensure that the timestamp we take for last mkbp is as close to the actual hardware interrupt from EC->AP. BRANCH=none BUG=b:129159505 TEST=passing CTS sensor run (except test 133 nullptr) with this change Change-Id: I94b214f021f0b63ff2883e5fe8e32acc83ce208f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1560390 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* rt946x: Allow board customize initialization parametersDaisuke Nojiri2019-04-232-17/+24
| | | | | | | | | | | | | | | | | Currently, initialization parameters are fixed. This patch allows a board to customize how the chip is initialized. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/80482240 BRANCH=none TEST=buildall Change-Id: I0be0547d73de4d3f37e80e763efaf7840fd678c2 Reviewed-on: https://chromium-review.googlesource.com/1553564 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* driver: lis2mdl: add standalone supportYuval Peress2019-04-233-22/+252
| | | | | | | | | | | | | | BRANCH=None BUG=b:128619310 TEST=Created new console commands to directly trigger init, read, and set_data_rate for the sensor. Manually verified behavior and register values from the magnetometer using ISH console. Change-Id: Ie162827f596056ee4cfd96be5c457e08708a9b9b Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1534339 Commit-Ready: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish/ish5: add console in use timeout mechanism in low power managmentstabilize-12121.BHu, Hebo2019-04-233-9/+62
| | | | | | | | | | | | | | | | | | | | | | | | on ISH, uart interrupt can only wakeup ISH from low power state via CTS pin, but most ISH platforms only have Rx and Tx pins, no CTS pin exposed, so, we need block ISH enter low power state for a while when console is in use. we have two default timeout values for this mechanism: 1: after ISH boot, have 15 seconds window can input console commands 2: refresh 60 seconds timeout for console use after each console input BUG=b:129246461 BRANCH=none TEST=verified on arcada platform Change-Id: Ic3bb33a7984e1bf55654403c76287617c8828daa Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1574375 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* mm8013: implement battery_serial_numberTing Shen2019-04-231-1/+2
| | | | | | | | | | | | | | | | Return ERROR_UNIMPLEMENTED causes "ectool battery" to fail. Need to return some dummy value. BUG=b:131034963 TEST=ectool battery BRANCH=None Change-Id: I66df131db3b532efd56afab87e97bb3def2fb01f Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1575350 Commit-Ready: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: move CPU clock selection to clock moduleRong Chang2019-04-232-2/+6
| | | | | | | | | | | | | | | | CPU clock management should be in clock module. BUG=b:120169529 BRANCH=none TEST=manual build and load on kukui, check SCP console command: > rw 0x405C4000 read 0x405c4000 = 0x00000803 Change-Id: Ic13e9a51cf682af33799b713849fd3a445e6cfdb Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538097 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: Set CPU clock to default before ULPOSC calibrationRong Chang2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | ULPOSC 1 & 2 calibration may fail if SCP CPU clock selection is configured to one of them. The SCP reset mechanism does not reset the clock selection. So before calibration, set CPU to default clock. BUG=b:125695639 BRANCH=none TEST=manual build and load on kukui, check remoteproc init correctly. check SCP uart console command 'ulposc', output non-zero clocks. Change-Id: I6807017808a663f8e80363dc0672748ab1957978 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538096 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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