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* Clear OWNERS for factory/firmware branchfirmware-gale-8281.BBrian Norris2021-09-102-10/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155174 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* npcx: add device id for npcx586g/npcx576gKevin K Wong2016-05-041-0/+4
| | | | | | | | | | | | BUG=none BRANCH=none TEST=version command shows the correct chip device id Change-Id: I312b343f97a99b3ff5ae7d6ec3606cff291b2b55 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/342130 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* board: rename it8380dev to it83xx_evbDino Li2016-05-037-1/+1
| | | | | | | | | | | | | | | | Unified board name for IT83-series. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST="make BOARD=it83xx_evb -j" and "make buildall -j" Change-Id: Ic96d0132fb31fcc8715d0dd810f8bd340035a640 Reviewed-on: https://chromium-review.googlesource.com/341843 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Shawn N <shawnn@chromium.org>
* apollolake: ignore PLTRST# from SOC unless RSMRST# is deassertedKevin K Wong2016-05-033-4/+25
| | | | | | | | | | | | | add optional chipset specific function to check if PLTRST# is valid BUG=chrome-os-partner:52656 BRANCH=none TEST=make buildall, able to boot to OS on amenia Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/341732 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Enable jittery clockBill Richardson2016-05-035-0/+71
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:52576 BRANCH=none TEST=make buildall; try on Cr50 I manually tested both highsec and highperf variants, as well as forcing the bootrom init to run. All the bank registers were loaded with meaningful values, and none of the SPI or USB functionality showed any problems. Change-Id: Ia91ba98ef4c667aec74195c4a7bbf72a5d1c8b2d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342030 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: fix issue in ecc parameter endian conversionnagendra modadugu2016-05-031-4/+4
| | | | | | | | | | | | | | | Only convert parameters that aren't NULL. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm_test/tpmtest.py pass & CPCTPM_TC2_2_20_04_05 Change-Id: I7d8133a0068ba50dc47ead7b4ce002d96d868dbe Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/341846 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* elm: Set USB_DP_HPD as inputNicolas Boichat2016-05-033-81/+2
| | | | | | | | | | | | | | | | This makes all board_typec_*dp* functions irrelevant: remove them. BRANCH=none BUG=chrome-os-partner:52352 TEST=USB_DP_HPD_C from AP side indicates which output is currently in use (native HDMI or ANX7688) Change-Id: Id60ab97ee9ce987ec4e36e5fd9be9a20908edbfe Signed-off-by: Nicolas Boichat <drinkcat@google.com> Reviewed-on: https://chromium-review.googlesource.com/338868 Commit-Ready: Koro Chen <koro.chen@mediatek.com> Tested-by: Koro Chen <koro.chen@mediatek.com> Reviewed-by: Rong Chang <rongchang@chromium.org>
* CR50: remove checks on RSA key buffer sizenagendra modadugu2016-05-031-5/+0
| | | | | | | | | | | | | | | | | | | | | | Remove buffer size checks in _cpri__GenerateKeyRSA(). The TPM stack passes in TPM2B buffers that may have the size field uninitialized. Callees are expected to assume that the buffer size is sufficient for the requested operation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=TCG test CPCTPM_TC2_2_20_03_02 reliably passes Change-Id: I3d9bc2475b82dfaa9ed1d2617b1c333ff4df409d Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/340883 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add the lock key to the keyboard mask on kevinDavid Schneider2016-05-021-1/+1
| | | | | | | | | | | TEST=confirm lock key scancode shows up in matrix BUG=none BRANCH=none Change-Id: I51ef44017ea57abd3cbbc69c55f3d9da7afff42b Signed-off-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341469 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Reduce system stack sizeShawn Nematbakhsh2016-05-021-1/+1
| | | | | | | | | | | | | | | | Reduce system stack size to 1K to match other recent chips. BUG=None TEST=Build + boot on kevin. BRANCH=None Change-Id: I0be6e865ca03f4eef2ee7a99856df8257d7269d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341850 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* sb_firmware_update: Set ac flag at fw update modeBruce2016-05-021-2/+19
| | | | | | | | | | | | | | | | | | Some reason cause the power off during battery fw update process. Then execute the process again, tool can't detect AC because EC can't read data from battery. So set AC_PRESS flag after check battery is in battery fw update mode. BUG=None BRANCH=None TEST=check the battery can execute fw update in this case. Change-Id: Iafe501eb1719a12425d5cac42d27c897e078acc1 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/341044 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_updater: retransmit upgrade blocks if target does not replyVadim Bendebury2016-05-021-25/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the target is running upgrade protocol version 2, it is capable of processing multiple transfer attempts of the same block. This patch allows timeouts when expecting the target acknowledges. If the acknowledge does not arrive in time, the host reports the timeout on the console and retransmits the same block to the target. BRANCH=none BUG=chrome-os-partner:52856 TEST=it is now possible to successfully upgrade cr50 on Kevin in one go: $ ./extra/usb_updater/usb_updater build/cr50/ec.bin read 0x80000 bytes from build/cr50/ec.bin open_device 18d1:5014 found interface 4 endpoint 5, chunk_len 64 READY ------- erase Target running protocol version 2 Updating at offset 0x00004000 sending 0x29620/0x3c000 bytes Timeout! Timeout! Timeout! Timeout! ------- update complete reboot bye Change-Id: Ib1c3179cb3a02c0ae6e5e949476553ae28b6a295 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341583 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: enhance upgrade protocol to allow upgrade block restartsVadim Bendebury2016-05-021-3/+38
| | | | | | | | | | | | | | | | | | | | | With this new protocol version the target watches the size of the received messages while reassembling an upgrade block. If a message of the header size arrives and it is not the last message of the block, the target considers it a re-start of the block transfer by the host (presumably because a chunk was lost and the host did not receive a confirmation of the block transfer in the preceding block transfer attempt.) BRANCH=none BUG=chrome-os-partner:52586 TEST=the upgrade command on the host reports target running protocol version 2, upgrades on B1 board still run smoothly. Change-Id: I2e16c1be5135c0b5a4f09ea293f09ecabf59ecb3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341630 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: verify that first message of each upgrade block is rightVadim Bendebury2016-05-021-11/+13
| | | | | | | | | | | | | | | | | | | When a new upgrade block starts, the host sends first a 12 byte message including the block size and header. The target must verify that the message is of the proper size and the contents make sense (the header is not all zeros). It also should drain the USB queue completely in case it holds a message of a different size. BRANCH=none BUG=chrome-os-partner:52856 TEST=upgrade still works fine on B1 Change-Id: I80538a3a1a5d507a84bd21b868a3db626bc6a4b0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341619 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: upgrade - improve verification of the first upgrade messageVadim Bendebury2016-05-021-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | When an upgrade transfer starts, the target expects to receive a 12 byte transfer start message from the host, carrying an empty payload of all zeros. The target and host can be out of sync for whatever reason, so when the target is expecting a transfer start message, the host can be sending a chunk of a code block instead. In this case the target pulls just 12 bytes off the receive queue, leaving the rest of the chunk there, which even more complicates error recovery. This patch makes sure that when expecting the upgrade transfer start message the target extracts all receive data from the queue, no matter how many bytes have been received, and then verifies that the size matches the expected size, and that the payload is all zeros, to confirm that the message is indeed the transfer start message. BRANCH=none BUG=chrome-os-partner:52586 TEST=cr50 firmware upgrade still works fine on B1 Change-Id: If5ec86d0385f97f0f361635b3903cea3a962b707 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341618 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: introduce versioning and backwards compatibility of usb_upgradeVadim Bendebury2016-05-022-10/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original version of usb_upgrade does not provide for any error recovery and also does not support any protocol version notion. Real life experience has shown that error recovery is essential, it needs to be introduced as a protocol enhancement. We want to stay backwards compatible though, so there is a need for protocol versioning. In the original version of the protocol target response is always the same: a 4 byte number which is the error code (and zero means no error). This patch modifies response to the very first packet from the host, the startup packet. The startup response is 8 bytes long. The first 4 bytes is still the same as before, the second 4 bytes carry the protocol version supported by the target, an integer in network byte order. Thus, receiving a 4 byte reply to the startup message tells the host that the target is running protocol version zero, 8 byte reply carries the actual version number in the last 4 bytes. The USB transfer function on the host is enhanced to accept responses shorter then expected, when allowed. BRANCH=none BUG=chrome-os-partner:52856 TEST=usb_updater can successfully update both old and new cr50 images, properly reporting protocol version as 0 or 1 respectively. Change-Id: I9920d2708b21f29615282161fc0eb027018f9378 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341617 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: drop: always start with USB facing external portVadim Bendebury2016-05-021-3/+8
| | | | | | | | | | | | | | | | | | | | | We want to be able to communicate with the chip no matter what the hardware conditions are, otherwise it is easy to lose the ability to re-program it from the external connector. With this patch the chip always comes up with the USB interface exposed and will stay in this mode until debug cable is pulled out. After that it will honor subsequent cable plug ins/pull out events as designed. BRANCH=none BUG=chrome-os-partner:52281,chrome-os-partner:50700 TEST=Suzy-q reliably creates serial interfaces when the chip is programmed with the code including this patch. Change-Id: I608fb1912f1b2e88f7a207cbfff145760da1a4e4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341580 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* usb_updater: shut down on errors more gracefully and simplify APIsVadim Bendebury2016-05-021-55/+53
| | | | | | | | | | | | | | | | | | | It might not matter much, but it is a good practice to explicitly release USB resources when terminating the app which used them. Also, make function signatures around the file simpler by introducing a structure to carry common USB endpoint properties: device handle, endpoint number and chunk size. BRANCH=none BUG=chrome-os-partner:52856 TEST=no change in functionality, upgrades on B1 still work fine, upgrades on Kevin still very unreliable Change-Id: I9157774a2f5591c70701ba822f20db6ba02e7029 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341616 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: fix debug messages not to include two newlinesVadim Bendebury2016-05-021-6/+6
| | | | | | | | | | | | | | The CPRITS() macro adds newline to all strings, there is no need to explicitly add newlines. BRANCH=none BUG=none TEST=usb upgrade debug messages do not span two lines any more Change-Id: I1991214ddaa5945bedba861d67b392973f6a3d0f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341615 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: recover from usb_upgrade interruptionsVadim Bendebury2016-05-021-1/+27
| | | | | | | | | | | | | | | | | | | | | The usb upgrade protocol is very fragile, any error while transferring data causes the state machine on the target to lock up, and the only way to resume the upgrade is to power cycle the device. With this patch USB callbacks which happen more than 5 seconds since the previous callback would be considered a start of new transfer, thus allowing to attempt a new upgrade without the power cycle. BRANCH=none BUG=chrome-os-partner:52856 TEST=the following script allows to upgrade successfully: $ while not ./extra/usb_updater/usb_updater build/cr50/ec.bin; do sleep 6; done Change-Id: Ibe1078cf62073ce89a31416522b0d6917bc923b9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341572 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* kevin: Add support 3 color LEDWonjoon Lee2016-05-015-10/+182
| | | | | | | | | | | | | | | | | | When system on .always blue When system is off .discharging : off .charging : red .full-charged : green Error : red - green switching BUG=None TEST=See LED behavier on kevin Change-Id: I93f0dbb503c68999825c455c8dc81b6bdaf397b4 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/341113 Reviewed-by: Shawn N <shawnn@chromium.org>
* Invert KSO2 on KevinDavid Schneider2016-04-302-1/+4
| | | | | | | | | | | | | TEST=confirm column 2 keys work BUG=none BRANCH=none Change-Id: Ib474a46ac723657b96970735dc4e3a1d0c8a8505 Signed-off-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341581 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: point multiply should check point for curve membershipnagendra modadugu2016-04-301-1/+3
| | | | | | | | | | | | | | | | _cpri__EccPointMultiply should check whether the provided point is on the curve prior to doing a multiply. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=TCG test CPCTPM_TC2_4_13_01_01 passes Change-Id: Ia92494070c62f7e03b395975138c0c8446a7284d Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/341112 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: add basic rbox supportMary Ruthven2016-04-298-6/+147
| | | | | | | | | | | | | | | | | This change modifies the behavior of RBOX by blocking the key0 and key1 output, when the power button is pressed. It also adds support for printing debug statements when various RBOX interrupts are triggered. BUG=none BRANCH=none TEST=On cr50 test board verify key0 and key1 out are not asserted unless the power button is pressed. Change-Id: I67a3c1b8009279015bdc87bcf0995cffa9ab6f03 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341470 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* kevin: Decode board versionShawn Nematbakhsh2016-04-292-0/+46
| | | | | | | | | | | | | | | Decode board version from analog voltage on BOARD_ID. BUG=chrome-os-partner:52642 BRANCH=None TEST=Verify 'ver' shows "Board: 0" on proto 1 board. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ifdbdd2e975e463ab45d81ee6eaa4ba017a2f29c0 Reviewed-on: https://chromium-review.googlesource.com/340241 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* kevin: GPIO changes for new proto buildShawn Nematbakhsh2016-04-294-26/+29
| | | | | | | | | | | | | BUG=chrome-os-partner:52171 TEST=Verify old kevin boards still boot + power sequence. BRANCH=None Change-Id: Iacc02beba05ef3e80ffa59aa7fc5718c12bae20c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338043 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: set SYS_RST_L as an inputMary Ruthven2016-04-291-1/+1
| | | | | | | | | | | | | | Setitng SYS_RST_L as an output contends with the EC setting it as an output. We will only drive the pin when necessary. BUG=none BRANCH=none TEST=power on kevin and make sure the AP is able to boot. Change-Id: Ie40cc4932ff92d20b021765c3aa356d8902f20e1 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341326 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Move board-specific rdd stuff out of chip/g/Bill Richardson2016-04-293-13/+11
| | | | | | | | | | | | | Poking GPIOs is something that belongs in board/ not chip/ BUG=none BRANCH=none TEST=make buildall; test on Kevin Change-Id: I798053c3760415ed787800d37eb81c765b826399 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341065 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* STM32: Add HSE and PLL to clock source selectionDaisuke Nojiri2016-04-294-51/+275
| | | | | | | | | | | | | | | | | | | This patch adds HSE and PLL as a system clock oscillator for STM32L4. This allows us to drive the chip at a higher frequency (up to 80 MHz), which is necessary to big-bang GPIO ports accurately. BUG=none BRANCH=tot TEST=make buildall. Verified console works on STM32L476G-Eval using HSE, PLL-HSE, PLL-HSI, PLL-MSI as an oscillator. Verified console runs soundly with different frequencies from 20 Mhz to 80 Mhz. Verified frequencies using oscilloscope on MCO (Microcontroller Clock Output) port up to 50 MHz. Change-Id: I493cdb6c323eb4e6a1560f6d030935c1950b1a2a Reviewed-on: https://chromium-review.googlesource.com/341275 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* STM32: Set UART clock sources to SYSCLKDaisuke Nojiri2016-04-292-3/+13
| | | | | | | | | | | | | | | | Since uart_freq_change assumes we drive UARTs at system clock, we need to set UARTs clock sources accordingly. This will allow us to clock up the chip without worrying about prescaler values set for HCLK and PCLK or the on/off status of HSI. BUG=none BRANCH=tot TEST=make buildall. Verified LPUART on stm32l476g-eval. Change-Id: I02898921e31b68cacbc2235a29c47a212c350afe Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341260 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: remove unused config option CONFIG_RSA, some cleanupnagendra modadugu2016-04-271-4/+3
| | | | | | | | | | | | | | | | | | | | CR50 does not depend on the rsa implementation in common This change removes the corresponding config option. Also remove a duplicate CONFIG_SHA256 option, and add a comment regarding CONFIG_SPS_TEST. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=compilation succeeds Change-Id: Ie01439899042c5fa981f884a01b83eb0b3eb6e32 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/340539 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Tell git to ignore all private subdirectoriesBill Richardson2016-04-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | Internal builds may have private*/ subdirectories cloned from repositories that we're not (yet) allowed to share publicly (boo). Tell git not to complain about them every time I run "git status". BUG=none BRANCH=none TEST=manual mkdir private-foo touch private-foo/bar.txt git status Observe the lack of complaints about private-foo Change-Id: I5281e3a533f9b1a548ced6f6716a388152c58776 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341032 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chell: Keep KB light PWM active during low-power idleShawn Nematbakhsh2016-04-271-1/+2
| | | | | | | | | | | | | | | BUG=chrome-os-partner:52783 BRANCH=glados TEST=Enable CONFIG_LOW_POWER_S0 on chell. Verify KB backlight does not flicker during idle. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib7cbaf955654cbb22a7beb7dc536468b532a769d Reviewed-on: https://chromium-review.googlesource.com/341003 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* pwm: Add PWM_CONFIG_DSLEEP config flagShawn Nematbakhsh2016-04-2712-28/+60
| | | | | | | | | | | | | | | | | | | Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a channel active during low-power idle / deep sleep. Currently it's supported by npcx and mec1322. BUG=chrome-os-partner:52783 BRANCH=glados TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify KB backlight does not flicker during idle. Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341002 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* servo_v4: add initial servo_v4 buildNick Sanders2016-04-276-0/+441
| | | | | | | | | | | | | | | | Add initial servo_v4 build, GPIOs, etc. Supports most features other than PD passthrough. BUG=chromium:571476 BRANCH=None TEST=updated servod is able to control gpio, gpio extender on servo v4 Change-Id: I71c9cb2bf24b732dd6a2e101d7b1c849c9f88af8 Signed-off-by: Nick Sanders <nsanders@google.com> Reviewed-on: https://chromium-review.googlesource.com/332803 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* fusb302: Delay after enabling CC measurement switchesShawn Nematbakhsh2016-04-271-6/+10
| | | | | | | | | | | | | | | | | | Delay after enabling CC measurements, before checking CC levels, in order to improve accuracy. BUG=None TEST=Manual on Kevin. Verify CC levels are consistent with a specific charger. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib9abab2abd68b071fb22200bcac36bea6e361d67 Reviewed-on: https://chromium-review.googlesource.com/340885 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: i2c slave driverVadim Bendebury2016-04-272-0/+233
| | | | | | | | | | | | | | | | | | | | | | | A fairly detailed description of the driver is included in the comments in the file. As of this submission the setup is fairly brittle, as clock stretching is not yet enabled, and there is no guarantee that the slave will prepare the data for the master in time. More testing will be required and enhancements will be added in the future. BRANCH=None BUG=chrome-os-partner:40397 TEST=with the rest of the patches applied, an i2c app running on the desktop allows read and write TPM registers using the USB-FTDI-I2C cable connected to the B1 board. Change-Id: I46b13d360ca92271702268f9088193b5ada583be Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340519 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* tpm_regs: clean up debug messagesVadim Bendebury2016-04-271-5/+5
| | | | | | | | | | | | | | Some debug messages were a bit ambiguous, and some just wrong, this patch fixes the wrong one and disambiguates the other two. BRANCH=none BUG=none TEST=observed the new generated message. Change-Id: I2b58ec050816ecdfe4b20dd8410910569767830d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340536 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* servo_micro: add gpio mode get and setNick Sanders2016-04-276-13/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO console commands currently only show input voltage level, and can only set level on predefined outputs. This change allows GPIOs to be cycled between output, input, and alternate function, as well as displaying the mode and asserted level (if any) in gpioget. This change creates CONFIG_CMD_GPIO_EXTENDED as the internal gpio interface needs to be changed to support this, and I can't test the other architectures. It may be worthwhile to add this for all, or not. This change is also necessary also for servo micro JTAG and PD UART support, as several pins are tied together on the flex and stm32 outputs need to be variously active or in high-z depending on mode. BUG=chromium:571477 TEST=gpioget <0|1|IN|A|ALT>; gpioget; BRANCH=None Change-Id: Iba32992db6244ee1e654db840d1c9c11dd2a0993 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338885 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* checkpatch: do not consider split text strings a problemVadim Bendebury2016-04-271-0/+5
| | | | | | | | | | | | | | | | | | The checkpatch complaints about both lines longer than 80 characters AND character strings split between lines. Damn if you do, damn if you don't. With this addition split character strings are not a problem any more. BRANCH=none BUG=none TEST=split character strings are not reported as a violation by the pre-upload script. Change-Id: I8b5919f086f8c19fe4e6e3a4b99a816111882f0d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340535 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* UART: Remove X-on/X-off flow controlAnton Staaf2016-04-271-50/+10
| | | | | | | | | | | | | | | | | | This doesn't appear to be used anymore, and the EC3PO replacement console doesn't support this yet. This also makes changing the UART driver API more difficult, so let's remove it. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ia6d9cf4c89e34683f38169dbec612a417c6ba630 Reviewed-on: https://chromium-review.googlesource.com/340842 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* UART: Remove enable/disable interrupt functionsAnton Staaf2016-04-279-104/+5
| | | | | | | | | | | | | | | | These were not being used and complicate changes to the UART API. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I73e256f09f7ea72f0cc4831cc7ce391a7125e555 Reviewed-on: https://chromium-review.googlesource.com/340841 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: enable AP and EC flash accessstabilize-8249.BMary Ruthven2016-04-264-0/+23
| | | | | | | | | | | | | | | | | | | | | The cr50 SPI master can control the external AP and EC SPI ROM. This change adds support for doing spi_transactions, but does not use the SPI transactions for anything except console commands. This support will be used for flashing the AP and EC through CCD. For now AP and EC flash select must be done manually using the spi_flash_select console command. Flash select should be disabled after use, because it will prevent the system from booting. BUG=chrome-os-partner:50701 BRANCH=none TEST=Enable spi_flash commands. Select AP ROM and verify spi_flashinfo, read, erase, and write commands work properly. Select EC ROM and verify the same commands. Change-Id: I16c55015794f8513effe0fa5712488a84bed2627 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339844 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Fix port enable check for low power idleShawn Nematbakhsh2016-04-252-2/+2
| | | | | | | | | | | | | | BUG=chrome-os-partner:52734 BRANCH=glados TEST=Plug 2 PD chargers on sentry, remove the first, verify that SLEEP_MASK_USB_PD is not briefly cleared. Change-Id: I62309194d8b5a694487282434fc63b5f39301ba3 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340564 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* STM32: Support LPUART consoleDaisuke Nojiri2016-04-256-5/+42
| | | | | | | | | | | | | | | This patch adds support for console on LPUART (low power UART). It is wired to the USB type B port on the board, which is also one of the power sources. So, using LPUART simplifies the set up. BUG=none BRANCH=tot TEST=Verified console works on stm32l476g-eval. make buildall Change-Id: Iccf697cfabdcb7e1362d8453708eb79610d2e0cb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340101 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Bring up STM32L476G-EvalDaisuke Nojiri2016-04-2518-16/+508
| | | | | | | | | | | | | This patch adds initial set of files to bring up STM32L476G-Eval board. BUG=none BRANCH=tot TEST=Tested console. make buildall && make tests Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340100 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* STM32: Add dma_select_channelDaisuke Nojiri2016-04-254-0/+38
| | | | | | | | | | | | | | | dma_select_channel selects which stream (peripheral) to be used on a specific channel. Some STM32 chips simply logically OR requests, thus do not require this selection. BUG=none BRANCH=tot TEST=make buildall && make tests. Verified on stm32l476g-eval. Change-Id: I7b64b78bdec80658992f58cb4c94ade972a1081c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340107 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* snoball: GPIO changes for proto 1Shawn Nematbakhsh2016-04-253-152/+6
| | | | | | | | | | | | | BUG=chrome-os-partner:52690 BRANCH=None TEST=`make buildall -j` Change-Id: I787e8bc2fb5ca04a0879eeec7a8d7169e36b7661 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340445 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* elm: modifications for EVTKoro Chen2016-04-254-16/+25
| | | | | | | | | | | | | | | | This add modifications for EVT, including: - Use SPI for KX022 motion sensor on the daughterboard - remove TMP432 - Use PF2 to control the external power of ANX7688 BRANCH=none BUG=chrome-os-partner:52245 TEST=make BOARD=elm -j Change-Id: I7d4021746bc8a2be0028076a5c3aeefd8736c1b0 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/337338 Reviewed-by: Rong Chang <rongchang@chromium.org>
* Move include/byteorder.h -> builtin/endian.hnagendra modadugu2016-04-222-28/+39
| | | | | | | | | | | | | | | | Move endian routines to builtin/ so that portable third_party code may build without glibc. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=none Change-Id: Icb900d1e9c56dc68ec1ef4b536ebc9dcf6ebcd69 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/340432 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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