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* Clear OWNERS for factory/firmware branchfirmware-lucid-8173.BBrian Norris2021-09-102-10/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155201 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* lucid:enable RW firmware verificationMary Ruthven2016-06-302-0/+30
| | | | | | | | | | | | | | | | | | | | Check RSA signature of RW firmware and jump to it if it is valid. BUG=chrome-os-partner:54824 BRANCH=lucid TEST=flash lucid with good and bad firmware. Verify it wont jump to the bad firmware. Change-Id: I97d7df81500e158963bdc835c22445471818b85e Reviewed-on: https://chromium-review.googlesource.com/356560 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 6feb319a8710bd54bf9ad30beabd82fa828831d0) Reviewed-on: https://chromium-review.googlesource.com/356820 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* add support for using flash commands to overwrite rwsigMary Ruthven2016-06-301-0/+5
| | | | | | | | | | | | | | | | | | | | | | When verifying RW using rwsig, we need to be able to erase the RW signature to remain in RO. This change excludes the RW signature from the area protected by system_unsafe_to_overwrite, so flash write can be used to overwrite the RW signature while still in the RW system image. BUG=none BRANCH=lucid TEST="ectool flashwrite 0x1ff00 corrupt_sig" runs successfully, and on reboot the EC firmware verification fails. Change-Id: I7e234664ae564eef30a8b021ea0539b6c0ae898e Reviewed-on: https://chromium-review.googlesource.com/356810 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 978c4961d605a2da7e79396b1f8db3d543db9059) Reviewed-on: https://chromium-review.googlesource.com/357900 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
* lucid: Add battery temp to temp_sensors listMary Ruthven2016-06-302-0/+23
| | | | | | | | | | | | | | BUG=none BRANCH=lucid TEST=verify "ectool temps 0" displays the battery temperature Change-Id: If8f58886f84b2aaffd8a517bf85633c34c9b7ca2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/347990 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 8f886b40f4335a43bde5da9096308ae91935c7eb) Reviewed-on: https://chromium-review.googlesource.com/356821
* common: Decouple temp sensor from thermal throttlingMary Ruthven2016-06-2913-1/+25
| | | | | | | | | | | | | | | | | Not everything with a temperature sensor uses thermal throttling. This change modifies the conditional build to enable building temp sensor source without thermal throttling. BUG=none BRANCH=lucid TEST=make buildall -j Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356484 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 7f67d27a53d521ecb430ec48758020e046c72f43) Reviewed-on: https://chromium-review.googlesource.com/357120
* lucid: Remove CONFIG_SYSTEM_UNLOCKEDMary Ruthven2016-06-291-3/+0
| | | | | | | | | | | | | Remove CONFIG_SYSTEM_UNLOCKED for final firmware BUG=None BRANCH=lucid TEST=`make -j buildall` Change-Id: I1704849334ad43c61cc9340ba1f446ee8e84215c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/357101 Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Rename and move board_set_gpio_hibernate_stateAnton Staaf2016-03-216-14/+16
| | | | | | | | | | | | | | | | | This function is no longer GPIO specific and fits better as part of the system API, so this moves it there and renames it board_hibernate_late. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I39d3ecedadaaa22142cc82c79f5d25c891f3f38c Reviewed-on: https://chromium-review.googlesource.com/330124 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* crc8: Support crc calculation across non-contiguous dataShawn Nematbakhsh2016-03-182-3/+20
| | | | | | | | | | | | | | | | | Building a single buffer for crc calculation is often inefficient, so add a new function that calculates crc8 from an existing crc8. BUG=chromium:576911 BRANCH=None TEST=Manual on sentry with subsequent commit. Verify that smbus communication with battery is functional. Change-Id: I05ffedb81ffcf0c126acda5f6212b3147b1580a1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333786 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ectool: Eliminate needless stderr output from `tempsinfo`Shawn Nematbakhsh2016-03-181-0/+3
| | | | | | | | | | | | | | | | | | `tempsinfo all` will probe all 24 sensor IDs, which will produce stderr output due to host command failure if a given sensor does not exist. Therefore, check memmap data for presence before probing a given ID. BUG=chrome-os-partner:51026 BRANCH=None TEST=Manual on Sentry. Verify "ectool tempsinfo all" dumps info on 4 temperature sensors and prints nothing to stderr. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14d65c1ad03eafafc21db41781c434b3ed74cb7e Reviewed-on: https://chromium-review.googlesource.com/333779 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Do not shutdown LPC in deepsleep.Divya Jyothi2016-03-172-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | During the resume sequence of S0ix EC can receive host commands early in the resume path when LPC is still disabled in EC. Host messages will be lost if the LPC interface with the kernel is down. Clock control was programed to 2 which means ring oscillator is shut down after completion of everty LPC transaction.To restart the oscillator EC should enable a wake interrupt on LPC LFRAME number and this mode can cause an increase in the time to respond to the LPC transactions. Keeping LPC always on shows minimal power impact as per datasheet Pg.390. The impact is < 0.45mW. BUG=chrome-os-partner:50627 TEST=Enter into S0ix and exit reliably. BRANCH=firmware-glados-7820.B Change-Id: I670b9b45c3a85c9bca249312a73a25dca52b313a Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332333 Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c03fd6e0eaa6ecd3205214f901facb9896a798b4) Reviewed-on: https://chromium-review.googlesource.com/332791
* servo_micro: add initial servo_micro buildNick Sanders2016-03-168-1/+602
| | | | | | | | | | | | | | | | | | * Update flash_ec to allow flashing servo_micro * Add servo_micro build BUG=chromium:571477 BRANCH=None TEST=updated servod is able to control gpio, gpio extender, SPI flash, ec uart, ap uart on test yoshi Signed-off-by: Nick Sanders <nsanders@google.com> Change-Id: I4d69c83ae581cb41da928a27c39b7152475d7ca8 Reviewed-on: https://chromium-review.googlesource.com/327214 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* oak: make sure power button is stable when waiting for releaseYH Huang2016-03-161-33/+4
| | | | | | | | | | | | | | | | | | The debounce timer might be too slow to actually update the state of debounced_power_pressed by the time we do power_button_is_pressed in the S3->S5 state transition. Call power_button_wait_for_release() instead of wait_for_power_button_release() to make sure there are no deferred actions. BRANCH=none BUG=chrome-os-partner:50362, chrome-os-partner:51109 TEST=During dev mode screen, press power button, note the device stays off TEST=sudo test_that -b oak <DUT_IP> firmware_FwScreenPressPower Change-Id: Ic60c1847ba461ef874dea5bf7d03675622f24beb Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/332310 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: Clean up CONFIG_PMIC_FW_LONG_PRESS_TIMER related codesKoro Chen2016-03-162-15/+0
| | | | | | | | | | | | | | | | | | | | | CONFIG_PMIC_FW_LONG_PRESS_TIMER was ported long time ago from Tegra, but the codes are actually not used and erroneous. It might wrongly trigger set_pmic_pwron(0), and turn off PMIC power accidentally. This causes POWER_GOOD lost and power state will go back to S5 during boot up. Clean up the codes by referencing check_for_power_off_event() of Rockchip. BRANCH=none BUG=none TEST=bootup and press power button quickly right after we are in S0. Bootup should still complete normally. Change-Id: Ie034efa3575dbebae4debb1afc206fddd9116350 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/332724 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: Add delay before we turn off VBATKoro Chen2016-03-161-0/+7
| | | | | | | | | | | | | | | | After power good is lost, PMIC requires some time to turn off all its internal power before we can turn off VBAT by set_system_power(0). This ensures the power measurement is within PMIC spec when system is shut down. BRANCH=none BUG=none TEST=measure the power rails of PMIC after system is shut down Change-Id: I55d4d99ed0ef69b103a4e52e9f9eec1c9e6265b5 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/332409 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: rev5: increase cycle time for LED in SUSPENDWei-Ning Huang2016-03-161-2/+9
| | | | | | | | | | | | | | Increase LED blink cycle time to reduce power consumption on Oak rev5 with GlaDOS ID. BUG=chrome-os-partner:50317 TEST=`make EXTRA_CFLAGS=-DBOARD_REV=5 BOARD=oak -j` Change-Id: Ic00512434965471a82b94ef431e0ec88c9e4c0c3 Reviewed-on: https://chromium-review.googlesource.com/332346 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
* npcx: Add 256KB alignment of RO & RW regions for npcx5m6g.Mulin Chao2016-03-154-38/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since npcx5m6g has larger than 128 KB code ram for FW, the original alignment between RO & RW regions isn't suitable for new chip. Therefore, we add 256KB alignment of them for npcx5m6g. In order to program the flash used by npcx5m6g, we add new board array, BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g and flash_npcx5m6g to program flash with different layout. Modified sources: 1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for npcx5m6g. 2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to distinguish which flash layout ec used. 3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with different layout. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/331903 Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_micro: add USB I2C interfaceNick Sanders2016-03-155-1/+332
| | | | | | | | | | | | | | | | | | Add a usb endpoint and class for i2c control via USB. Used for servo micro and servo_v4 to export USB control through servod. BUG=chromium:571477 BRANCH=None TEST=updated servod is able to control gpio extender on servo_micro Signed-off-by: Nick Sanders <nsanders@google.com> Change-Id: Id44096f8c9e2da917c0574d28dfcbcc0adf31950 Reviewed-on: https://chromium-review.googlesource.com/329322 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chell: Indicate when charging in suspendDuncan Laurie2016-03-151-2/+7
| | | | | | | | | | | | | | | | | | | | Currently when in suspend the LED blinks white no matter what the state of the battery or charging is. This is very confusing for users who expect to be able to plug in a charger with the system in suspend and see that it starts to charge. Past platforms from this OEM have had two LEDs so this has not been an issue. BUG=chrome-os-partner:49151 BRANCH=glados TEST=put chell in suspend, plug in charger to see amber LED and then remove the charger and see that it blinks white again. Change-Id: I60e849d7b8b717fb568d7d5d64046621c1c34157 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/332625 Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: trng: handle (unlikely) TRNG timeoutVadim Bendebury2016-03-141-2/+8
| | | | | | | | | | | | | | | It turns out TRNG could turn idle under certain circumstances, and needs to be restarted in that case. This code adds a check for the idle state and necessary recovery. BRANCH=none BUG=b:27646393 TEST=none yet Change-Id: Ibd0a13f40f5ce081d4211b2c0f1026468967f826 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/332573 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* pd: Add error handling for pd_send_request_msg()Shawn Nematbakhsh2016-03-141-7/+14
| | | | | | | | | | | | | | | | | | | If we have already completed negotiation as a sink and pd_send_request_msg() fails, issue a soft reset so we don't remain indefinitely at our previously negotiated voltage. BUG=chrome-os-partner:50346 BRANCH=glados TEST=Manual on chell. Attach zinger to port 1, then attach zinger to port 2. Verify that port 1 negotiated to 20V. Detach port 1 and verify port 2 successfully negotiates to 20V and begins charging. Change-Id: I4f8ff9a1e3ef49858f6ae5c3ccb5b5d4d847e2d1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/332642 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kevin: Add rk3399 power sequencingShawn Nematbakhsh2016-03-144-3/+18
| | | | | | | | | | | | | BUG=chrome-os-partner:50819 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4e1c44a897aae7f22605911fbf4e8de3056b9bbd Reviewed-on: https://chromium-review.googlesource.com/331659 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* power: Add support for rk3399 power sequencingShawn Nematbakhsh2016-03-143-0/+216
| | | | | | | | | | | | | | | | Add power-up sequencing for rk3399. This is very much a WIP and the sequence will surely change greatly. BUG=chrome-os-partner:50819 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3bacdc8516cfe081411032d55374dd1ab21b2d9d Reviewed-on: https://chromium-review.googlesource.com/331658 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Cr50: cleanup: put macro args inside parensBill Richardson2016-03-111-1/+1
| | | | | | | | | | | | | Just to be safe... BUG=none BRANCH=none TEST=make buildall; try on Cr50 board Change-Id: I5b605a50f85dbfeb404fa93b59d795b7f8a0d5c5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/332197 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kunimitsu: remove CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5Kevin K Wong2016-03-111-1/+0
| | | | | | | | | | | | | | | | skylake.c does not make use of pause_in_s5 and related code, so it will always has 10 second pause in POWER_S5 before transition to POWER_S5G3, and this CONFIG flag is adding about 290 bytes of unused code for host command and console command. BUG=none BRANCH=firmware-glados-7820.B TEST=make buildall; system can shutdown and enter SOC-G3 properly Change-Id: I1d507b925e13f794e9826a43ebdad898087a6663 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332025 Reviewed-by: Shawn N <shawnn@chromium.org>
* Kunimitsu/Lars: correct adc voltage readingKyoung Kim2016-03-112-2/+16
| | | | | | | | | | | | | | | Add adc correction parameter for VBUS channel. BUG=chrome-os-partner:49192 BRANCH=glados TEST=make -j buildall Change-Id: Ia613d92936a1f4d2dcd9f1cd26f43ecfe9c0eab1 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331401 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* core: fix unaligned accessKevin K Wong2016-03-111-0/+2
| | | | | | | | | | | | | | | | without this, there could be unaligned access of __flash_lpfw_start variable in system_hibernate function which causes exception. BUG=none BRANCH=none TEST=make buildall, able to enter/exit EC hibernate Change-Id: I6c0400fd88f3b815a42a70c2983a8f8ecd79b398 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331653 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: Initial board commitShawn Nematbakhsh2016-03-107-0/+785
| | | | | | | | | | | | | | | | Initial EC board support for kevin, a npcx5m5g part with SPI host interface. BUG=chrome-os-partner:50819 BRANCH=None TEST=`make BOARD=kevin` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0d878edd7e8c7f59cfcb8e16637a5b589552eba9 Reviewed-on: https://chromium-review.googlesource.com/330856 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* mkbp_event: prevent unnecessary interrupts to APKoro Chen2016-03-101-2/+2
| | | | | | | | | | | | | | | | | | | | After commit 237406c5b12ed9934fc6eab7d24f30ba6e70fdce, there is chance that pd_power_supply_reset() will be called during S0->S3, and it interrupts AP and fails suspend if we are using MKBP_EVENT. This is because mkbp_send_event() does not check power state POWER_S0S3. Modify the condition to check events when AP is not in S0. BRANCH=none BUG=chrome-os-partner:50833 TEST=powerd_dbus_suspend always works without being resumed Change-Id: Id905a2cd4d2a0376bca163f40c68bcf4208d8bf5 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/331160 Commit-Ready: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Milton Chiang <milton.chiang@mediatek.com> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
* Lars: Manually Revert "Lars: Add ALS support"Ryan Zhang2016-03-084-24/+5
| | | | | | | | | | | | | | - als * revert#315470 has conflict error msg BUG=chrome-os-partner:50730 BRANCH=lars TEST=`make -j buildall` Change-Id: I955916d5ff052820337aac8e59ff38af33655320 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/331004 Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: move platform independent stub calls back to third_partynagendra modadugu2016-03-081-22/+0
| | | | | | | | | | | | | | | | | Move _math__Comp and _math__uComp from stubs.c back to third_party/tpm2 as they are platform independent. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 CQ-DEPEND=CL:330855 TEST=compilation succeeds Change-Id: I2a1611e0b264720d71ac1fa0935cfa2498e04fdc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/330951 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* util/iteflash: Return error on all verify failuresShawn Nematbakhsh2016-03-081-1/+2
| | | | | | | | | | | | | BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Iefc8e1eaf1e5d7c8533d8497c227c8c16eb2c06d Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/331200 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Compilation fixes for upcoming board designsShawn Nematbakhsh2016-03-082-3/+8
| | | | | | | | | | | | | | | | | - Send host commands to TCPCs based upon CONFIG_HOSTCMD_PD, since boards with off-the-shelf TCPCs will also have a PDCMD task. - Don't log VBUS voltage if we have no VBUS ADC channel. BUG=chrome-os-partner:50819 BRANCH=None TEST=`make buildall -j` with subsequent kevin board commit. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I33347402ec31e1754ad8e9a62814d5c1f345737d Reviewed-on: https://chromium-review.googlesource.com/331343 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Rename CONFIG_SHI to CONFIG_HOSTCMD_SPSShawn Nematbakhsh2016-03-084-5/+5
| | | | | | | | | | | | | | | | | CONFIG_SHI ("SPI host interface") has identical meaning to CONFIG_HOSTCMD_SPS ("Accept EC host commands over the SPI slave"). Use CONFIG_HOSTCMD_SPS, since it came first and is already defined in config.h. BUG=chrome-os-partner:50819 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I665c405ad72caa3b84e583a80c0893e4c625632a Reviewed-on: https://chromium-review.googlesource.com/331342 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lucid: fix adc vbus sensingMary Ruthven2016-03-081-2/+2
| | | | | | | | | | | | | | This change changes the full ADC range for VBUS to the correct value. BUG=none BRANCH=none TEST=Verify VBUS voltage reported by `adc` matches measured voltage on scope. Change-Id: I3497ea790c4cbce66845d4cc661e1a0437c1cdfd Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/331283 Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: move utility method reverse() to common/util.cnagendra modadugu2016-03-073-13/+20
| | | | | | | | | | | | | | | | | reverse() swaps the endian-ness of a buffer of specified length. This change moves the implementation to a common location. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=compilation succeeds Change-Id: If8c97f53cc199d63c1caebbd999e1c099814387e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/331333 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: set result size in _cpri__GenerateKeyEcc, _cpri__GetEphemeralEccnagendra modadugu2016-03-071-3/+11
| | | | | | | | | | | | | | | | _cpri__GenerateKeyEcc, and _cpri__GetEphemeralEcc are expected to set the size of the result in accordance with the curve being used. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py, test CPCTPM_TC2_2_14_02_05 passes Change-Id: I558cc56f689c2d33c12876ddbfde7e9659613d2c Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/331210 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* oak: Fix rev5 battery LEDKoro Chen2016-03-071-12/+17
| | | | | | | | | | | | | | rev5 battery LED control was misplaced in wrong function. Move it back to oak_led_set_battery(). BRANCH=none BUG=chrome-os-partner:49375 TEST=ectool led battery [green red off] are correct Change-Id: I83bc24c7ea7695be2a638e97b7db6e0c38840a16 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/330509 Reviewed-by: Rong Chang <rongchang@chromium.org>
* sb_firmware_update: Remove battery HWID checkBruce2016-03-071-9/+0
| | | | | | | | | | | | | | | | | We're supporting a wide range of batteries, and since file name matching is based on HWID, we don't need to maintain a separate table of supported HWIDs in our utility. BUG=chrome-os-partner:49589,chrome-os-partner:50469 BRANCH=None TEST=buildall Change-Id: I3e7c62379c07a598e23f3c543959503d3d25aee3 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/330231 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* iteflash: Initialize variable that later used in the functionAnatol Pomozov2016-03-061-1/+1
| | | | | | | | | | | | | | | | | | Latest GCC gives compiler error: util/iteflash.c: In function verify_flash: util/iteflash.c:927:9: error: res may be used uninitialized in this function [-Werror=maybe-uninitialized] return res; ^ BUG=None TEST=`make buildall -j` outside chroot BRANCH=None Change-Id: I184d8673020552797fd54bb98ee582a63debbf16 Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/330873 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Add CHIP_VARIANT variant for different versions of npcx ec.Mulin Chao2016-03-056-7/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT variant to distinguish which verson ec is. In config_chip.h, we use CHIP_VARIANT to specify the size and start address of program memory. Ecst tool also needs a chip parameter to make sure the address range checking of entry pointer won't fail. Modified sources: 1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec of npcx ec. 2. config_flash_layout.h: Replace constant value with CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE. 3. build.mk: Add -chip parameter for ecst tool to check entry address. 4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g). BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/330072 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Add 1.8V IO support for some GPIOs and I2C pins.Mulin Chao2016-03-055-60/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 1.8V IO support for some GPIOs and I2C pins. We use a array (gpio_lvol_table) to confine which IO pins can switch to 1.8V. Before setting it to support low voltage level, FW should set IO pin's type to open-drain and disable internal pulling up or down. We also add examples in gpio.inc of npcx_evb and npcx_evb_arm to indicate how to set GPIO & I2C pins to 1.8V if user adds CONFIG_TEST_1P8V definition in board.h. In i2c.c driver, this version removes the internal pull-up feature of i2c ports since the driving force is too weak. (about 30K ohm) Modified sources: 1. gpio.c: Add 1.8V IO support for some GPIOs and I2C pins. 2. i2c.c: Remove internal pull-ups feature for i2c pins and move 1.8V support to gpio.c. 3. register.h: Modified NPCX_LV_GPIO_CTL register & bits definitions. 4. npcx_evb\gpio.inc: Add examples of 1.8V IO. 5. npcx_evb_arm\gpio.inc: Add examples of 1.8V IO. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I73a840ae321820212e50d609dab17576117a7d64 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/330037 Reviewed-by: Shawn N <shawnn@chromium.org>
* oak: set up base accelerometer rotation matrixRicky Liang2016-03-041-1/+8
| | | | | | | | | | | | | | | The base accelerometer on oak rev5 needs to be rotated 180 degrees along the z-axis to match the standard reference frame. BUG=chrome-os-partner:50312 BRANCH=none TEST=manually rotate my oak rev5 and verify that `ectool motionsense` reports correct accelerometer readings Change-Id: I05a377b5f0827e2aad47d388dc3264d451580989 Signed-off-by: Ricky Liang <jcliang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/330484 Reviewed-by: Rong Chang <rongchang@chromium.org>
* Common : Fix ectool led cmd segmentation faultRyan Zhang2016-03-041-1/+1
| | | | | | | | | | | | | | | | | | led_color_names[] should have EC_LED_COLOR_COUNT numbers of data. A missing data cause strcasecmp() compare argv[] with NULL in find_led_color_by_name(), that results in Bundle Image test error BUG=chrome-os-partner:50612 BRANCH=lars TEST=`make -j buildall`, `ectool led power blue=255` with homemade ectool. Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Change-Id: I2132775f9d4a074517f9a98b81919dd77bc86102 Reviewed-on: https://chromium-review.googlesource.com/330075 Commit-Ready: David Wu <david_wu@quantatw.com> Tested-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* fusb302: update driver for FUSB302BJoe Bauman2016-03-032-15/+75
| | | | | | | | | | | | | | | | | Update pull-ups code Manage BIST Test Data bit BUG=none BRANCH=none TEST=PD contract established with various devices Signed-off-by: Joe Bauman <joe.bauman@fairchildsemi.com> Change-Id: Ib2e5f7f5e29f280835ae890148f5c3dd2504a2f9 Reviewed-on: https://chromium-review.googlesource.com/329034 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* oak: fix issues on building oak rev1-4 ECRong Chang2016-03-033-19/+22
| | | | | | | | | | | | | | | | | | | The default target hardware is rev5. This is a maintainess change for old and deprecated HW. BRANCH=none BUG=chrome-os-partner:49114 BUG=chrome-os-partner:50720 TEST=manual for N=1,5 do make BOARD=oak clean && make BOARD=oak EXTRA_CFLAGS="-DBOARD_REV=$N" -j Signed-off-by: Rong chang <rongchang@chromium.org> Change-Id: Ibb4ebf9fab429964ace7c3e548598f0fb08e7dea Reviewed-on: https://chromium-review.googlesource.com/330065 Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* Cr50: Modify flash write to account for erase block boundariesScott2016-03-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flash writes must have starting offsets and byte lengths that are multiples of 4 bytes. This requirement is already covered. One additional requirement is that a batch write not cross a flash block boundary. Added a check in flash_physical_write() to check if this boundary would be crossed and if so to reduce the write size so that it ends at the block boundary. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual Used the TPM NVMem section and executed flash writes/reads using a console command utility that I created to test NVMem accesses. Note that the console output only exists in the console command related functions. This test has the offset 12 bytes from the block boundary and 64 bytes long. The counting pattern shows that the write fills the last 12 bytes, then moves to the next block as expected. > nvmem wr 0xff4 0x40 3 nvmem wr: o = ff4, s = 64|0x40 start = 0xff4, end = 0x1034 block 0: block_offset = 0x40800 Call Erase(0x80800, 0x800) block 1: block_offset = 0x41000 Call Erase(0x81000, 0x800) Nvmem: writing 64 bytes, start = 0x80ff4 > nvmem rd 0xfe0 0x80 nvmem rd: o = fe0, s = 128|0x80 0x80fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x80ff0: ff ff ff ff 00 01 02 03 04 05 06 07 08 09 0a 0b 0x81000: 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 0x81010: 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 0x81020: 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 0x81030: 3c 3d 3e 3f ff ff ff ff ff ff ff ff ff ff ff ff Also tested the case where a write should end exactly at the block boundary. > nvmem wr 0xff0 16 3 nvmem wr: o = ff0, s = 16|0x10 start = 0xff0, end = 0x1000 block 0: block_offset = 0x40800 Call Erase(0x80800, 0x800) Nvmem: writing 16 bytes, start = 0x80ff0 > > nvmem rd 0xfe0 0x80 nvmem rd: o = fe0, s = 128|0x80 0x80fe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x80ff0: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0x81000: 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 0x81010: 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 Change-Id: Icbe66d3f79d84ed29ecc6207537ea0bf42781f3c Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/330175 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chell: Enable HW charge ramping for BC1.2 suppliersShawn Nematbakhsh2016-03-022-0/+35
| | | | | | | | | | | | | | | | | | | Use ramp limits from glados. BUG=chrome-os-partner:50689 BRANCH=glados TEST="reboot ap-off" on chell, then attach DCP, SDP and proprietary chargers. Verify through "battery" charge current that input current is ramps and settles on a value within spec. Change-Id: I6ff42510cd33a0678329e8de528917653fef3424 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/330155 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* spi_flash: Reload watchdog after erasing each 32K blockShawn Nematbakhsh2016-03-021-0/+5
| | | | | | | | | | | | | | | | | A single erase host command may erase an arbitrarily large region of storage, which may lead to our watchdog firing. BUG=chrome-os-partner:50587 BRANCH=glados TEST=Manual on glados, flash RW EC / PD FW while plugging + unplugging zinger. Verify that watchdog doesn't fire. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I90dc85306aec43326c11c794861f68c6e12686e4 Reviewed-on: https://chromium-review.googlesource.com/329987 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* GPIO: Move STM32 specific gpio_enabled_clocksAnton Staaf2016-03-024-10/+18
| | | | | | | | | | | | | | | | | | | | This function should not be part of the public GPIO API. It is only available and used in the STM32 implementation. This moves the prototype to a chip specific gpio.h that is used within the STM32 chip directoy. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Manually verify GPIO functionality on discovery board Change-Id: If9c97f8038b26815318652ca62c1132c95519fa2 Reviewed-on: https://chromium-review.googlesource.com/329968 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* USB: Add bounds checking to USB-SPI bridge readAnton Staaf2016-03-021-8/+10
| | | | | | | | | | | | | | | | | | | | | Previously a bogus rx_count value from the USB hardware could have caused a buffer overflow while copying from the packet ram to the DMA bounce buffer. I'm not sure if it is possible to cause the hardware to generate a bogus rx_count, I doubt it, but this is now nicely paranoid Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Test SPI bridge functionality on discover board Change-Id: I080ba1c1f05c2b0a86a4c6eb89e8c1387827466e Reviewed-on: https://chromium-review.googlesource.com/329849 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Nick Sanders <nsanders@google.com>
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