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* Clear OWNERS for factory/firmware branchfirmware-mccloud-5827.BBrian Norris2021-09-102-10/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155204 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* zinger: implement fault protectionVincent Palatin2014-05-055-12/+120
| | | | | | | | | | | | | | | | | | | | | | Detect over-current and over-voltage and trigger a fault. The over-current threshold is 10% over 3A (3.3A). Only currently implement the slow protection, the fast interrupt-based one will be done later. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28331 TEST=with Zinger connected to an electronic load, adjust the current to 3.35A and see the output voltage cut. Change-Id: I0e848192392fd73f0839d4bcb806528b2a6b9122 Reviewed-on: https://chromium-review.googlesource.com/197947 Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* tegra: keeps AP in off state for "reboot ap-off"Louis Yung-Chieh Lo2014-05-031-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XPSHOLD is not always removed after chipset_force_shutdown(). This is different to the GAIA design. So, check the RESET_FLAG_AP_OFF flag again while check_for_power_on_event(). BUG=chrome-os-partner:28371 BRANCH=tot,nyan TEST=verify on big. re-flash ec: power on 2, AP is up. AP is on, reboot@EC: power on 1, AP is up. AP is off, reboot@EC: power on 2, AP is up. AP is on, reboot ap-off@EC: AP keeps off (see FLAG_AP_OFF flag) AP is off, reboot ap-off@EC: AP keeps off (see FLAG_AP_OFF flag) reboot ap-off@EC, then 'powerbtn': AP is off at boot, then power on 4 reboot@EC: power on 2, AP is up. re-plug AC (remove battery): power on 2 re-plug battery (without AC): power on 2 (but my battery is dead) power off (S5), power on: power off 4, power on 5 power off (G3), power on: power off 4, power on 5 lid close / power off (S5)/ lid open: power on 3 lid close / power off (G3)/ lid open: power on 3 press power button and release: nothing happens after 15s. AP keeps in S5. button off (S5)/ on: power off 3, power on 4 button off (G3)/ on: power off 3, power on 4 power off (S5)/ button on: power off 4, power on 4 power off (G3)/ button on: power off 4, power on 4 button off (S5)/ power on: power off 3, power on 5 button off (G3)/ power on: power off 3, power on 4 button off (S5)/ lid open: power off 3, power on 3 button off (G3)/ lid open: power off 3, power on 3 is off, long press button (60s): power on 4, too long, shutdown, stay off is on, long press button (60s): power off 3, stay off AP is on, apreset cold: entered to S5, power off 3, power on 5 AP is on, apreset warm: power state is not changed, but reboots to BIOS Change-Id: I9ccd13ab4b5f38be1ad8d6c9a04724b56bc5b166 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197604 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* blaze: remove from ToT.Louis Yung-Chieh Lo2014-05-037-735/+1
| | | | | | | | | | | | | | Since we already created the firmware-nyan-5771.B branch, we can remove this from ToT now. But for sure we are still able to cherry-pick changes back to ToT or from ToT. BUG=none BRANCH=tot TEST=make buildall Change-Id: I637d27b9f8672c5d17b60e210a5211ab8e19b54a Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197165
* pd: more robust receptionVincent Palatin2014-05-023-5/+15
| | | | | | | | | | | | | | | | | | Ensure that we finish reception if and only if we started it whatever other events happened. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28332 TEST=Connect Zinger to Firefly, request higher voltage and ensure that Firefly was still getting the Pings after several hours. Change-Id: Ie99984aeb4c565be39d349457dbd2813203b3f5b Reviewed-on: https://chromium-review.googlesource.com/197946 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: better sink transitionsVincent Palatin2014-05-021-13/+42
| | | | | | | | | | | | | | | | | | Ensure that the power sink as expected by the standard or times out if nothing happens. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28332 TEST=connect Firefly to Zinger and transition between voltages using Firefly buttons. Change-Id: I99e482982e4788a52bc2c1a57d672c3d71ff22e2 Reviewed-on: https://chromium-review.googlesource.com/197052 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* cortex-m0: fix hard-faults during software interrupt calls part 2Alec Berg2014-05-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is another patch to fix the bug which causes a HardFault exception at the "svc" instruction in __wait_evt(). The HardFault is due to a priority escalation problem in which "svc" is called when the PRIMASK is high, meaning interrupts are disabled. The issue was that an interrupt can occur just before the "svc" instruction, and when an interrupt fires that performs a context switch, the IRQ handler disables interrupts setting the PRIMASK reg high. The arm v6 reference manual specifies that "PRIMASK unchanged on exception exit". So, therefore, we must clear PRIMASK by running "cpsie" before exiting IRQ handler. BRANCH=none BUG=chrome-os-partner:28296 TEST= Reproduce the problem on a fruitpie by inserting dummy for loop in __wait_evt() before "svc" call: asm volatile("isb"); for (i = 0; i < 250; i++) ; __schedule(1, resched); Then, when running pd dev, the system gets the HardFault exception within a few minutes because there is more time for an interrupt to occur and disable interrupts right before call to "svc". After applying this patch, the code has run for > 3 hours without a HardFault. Change-Id: Ic50252b09c40c7d76975ff7f16d799c9eae2bde6 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197839 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* test: build target test only when the full runtime is availableVincent Palatin2014-05-021-0/+2
| | | | | | | | | | | | | | | | | | | For targets not using the common runtime functions, the current test content does not make much sense and fails to build properly : de-activate the tests build in that case. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28480 TEST=USE=usbpd emerge-samus chromeos-ec Change-Id: Ic6477861b5a86916f29a9f6bb70ed0def3661886 Reviewed-on: https://chromium-review.googlesource.com/197883 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Increase some task stack sizes to handle more FP regs.Bill Richardson2014-05-013-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With change b610695b61db3b3784e2a516c91f429139616100, we fixed a problem with the number of FP regs that were being saved on the stack. That change decreased the required stack size for non-FP tasks by 64 bytes, but increased the size needed for FP tasks (such as the lightbar). The lightbar task was previously using within 64 bytes of its alloted stack, so handling the task switching correctly meant that it now overflowed. The hooks task had the same problem, but was hidden by the lightbar task. This CL bumps the LARGER_TASK_STACK_SIZE up a bit, and switches the lightbar task to use it instead of the default size. BUG=chrome-os-partner:27971, chrome-os-partner:28407 BRANCH=ToT TEST=Try it on both Link and Samus. Before this change, the Samus lightbar was overflowing its stack every time the AP booted (causing the lightbar to do things). With this change, it doesn't. Here are typical stack sizes after this CL: Task Ready Name Events Time (s) StkUsed 0 R << idle >> 00000000 28.394913 328/512 1 HOOKS 00000000 0.534085 640/768 2 R LIGHTBAR 10000000 5.359356 520/768 3 CHARGER 00000000 0.094674 384/512 4 CHIPSET 00000000 0.003353 320/512 5 KEYPROTO 00000000 0.002814 312/512 6 HOSTCMD 00000000 0.002942 244/512 7 R CONSOLE 00000000 0.193776 340/768 8 POWERBTN 00000000 0.000392 248/512 9 KEYSCAN 00000000 0.409337 332/512 Change-Id: Ica93608c8adb225410a62ec3a0a27944c479270a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197733 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Keyborg: Fix column orderingVic (Chun-Ju) Yang2014-04-301-10/+10
| | | | | | | | | | | | | | Column 0 is on the slave side. Fix this. BUG=None TEST=Press a finger at the center of the panel. See a single shape in touch data. BRANCH=None Change-Id: Ic3a9a4fafc6e7ee39a1c3422905cf3b1758f335a Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197641 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* baytrail: Workaround for stuck boot processRandall Spangler2014-04-305-13/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases, the system will boot to S0 from the point of view of the EC, but PLTRST# will never deassert. Work around this by waiting 50 ms for PLTRST# to deassert. If it doesn't, force the chipset all the way down by deasserting RSMRST#, then pulse the power button to turn it back on. Also add a powerfail debug command to simulate this failure event, so that the recovery process can be tested. Add API to the LPC module to get the state of PLTRST#, and to the power button state machine to force it released when we shut down the chipset and and force another power button pulse as we reset the chipset. BUG=chrome-os-partner:28422 BRANCH=baytrail TEST=1. Boot system. Should boot normally. Shut system down. 2. powerfail 3. Boot system. On the EC console, should see the system come up, go back down through G3S5, then come back up. From the user's point of view, it just boots. 1. Boot system. Should boot normally. (That is, powerfail is not sticky) Change-Id: Ia57f196606f79b9f2fce7d9cd109ab932c3571aa Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197523 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Keyborg: Disable SWD portsVic (Chun-Ju) Yang2014-04-302-4/+7
| | | | | | | | | | | | | | | | | Most of the time we don't need to use a debugger during runtime. Let's disable SWD ports so that we can use the two pins for touch scan. We can still re-flash the chips as long as we hold the reset pin when entering SWD mode. BUG=None TEST=Check we can still re-flash the chips BRANCH=None Change-Id: Ieb34406f4bc6d6a753ec840b3072f363c7b17c08 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197196 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Keyborg: Refine master slave identificationVic (Chun-Ju) Yang2014-04-302-8/+29
| | | | | | | | | | | | | | | | | | | | The current identification method uses SPI_NSS as master/slave indication. However, if the other chip is not reset at the same time, it would drive SPI_NSS and fails the identification. Since the master chip is equipped with USB connection, we can identify the chips with USB pull up pin, which doesn't suffer from this problem. Also updates the comments on pin usage. BUG=None TEST=Reset the chips repeatedly. BRANCH=None Change-Id: Iccd7e73fca85abfa554f90dcb7e354cc4cc04626 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197194 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Keyborg: implement matrix scanningVic (Chun-Ju) Yang2014-04-308-3/+479
| | | | | | | | | | | | | | This implements dual chip matrix scanning. Now the scan result is only dumped to debug output. BUG=None TEST=Put a finger on the panel and see its shape. BRANCH=None Change-Id: I015c901b42e24fe4a6249c12c37bc5bfcb308c9f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196468 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32mon: fix STM32F03x flash sizeVincent Palatin2014-04-301-1/+1
| | | | | | | | | | | | | | | | | The current SKU has 32kB. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=read-back the flash content from a Zinger power brick using "stm32mon -r". Change-Id: Id74e585f4b49b9ef5fecdec8182f3710eb0b4960 Reviewed-on: https://chromium-review.googlesource.com/196690 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Add support for the Firefly boardVincent Palatin2014-04-307-1/+539
| | | | | | | | | | | | | | | | | | | Firefly is the test/burn-in board for Zinger production. It's acting a Power Delivery sink. The plug polarity is not managed correctly yet. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: I57f525ad04c519f2fa458635a1c6cc45a503e5ac Reviewed-on: https://chromium-review.googlesource.com/195586 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* pd: handle plug polarityVincent Palatin2014-04-306-25/+54
| | | | | | | | | | | | | | | | | | | | Use the plug polarity detected by the ADCs to do the PD communication on the right CCx line. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28339 TEST=make buildall on Firefly, plug Zinger connector in both direction and see it can control it either way. on Fruitpie, use CC1 or CC2 and see it can communicate on both. Change-Id: I81cb00f164cb8194fba73b383014e81c37d975e2 Reviewed-on: https://chromium-review.googlesource.com/197520 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* pd: update policy, timeout and board callbacksVincent Palatin2014-04-306-28/+49
| | | | | | | | | | | | | | | | | | | | | | | Slightly modify interfaces for better sink-only devices implementation (eg Firefly) update the host mode management and the voltage selection and add a hook for board checks. Simplify the reception timeout and fix other timeout detections. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall and use with the follow-up firefly board configuration CL. Change-Id: I0240295764c8605793dc80a2fc21357af1740744 Reviewed-on: https://chromium-review.googlesource.com/195585 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Added v1 version of ectool gpioget supporting more functionsstabilize-5807.0.BMohammed Habibulla2014-04-293-20/+166
| | | | | | | | | | | | | | | | | ectool gpioget - returns all GPIOs (with flag info) ectool gpioget <GPIO_NAME> - get value of <GPIO_NAME> ectool gpioget count - returns number of GPIOs ectool gpioget all - returns all GPIOs (with flag info) BUG=chromium:344969 TEST="ectool gpioget [<subcmd> <GPIO_NAME>]" returns correct information on squawks BRANCH=none Change-Id: Ib6f0d8135a76501f08b084bfd7eb1f2689d5d6e0 Signed-off-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196680 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: pd: add config option to use SPI master for USB PD trasmitAlec Berg2014-04-295-20/+99
| | | | | | | | | | | | | | | | | | | | | | | Added config option CONFIG_USB_PD_TX_USES_SPI_MASTER which switches to use SPI master for PD transmit. The advantage of SPI master mode is at the end of the tranmission, we don't have to send any dummy 0 bits. When the option is set, the CPU_CLOCK must be set to 38.4MHz, so that the SPI master can generate the correct clock frequency. BUG=chrome-os-partner:28309 BRANCH=none TEST=Tested by connecting two fruitpies together across CC1. One fruitpie has been modified such that the MISO and MOSI lines are swapped and is running PD TX in SPI master mode with 38.4MHz clock, while the other is running PD TX in SPI slave mode. On EC console ran pd charger on one board and pd dev on other board. Verified that communication works with no errors. Ran for 10 minutes in each configuration. Change-Id: Ib24030d34d95d59f4ac6c2dae98bf7adda1ada01 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197215 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Rename battery_vendor_params() to battery_override_params()Dave Parker2014-04-298-25/+28
| | | | | | | | | | | | | | | | | | | | Charger V1 only. This is a clearer name for the intent of the function to override the charging parameters requested by the battery. This also disabmiguates this function with a new host command to get and set arbitrary vendor parameters in the battery. BUG=chrome-os-partner:25145 BRANCH=ToT TEST=`make buildall -j`. Change-Id: I1e8762d359c0e91c5b2a539553d22c12c9850c03 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195823 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197164 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add host command to set battery vendor parametersDave Parker2014-04-295-0/+179
| | | | | | | | | | | | | | | | | | | | Also adds 'battparam' console command. BUG=chrome-os-partner:25145 BRANCH=ToT TEST=Run 'ectool batteryparam set 0 0x1234' 'ectool batteryparam get 0' and on the console: 'battparam 0' 'battparam 0 0x1234' on a board that implements parameter 0. Change-Id: I9cc54d001631f53dd39ae64cfdeececaa1747181 Original-Change-Id: Ib2812f57f2484309d613b23dab12ad43e0417bd2 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195824 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197162
* zinger: remove race condition in event handlingVincent Palatin2014-04-291-0/+3
| | | | | | | | | | | | | | | | | | In the micro runtime for Zinger, wait for events with interrupt disabled to avoid race conditions where the event interrupt happens just after we tested it and before going to sleep. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make BOARD=zinger, test Zinger PD communication from Firefly. Change-Id: I10b919450a61fac7ea50e84dd73bcc568150e179 Reviewed-on: https://chromium-review.googlesource.com/197051 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* util: fix support for dedicated debug dongle in flash_ecVincent Palatin2014-04-291-2/+7
| | | | | | | | | | | | | | | | | | | | | | When using a "non-servo" debug dongle or integrated FTDI chip to flash a STM32 microcontroller, add the option to toggle the reset of the microcontroller if the control exists. This was not done for the original Toad version because it cannot control the reset line, but now Firefly, Zinger, Fruitpie debug interfaces can do it. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=./util/flash_ec --board=zinger Change-Id: Ia21e3b3403e56b4c0797582659d9a3a0c26bb8bb Reviewed-on: https://chromium-review.googlesource.com/197050 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: fix GPIO EXTINT maskingVincent Palatin2014-04-263-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | The external interrupts above 15 are not used for GPIO IRQ handling, but for special purpose interrupts from internal peripherals (e.g. RTC, comparator, wake-up ...). When processing the GPIO interrupts, we should explicitly skip those interrupts, else if a GPIO interrupt happens first followed by another EXTINT, the loop in gpio_interrupt() will try to process it and do an out-of-bound read of the exti_events array. This will retrieve a garbage handler triggering a memory fault. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28296 TEST=on Firefly, press the buttons to trigger GPIO interrupts while there are a bunch of comparator interrupt on EXTIN21 (due to on-going USB PD communication). I no longer see HardFaults. Change-Id: Id90fab30215b0f7f8060c19de63a7ca8418b7b3c Reviewed-on: https://chromium-review.googlesource.com/197019 Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* cortex-m0: fix hard-faults during software interrupt callsVincent Palatin2014-04-251-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From time to time (usually under heavy interrupt load), the runtime on Cortex-M0 was panic'ing at the "svc" instruction with a HardFault exception (inside the wait_event() function). The issue was probably the following : the wait_event() code is doing an atomic_read_clear() whose critical section disables interrupts and re-enables them using "cpsie i", then do __schedule() call which is essentially a "svc" instruction. According to ARMv6-m reference manual : "If execution of a CPS instruction: increases the execution priority, the CPS execution serializes that change to the instruction stream. decreases the execution priority, the architecture guarantees only that the new priority is visible to instructions executed after either executing an ISB instruction, or performing an exception entry or exception return." So, when we are executing the "svc", PRIMASK.PM can still be seen as 1 (while it was set to 0 by "cpsie i") and in that case the software interrupt is replaced by a HardFault. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28296 TEST=run Firefly board under load for extended periods of time. Change-Id: Ie355c36f06e6fe2fee5cca8998a469fa096badad Reviewed-on: https://chromium-review.googlesource.com/196659 Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* battery: don't talk to battery after cut-offLouis Yung-Chieh Lo2014-04-255-7/+86
| | | | | | | | | | | | | | | | | | | | | Add a shortcut in smart battery driver and i2c passthru. Once the battery cut-off order is submitted (in the factory line), the EC will no longer talk to battery. BUG=chrome-os-partner:28248 BRANCH=tot,nyan TEST=See below > remove AC, cutoff: expect system is off. > cutoff, then remove AC: expect system is off. > cutoff, wait for 1 min, then remove AC: expect system is off. Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Change-Id: Ied963c19d17d581ce99e4543469cf2fa165f0439 Reviewed-on: https://chromium-review.googlesource.com/196657 Tested-by: Yung-chieh Lo <yjlou@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
* charger v2: only configure charger when AC is on.Louis Yung-Chieh Lo2014-04-241-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The CL fcf26a4 enabled periodically charge_request(). However, that could fail and generates lots of error message in the EC console if the AC is not on and charger refuses the request (even it is 0v/0mA). BUG=none BRANCH=tot,nyan TEST=make runtests. Tested on big. Expect NO below annoying error message [1.353104 charge_request(0mV, 0mA)] [1.453170 charge_request(0mV, 0mA)] [1.553281 charge_request(0mV, 0mA)] [1.653317 charge_request(0mV, 0mA)] in the follwing cases: AC on, battery attached, power on, then remove/plug in AC. AC on, battery attached, power on, then remove/plug in battery. AC on, battery removed, power on, then plug in and remove battery. AC off, battery attached, power on, then plug in and remove AC. 'chgstate' also shows good state. At final, charge for 10 mins. Change-Id: Icc729c52246df1ecfb7f289b5078dbc122b20a74 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196678 Reviewed-by: Lin Cloud <cloud_lin@compal.com> Tested-by: Lin Cloud <cloud_lin@compal.com> Reviewed-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Keyborg: increase UART baud rate to 38400Vic (Chun-Ju) Yang2014-04-241-3/+3
| | | | | | | | | | | | | | | | We are running a minimal runtime with less overhead. This allows us to run UART at 38400 bps. Let's update the config for easier debugging. Also fix a potential underflow bug. BUG=None TEST=See debug output at 38400 bps BRANCH=None Change-Id: Ic9e4f9d545f5dbc4a0816a843b0f01a4cf219666 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196190 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Keyborg: chip-to-chip SPI communicationVic (Chun-Ju) Yang2014-04-246-12/+585
| | | | | | | | | | | | | | | | | | This implements a simple SPI driver for the two chips to exchange packets. There are both sync interface and async interface. Sync interface is easier to use, and async interface frees the CPU while the DMA takes care of the communication. BUG=None TEST=Hello test passed BRANCH=None Change-Id: I9823bad5cae6d1fa8f3658d17af4b998d3735a3e Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195533 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Keyborg: Implement master/slave identificationVic (Chun-Ju) Yang2014-04-245-3/+170
| | | | | | | | | | | | | | | The two chips work together, so let's teach them how to tell master from slave. After identification, the two chips shake hands through the two sync signals. BUG=None TEST=Disable handshake on master. See slave fail. Vice versa. BRANCH=None Change-Id: Idb6a56128f608dd2ee5c453f75abea475fe1779f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195395 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Big: Correct the charger IC drivercloud_lin2014-04-244-1/+242
| | | | | | | | | | | | | | Add bq24735 driver and move to here for further developing BRANCH=big BUG=None TEST=test basic charing/discharging function Change-Id: I66c22a29cf94383cec86c5cf53db82494504fa77 Reviewed-on: https://chromium-review.googlesource.com/196541 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Tested-by: Lin Cloud <cloud_lin@compal.com> Commit-Queue: Lin Cloud <cloud_lin@compal.com>
* battery: move cut-off commands to common/battery.cstabilize-5791.0.BLouis Yung-Chieh Lo2014-04-239-26/+58
| | | | | | | | | | | | | | | So that host and EC commands will be defined in common/battery.c. The board-specific battery.c can focus on the proprietary method. BUG=chrome-os-partner:28248 BRANCH=tot,nyan TEST=make buildall runtest Tested "cutoff" in EC console on big. Change-Id: I213c0d601d0241c8dea309d6ac60c72452d2d100 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196621 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* charger v2: supports charger watchdogLouis Yung-Chieh Lo2014-04-232-23/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some chargers support a timeout mechanism that it would stop charging if no voltage/current setting comes from battery or EC. This is designed for safety. In charger v1, it always updates charger periodically. But in v2, old code only updates charger when needed. New code updates the charger periodically. Also keep the ability for debugging. A manual mode is introduced so that any requested volt/curr from host and force idle mode request would trigger this mode. To leave this mode, just disable the force idle mode. BUG=chrome-os-partner:28201,chrome-os-partner:28208 BRANCH=nyan TEST=See below. Plug AC and battery. Wait for 10 mins and the battery is charged normally. 'chgstate idle on': the charger doesn't charge the battery. 'chgstate idle off': charge again. Plug in AC and remove battery: No annoying repeated message and works fine. Plug in battery and remove AC: No annoying repeated message and works fine. Power up machine with battery only: No annoying repeated message and works fine. Power up machine with AC only: No annoying repeated message and works fine. Change-Id: I00d62f8afa2fe2627ea9259f11679ced02af897a Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196385
* accel: add accel driver for lsm6ds0Alec Berg2014-04-234-223/+492
| | | | | | | | | | | | | | | | | | | | This adds the basics for the accelerometer potion only of the ST lsm6ds0 accel/gyro. Still need to add the acceleration interrupt functionality, and all of the gyro portion of the chip. BUG=none BRANCH=none TEST=Tested on a samus prototype hacked up to have the lsm6ds0 connected to the EC i2c bus. Added motion sense task to the samus tasklist, added accelerometer information to the samus board file, and tested console functions interacting with accelerometer. The data seems reasonable, and can successfully change data rate and range. Change-Id: I7949d9c20642a40ede82dc291b2c80f01b0a7d8b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196426 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nyan: add info_precharge for drained batteryLouis Yung-Chieh Lo2014-04-224-15/+107
| | | | | | | | | | | | | | | | | | Charger v2 assumes the battery_get_info() always returns non-NULL even if the battery is not detected, for example, in the over-drained situation. Thus, add a new struct so that we know what the conservative setting is to pre-charge the unknown battery. BUG=chrome-os-partner:28112 BRANCH=nyan,big,blaze TEST=See issue tracker for the test procedure. Change-Id: Ica4fe75d154e2f195eb1da19ba045346da383b6c Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195596 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Devin Lu <Devin.Lu@quantatw.com> Tested-by: Devin Lu <Devin.Lu@quantatw.com>
* Squawks: Adjust charge thresholds for altering LED behaviorDave Parker2014-04-221-5/+12
| | | | | | | | | | | | | | | | | | | | | The EC and host have different ways of computing and presenting the battery charge level. This change adjusts the charge levels at which the charging LED indicates a full and low battery to match what is presented to the user in the host UI. BUG=chrome-os-partner:27743,chrome-os-partner:27746 BRANCH=rambi,tot TEST=Run "battfake 91" which charging, verify charging LED turns green and the UI reports 95%. Run "battfake 13" while discharging, verify charging LED blinks amber (1 sec on, 1 sec off) and the UI reports 10%. Change-Id: Iaffffb57a7fbfd14ebb90363cbd4aa1a9becf022 Original-Change-Id: I203c90a65e4aa2907a14077a9276674ecfa292f2 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/194347 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195848
* Fixed the stack overflow bug in 'battery' console command.stabilize-5784.0.BLouis Yung-Chieh Lo2014-04-215-15/+61
| | | | | | | | | | | | | | | | | On the Nyan EC, we almost run out of the stack of console task. Instead of making that struct static or global, we print the cached data. Read the issue tracker for more detailed discussion. BUG=chrome-os-partner:28027 BRANCH=tot TEST=verified on nyan with/without battery. The "battery" console command doesn't crash the system. Change-Id: Id5246724760aed4cf1df827baf115007b2ffb48e Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/194875 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add STM32TS60 supportVic (Chun-Ju) Yang2014-04-2013-0/+533
| | | | | | | | | | | | | | | | This chip got small flash and RAM, so the common runtime is disabled. Now the code only boots and print something every second to check debug console and timer are good. BUG=None TEST=Boot and see console output TEST=make buildall BRANCH=None Change-Id: I01150e8250a404628d1a3b81e677ac4c29782d7f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195382 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* blaze: add ectool discharge commandDevin Lu2014-04-182-0/+13
| | | | | | | | | | | | | | just picks up this commmand for factory. BRANCH=ToT BUG=None TEST=Run ectool chargecontrol command with each option (normal, idle, discharge) on blaze. Verifiy battery can discharge. Change-Id: Id57b42796a26aaf85258048260d06923b78f0773 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195535
* tegra: move to charger v2.Louis Yung-Chieh Lo2014-04-184-15/+3
| | | | | | | | | | | | | | | | | | | This would move all tegra boards to charger v2. Also removed the unnecessary charge_keep_power_off(), which was designed for USB power port and doesn't apply to Tegra platform. BUG=none BRANCH=nyan,big,blaze TEST=build and run on nyan. Change-Id: I9517a8885726ad6dce5a2865402da4b9551e009f Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/194384 Commit-Queue: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Devin Lu <Devin.Lu@quantatw.com> Tested-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cortex-m: store FPU regs on context switchAlec Berg2014-04-183-14/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added storing of FPU regs on context switches when CONFIG_FPU is defined. On context switches, EXC_RETURN[4] is checked in order to tell which tasks have used floating point and which have not. The FPU regs are only stored on task stacks for tasks that use the floating point. Tasks that use floating point will therefore require roughly an additional 128 bytes of stack space, and context switches will take about 32 clock cycles longer for each task involved in the switch that uses FP. For tasks that don't use floating point, the stack usage actually decreases by 64 bytes because previously we were reserving stack space for FPU regs S0-S15 on every context switch for every task, even though we weren't doing anything with them. If a task only uses the FPU for a brief window, it can call task_clear_fp_used() in order to clear the FP used bit so that context switches using that task will not backup FP regs anymore. BUG=chrome-os-partner:27971 BRANCH=none TEST=Tested on glimmer and peppy. Added the following code, which uses the FPU in both the hooks task and the console task. Note, I tested this for a handful of registers, notably registers in the group s0-s15 which are backed up by lazy stacking, and registers in the group s16-s31 which are backed up manually. float dummy = 2.0f; static void hook_fpu(void) { union { float f; int i; } tmp; /* do a dummy FP calculation to set CONTROL.FPCA high. */ dummy = 2.3f*7.8f; /* read and print FP reg. */ asm volatile("vmov %0, s29" : "=r"(tmp.f)); ccprintf("Hook float 0x%08x\n", tmp.i); /* write FP reg. */ tmp.i = 0x1234; asm volatile("vmov s29, %0" : : "r"(tmp.f)); } DECLARE_HOOK(HOOK_SECOND, hook_fpu, HOOK_PRIO_DEFAULT); static int command_fpu_test(int argc, char **argv) { union { float f; int i; } tmp; /* do a dummy FP calculation to set CONTROL.FPCA high. */ dummy = 2.7f*7.8f; /* read and print FP reg. */ asm volatile("vmov %0, s29" : "=r"(tmp.f)); ccprintf("Console float 0x%08x\n", tmp.i); if (argc == 2) { char *e; tmp.i = strtoi(argv[1], &e, 0); if (*e) return EC_ERROR_PARAM1; /* write FP reg. */ asm volatile("vmov s29, %0" : : "r"(tmp.f)); } else { task_clear_fp_used(); } return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(fputest, command_fpu_test, "", "", NULL); When you call fputest 5 from EC console before this CL, then on the next HOOK_SECOND, the value of register s29 is 5, instead of 0x1234 because register s29 is not saved on context switches: Hook float 0x00001234 > fputest 5 Console float 0x00001234 Hook float 0x00000005 When this CL is in use, the register holds the correct value for each task: Hook float 0x00001234 > fputest 5 Console float 0x00001234 Hook float 0x00001234 > fputest Console float 0x00000005 Hook float 0x00001234 Change-Id: Ifb1b5cbf1c6fc9193f165f8d69c96443b35bf981 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/194949 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* lpc: ACPI query-next-event drops masked eventsRandall Spangler2014-04-172-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, you could use EC_CMD_ACPI_QUERY_EVENT to read events that were masked off (that is, events which would not generate SCI/SMI/wake signals). The handlers for those signals on the host would still act on the masked-off events - for example, causing unwanted power button keypresses/releases. Now, EC_CMD_ACPI_QUERY_EVENT will only return events which are unmasked. This does not affect storing of events at event generation time. Events are still queued; they won't be dropped until the host attempts to read the next event. This gives the host a chance to set a mask later in boot (but before querying any events) to capture events which happened early in the boot process. BUG=chrome-os-partner:26574 BRANCH=rambi TEST=At EC console, type 'hostevent set 0x80' but don't press enter. Hold down the power button; UI starts fading to white. Press enter at the EC console to issue the hostevent command. System should continue shutting down, not fade back as if the power button were released. Change-Id: Id2cb14b0979f49cdd42424b9a61b310a2bb506f5 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/194935 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* blaze: implement the power and battery LED behaviorDevin Lu2014-04-175-6/+199
| | | | | | | | | | | | | | | | | | | Add LED behavior for blaze that will the same as falco and kip. BUG=None BRANCH=ToT TEST=manual Check battery LED show Amber when battery in charging. Check battery LED show white when battery fully. Check battery LED show blinking every 500ms when charging error. Check PWR LED light when system power on. Check PWR LED off when system power down. Check PWR LED will blinking every 1sec when system into suspend. Change-Id: I830952361d3282ff78d29a9a33bd09b64b093ee1 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/193744 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
* blaze: add battery configurationDevin Lu2014-04-171-45/+30
| | | | | | | | | | | | | | | | | Set battery cut off command and config battery configuration for blaze. BUG=chrome-os-partner:27120 BRANCH=ToT TEST=manual build ec and flash to blaze board, verify battery works. Verify battery cut off function is workable. Change-Id: I2e1f7de9c6370a2a02fb56fc4520f4bc062b4d6b Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193000 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
* big: Modify LGC battery setting based on battery speccloud_lin2014-04-122-5/+8
| | | | | | | | | | | | | | | | 1. Modify voltage_max 2. Set CP point BUG=chrome-os-partner:27859 BRANCH=Big TEST=Plug in AC and battery, use UART command "charger" to check v_batt and I_in and the values are correct. Change-Id: If83a444338e8d520e6c2f4d04ca6016c14cea8bd Reviewed-on: https://chromium-review.googlesource.com/193584 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Commit-Queue: Lin Cloud <cloud_lin@compal.com> Tested-by: Lin Cloud <cloud_lin@compal.com>
* Smart Battery: Buffer battery parameters while they are updatedDave Parker2014-04-121-33/+34
| | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:27736 BRANCH=ToT TEST=Verify battery charges and 'battery' console command returns sane values. Original-Change-Id: I57d9d432bce4ed28678dddc43fa5166905525557 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193338 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Conflicts: driver/battery/smart.c Change-Id: Idae79859961da888e652b3af306ba49c467b412e Reviewed-on: https://chromium-review.googlesource.com/193655 Tested-by: Dave Parker <dparker@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dave Parker <dparker@chromium.org>
* Zinger board configurationVincent Palatin2014-04-128-187/+502
| | | | | | | | | | | | | | | | | | Add the USB Power delivery PHY configuration, and all the pins and details to use the real Zinger board. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: Ic2d3616c9fd2bf3ebeccba74a5519697e7c3e899 Reviewed-on: https://chromium-review.googlesource.com/194220 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* FruitPie board configurationVincent Palatin2014-04-128-16/+455
| | | | | | | | | | | | | | | | | Add all the pins configuration to use the real FruitPie board and the USB Power Delivery configuration. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make BOARD=fruitpie Change-Id: I8c20118400cb6a2e26b541a9ee2da5b706299fcf Reviewed-on: https://chromium-review.googlesource.com/189862 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: USB Power Delivery physical layerVincent Palatin2014-04-123-0/+497
| | | | | | | | | | | | | | | | | Implementation of the physical layer for USB Power Delivery communication using the STM32 chip. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: I2a4adeef572b97a284bf52ab9d14d23246c56d18 Reviewed-on: https://chromium-review.googlesource.com/189867 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
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