summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* chromeos-ec: Refine FMAP.Hung-Te Lin2012-07-181-37/+33
| | | | | | | | | | | | | Make EC FMAP more compliant to existing devices (EC_RO, EC_RW, RW_FWID), eliminating unnecessary areas (RO_SETION, EC_IMAGE), and add more detailed comments to each area. BUG=chrome-os-partner:11360 TEST=emerge-link chromeos-ec; dump_fmap -x ec.bin Change-Id: I3d30d6fe0d3cee2e944009dccef488f7215b6395 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27739
* Add EC flash protect command to ectoolRandall Spangler2012-07-185-37/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:11150 TEST=manual Enable WP GPIO. Then from a root shell localhost ~ # ectool flashprotect Flash protect flags: 0x00000008 wp_gpio_asserted Writable flags: 0x00000005 ro_at_boot rw_now localhost ~ # ectool flashprotect enable Flash protect flags: 0x0000000b wp_gpio_asserted ro_at_boot ro_now Writable flags: 0x00000004 rw_now localhost ~ # ectool flashprotect enable Flash protect flags: 0x0000000b wp_gpio_asserted ro_at_boot ro_now Writable flags: 0x00000004 rw_now localhost ~ # ectool flashprotect now Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now rw_now Writable flags: 0x00000000 localhost ~ # ectool flashprotect now Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now rw_now Writable flags: 0x00000000 localhost ~ # ectool flashprotect disable Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now rw_now Writable flags: 0x00000000 Unable to set requested flags (wanted mask 0x00000001 flags 0x00000000) Which is expected, because writable mask is 0x00000000. Then disable WP GPIO and reboot localhost ~ # ectool flashprotect Flash protect flags: 0x00000001 ro_at_boot Writable flags: 0x00000001 ro_at_boot localhost ~ # ectool flashprotect disable Flash protect flags: 0x00000000 Writable flags: 0x00000001 ro_at_boot Change-Id: Idc5de3b3033521467aca8fb0ba9b7c378d0ad2a1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27799
* Better handling of corner cases for flash protectionRandall Spangler2012-07-181-13/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If WP isn't asserted, 'flashwp now' does nothing. If WP is already enabled, 'flashwp enable' succeeds. BUG=chrome-os-partner:11150 TEST=manual (disable physical WP) flashwp now flashinfo -> nothing protected flashwp enable flashinfo -> ro_at_boot set, nothing protected (enable physical WP) reboot flashinfo -> ro_at_boot ro_now flashwp enable -> (succeeds) flashwp disable -> fails flashinfo -> ro_at_boot ro_now flashwp now flashinfo -> ro_at_boot ro_now rw_now (disable physical WP) reboot flashwp disable flashinfo -> nothing protected Change-Id: I4660d822886635e71ab1636c737611214852f58c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27798
* Use config values for flash protect/erase/write sizesRandall Spangler2012-07-189-137/+77
| | | | | | | | | | | | Since they're config values anyway. Gets rid of an unneeded layer of function call. BUG=chrome-os-partner:11150 TEST=build link, snow, daisy; flashinfo returns same values Change-Id: I27fa007f64a446f1ec0fe22ae16c5c1ac667f8e9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27797
* Remove flash_read()Randall Spangler2012-07-186-115/+58
| | | | | | | | | | | | | | | | | | | Everything now uses flash_dataptr() to get at flash memory rather than calling the read function, since the read function adds a needless memcpy(). BUG=chrome-os-partner:11150 TEST=manual flashwp enable reboot flashinfo -> should show ro_at_boot flashwp disable reboot flashinfo -> should no longer show ro_at_boot Change-Id: I1830e2f036cf6777115c782c1737335ff2eb4ce0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27796
* Continue refactoring flash write protectRandall Spangler2012-07-183-54/+84
| | | | | | | | | | | | | | | | | | | | | Now properly detects partially-protected flash banks. Also renames 'flashwp lock/unlock' to 'flashwp enable/disable' BUG=chrome-os-partner:11150 TEST=manual ww 0x400fe400 0x7fffffff flashinfo -> ro_now PARTIAL reboot ww 0x400fe404 0x7fffffff flashinfo -> rw_now PARTIAL flashwp now flashinfo -> ro_now rw_now (and NOT partial) Change-Id: I9266a024eee6d75af052cd47e3f54468ad959a12 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27795
* Move looking at write protect GPIO to button/switches moduleRandall Spangler2012-07-183-9/+22
| | | | | | | | | | | | | | | | | | Since that already monitors the WP signal for reporting it as a switch. And if we have that code in two places and the WP signal polarity changes, we'll inevitably forget to change it in the other place... BUG=chrome-os-partner:11150 TEST=manual flashinfo -> WP pin asserted remove WP screw flashinfo -> WP pin deasserted Change-Id: I6091c8bb470c357e02ede8a5b184b2a76b70dc60 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27720
* Stop reporting keyboard recovery switchRandall Spangler2012-07-181-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | This uses the new keyboard recovery EC event to determine when keyboard recovery is requested. It is paired with a change to the EC to stop reporting keyboard recovery as a switch, since that didn't provide a good mechanism for the AP to tell the EC to stop reporting the switch value. This REQUIRES an updated BIOS; without it you won't be able to get into recovery mode manually. You'll need to press space at the developer screen, or use the debug console to request recovery. Your BIOS must have https://gerrit.chromium.org/gerrit/27509. BUG=chrome-os-partner:10034 TEST=manual 1. boot using power+refresh+esc. See insert screen. 2. power button to power off 3. power button to power on. Boots to Chrome OS (not insert screen). Change-Id: I699ce004ed1190044170c4ea810b8969b40f523b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27508 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Continue simplifying flash write protectRandall Spangler2012-07-183-101/+39
| | | | | | | | | | | | Now that read-only code is protected iff the persistent state is locked, we don't need to track per-block in the persistent state. BUG=chrome-os-partner:11150 TEST=if it builds and boots, it's fine Change-Id: I80e6a85c0c72136b7ed8964ce02c8abdbaafe637 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27719
* Move flash commands into flash_common.cRandall Spangler2012-07-183-236/+227
| | | | | | | | | | | In preparation for more flash refactoring. BUG=chrome-os-partner:11150 TEST=build link, snow Change-Id: If877e5ebee5af0f9b167ec7b28fd9d718d0108ec Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27718
* Simplify flash protection, part 1Randall Spangler2012-07-189-177/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | 1. If the flash protection state is locked, RO firmware is explicitly locked. 2. Protecting flash now locks the entire flash. BUG=chrome-os-partner:11150 TEST=manual flashinfo -> nothing protected flashwp now flashinfo -> unlocked,applied; everything protected reboot flashinfo -> nothing protected flashwp lock -> flashinfo -> locked,applied; now has 40 Y's at start and 1 at end reboot flashinfo -> locked,applied; now has 40 Y's at start and 1 at end remove WP screw reboot flashinfo -> locked, not applied; nothing protected flashwp unlock flashinfo -> nothing protected Change-Id: I2cf0e8bfe82ab7a5bf88b9161b7a05b889cae71a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27717
* Remove the keyboard "cold reset" hackDuncan Laurie2012-07-181-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This was needed because we could not do a clean reset with CF9 and were relying on the keyboard reset pulse to trigger a cold reset. However it has the downside of causing a kernel panic to be a cold reset and the kernel panic information in memory is lost. Now that we have a VR workaround this hack can be disabled and the keyboard can instead issue a warm reset. BUG=chrome-os-partner:11036 TEST=manual 1) install this EC on a Link device and boot 2) log in and execute "echo panic > /proc/breakme" 3) after reboot look for kernel entry in /var/spool/crash Change-Id: I1134618f0a202d37aaae69a1d857fa8853a7e52c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27722 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Remove old flash WP commandsRandall Spangler2012-07-182-145/+2
| | | | | | | | | | | | These don't accurately reflect how flash write protect was/is implemented. BUG=chrome-os-partner:11150 TEST=build link, snow Change-Id: I126253a2ce05e5d3a51471c32211e6cacbfd85d4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27716 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* ir357x: update voltage regulator settingsVincent Palatin2012-07-181-30/+85
| | | | | | | | | | | | | | | | | | | | - add settings for IR3570A - disable low voltage fault and keep ready signal when SVID=0. (on IR3571 and IR3570A) - match IR3571 settings with IR3571_REV7_DRC_6_28_12 to ensure we are meeting all power requirements. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8397 chrome-os-partner:10171 TEST=on Link EVT with IR3571 and Link EVT reworked with IR3570A, test reboot and RC6+. Change-Id: Ibe34e3c6f0de1e6a08d526fe5fce743feb42645c Reviewed-on: https://gerrit.chromium.org/gerrit/27504 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Set power LED to green when we are trickle charging nearly fullVic Yang2012-07-183-28/+34
| | | | | | | | | | | | | | | | | | | When battery is nearly full, battery sometimes demands for very low current and we are actually trickle charging. This causes the last part of charging process very long, but the actual charged amount is only few mAh. Let's set power LED to green in this case so that user doesn't feel the device is charging forever. BUG=chrome-os-partner:11248 TEST=Charge the battery to nearly full. Disconnect and connect AC power. Check the power LED is green when we are trickle charging. Change-Id: Ide108778232e9f1d3abe6b61af7518af25040d10 Reviewed-on: https://gerrit.chromium.org/gerrit/27264 Commit-Ready: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Enable Lucas EC WP again.Louis Yung-Chieh Lo2012-07-182-26/+95
| | | | | | | | | | | | | | | | | | | | | | | | | Uncomment back the old code and fix the bug of WRP bit definition and also write_opt(). Note that to make this functional, wp_pin_asserted() always returns true. Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Change-Id: Ic09d3346ca68a2700697ff863f0fa08525129b11 BUG=chrome-os-partner:9849 TEST=run on lucas. > flashwp set 0 0x1f000 > flashwp lock > flashinfo # ensure the setting is right. stm32mon -r to read the firmware. stm32mon -w to write a different image. stm32mon -r to read again and compare the firmware is non-changed. > flashwp unlock Command returned error 1 stm32mon -u to unlock write protection. Reviewed-on: https://gerrit.chromium.org/gerrit/27503 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
* gaia_power: Allow AP power to be controlledSimon Glass2012-07-171-2/+37
| | | | | | | | | | | | | | | | Enhance the power command to support turning power on/off. Do this by requesting the state of the main power control loop, rather than hacking in new states or flags. BUG=chrome-os-partner:11427 TEST=manual Try 'power on' and 'power off' and see that it obeys. Change-Id: Ie6db41dda16176818510f8902ab803e165494424 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27654 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* gaia_power: Add power command to check power state.Simon Glass2012-07-171-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to see the current AP power state, and x86 has a command for this. Add one for gaia. BUG=chrome-os-partner:11427 TEST=manual (start with power off) > powerinfo off (press power button) > [batt] state idle -> pre-charging AP running ... Power button released Setting pwron timer 10038870 powerinfo on > Releasing pwron (after kernel boots, make device go into suspend by typing this at kernel command line: type echo mem > /sys/power/state) > powerinfo suspend Change-Id: I3244b3a7fd0b6dd689f3470fb97ffe5a72c8d8f9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27653 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* stm32mon supports read unprotection.Louis Yung-Chieh Lo2012-07-171-5/+36
| | | | | | | | | | | | | | | | | Details please refer to AN3155 document. BUG=None TEST=run on real machine. % stm32mon -U % stm32mon -u % stm32mon -w new_image Change-Id: I070e18a7cb112afe0ab0d0f0bd06cecc4eefb37e Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27630 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
* Tidy debug output for reboot commandRandall Spangler2012-07-171-1/+1
| | | | | | | | | | | | Should print what command is being executed, to help debug software sync BUG=chrome-os-partner:11087 TEST=power on system, look for updated debug message, for example [1.636893 Executing host reboot command 5] Change-Id: Ib543fc265fe881dc2089119ab3c0a52b0fce3b4d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27659
* Rename ROLLBACK constant to PSTATERandall Spangler2012-07-171-5/+7
| | | | | | | | | | | | Since flash_common calls the top bank of flash pstate, use the same nomenclature in config.h BUG=none TEST=build link Change-Id: I22efe7d0fd3a24bc0b2b4a6632406f0e1e529dc6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27662
* Fix I2C arbitration timeout when chipset is suspendedRong Chang2012-07-171-2/+3
| | | | | | | | | | | | | | | When system is off or suspended, board_i2c_claim() should not wait for AP's signal. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:11285 TEST=manual Put AP into suspend Type 'i2c r 0x90 0' and see that no arbitration error is obtained. Change-Id: I22243457fc29bc6c88f413ce0660c700e54f6761 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27498
* daisy: Re-read suspend gpio when asked for chipset stateRong Chang2012-07-171-0/+7
| | | | | | | | | | | | | | | | | | The SUSPEND_L GPIO is marked interruptable, but this apparently does not work, and the gaia_suspend_event() function is not updated as expected. As a workaround, check the GPIO value on ever call to chipset_in_state(). BUG=chrome-os-partner:11285 TEST=manal Using new 'power' command check that the state updates when the AP is in suspend from 'on' to 'suspend'. Change-Id: I9c520e69b9910c649bf6d8381ee167da6facc634 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27652 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Don't waste space on vblock and root key if not doing sig-based EC vbootRandall Spangler2012-07-172-8/+29
| | | | | | | | | BUG=chrome-os-partner:11455 TEST=dump_fmap build/link/ec.bin; shouldn't see VBLOCK or ROOT_KEY sections Change-Id: I8c1309936d86772fdf9aecdc8d95f0578ef0f65b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27661
* Rename section A to RW, to match other platformsRandall Spangler2012-07-176-43/+43
| | | | | | | | | | | | | BUG=chrome-os-partner:11149 TEST=make link, snow, bds; on reboot, sysjump rw sysinfo <- should indicate current image is rw Then on root shell, ectool version <- should indicate rw Change-Id: I833fcb814165379dd044e4cb46ae338e5da81212 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27660
* Remove firmware BRandall Spangler2012-07-1715-171/+22
| | | | | | | | | | BUG=chrome-os-partner:11449 TEST=build link, snow, bds; ectool reboot_ec cold to make sure enums line up Change-Id: Ie09db2080a00f1a7e2c05579b9b41ea5137c1af0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27658 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Rename A and B images to RW and RW_B, part 1Randall Spangler2012-07-1712-96/+97
| | | | | | | | | | | | | | | | | | | All of our current EC configs have RO and a single RW image. Calling that image 'A' is confusing, particularly when combined with EC software sync (where the RW image is updated from either the A or B AP RW firmware). So, rename it. This changes all the build artifacts and constants. Internal EC commands and host commands still refer to A/B; that will be fixed in part 2. BUG=none TEST=build link, snow, bds Change-Id: Icfed4914745f0799bb71befb6a6563cfd8bc90ab Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27649 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fix a bug in I2C host command handlerVic Yang2012-07-161-0/+1
| | | | | | | | | | | | | Signed-off-by: Vic Yang <victoryang@chromium.org> BUG=none TEST='ectool i2cread' succeed. Change-Id: I0639c340b600ff5e07b9c0aa707fe335e90771b5 Reviewed-on: https://gerrit.chromium.org/gerrit/27599 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Ready: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* Append "shift" to version string in shifted imageVic Yang2012-07-161-0/+4
| | | | | | | | | | | | | | | | For EC update test, we produce binary-wise shifted image. To make it easier to tell if update has succeeded, let's append "shift" to the verison in this image. BUG=chrome-os-partner:10264 TEST=Build shifted image and check the version string. Change-Id: I16187611cf61fc97a74bc3707a77ad9ad5274f37 Reviewed-on: https://gerrit.chromium.org/gerrit/27577 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Ready: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* Flash pre-init reboots if it needs to clear protection registersRandall Spangler2012-07-168-26/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:11171 TEST=manual 1. Clear some of the writable-bits in the flash registers > ww 0x400fe40c 0xffff1234 write 0x400fe40c = 0xffff1234 > rw 0x400fe40c read 0x400fe40c = 0xffff1234 2. Reset using power+refresh 3. Register should be clear again > rw 0x400fe40c read 0x400fe40c = 0xffffffff 4. Sysinfo should indicate reset-pin reason AND hard-reset reason > sysinfo Reset flags: 0x0000000a (reset-pin power-on) 5. Reset using power+refresh 6. Sysinfo should indicate reset-pin reason only > sysinfo Reset flags: 0x00000002 (reset-pin) 7. Clear writable-bits again > ww 0x400fe40c 0xffff1234 write 0x400fe40c = 0xffff1234 8. Jump to another image. This should NOT trigger a hard reset. > sysjump A > sysinfo Reset flags: 0x00000402 (reset-pin sysjump) Change-Id: Ie1d6af2acc68217bb82faae464798ee85d63d1ea Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27540 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Print console messages for overtemp and shutdownDuncan Laurie2012-07-162-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | I have a system with bad temperature sensors and the EC is constantly shutting the system down, but provides no visible indication that it is doing so. I have serious concerns about the EC behavior in this case as it seems to be doing things it shouldn't. However just providing indication via the console about what it is doing is at least useful for development and debug. BUG=none TEST=boot on system with bad temp sensors and see that the EC indicates it is initiating a shutdown. [14.008340 critical temperature; shutting down] [14.008660 x86 power force shutdown] [14.009153 LPC RESET# asserted] Change-Id: I6beeb269a135bd8c245c0357670fe29648d48968 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27553 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix return code from ectoolRandall Spangler2012-07-161-39/+42
| | | | | | | | | | | | | lbplay and burn_my_ec didn't have this problem. BUG=chrome-os-partner:11402 TEST=ectool lightbar init && echo $? Should echo 0 Change-Id: I7e9585555cc285ff02502fd4e6bb80e41c889e9d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27527 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Support preserving reset flags across a resetRandall Spangler2012-07-165-20/+42
| | | | | | | | | | | | | | | | | | | | This is needed for flash pre-init to be able to hard reset to clear uncommitted write protect flags without losing the reset flags. BUG=chrome-os-partner:11368 TEST=manual Use reboot and sysinfo commands... 1. reset with keyboard. flags -> reset-pin 2. 'reboot soft preserve' flags -> soft reset-pin power-on 3. 'reboot hard preserve' flags -> hard soft reset-pin power-on 4. 'reboot soft'. flags -> soft 5. 'reboot hard'. flags -> hard power-on Change-Id: I6164a78d99c5c10330f90f651148c5795e7afdda Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27418
* Refactor reset reasonsRandall Spangler2012-07-168-124/+224
| | | | | | | | | | | | | | | | | | | | | | | | | Reasons are really bitflags, not a single reason. This will make it easier to implement flash protection on LM4, where hibernate is a subset of power-on reasons. Also added some additional flags we pass in a hibernate register so... 1) We don't recognize spurious RTC wake reasons 2) Hard reset via system_reset(1) is detected as a hard reset, not a RTC wake BUG=chrome-os-partner:11368 TEST=manual 1. Keyboard reset = power-on reset-pin 2. Pull battery = power-on 3. reboot = soft 4. reboot hard = power-on rtc-alarm 5. hibernate 10 then push power button = power-on wake-pin 6. reboot 3 sec later = soft 7. hibernate 1 = power-on rtc-alarm Change-Id: Icbbdbcf6dfd13c8a6a4f80a23f64cebebbfba26e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27417
* Use openocd auto-erase when writing flash, and use sysresetreq to resetRandall Spangler2012-07-162-8/+7
| | | | | | | | | | | | | | | According to its datasheet, LM4 doesn't support vectreset, but does support sysresetreq. Using sysresetreq properly resets all peripherals and cleanly resets the LM4. Auto-erase makes the flash command faster. BUG=none TEST=flash_link_ro, flash_link_a, flash_link, all with different images Change-Id: I80b72de2ee0f42cee1b0f2f2a53062384d2c29aa Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27416
* Refactor HIBDATA access so we can use multiple hibernate regsRandall Spangler2012-07-162-34/+55
| | | | | | | | | BUG=chrome-os-partner:11368 TEST=none Change-Id: I33ba317ce1cff957add7ebe34860fa4a3c686ca0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27380
* Debounce charging voltage when cross 8.0VRong Chang2012-07-152-18/+55
| | | | | | | | | | | | | | | | | | | | | Link battery pack specification suggested a lower charging current when voltage pass 8.0V. But the lowering the current in constant current phase leads voltage drop. And the battery goes back to high current zone, < 8.0V. This CL adds a 10 seconds debounce time to prevent charging current change too quickly. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:9572 TEST=manual watch battery V+ on oscilloscope when charging voltage cross 8.0V Change-Id: I002f941e33b029e38f813ab2e292c6b73a054352 Reviewed-on: https://gerrit.chromium.org/gerrit/27275 Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* Define __packed inside ec_commands.hRandall Spangler2012-07-131-0/+8
| | | | | | | | | | | | Kernel and U-boot define it elsewhere, but coreboot doesn't. So put it here for greatest compatibility. BUG=none TEST=if it builds it works Change-Id: I595910e9198e37bc97d23cd4c249454e1ed64cd8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27375
* Security fix: bounds check in vboot_hash_start()Bill Richardson2012-07-131-8/+8
| | | | | | | | | | | | | | | Changed the parameters from int to uint32_t (which is how it was called anyway). BUG=chrome-os-partner:11045 TEST=manual No visible change. Nothing should break. Change-Id: I4fbe34f67df7d37f5039987a7a89e626916d6eb6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27382 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Security fix: check lightbar_sequence num paramBill Richardson2012-07-131-1/+1
| | | | | | | | | | | | | | | Make sure that a negative 'num' param won't be accepted if passed by a malicious caller. BUG=chrome-os-partner:11048 TEST=manual No visible changes, everything should continue to work. Change-Id: I8128d24adc99e5ff954a6b8065e1bfa8bf20630e Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27386 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Security fix: validate index in controller_write()Bill Richardson2012-07-131-0/+2
| | | | | | | | | | | | | | Make sure it doesn't run off the end of the I2C device list. BUG=chrome-os-partner:11051 TEST=manual No visible changes. Everything should continue to work. Change-Id: I43182361cda6be578e57acef01afb27260cea80a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27390 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charger: Add delay in tasker task to avoid lockupSimon Glass2012-07-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The charger task relies on calc_next_state() performing a delay before returning. My reading of the code suggests that this doesn't happen always. For example: When pre-charging: if (battery_temperature(&batt_temp) == EC_SUCCESS) return ST_CHARGING; When discharging and capacity is low: /* Check remaining charge % */ if (battery_state_of_charge(&capacity) == 0 && capacity < 10) return notify_battery_low(); I would like to suggest that the code be refactored to more like: int next_checkms = 5000; /* next time to check battery */ while (1) { int action = ACTION_NONE; err = get_state(&state); if (!err) { action = calculate_action(&state); err = perform_action(action, &next_check_ms); } usleep(next_check_ms * 1000); } so that the delays are really clear, the state is all read at once, there is no reliance on earlier state, and we always delay even on error. In the meantime, this CL inserts a mandatory 5 second delay in the loop, which should prevent the charger task lockup. BUG=chrome-os-partner:11285 TEST=manual (please do this test before committing) 1. boot to kernel, see that battery can be seen 2. suspend and resume device 3. see that the charger loop does not cause an EC watchdog reset and AP power off/reset. There should be no watchdog warning message on the EC console. Change-Id: I141e374933c4dc0ec60bcdccf96443f57067c585 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27353 Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Katie Roberts-Hoffman <katierh@chromium.org> Commit-Ready: Katie Roberts-Hoffman <katierh@chromium.org>
* Add GPIO get/set host commandVic Yang2012-07-133-1/+144
| | | | | | | | | | | | | | | | These commands are used in factory test. If system is locked, GPIO commands are disabled for security reason. BUG=chrome-os-partner:11164 TEST= - 'ectool gpioget enable_backlight' gives 1. - 'ectool gpioset enable_backlight 0' turns off display. - Lock system. Check these commands return error. Change-Id: I3ea41285075ebe963ba7d30e4ae183cef9b1c105 Reviewed-on: https://gerrit.chromium.org/gerrit/27019 Commit-Ready: Vic Yang <victoryang@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* Fix unit testsVic Yang2012-07-1317-33/+112
| | | | | | | | | | | | | | Recently, there have been several changes to LPC and host command modules. This CL fixes unit tests after these changes. BUG=none TEST=All test passed. Change-Id: I263716899af78a61e324fcd0b2636b948617a264 Reviewed-on: https://gerrit.chromium.org/gerrit/27354 Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Ready: Vic Yang <victoryang@chromium.org>
* Add a test of flash read/write/erase testVic Yang2012-07-135-5/+72
| | | | | | | | | | | | | | This test checks physical read/write/erase functions are called correctly. BUG=chrome-os-partner:10261 TEST=Test passed. Change-Id: Iff58f352bd732a0da9b7b7fe68c4bf87c84906a8 Reviewed-on: https://gerrit.chromium.org/gerrit/27144 Reviewed-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Ready: Vic Yang <victoryang@chromium.org>
* Add a host command to force charge state in IDLE modeVic Yang2012-07-123-2/+70
| | | | | | | | | | | | | | | This command should only be accessible when flash write protect is unlocked. BUG=chrome-os-partner:9716 TEST= - Check we can charge and discharge normally. - Connect AC and force idle. Check battery current is 0 mA. Change-Id: I74a318c1f5562d6a23b722736615fd1f883dc35a Reviewed-on: https://gerrit.chromium.org/gerrit/27259 Commit-Ready: Vic Yang <victoryang@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* Add keyboard recovery eventRandall Spangler2012-07-124-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | This is set when the EC boots and sees the recovery key combo. This is preferable to the memmap'd keyboard recovery switch, which the host has no way of clearing. The idea is that the host RO firmware reads this event and sets the recovery reason. I will be removing the memmap'd keyboard recovery switch once U-boot and coreboot check this new event. BUG=chrome-os-partner:10034 TEST=manual 1. power+esc+refresh; should see this even in EC log [0.000838 event set 0x00004000] (time of event may vary) 2. reboot EC; should NOT see the event Change-Id: Id0672749f63c5022624a72ec91d30dcadfea5ef8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27328
* Add ectool support for get/clear event B flagsRandall Spangler2012-07-121-0/+56
| | | | | | | | | | | | BUG=chrome-os-partner:11172 TEST=from root shell eventget b -> 0x2088 eventclear b 0x80 eventget b -> 0x2008 Change-Id: Ic0ad6475f2b770522b50b51f6695c6ea77ced19a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27322
* Simplify host event processingRandall Spangler2012-07-125-62/+65
| | | | | | | | | | | | | | | | | | | | | | | | Now both copies of the event state live in host_event_commands.c, and lpc / memmap just shadows the main copy. BUG=chrome-os-partner:11172 TEST=manual Boot system. should see events 0x2000, 0x80, 0x08 get set and then cleared. At U-boot prompt, type on keyboard. Should set event 0x1000 get set, but only on the first keypress (because U-boot doesn't consume that event). Then from EC console, hostevent clear 0x1000 -> see event 0x1000 clear hostevent clear 0x1000 -> no debug output (it's already clear) hostevent clearb 0x1000 -> see event copy B 0x1000 clear hostevent clearb 0x1000 -> no debug output (copy B is already clear) Change-Id: I855c035865649ba1490cd9027157d5bcdcc9895f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27321
* Add second copy of event stateRandall Spangler2012-07-123-8/+56
| | | | | | | | | | | | | | | | | | U-boot and ectool need this to see what events have occurred, in a way which doesn't conflict with ACPI/SCI/SMI. BUG=chrome-os-partner:11172 TEST=manual - boot EC - look at event set / event clear debug output; that's for copy A - from ec console, hostevent -> events=0, events-B = 0x2088 hostevent clearb 0x2000 -> events-B = 0x88 Change-Id: If842b157914426df593d82af2bfb08a923caa34b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27317
View Lorry Controller Status