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* bq25710: Refactor Vmin Active Protection register initializationCaveh Jalali2021-11-131-18/+29
| | | | | | | | | | | | | | | | This separates the initialization of the Vmin Active Protection register into a dedicated function. BRANCH=none BUG=b:185190976 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ib75d028c0a5bb5982fe34bf756a68f942769fad1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3277939 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Keith Short <keithshort@chromium.org>
* bq25710: Make VSYS_TH2 Kconfig friendlyCaveh Jalali2021-11-1311-18/+39
| | | | | | | | | | | | | | | | | | | This adds the CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM config option to decide if CONFIG_CHARGER_BQ25720_VSYS_TH2_DV should be applied. It is no longer sufficient to set CONFIG_CHARGER_BQ25720_VSYS_TH2_DV to the desired value. This matches how defines are generated by kconfig and allows IS_ENABLED() to be used. BRANCH=none BUG=b:185190976 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ie3a6aa2d585d7975ada2863fd20ad296b23d504c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3277938 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: brya: Add power sequencing support using shimDivya Sasidharan2021-11-126-7/+125
| | | | | | | | | | | | | | Add required configs for power sequencing brya. BUG=b:200975143 BRANCH=main TEST=zmake testall; check AP power state transitions to S0, verify booting up to kernel. Change-Id: Ib02cc4dc1be11af024f485efd5b73c613a4d1ac2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3176402 Reviewed-by: Keith Short <keithshort@chromium.org>
* core/cortex-m0: Use symbolic name instead of r0Tom Hughes2021-11-121-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With gcc, the generated assembly for exception_panic after this change removes a "adds r0, r0, #0" instruction and a nop. 00000000 <exception_panic>: 0: 4b08 ldr r3, [pc, #32] ; (24 <exception_panic+0x24>) 2: 4809 ldr r0, [pc, #36] ; (28 <exception_panic+0x28>) 4: 469c mov ip, r3 ; No more "adds r0, r0, #0" here 6: f3ef 8109 mrs r1, PSP a: f3ef 8205 mrs r2, IPSR e: 466b mov r3, sp 10: c0fe stmia r0!, {r1, r2, r3, r4, r5, r6, r7} 12: 4641 mov r1, r8 14: 464a mov r2, r9 16: 4653 mov r3, sl 18: 465c mov r4, fp 1a: 4675 mov r5, lr 1c: c03e stmia r0!, {r1, r2, r3, r4, r5} 1e: 46e5 mov sp, ip 20: f7ff fffe bl 0 <exception_panic> ; No more nop here 24: 20003f70 .word 0x20003f70 28: 20003f74 .word 0x20003f74 BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=c2d2 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I5282369fd97a21b5927175adecff2ba74c4f8fc3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213608 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/cortex-m: Use symbolic name instead of r0Tom Hughes2021-11-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This assembly is supposed to force the compiler to use r0 for pregs and r12 for pstack. When compiling with clang, it uses r12 for pregs and r0 for pstack, so the "stmia r0" instruction is using the wrong value. Instead of assuming that pregs will be in r0 and pstack will be in r12, just use the symbolic name ("pregs") with the stmia instruction. This generates the correct behavior regardless of whether pregs or pstack use r0 or r12. With gcc, the generated assembly for exception_panic after this change removes the "mov r0, r0" instruction and adds a nop at the end: 00000000 <exception_panic>: 0: 480e ldr r0, [pc, #56] ; (3c <exception_panic+0x3c>) 2: f8df c03c ldr.w ip, [pc, #60] ; 40 <exception_panic+0x40> ; No more "mov r0, r0" here 6: f3ef 8109 mrs r1, PSP a: f3ef 8205 mrs r2, IPSR e: 466b mov r3, sp 10: 05d6 lsls r6, r2, #23 12: bf1c itt ne 14: 2400 movne r4, #0 16: 2500 movne r5, #0 18: f04f 0600 mov.w r6, #0 1c: f04f 0700 mov.w r7, #0 20: f04f 0800 mov.w r8, #0 24: f04f 0900 mov.w r9, #0 28: f04f 0a00 mov.w sl, #0 2c: f04f 0b00 mov.w fp, #0 30: e880 4ffe stmia.w r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 34: 46e5 mov sp, ip 36: f7ff fffe bl 0 <exception_panic> 3a: bf00 nop ; adds nop instruction BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=bloonchipper TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I150d685bde701171630ae02b16e6050e1e0e77a6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213606 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* zephyr: flash: npcx: Fix physical_get_protect_flags()Jun Lin2021-11-121-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | Protecting status register by /WP works when SRP0 is enabled. The getting protect flags function should check Status Register Protect 0 (SRP0) bit & Quad Enable (QE) bit for EC_FLASH_PROTECT_ERROR_INCONSISTENT flag. This CL adds the following: 1. SRP0 & QE bits check for npcx flash. 2. EC_FLASH_PROTECT_ERROR_UNKNOWN flag This change aligns with the change in the CL:3246882 of ECOS. BUG=none BRANCH=none TEST=Protect a range & don't set the SRP0. Check flag by `flashinfo`. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I1e53222c25b7d74681961c6e78fbf05a590665eb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3268038 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: flash: npcx: Disable flash QE bit at initJun Lin2021-11-121-17/+42
| | | | | | | | | | | | | | | | | | | | | In NPCX9 production devices, the flash status register’s quad enable bit (non-volatile) will be set by default. When the QE bit of Status Register-2 is set for Quad I/O, the WP# signal is not supported since this pin is used as IO2. This CL clears the QE bit at init to make sure WP# support is enabled. This change aligns with the change in the CL:3246881 of ECOS. BRANCH=none BUG=none TEST=Set QE bit & reboot the ec. Check the QE bit is disabled. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: Ide93ce466b61ed3358488bb91c07f9a62bce7fa1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3268037 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: flash: npcx: Refactor flash_get_status()Jun Lin2021-11-121-35/+16
| | | | | | | | | | | | | | | | | | | | | NPCX internal flash status register 1/2 are always read at the same time. This CL merges flash_get_status1() and flash_get_status2() into one function. This improves the performance by eliminating duplicate mutex function call operations. This change aligns with the change in the CL:3247742 of ECOS. BUG=none BRANCH=none TEST=write status1/2 registers with different values, read them back with console command "flashchip" Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I414424401df22eaa577d3e5238cdeae06eb5e61d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3268036 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: fix CONSOLE_READ_NEXTKeith Short2021-11-121-1/+4
| | | | | | | | | | | | | | | | | Running "ectool console" from the AP uses the subcommand CONSOLE_READ_NEXT, but this never returned valid data. Fixed by setting the current snapshot head, to the current buffer head instead of current buffer tail. BUG=none BRANCH=none TEST=Run "ectool console", verify console data is shown. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I9cbd7c11f1a0695370454f1687c1be7205a2b4d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3278638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Configure tcpci gpio alerts in testJeremy Bettis2021-11-123-3/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIOs to overlay.dts. Setup GPIO interrupts in gpio_map.h. Implement tcpc_alert_event. This should probably be in a zephyr stub instead, but today, this is board specific. Add init hook to enable the usbc interrupts. Interrupts have to be enabled by a driver or board, and these are normally enabled by the board. BRANCH=None BUG=b:201314530 TEST=Observed in gdb. Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I23bb328ffd5402e923abf8464395ca1dd2dd86de Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3269060 Tested-by: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* qcom: Add checks for EFS2 to the power on sequenceKeith Short2021-11-121-7/+16
| | | | | | | | | | | | | | | | | | | | | | | When EFS2 is enabled, the normal boot will always have the EC_RESET_FLAG_SYSJUMP set. Always enabled auto power on of the AP unless one of the following conditions is true: 1. EC_RESET_FLAG_AP_OFF reset flag is set 2. EC_RESET_FLAG_SYSJUMP reset flag is set, and EC_RESET_FLAG_EFS is not set. BUG=b:193719620 BRANCH=none TEST=Verify EC powers up AP after performing a sysjump when EFS2 is enabled. TEST=Set recovery mode, verify EC goes back to RO. On power down, EC jumps to RW and the AP stays in G3. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I222c5f6c729901b455888432cd01fe7e67b4aa7a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3257770 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ectool: Change "ectool temps all" output similar to EC console commandB R, Harsha2021-11-122-14/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Retrieve sensor name and thermal fan percentage. To the print statement add additional parameters - sensor_name, temperature converted from kelvin to Celsius and thermal_fan_percent in addition to temperature reading in Kelvin. Also update the display and help message of temps command for both EC and CPU console Sample output: 21-11-12 23:48:28.062 DDR and SOC 314 K (= 41 C) 40% CPU Console: localhost ~ # ectool temps all --sensor name -------- temperature -------- fan speed -- DDR and SOC 314 K (= 41 C) 40% BRANCH=none TEST=make buildall -j, zmake testall, Run ectool temps all on CPU console and Run temps all on EC console, See a sample output above Signed-off-by: B R, Harsha <harsha.b.r@intel.com> Change-Id: Id86652d426fdbf30a1b27db8c2d2e7ce1b9a1d4c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3252569 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
* ectool: Add 'tsv' parameter to usbpdmuxinfoDrew Davenport2021-11-121-13/+49
| | | | | | | | | | | | | | | | | | The 'tsv' parameter can be used to output in tab-separated-value form, which is intended to be parsed in scripts or programs. Column definitions can be accessed in the ectool help command. BRANCH=none BUG=b:205858702 TEST=Run `ectool usbpdmuxinfo` with various arguments Change-Id: Ifcf3eb76815e071b2e43cf244a5345a40fc6771e Signed-off-by: Drew Davenport <ddavenport@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3278632 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Drew Davenport <ddavenport@chromium.org> Tested-by: Drew Davenport <ddavenport@chromium.org>
* zephyr: flash: npcx: move the flash operations to upstreamJun Lin2021-11-1214-472/+216
| | | | | | | | | | | | | | | | | | | | | | | | In PR:39644, the SPI (FIU/UMA) driver is added to the Zephyr upstream. The flash access now can be via the flash APIs in spi_nor driver, including flash write/read/erase/read_jedec_id. Note that because there is no API in the flash driver to read/write the status register, it is implemented here via the spi_transceive API. BRANCH=none BUG=b:202295086 TEST=pass "zmake testall" TEST=enable flash console command on volteer and npcx9_evb, test the following flash related commands: flashread/flashwrite/flasherase/flashwp/flashchip/flashinfo. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Cq-Depend: chromium:3261416 Change-Id: I012ea359695a22cbb54d39124b4b78ff95cca36d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3261447 Tested-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Guybrush Zephyr: Add LED controlDiana Z2021-11-124-0/+132
| | | | | | | | | | | | | | | | Add PWM definitions for LEDs and copy the board LED control code for the on/off states. BRANCH=None BUG=b:195137794 TEST=on guybrush, verify charging LED when charging, white LED when on, blinking white in suspend Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I80ea849e8f1267c090a995a4b74275a88006c211 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276906 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Guybrush Zephyr: Enable keyboard backlightDiana Z2021-11-123-0/+13
| | | | | | | | | | | | | | | Enable the keyboard backlight functionality. BRANCH=None BUG=b:195137794 TEST=on guybrush, use kblight command to turn the backlight brighter and darker Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ib6e236401fd40184150229a069a2d3ef24a721d3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276905 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Zephyr: Add enable GPIO for KB backlightDiana Z2021-11-121-0/+1
| | | | | | | | | | | | | | | Add the standard name for the GPIO to enable the keyboard backlight to the GPIO names. BRANCH=None BUG=b:195137794 TEST=zmake testall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I7827274d5db042e341bc52fcdebbfdc05c317b0c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276904 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Guybrush Zephyr: Add fan controlDiana Z2021-11-125-2/+64
| | | | | | | | | | | | | | | Add in first PWM and fan for guybrush to use. BRANCH=None BUG=b:195137794 TEST=load on guybrush and observe fan no longer sounds like a jet taking off Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ic423f11168fd3654495b9b79bc39d312ccdf909e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276903 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Guybrush Zephyr: Update active charge port setDiana Z2021-11-121-25/+45
| | | | | | | | | | | | | | | | Guybrush's active charge port set was recently updated to catch more dead battery corner cases, so updating the zephyr copy to also contain these improvements. BRANCH=None BUG=None TEST=zmake testall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ifd78584709cd4e56ea7de57e1bee330d3baba6a9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276902 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Guybrush zephyr: Remove TODODiana Z2021-11-121-1/+0
| | | | | | | | | | | | | | | It turns out that SW charge ramping is automatically enabled because our charger is known to have HW ramping broken on it. Hooray for Kconfig. BRANCH=None BUG=b:195137794 TEST=zmake testall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I3e46ceeb249450bac6413a4a46e2cc44f29f361f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276901 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* power: add casts for power signalsTom Hughes2021-11-123-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When building with clang, it warns: power/icelake.c:49:11: error: implicit conversion from enumeration type 'enum espi_vw_signal' to different enumeration type 'enum gpio_signal' [-Werror,-Wenum-conversion] .gpio = SLP_S4_SIGNAL_L, ^~~~~~~~~~~~~~~ include/power/intel_x86.h:40:25: note: expanded from macro 'SLP_S4_SIGNAL_L' Although "enum espi_vw_signal" and "enum gpio_signal" are not directly compatible, it appears that the code in power/common.c takes that into account by calling espi_signal_is_vw(). BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibb3ac42516d2e293cf707ca92eacd6bd7c11049c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3243003 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* power: Combine chipset_reset_reason and chipset_shutdown_reasonTom Hughes2021-11-1215-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | When building with clang, it warns: power/amd_x86.c:59:18: error: implicit conversion from enumeration type 'enum chipset_reset_reason' to different enumeration type 'enum chipset_shutdown_reason' [-Werror,-Wenum-conversion] report_ap_reset(reason); The two enums are already set up so that they don't overlap, so just combine them into a single enum. BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => All boards match, except: burnet cerise damu fennel jacuzzi juniper kakadu kappa katsu kodama krane kukui makomo stern willow Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I47620e59e02a84c04dde4469f36ad37dccbcd9e5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3238250 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* zephyr: Add clangd cache to gitignoreJeremy Bettis2021-11-121-0/+4
| | | | | | | | | | | | | | | Using the clangd language server creates an index cache. BRANCH=None BUG=None TEST=None Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: Ic5c8739b9ab3b4f07b98a204932b0af3dd15206b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3270400 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Aaron Massey <aaronmassey@google.com>
* bq25710: Separate Vmin Active Protection register settingCaveh Jalali2021-11-121-16/+14
| | | | | | | | | | | | | | | | This moves the Vmin Active Protection register setting out of a conditional. Setting this register only needs to depend on relevant config options which are already in place. BRANCH=none BUG=b:185190976 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I3998d5b04064d4dda1c2bdf3881954ef4068d05d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3277942 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* bq25710: Set IL_AVG to 10A on bq25720Caveh Jalali2021-11-121-0/+27
| | | | | | | | | | | | | | | | | | | | This reduces the converter inductor average current clamp to 10 A on the bq25720 from the default 15 A. This means both chip variants will use the same 10 A limit. All current designs using the bq25720 prefer the 10 A setting, so it makes sense to over-ride the default on the bq25720 to mimic the bq25710 behavior. There is no need to make this configurable at this time. BRANCH=none BUG=b:185190976,b:192108571 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I8d903eb8d46e145467b26fe8d6f6336ca20f3f5a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3277937 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* build: add option to disable -Werror flagMichał Barnaś2021-11-124-2/+22
| | | | | | | | | | | | | | | | | | This commit adds possibility to disable treating warnings as errors. In CrOS EC, define NO_ERRORS=1 as make parameter. In Zephyr, use --no-errors flag when configuring using zmake. BRANCH=main BUG=b:197888003 TEST=Add unused static function. Build without flags, compilation should fail. Build with no-errors flags, only warning should be visible. Change-Id: I7f873b7530317b74ff2865f420c4c248b4a95360 Signed-off-by: Michał Barnaś <mb@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3264191 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* bugzzy : change accel/gyro sensorYongBeum.Ha2021-11-123-3/+94
| | | | | | | | | | | | | | | | | | support LSM6DSM(LSM6DSL) for accel/gyro sensor. BUG=b:204832951 BRANCH=None TEST=make -j BOARD=bugzzy then flash and check motionsensor Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I592fdc970dda1fb9bc86c27d0ed60d8e6b5ef6e5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3269256 Reviewed-by: Edward Doan <edoan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com> Commit-Queue: Edward Doan <edoan@chromium.org>
* ISL923x: Set charge current to 0 when ocpc precharge completeMichael5 Chen12021-11-121-0/+1
| | | | | | | | | | | | | Set primary charge current to 0 when enable ocpc charge. BUG=b:202796060 BRANCH=dedede TEST=SIT check function is PASS Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Change-Id: I0c635624c79935f50da591400d16fe77a66b70be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3274732 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tomato: tune DP EQ settingTing Shen2021-11-121-2/+2
| | | | | | | | | | | | | | | | | See issue link for analysis BUG=b:203637200 TEST=make BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I9eda3e1da068cde79eb57e8a62d05cf4fbfd8257 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3246163 Reviewed-by: Parker Lin <parkerlin@google.com> Reviewed-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Parker Lin <parkerlin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* ite: Fix SRAM size for ITE81302-512Andrew McRae2021-11-121-4/+4
| | | | | | | | | | | | | | The ITE81302-512 has 60Kb of SRAM. BUG=b:204231736 TEST=make -j buildall BRANCH=none Change-Id: I64f3a41c6df1738cdbb409c8098f485e8e224bb7 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276027 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* baseboard: dedede: Reduce amount of logsGwendal Grignou2021-11-121-0/+2
| | | | | | | | | | | | | | | When there is a sensor stack, printing a log for every command may overwhelm the EC. Reduce logs by default, consistenly with other boards. BUG=b:201961774 BRANCH=keeby TEST=check the reduce amount of log in servo on bugzzy. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I79b3a2a2d375dfb3a94eb30778f707f0f2fb6aef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3273095 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* drawcia_riscv: Add RISC-V variant for Nereid reworkAndrew McRae2021-11-1211-0/+1807
| | | | | | | | | | | | | | Create an EC build for a drawcia (drawlat) that uses a pin-compatible ITE81302-512 instead of a ITE8320. BUG=b:204231736 TEST=make -j buildall BRANCH=none Change-Id: Ie4bd9eab6c9c4f8c6df26ccf614584375c653a96 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3275100 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* ite: Add support for ITE81302-512 variantAndrew McRae2021-11-121-2/+10
| | | | | | | | | | | | | | Add support for 512Kb version of ITE81302BX. Required for rework of drawlat to support Nereid zephyr support. BUG=b:204231736 TEST=make -j buildall BRANCH=none Change-Id: I54b3fe0957c0f20a711682e380ef83b95d26a2b3 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276025 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* zephyr test: Verify SYV682 FRS_EN signalAbe Levkoy2021-11-115-13/+52
| | | | | | | | | | | | | | | In the SYV682 emulator, only assert FRS status when FRS is enabled via GPIO. In the test, check that FRS enable and disable updates the GPIO. BUG=b:190519131 TEST=zmake configure --test zephyr/test/drivers BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I50f640882f7e59a0e609614c400e93c75fe34e0c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3271350 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* TC DRP Test: Add LPM wake checkDiana Z2021-11-111-0/+21
| | | | | | | | | | | | | | Verify we wake the TCPC when we're changing our toggle state and it's asleep. BRANCH=None BUG=b:195393479 TEST=make -j run-usb_typec_drp_acc_trysrc Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I515f3303ed405728871e45de708e5bc119ffe31f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276665 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC Mock: Add LPM wake callbackDiana Z2021-11-112-0/+8
| | | | | | | | | | | | | Track LPM wake requested, and clear it on LPM entry. BRANCH=None BUG=b:195393479 TEST=make -j run-usb_typec_drp_acc_trysrc Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I4f2de6901584538805afbe1df19da6fede0135c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276664 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TC DRP Test: Add LPM configDiana Z2021-11-111-0/+4
| | | | | | | | | | | | | | Nearly every board uses LPM with its TCPCs, so configure this for our TC DRP unit test as well. BRANCH=None BUG=b:195393479 TEST=make -j run-usb_typec_drp_acc_trysrc Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ic53074aad299cd350a8f8a52cf87edaf2ebdce94 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276663 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Wake TCPC when changing dual roleDiana Z2021-11-111-1/+7
| | | | | | | | | | | | | | | | If a TCPC is in LPM and a request for a dual role change comes in, wake the TCPC if it has a function to do so. Otherwise, the TCPC wouldn't be woken until after the LPM exit debounce. BRANCH=None BUG=b:195393479 TEST=on storo, observe that the wake timing of unattached ports on power transitions makes more sense Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ibdfba9ae07949348a83b2373928f200aac073323 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262587 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* RAA489000: Configure I2C wake functionDiana Z2021-11-111-0/+1
| | | | | | | | | | | | | Configure the function for i2c wake. BRANCH=None BUG=b:195393479 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I2149e6ca91322e850393a26946128da9d11cde2b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262586 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPCI: Add an interface for I2C wakeDiana Z2021-11-114-0/+32
| | | | | | | | | | | | | | | | | | When we wake a TCPC from I2C idle, there is a procedure in the TCPCI specificaiton to follow. Implementing the full procedure will take some refactoring, but for now at least send the i2c wake to the chip when we plan to wake it. Otherwise, we don't actually wake the chip until the LPM exit debounce finishes, which isn't in the intended use of the LPM exit debounce. BRANCH=None BUG=b:195393479 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I6d5a6d27cce653ab02b59ab0e09d06657f640c39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262585 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* bq25710: Allow BATOC threshold to be configuredCaveh Jalali2021-11-114-0/+33
| | | | | | | | | | | | | | | | This adds support for selecting the minimum BATOC protection threshold to be used with EN_BATOC. The minimum threshold is 150% of PROCHOT IDCHG on the bq25710 and 133% of PROCHOT IDCHG_TH2 on the bq25720. The default threshold is 200% on both chips. BRANCH=none BUG=b:185190976 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I22576d1cf7c78bfefeb1c2582434ddc0220a1928 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3275001 Reviewed-by: Keith Short <keithshort@chromium.org>
* bq25710: Allow ACOC_VTH to be configuredCaveh Jalali2021-11-114-0/+26
| | | | | | | | | | | | | | This adds support for selecting 133% of ILIM2 for the AC over-current protection threshold. The chip default is 200% of ILIM2. BRANCH=none BUG=b:185190976 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I75457185fca905519897b66d460752989b3a7ff2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3275000 Reviewed-by: Keith Short <keithshort@chromium.org>
* bq25710: Allow EN_ACOC to be configuredCaveh Jalali2021-11-114-0/+30
| | | | | | | | | | | | | | | This adds support for enabling AC over-current protection (EN_ACOC bit). The converter turns off when the OC threshold is reached. The threshold is determined by the ACOC_VTH bit. BRANCH=none BUG=b:185190976 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I1bc8e34ee4e7cef0d6d796387eb4f290fada82d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3274999 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Increase stack size for x86 chipset taskRajesh Kumar2021-11-111-2/+6
| | | | | | | | | | | | | | | | | | | Default stack size '684' is not enough for x86 specific chipset task, insufficient stack causes task to crash. To fix this, stack size has been increased to 1056 for x86 specific chipset. BRANCH=None BUG=b:205746466 TEST=zmake configure -B ~/tmp/brya brya -b Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com> Change-Id: I9005683ec58070b38ed34060d92e206c576ed17b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3271777 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
* bq25710: Refactor charge option 2 register initializationCaveh Jalali2021-11-111-9/+20
| | | | | | | | | | | | | | | | | This separates the initialization of the charge option 2 register into a dedicated function. Multiple bit-fields will need to set in this register based on board configuration, so it's best to group these operations in one place. BRANCH=none BUG=b:185190976 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ief0f5b3d956f199544afe4f68217cfff01cb0c3b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3274998 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: ppc: use interrupt from driverDawid Niedzwiecki2021-11-111-5/+2
| | | | | | | | | | | | | | | Use a pointer to a interrupt routine from ppc driver instead of the hardcoded functions. BUG=b:194432779 TEST=zmake testall & Make sure PD works on Herobrine on both ports BRANCH=main Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I31e07b50069644ab94ab56f9354893722430ab3e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3270682 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* ppc: add an interrupt pointer to the ppc driver APIDawid Niedzwiecki2021-11-115-0/+11
| | | | | | | | | | | | | | | Add a pointer to interrupt handler to ppc driver API. It allows calling the pointer from ppc_chips array instead of hardcoded functions. BUG=b:194432779 TEST=build EC for all boards BRANCH=main Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I163a8ec91a02f8095d8dca76a56b9c9c91962228 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3270681 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: Specify Alert# gpio in tcpci emulatorJeremy Bettis2021-11-112-13/+57
| | | | | | | | | | | | | | | | | | Add alert_gpio property to tcpci-emul node in dts. Set the emulated Alert# gpio when the alert status changes. BRANCH=None BUG=b:201314530 TEST=Watched the interrupt fire in gdb. Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I190b591cdcb71da58d587faf2a48cdf2d9ef3edb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3269059 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Tristan Honscheid <honscheid@google.com> Reviewed-by: Tomasz Michalec <tmichalec@google.com>
* zephyr: guybrush: Drop PLATFORM_EC_{BOARD,BASEBOARD} variablesJack Rosenthal2021-11-111-5/+0
| | | | | | | | | | | | | | We don't use these, a little bit by design, so that Skyrim has no dependency on the legacy board & baseboard directories. BUG=none BRANCH=none TEST=zmake testall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie5a46c23b033415d039081addbe9a58590f131a2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3271875 Reviewed-by: Diana Z <dzigterman@chromium.org>
* power/mt8192: remove unused variableTing Shen2021-11-111-3/+0
| | | | | | | | | | | | | | BUG=none TEST=makeall BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: If1199ed3ad87867c7d6ace54c0865369e6cf7638 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3275003 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
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