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* Clear OWNERS for factory/firmware branchfirmware-reef-9042.87.BBrian Norris2021-09-102-10/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155232 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* charger: bd9995x: Disable topoff modeShawn Nematbakhsh2017-09-061-3/+1
| | | | | | | | | | | | | | | | | | | | Zero ITERM_SET to keep the charger out of topoff mode, since it has undesirable side-effects related to dead / low battery charging. BUG=b:35575421 BRANCH=reef TEST=Previous testing on kevin with same register setting. Change-Id: Ic1dd280e1069d410895498c0f72989654a6b8c63 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/636152 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 98405d4eaec40e1ac9b8f0344ea8ddbc2747a4c9) Reviewed-on: https://chromium-review.googlesource.com/644808 Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* usb_pd_protocol: Req SNK Cap if not received yet.Aseda Aboagye2017-08-151-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the SRC_READY state, we'll only request sink caps if we haven't received them yet and only if its the first transition to the state. However, we also don't send any PD traffic in that state if there's an incoming message in order to prevent a collision. This could create a scenario where upon entry to the SRC_READY state, a message is incoming. When this occurs, we never request the sink caps. This commit simply removes the condition that we may only request sink caps on the first transition to the SRC_READY state. BUG=b:64037926 BRANCH=gru TEST=Flash kevin; Connect to a DR port partner; Verify that sink caps are requested even after the first transition to the SRC_READY state. Change-Id: I714d12cf2eeabfa4b80b04bda257b3c38a29f162 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Change-Id: I6bc9ad01d45e6584a7a14b28806ae4872a22d98f Original-Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/611320 Original-Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615003 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* charge_manager: Consider port in source PDO.Aseda Aboagye2017-08-156-20/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is defined for a board, as its name implies, the board can source a higher current if there is only one port acting as a source. This commit fixes an issue with selecting the right source capability message to advertise. charge_manager_get_source_pdo() was simply checking if there was more than one sink connected, instead of checking if there were any *other* sinks connected. In the event that a sink was connected to a different port, we would advertise the max source PDO. BUG=b:64037926, b:35577509 BRANCH=gru,eve,reef TEST=Connect sink to port 1. Connect a AMA to port 0 that claims that VBUS isn't necessary. Start sending source caps, verify that the max PDO is not being advertised in the source caps. Change-Id: I1fa0eee1f201919f772c4aa74542e61c0e9baba0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Change-Id: Ie4145ecaf98d5b9070ad3e8b139e5653685fa801 Original-Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/610479 Original-Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615002 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* driver: kionix: Forgive i2c read failures while the acc is resettingGwendal Grignou2017-05-261-5/+0
| | | | | | | | | | | | | | | | | | | | | | | Port changes cl/288874 to generic kionix driver. From cl/288874: After we write SRST in CTRL2, there seems to be a period of time where the accelerometer doesn't respond to i2c commmands. Instead of failing the init just consider it as part of the timeout period. BUG=chrome-os-partner:39269,chrome-os-partner:63146 TEST=make -j buildall BRANCH=veyron,cave Reviewed-on: https://chromium-review.googlesource.com/445973 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 4a34b0d88f6b0075ee66a18f4aa22325dc766eb6) Change-Id: I2197aa7741d1482b76c7c07b0cb0c171aab86a59 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446417 (cherry picked from commit 9af60bb7955a8bba0710798d1dcf2a4d2c2aae6b) Reviewed-on: https://chromium-review.googlesource.com/517432
* driver: kionix: Increase init delay to 20msGwendal Grignou2017-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Port changes cl/289037 to generic kionix driver. Form cl/289037 Sometimes the accelerometer doesn't initialize nicely. Increase the timeout to 20ms. BUG=chrome-os-partner:39269,chrome-os-partner:63146 TEST=buildall BRANCH=veyron,cave Change-Id: I4e4d8951fc821b8b33daa53e6c3b8da5ffa7acde Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446132 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 11c00e1a4116bb0ac387c0264053e66e41a5ec92) Reviewed-on: https://chromium-review.googlesource.com/446699 (cherry picked from commit eb85cc2101ffccce6f54168782afac797f764202) Reviewed-on: https://chromium-review.googlesource.com/517429
* Revert "Sand: Add temperature sensor"Aaron Durbin2017-05-022-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1509cc7050789b783b9185d01f4b9c0643c9cdaf. Reason for revert: <INSERT REASONING HERE> Original change's description: > Sand: Add temperature sensor > > + follow Reef's config > sensor 0: battery > sensor 1: ambient > sensor 2: charger > > BUG=None > BRANCH=firmware-reef-9042.B > TEST=`make -j BOARD=sand`, system can get 3 temperatures > Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> > Change-Id: Ifd634bf102c180e05cf09f18185ef2cecd7072c7 > Reviewed-on: https://chromium-review.googlesource.com/487685 > Reviewed-by: Aaron Durbin <adurbin@chromium.org> > (cherry picked from commit 8b60d4b4b9456618ae7983b9cda545abd4aae23c) > Reviewed-on: https://chromium-review.googlesource.com/492773 > Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> > TBR=adurbin@chromium.org,David.Huang@quantatw.com,dnojiri@chromium.org,ryan.zhang@quanta.corp-partner.google.com NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=None Change-Id: If3daa3bb78a99c0b4d13b3464cc64300c7c9bc66 Reviewed-on: https://chromium-review.googlesource.com/493766 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Sand: Add temperature sensorRyan Zhang2017-05-022-0/+2
| | | | | | | | | | | | | | | | | | + follow Reef's config sensor 0: battery sensor 1: ambient sensor 2: charger BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=sand`, system can get 3 temperatures Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: Ifd634bf102c180e05cf09f18185ef2cecd7072c7 Reviewed-on: https://chromium-review.googlesource.com/487685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8b60d4b4b9456618ae7983b9cda545abd4aae23c) Reviewed-on: https://chromium-review.googlesource.com/492773 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Eve,Gru,Poppy,Reef: forbid DR_SWAP in RO firmware.Vincent Palatin2017-04-287-21/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when we jump from RO to RW, we forget our USB PD state. To recover from this, we send a SOFT_RESET (resetting the counters...), then either the USB PD partner is happy about it and we can continue, or it will issue a HARD_RESET to recover from our mismatched vision of the current connection (e.g wrong role) resulting in a reset of VBUS. The following use-case is still problematic: if the system is not write-protected (ie it does USB PD negotiation in RO EC) and we have no battery (or fully drained-one) as buffer, when we are connected to a PD power supply, if it issues the HARD_RESET mentioned above, we are going to brown-out. It's happening with power-supplies supporting DR_SWAP, the RO EC will negotiate a power-contract (as a sink), then try to reverse data role (from UFP to DFP) to identify the power-supply. We end-up being Sink/DFP, then when we sysjump to RW, we reset roles and send the SOFT_RESET as Sink/DFP, the power-supply identifies the incorrect data role and issues the HARD_RESET browning us out. As a workaround, now we never ask for the DR_SWAP in RO firmware and stays Sink/UFP. This is not affecting regular write-protected machines (which are not doing USB PD in RO EC). For developers, we are no longer doing the DR_SWAP in RO mode, this is mostly innocuous for a regular power-supply, but this would break the docking use-case. Normally, we will do it as soon as we have jumped to RW, so the dock should still work unless the developer is using the machine with RO EC (eg EC development with soft-sync disabled). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=reef BUG=b:35648282 TEST=Boot Snappy without battery. Verify RO image doesn't swap data roles and soft reset issued by RW image as SNK/UFP is accepted by the HP adapter. Change-Id: Id184f0d24a006cd46212d04ceae02f640f5bda65 Reviewed-on: https://chromium-review.googlesource.com/468651 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d2f96db9d0328ef94cead76200ced7b52a300eed) Reviewed-on: https://chromium-review.googlesource.com/490519 Reviewed-by: YH Lin <yueherngl@chromium.org> Commit-Queue: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org>
* ec: add initial nasher related filesYH Lin2017-03-259-0/+2898
| | | | | | | | | | | | | Deriving the files from reef. Likely to be changed later on. BUG=b:36457849 TEST=emerge-nasher chromeos-ec Change-Id: I3936383ad5c15b8189918b925bd6f1829eba45fe Reviewed-on: https://chromium-review.googlesource.com/458972 Reviewed-by: YH Lin <yueherngl@chromium.org> Commit-Queue: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org>
* bd9995x: Disable IADPDaisuke Nojiri2017-03-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables IADP immediately after the EC boots. We observed noise on IADP/RESET pin causing SEL_ILIM_VAL to randomly change. This seems the cause of b:35648317. We enabled IADP to fix b:35647661 initially and also followed the vendor's recommendation. However, the issue is only reproducible on the particular board which was used for power measurement and we did not see the issue on other boards with IADP disabled. Also the vendor assumed our EC doesn't control IBUS_LIM_SET and ICC_LIM_SET. (I think they assumed like other thier customers our EC controls ILIM by DAC connected to IADP/RESET pin.) If ILIM is not set by EC and IADP is disabled, the system would brownout because ILIM stays at 128mA. Therefore, it was (mistakenly) recommended that our EC should keep IADP enabled. Cros EC configures IBUS_LIM_SET and ICC_LIM_SET dynamically thus the above concern does not apply. We also found that we have too much noise on IADP/RESET pin. The noise is not big enough to cause the chip to reset but it's big enough to cause ILIM to fall in 128mA zone. We think this is why the boards fail to boot from battery cutoff or no battery. (Contrary to the vendor's explanation, it seems IADP/RESET pin continusouly affects ILIM not only in the early chip power-up period.) BUG=b:35648317 BRANCH=none TEST=Booted two Electro and two Snappy from 1) dead battery 2) no battery 3) battery cutoff. Change-Id: Ic675f1354b9ef222ceec8ce112b19713812d2752 Reviewed-on: https://chromium-review.googlesource.com/458676 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 32d670a054811370cae9100c5a01efcdb6c49412) Reviewed-on: https://chromium-review.googlesource.com/457829 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* tcpm: Call usb_mux board_init on exit from low power modeDaisuke Nojiri2017-03-178-13/+38
| | | | | | | | | | | | | | | | | | PS8751 does not restore all register contents when resuming from low power mode. This change makes tcpm call board_init when it stops auto-toggling so that register contents can be restored. BUG=b:35585399 BRACH=none TEST=On Snappy, the board_init funciton is called every time a device is plugged in and register contents are restored. Change-Id: I50c51334f43c02e3c4d8453e1e966bf6eb3ce769 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/454139 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/456619
* anx74xx: Restore behaviour if CONFIG_USB_PD_TCPC_LOW_POWER is unsetNicolas Boichat2017-03-171-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Commit 18327455c1 ("ANX74xx: add TCPC low power mode for different DRP state") introduced new code to put ANX74xx in low power mode. However, this broke existing boards that do not enable CONFIG_USB_PD_TCPC_LOW_POWER (and therefore do not implement cable detection interrupt). BUG=chrome-os-partner:59841, chrome-os-partner:61640 BUG=chrome-os-partner:62964 BRANCH=none TEST=on poppy, connect USB-A keyboard to ANX port via A-C adapter: keyboard works Change-Id: I4b66511b816afee402a7e769aa6d2c323724d071 Reviewed-on: https://chromium-review.googlesource.com/443865 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 3c59a1f734999715e2e060594dd16d0272916714) Reviewed-on: https://chromium-review.googlesource.com/456485 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
* tcpm: anx74xx: Only connect aux to sbu when DP mode is selectedScott2017-03-161-38/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The anx74xx tcpm driver for the usb_mux_set() function is always connecting the DP aux lines to the SBU signals regardless of whether the bit flag MUX_DP_ENABLED was set or not. For CCD opertation the sbu lines are used to establish a USB connection to H1. This means that if a PD port ever attaches to a sink debug accessory, usb_mux_set would result in interrupting the USB connection being used for CCD. In addition, the anx74xx_tcpm_mux_exit() function had a bug where the value read from ANALOG_CTRL_5 was being masked by 0x09 and then written to ANALOG_CTRL_2. Added functions anx74xx_tcpm_mux_enter_safe_mode() and anx74xx_tcpm_mux_exit_safe_mode() so that writes to the 3 CTRL registers that are used to configure ALT_DP mode can be easily bookended. BUG=b:36007652 BRANCH=reef TEST=Connected servo_v4 to port 0 of electro, verified that H1 console access worked. Then initiated a data role swap so that port 0 on electro was in DFP mode and the H1 console stayed connected. - Tested with dingdong that could connect to a 4k monitor. - Tested with USB3 flash drive. - Tested Anker USBC -> USBA hub Change-Id: I2d045134fbdd21b6b492bbeabc85ab23aef73b9a Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/451837 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: S Wang <swang@analogix.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit d3cc4835bba84f8767480272cd3057c066922ae2) Reviewed-on: https://chromium-review.googlesource.com/456477 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
* Sand:remove unsupport functionsRyan Zhang2017-03-154-247/+1
| | | | | | | | | | | | | | | | + remove Gyro related config + remove Accel related config BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=reef`, system can power up. Change-Id: I36a0090f8ea1c2f5b0843001be5d06669b25da92 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/454419 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* pyro: limit max input current for safetyBruce2017-03-141-0/+1
| | | | | | | | | | | | | | | | Max = Max * 95% Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: Ifa57171114f38640fbe868e7042b3962eab284e0 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/454776 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* BD9995X: Do not overwrite the charging current in idle modeVijay Hiremath2017-03-141-1/+3
| | | | | | | | | | | | | | | | | If the charging current is less than the BD9995X's minimum charging current it is overwritten to BD9995X's minimum charging current. However in idle mode we write the charging current which is known to the charger during that time, which can be less than the BD9995X's charging current. Hence, do not overwrite the charging current in idle mode. BUG=b:35984679 BRANCH=none TEST=Manually tested on Electro. In idle mode charge current is 0mA. Change-Id: I2e605b63c8519383c6a62d76718bc52660e7270e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/454984 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* snappy: Lock EC and PD communicationBruce2017-03-141-6/+1
| | | | | | | | | | | | | | | | | | Follow reef setting BUG=none BRANCH=reef TEST=make buildall Change-Id: I51fb9aa17d5d9eaf15d54df9f45db12b503b31b9 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/444591 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 70cdfe933377e6ecc02d071165af1852e9d60341) Reviewed-on: https://chromium-review.googlesource.com/451689 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* bd9995x: Do not set IADP monitoring enable bitDaisuke Nojiri2017-03-131-9/+0
| | | | | | | | | | | | | | | | | IADP monitoring bit was set to the default value for the devices with an RO image which clears the bit (and causes the issue). This patch removes the code so that we do not touch the IADP monitoring bit since transitioning from 0->1 may cause other issues. BUG=b:35647661 BRANCH=reef TEST=none Change-Id: I4413e0bd2de3f4e3912cbe6e73b8cad641ee9245 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/453400 Reviewed-by: Shawn N <shawnn@chromium.org>
* charger/bd9995x: enable IADP bit when charger init.Bruce2017-03-131-2/+3
| | | | | | | | | | | | | | | | | | | | When plug in adapter with dead battery, the charger will be flow back to the adapter. Then adapter will OVP. Enable IADP bit at address 0x40(BD9995X_CMD_VM_CTRL_SET) when charger init. It will fix this phenomenon. Enable IADP pin current limit due to we've already deployed the clearing to existing. BUG=chrome-os-partner:62646, 61691 BRANCH=reef TEST=check charger don't flow back to adapter with dead battery Change-Id: Id6202f3dd51cb7e1c43a124660e09de39f6c041b Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/453399 Reviewed-by: Shawn N <shawnn@chromium.org>
* snappy: Disable MPUBruce2017-03-111-0/+2
| | | | | | | | | | | | | | | | | Follow reef setting. BUG=none BRANCH=reef TEST=Boot to OS Change-Id: I510b7375dd492882e99fdc7fabeac016455c212c Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/452399 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 67ce1579a8892c2f30d8f54d3c8fcb9d72d6c56a) Reviewed-on: https://chromium-review.googlesource.com/453140
* pyro: Disable MPUBruce2017-03-101-0/+2
| | | | | | | | | | | | | | | Follow reef setting BUG=none BRANCH=reef TEST=Boot to OS Change-Id: I0bc69931c90463cdb04b90cde02f8a7d864a2607 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/453138 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* snappy: Add state for discharge + fullBruce2017-03-102-0/+7
| | | | | | | | | | | | | | | | | | Follow reef setting. When battery is fully charged, light white. BUG=none BRANCH=reef TEST=Fully charge. Plug in charger. LED lights white. Change-Id: I1096fe616ab5ec5954eea142e28fad08f16731ed Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451228 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 876157085e0ce53de870f23993a6badc5683f16d) Reviewed-on: https://chromium-review.googlesource.com/452184
* Electro: DP CTS testing failed in HBR2 deterministic JitterRyan Zhang2017-03-102-0/+5
| | | | | | | | | | | | | | | | Uploading CL according EE's requirement. Need to overwrite PS8751 Address: 0x16, offset: 0xD3, Data: 0x98 BUG=b:36044164 BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=reef` Change-Id: I60d5c6724fd047770ddd0af1d204571d59c6e25e Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451047 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* pyro: Add state for discharge + fullBruce2017-03-092-0/+10
| | | | | | | | | | | | | | | | | | | | Follow reef setting. When battery is fully charged, pyro starts discharging to protect battery and starts charging again when charge level goes down around 95%. To prevent the battery LED from showing green with the charger plugged in. BUG=none BRANCH=reef TEST=Fully charge Electro. Plug in OEM charger. LED lights green. Change-Id: If8560cbc3975b35ae84a9df2bdf5331c653143d1 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/452180 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* pyro: Lock EC and PD communicationBruce2017-03-091-6/+1
| | | | | | | | | | | | | | | | | | | Follow reef setting BUG=none BRANCH=reef TEST=make buildall Change-Id: I5e6bfed319f1cda8b2719393210a503c416d404e Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/444487 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b8c896788390526441fa52a0a3ce0b58675e7bc1) Reviewed-on: https://chromium-review.googlesource.com/451681 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* snappy: limit max input current for safetyBruce2017-03-091-0/+1
| | | | | | | | | | | | | | Cancel snappy total power spec (adapter - 5W), follow reef setting. Max = Max * 95% BUG=b:35937839 BRANCH=reef TEST=make buildall Change-Id: Id1742313b1d738f3401742f35229864611cf5de9 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451227 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* anx74xx: fix role bits for GOOD_CRCVincent Palatin2017-03-082-37/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were 2 mistakes when setting the data/power roles for automatic GOOD_CRC: - the bit numbers for data role and power role were swapped. - the function can only set and not reset the bits. Try to simplify this code by: - removing the duplicated name for register 0x9C (aka AUTO_GOODCRC_1) - avoiding the multiple read/modify/write by using AUTO_GOODCRC_1 for the actual settings (and letting the enable bit always on) and GOOD_CRC_2 for enabling/disabling it, so we can do simple writes. - answer only on SOP (not SOP' or SOP''). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=reef BUG=b:35648282 TEST=On Snappy, connect a given power supply, record the USB PD traces and see that the GOOD_CRC messages are still correct after the DR_SWAP. Change-Id: I848b1dcbc0e06806649e64a9664f3fba21bdd448 Reviewed-on: https://chromium-review.googlesource.com/448040 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: S Wang <swang@analogix.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit c21ad5898e452bdd0646db3c1b6fbe4721034b8e) Reviewed-on: https://chromium-review.googlesource.com/451678 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Reef: Disable MPUDaisuke Nojiri2017-03-081-0/+2
| | | | | | | | | | | | | | | | Reef RAM / code regions aren't a power of 2, so we cannot program MPU to protect the regions we desire. BUG=b:36037354 BRANCH=none TEST=Boot to OS Change-Id: I2d1e87eb97f9524620943262845823331f9f71a0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/450831 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e30782912d080ead3a50deaf475b3880f7d2c91) Reviewed-on: https://chromium-review.googlesource.com/451677
* Sand:update battery configRyan Zhang2017-03-082-582/+148
| | | | | | | | | | | | | | | | | | | | | | Change charging policy to Lars' to followed battery's requirement. To make sure battery can provide power, we need to check DFET is on/off. This would be done in another patch after battery vendor provide register data. + remove reef's fast charge policy + Add SMP battery config + Add LG battery config BUG=None BRANCH=firmware-reef-9042.B TEST=system can find different battery and charge normally. Change-Id: Iae4f9ed013c7ceb54cbdade7a0294163c230dad8 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/445846 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* pdcontrol: Suspend port individuallyDaisuke Nojiri2017-03-076-70/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pdcontrol suspend command will be used to prevent tcpm from putting the chip into sleep while firmware update is taking place. Currently the command suspends or resumes port 0. This patch makes the command apply to ports individually. pd enable console command now takes a port number: pd <port> enable/disable. This patch also replaces CONFIG_USB_PD_COMM_ENABLED with _DISABLED. When it's defined, PD communication is disabled at startup. Plankton undefines CONFIG_USB_PD_COMM_ENABLED enable, intending to disable PD communication at startup. Therefore, this patch defines CONFIG_USB_PD_COMM_DISABLED in its board.h. BUG=b:35586859 BRANCH=none TEST=From AP console: localhost # /tmp/ectool pdcontrol suspend 1 [600.188013 TCPC p1 suspended!] > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SUSPENDED, Flags: 0x0020 localhost # /tmp/ectool pdcontrol resume 1 [678.516613 TCPC p1 resumed!] > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 From ec console: > pd 1 disable Port C1 disable > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 > pd 1 enable Port C1 enabled > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 Change-Id: Ia0cc4904ac52adc4b89de20918968c8df78b9c80 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/447968 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit ad089de4b0430e5d997b9f6d6f187daae1fb11dc) Reviewed-on: https://chromium-review.googlesource.com/450990 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* pyro: Fix power-up sequence for Anx3429Bruce2017-03-071-4/+16
| | | | | | | | | | | | | | | | | | Power-up sequence must bring up PWR_NE followed by RESETN according to Figure 5-16 of the datasheet. Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: I8d411ec8f38f20d3d9572426db189ce94fa68b54 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451043 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* pyro: Set RW boot power threshold to 18wBruce2017-03-071-1/+1
| | | | | | | | | | | | | | | | | | Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: If5964ba7416ebfdf235acb5bdaf7d911331b85ef Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/449560 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e0b5aabd2b4f87deffff6b60057846be371103e) Reviewed-on: https://chromium-review.googlesource.com/451038 Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com>
* pyro: Name USB port numbers appropriatelyBruce2017-03-071-9/+22
| | | | | | | | | | | | | | | | | | | | | Some USB PD port numbers are not named. Some numbers are named using I2C port names. This patch fixes them Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: I4a9d3a765f6de84ac1a6f3e903171a505bc37d6c Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/449123 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f2162b401bb8059709ae2caf0bf0eb2b353618f) Reviewed-on: https://chromium-review.googlesource.com/451037 Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com>
* charger: Add state for discharge + fullDaisuke Nojiri2017-03-045-2/+23
| | | | | | | | | | | | | | | | | | | | | | When battery is fully charged, Reef starts discharging to protect battery and starts charging again when charge level goes down around 95%. To prevent the battery LED from showing blue with the charger plugged in, this patch adds a new state for discharge + nearly full. Reef shows a color indicating battery is full if an external charger is present. BUG=b:35775017 BRANCH=none TEST=Fully charge Electro. Plug in OEM charger. LED lights blue. Change-Id: I4c7c62f2c51c1d39188d1b271331984e89d5d7a3 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/448961 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 7757a8e872588fda9643f31399c5641982e07439) Reviewed-on: https://chromium-review.googlesource.com/449477 Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* npcx: gpio: Fixed bug GPIO's ISRs clear the other pending bits.Mulin Chao2017-03-031-5/+6
| | | | | | | | | | | | | | | | | | | | Since the interrupts of MIWU group E/F/G/H of table 0 are the same (interrupt 11), we need to handle LPCs' and GPIOs' events at the same ISR. But we also found there is a leak that ec has the chance to skip the other events which don't belong to GPIOs unexpectedly. (For example, LRESET and eSPI Reset) This CL fixed this issue by only clearing pending bits belong to GPIOs in their ISRs. BRANCH=none BUG=b:35648154 TEST=passed warm-reset testing on pyro over 12 hours. Change-Id: Ie626db00b54cff566798b4a593f6b0267a6fadc2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/449474 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* Sand:Update LED behaviorRyan Zhang2017-03-031-36/+12
| | | | | | | | | | | | | | | | + Follow Change#446580 BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=sand` Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Change-Id: I056fa7f472a034eaf9ebe1e0d5d3163095f6031b Reviewed-on: https://chromium-review.googlesource.com/448439 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ryan Zhang <Ryan.Zhang@quantatw.com> Tested-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
* npcx: flash: Lock all flash access before flash_execute_cmd() callsShawn Nematbakhsh2017-03-021-2/+39
| | | | | | | | | | | | | | | | | | | | | | | Any call to flash_execute_cmd() can interfere with UMA / mapped read access, so grab the mutex first. BUG=b:35587287,b:35848370 BRANCH=reef TEST=Verify SW sync completes 8 hour stress test on kevin. Also verify 'ectool flashspiinfo' succeeds. Change-Id: Ib1b04371546c27517c1b1ac860e9afbc1fed435e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/447905 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 850a227aea334bbb82119cf7811d4a53b72de23e) Reviewed-on: https://chromium-review.googlesource.com/449056 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Revert "pyro: Enable CONFIG_POWER_BUTTON_IGNORE_LID"Keith Tzeng2017-03-021-8/+0
| | | | | | | | | | | | | | | DVT2/PVT HW fixed the LID_OPEN leakage issue, so revert this. This reverts commit 5fe810db60fa66cbe83db296438848b820e90e95. BUG=chrome-os-partner:61707,chrome-os-partner:61696 Change-Id: I5028d288193fc482803f28f78fdb3d72524e304d Reviewed-on: https://chromium-review.googlesource.com/448276 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c425cbae0be48cf9a9a5b30610c282ced1328d70) Reviewed-on: https://chromium-review.googlesource.com/448281 Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com>
* pd: Store PD active state in battery-backed memoryShawn Nematbakhsh2017-02-278-14/+85
| | | | | | | | | | | | | | | | | | | | | | | | | Our previous idea to cut Rd for many reset cases cannot work if cr50 consistently resets the EC by asserting the reset pin shortly after power-on. Therefore, make a decision based upon whether battery-backed memory indicates we previously negotiated a PD power contract as a sink. If we previously did not negotiate a contract, or if power was removed from the device (causing battery-backed memory to wipe) then we can assume that we don't have an active power contract. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/443356 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446873
* system: Add generic bbram read / write routinesShawn Nematbakhsh2017-02-2711-108/+182
| | | | | | | | | | | | | | | | | | | | Add generic routines to read or write a byte to battery-backed RAM, and implement vbnvcontext get/set using these routines. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, with subsequent commit, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d Reviewed-on: https://chromium-review.googlesource.com/444444 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit f0b564b4a031fdc974a98a13308a62a460ae4a69) Reviewed-on: https://chromium-review.googlesource.com/446715
* pdchipinfo: Add option to force renewalDaisuke Nojiri2017-02-277-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds an option to pdchipinfo command to force ec to get the version from the chip instead of the cache (if it's available). This option will be used after firmware update, which makes the cache value stale. BUG=chrome-os-partner:62383 BRANCH=none TEST=Run ectool as follows: localhost ~ # /tmp/ectool pdchipinfo 0 on vendor_id: 0xaaaa product_id: 0x3429 device_id: 0xad fw_version: 0x15 localhost ~ # /tmp/ectool pdchipinfo 1 on EC result 2 (ERROR) Change-Id: Icefe96d7fc1208b991a4caa13aaf4f04052edba7 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/441271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 4d6eb1bc01ddbc87bbd53a317cfddd78f9cce1b2) Reviewed-on: https://chromium-review.googlesource.com/446714 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Reef: Fix power-up sequence for Anx3429Daisuke Nojiri2017-02-261-4/+16
| | | | | | | | | | | | | | | | | | Power-up sequence must bring up PWR_NE followed by RESETN according to Figure 5-16 of the datasheet. BUG=chrome-os-partner:63045 BRANCH=none TEST=Test charging, external monitor, usb flash drive in s0/s3/s5. Change-Id: I0e69f0fd0a06f3c828ca59172e0ca045cdc4f5d7 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/445934 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 918cb2ca3aacf6fa4bda71619fbeaea1c0257bdf) Reviewed-on: https://chromium-review.googlesource.com/446708 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Reef: Fix battery LED behaviorDaisuke Nojiri2017-02-261-35/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the battery led behave as follows: Charge: Amber on (S0/S3/S5) Full charge: Blue on (S0/S3/S5) Discharge in S3: Amber on 1sec off 3sec Discharge in S5: Off Error: Amber on 1sec off 1sec Discharge in S0: Blue on BUG=chrome-os-partner:63202 BRANCH=none TEST=Fully charge Electro, then the LED shows with no charger in s0: blue with charger in s0: blue with no charger in s3: blinking amber with charger in s3: blue with no charger in s5: off with charger in s5: blue When not fully charged, the LED shows solid amber in s0/3/5. Change-Id: Idbfbbf35b951ce73c06377f292746c8c1c3ce0fd Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446580 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b7f8d9df654945827d6a21332e140ddecb8bdd1b) Reviewed-on: https://chromium-review.googlesource.com/446709
* Reef: Name USB port numbers appropriatelyDaisuke Nojiri2017-02-261-10/+23
| | | | | | | | | | | | | | | | | Some USB PD port numbers are not named. Some numbers are named using I2C port names. This patch fixes them BUG=none BRANCH=none TEST=make buildall Change-Id: I0c413d2112f8ad5b584d7037519c74cd8cebf54a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/445866 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> (cherry picked from commit 3ce5e5d8b3ebdd9abf9d182082a81e29bd899d2b) Reviewed-on: https://chromium-review.googlesource.com/446710
* snappy: Open interrupt gate for trackpadBruce2017-02-231-1/+5
| | | | | | | | | | | | | | | | | | Follow reef setting. BUG=none BRANCH=reef TEST=Verified the value was 0 by gpioget command. Change-Id: Iaa03f6937e4143e38f9d4c8b293b596089188b8c Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/444486 Commit-Ready: Chen Wisley <wisley.chen@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 237b450f4bac463263cc2d6364505241eb54e084) Reviewed-on: https://chromium-review.googlesource.com/446136 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Sand:remove unsupport functionsRyan Zhang2017-02-234-169/+5
| | | | | | | | | | | | | | | + remove Volume Buttons + remove ALS related config + remove Tablet Mode BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=sand`, system can boot up Change-Id: I46c9efb5904a4ac63e5d25d1a187b0ed5c99ee74 Signed-off-by: Ryan Zhang<Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/446139 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* snappy: add ANX74XX low power mode for different DRP stateBruce2017-02-221-2/+11
| | | | | | | | | | | | | | | | | | Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: I94ee7ddc9a698e03d0f0b2872beee95cc836a7ae Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/444585 Commit-Ready: Chen Wisley <wisley.chen@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 4b7e8774d88eccab4713d8fb3c1b12f81ab8b623) Reviewed-on: https://chromium-review.googlesource.com/446137 Commit-Queue: Chen Wisley <wisley.chen@quantatw.com>
* Basking: Add CPT battery configRyan Zhang2017-02-221-9/+33
| | | | | | | | | | | | | | | update CPT's config BUG=chrome-os-partner:60899 BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=reef` Change-Id: I1f5f46af6ebf6c53a257f1508756414471f58368 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/443944 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: David Huang <David.Huang@quantatw.com> Tested-by: David Huang <David.Huang@quantatw.com>
* snappy: support lid accel matrix by board version.Bruce2017-02-211-10/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the new form-factor has the lid accelerometer on the reversed side facing the B-cover, the matrix setting depending on board version; in such matter, it should be able to compatible with old version of boards. We create a new hook function for board specific tweaks, this is because since the commit of 0c57824 ("reef: Re-factor PP5000 and PP3300 enable/disable"), the board_init() is no longer a good place for tweaks, because ADC read should come after adc_init(); such that, new hook ensures robust ADC reading which is the source of board version. Also, we fix an arithmetic error for version-3 workaround, i.e. patch the commit of ca99f38 ("snappy: BMI160 is powered down on board v3 and older in S3"), else it could trigger unexpected EC panic like this: [89.770776 chipset -> S3] [89.771222 power state 2 = S3, in 0x006d] [89.772428 I2C unwedge failed, SCL is being held low] [89.773775 TCPC p0 Low Power Mode] [89.812962 Reset i2c 01 fail!] ...snip... [91.816415 Unexpected i2c state machine! 1] Time: 0x00000000057a7d9c us, 91.913628 s Deadline: 0x00000000057a8a1d -> 0.003201 s from now ...snip... Rebooting... --- UART initialized after reboot --- [Reset cause: soft] ...snip... BUG=chrome-os-partner:62676 BRANCH=reef TEST=check the DVT1 and DVT2 unit rotate normally. Change-Id: Ic53e67e0c97e57056587adb6b260e81c0f99437a Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/442252 Commit-Ready: Chen Wisley <wisley.chen@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Harry Pan <harry.pan@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 08928c1f76f932f259c5dd5db7e007992e7e8887) Reviewed-on: https://chromium-review.googlesource.com/444727 Commit-Queue: Chen Wisley <wisley.chen@quantatw.com>
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