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* ectool: add PD_CHIP_ON support.Caveh Jalali2017-08-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this adds CLI support for the new PD_CHIP_ON subcommand of ec_pd_control_cmd. TEST=rebuilt ectool to see if "ectool pdcontrol on" does something useful. copied new build to electro: ec> i2cxfer rlen 0 0x50 1 0x10 Unknown error Usage: i2cxfer r/r16/rlen/w/w16 port addr offset [value | len] ec> ap$ /tmp/ectool pdcontrol on 0 ec> i2cxfer rlen 0 0x50 1 0x10 Data: aa2934ad000000000000010000050500 ec> so, "pdcontrol on" had the desired effect of bringing the chip out of sleep mode. BRANCH=none BUG=b:35586895 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/599361 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 10dab9c7dd2068876c204d5fcdb7c5de522f3003) Change-Id: Ib36151ef72479552be5f3a02627f1d727d38a6fe Reviewed-on: https://chromium-review.googlesource.com/625245 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* PD_CONTROL: add subcommand to power up a TCPC.Caveh Jalali2017-08-223-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | add a subcommand to the PD_CONTROL message to power up a specific TCPC. in practice, this typically just takes the TCPC out of sleep mode for cases where sleep mode is controlled by the EC. under the covers, board_set_tcpc_power_mode() gets a weak function definition so we don't need to special case this everywhere. TEST="make buildall" passes; "make tests" passes for reef. BRANCH=none BUG=b:35586895 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/596796 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 28bfc8037156ba0f9c8189ef6e8b7c8a7d22d4cc) Change-Id: Ibc67ab40c65b6b441689509b4bb1a7c1203db5ec Reviewed-on: https://chromium-review.googlesource.com/625065 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* usb_pd_protocol: Req SNK Cap if not received yet.Aseda Aboagye2017-08-171-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the SRC_READY state, we'll only request sink caps if we haven't received them yet and only if its the first transition to the state. However, we also don't send any PD traffic in that state if there's an incoming message in order to prevent a collision. This could create a scenario where upon entry to the SRC_READY state, a message is incoming. When this occurs, we never request the sink caps. This commit simply removes the condition that we may only request sink caps on the first transition to the SRC_READY state. BUG=b:64037926 BRANCH=gru TEST=Flash kevin; Connect to a DR port partner; Verify that sink caps are requested even after the first transition to the SRC_READY state. Change-Id: I714d12cf2eeabfa4b80b04bda257b3c38a29f162 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Change-Id: I6bc9ad01d45e6584a7a14b28806ae4872a22d98f Original-Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/611320 Original-Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615003 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 09fc609f16a0195ec7b925b6cdc5fa3960c3dcf3) Reviewed-on: https://chromium-review.googlesource.com/619276
* charge_manager: Consider port in source PDO.Aseda Aboagye2017-08-176-20/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is defined for a board, as its name implies, the board can source a higher current if there is only one port acting as a source. This commit fixes an issue with selecting the right source capability message to advertise. charge_manager_get_source_pdo() was simply checking if there was more than one sink connected, instead of checking if there were any *other* sinks connected. In the event that a sink was connected to a different port, we would advertise the max source PDO. BUG=b:64037926, b:35577509 BRANCH=gru,eve,reef TEST=Connect sink to port 1. Connect a AMA to port 0 that claims that VBUS isn't necessary. Start sending source caps, verify that the max PDO is not being advertised in the source caps. Change-Id: I1fa0eee1f201919f772c4aa74542e61c0e9baba0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Change-Id: Ie4145ecaf98d5b9070ad3e8b139e5653685fa801 Original-Signed-off-by: Aseda Aboagye <aaboagye@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/610479 Original-Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615002 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 444bf5e44a3764c1517c0e69a49153020213943e) Reviewed-on: https://chromium-review.googlesource.com/619275
* Sand:update battery configRyan Zhang2017-08-081-1/+8
| | | | | | | | | | | | | LG battery change its device name from "Empoli" to "AC16B8K" BUG=None BRANCH=firmware-reef-9042.B TEST=system can find different battery and charge normally. Change-Id: I6d4837072e6a1ba7f81d044d989e9883cd6c620c Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/599271 Reviewed-by: Shawn N <shawnn@chromium.org>
* snappy: check RO/RW image to set input currentBruce2017-08-021-1/+3
| | | | | | | | | | | | | | | Device can't boot without battery on parade port by snappy adapter. System will shutdown due to set input current 512 mA when RO jump to RW. So identify image to set default input current or not. BUG=b:62517753 BRANCH=reef TEST=device can boot without battery on parade port. Change-Id: I2e388ad9e5ff85ad8518e2a21062777d74ff8306 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/552197 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* snappy: Enable keyboard backlightDevin Lu2017-07-203-0/+4
| | | | | | | | | | | | | Enable the keyboard control of the keyboard backlight. BUG=none BRANCH=reef TEST=flash the board, test the keyboard backlight function. Change-Id: Icd23535f6729b3821c58c91ba748161ea69a1a79 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/576594 Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_pd: only service interrupts on enabled ports.Caveh Jalali2017-07-133-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as it turns out, we're pretty aggressive in iterating over all TCPCs checking for alerts when any of them generate an interrupt or their interrupt line is low. this can cause unfortunate behavior if the driver hasn't initialized itself (and the chip) yet for interrupts to be handled or we've released (disconnected) the driver so we can do a TCPC firmware update. so, check the PD task state to see if it makes sense to service the port's interrupt. note: there seems to be a quirk with the ps8751 in that it holds its ALERT# (interrupt) line low during firmware update. this line is supposed to be falling edge triggered, so it's technically not interrupting, but since we also poll the line level, we think there's a continuous interrupt that isn't acutally there. we get away with this because pd_exchange_status() has a 5ms delay in its polling loop to avoid spinning. the particular test case was to unplug the PD power brick during TCPC firmware update (over i2c). the interrupt handler would be called, accessing the TCPC over i2c and causing all sorts of havoc. TEST=tested with follow-up CLs and verified ps8751 firmware update works on electro. BRANCH=none BUG=b:35586896 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/544661 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 4a8b509020ce5104abf9b43335283cb39c7b75b2) Change-Id: I4649d379bf1608e2be05aa3271584388d7a57a4a Reviewed-on: https://chromium-review.googlesource.com/568417 Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Caveh Jalali <caveh@google.com>
* tcpm: add .release driver operation.Caveh Jalali2017-07-139-4/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | similar to the USB_PD_TCPC case, add release/init operations when the pd_task enters/leaves the PD_STATE_SUSPENDED state. one use case for PD_SUSPEND is to get exlusive access to the TCPC for things like firmware update, so the release/init operation is needed to get the TCPC and driver into a good state. updated all tcpm_drv style drivers. for backward compatibility, "old" drivers that may not handle init/release properly simply return EC_ERROR_UNIMPLEMENTED for tcpm_release(). pd_task() uses this as a signal that it should not try to re-init() the driver. [cherry-pick edits: PD_DEFAULT_STATE takes no args] TEST=tested in combination with follow-on CLs to do TCPC firmware update on electro. also built for kevin, eve, sand which are some of the other boards using these drivers. "make buildall -j" passes. BRANCH=none BUG=b:35586896 Reviewed-on: https://chromium-review.googlesource.com/544660 Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: I3d2964a79e710428f7a6e7004d68ab424af85be8 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/569077
* pd_suspend: coordinate with pd_task().Caveh Jalali2017-07-131-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | looks like we had a bit of a race condition: set_state() was effectively just an assignment opration to pd[port].task_state. it's called asynchronously from pd_set_suspend() in response to a PD_SUSPEND message from the AP as well as from pd_task() before it enters its main event loop. this can take a long time because tcpci_tcpm_init() has a 300ms timeout. last one wins. similarly, when pd_task() is running its main loop, pd_set_suspend() really needs to wait for pd_task() to actually enter the PD_STATE_SUSPENDED state before the caller can assume that the pd_task() has stopped accessing the TCPC. the particular failure case was when depthcharge would decide to do a TCPC firmware update. it starts by sending a PD_SUSPEND to the EC, then accessing the TCPC. unfortunately, the pd_task() hadn't gotten out of the way yet, thus causing TCPC access chaos. so, i'm adding a req_suspend_state flag to the pd_protocol struct so we can tell pd_task() to suspend itself in a controlled manner. when pd_task() is ready to do a state change - basically at the top of the main event loop - it'll change to PD_STATE_SUSPENDED and clear the req_suspend_state flag. in any case, pd_set_suspend() still needs to wait around for pd_task() to enter the suspended state as we don't have a fancy handshake mechanism between these tasks. [cherry-pick edits: PD_DEFAULT_STATE takes no args] TEST=in combination with some follow-on CLs, ps8751 firmware update works properly where previously it needed a ~2 second delay for the EC pd_task() to settle. the way to trigger the failure was to insert or remove the power brick. BRANCH=none BUG=b:62356808 Reviewed-on: https://chromium-review.googlesource.com/544659 Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: I363803ff60db31ccf84d592f8c9d1610fbe0f9ce Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/569011
* ps8751: assert reset for at least 1ms.Caveh Jalali2017-07-125-10/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | the 1ms reset hold time isn't in the ps8751 datasheets (yet), but that's what our parade support contact recommended. i'm applying this fix to reef (electro) and coral as these two boards were missing any sort of reset hold time. other boards using the ps8751 seem to already have a 1ms or 10ms delay. [edits in cherry-pick: applied same fix to pyro,sand,snappy] TEST=rebuilt, reload EC image on electro... no ill effects noted. BUG=b:62642003 BRANCH=reef Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/540742 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 053cb4bb24a948f917b78e7e17ffdff8733d01a0) Change-Id: I240bfcf72cfaf87005fb5d6d008a839de164c7b6 Reviewed-on: https://chromium-review.googlesource.com/568248 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Trybot-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* lucid: remove from reef firmware branch.Caveh Jalali2017-07-1211-1213/+0
| | | | | | | | | | | | | | | | | lucid no longer builds on the reef firmware branch due to space constraints, so just remove its board files so we don't build it. took board name out of flash_ec as well. BUG=none BRANCH=reef TEST=buildall -j passes Change-Id: Idf58ef00ba4d2db06d9736717d8e85663b4db4cd Reviewed-on: https://chromium-review.googlesource.com/568853 Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Trybot-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* driver: kionix: Forgive i2c read failures while the acc is resettingGwendal Grignou2017-05-261-5/+0
| | | | | | | | | | | | | | | | | | | | | | | Port changes cl/288874 to generic kionix driver. From cl/288874: After we write SRST in CTRL2, there seems to be a period of time where the accelerometer doesn't respond to i2c commmands. Instead of failing the init just consider it as part of the timeout period. BUG=chrome-os-partner:39269,chrome-os-partner:63146 TEST=make -j buildall BRANCH=veyron,cave Reviewed-on: https://chromium-review.googlesource.com/445973 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 4a34b0d88f6b0075ee66a18f4aa22325dc766eb6) Change-Id: I2197aa7741d1482b76c7c07b0cb0c171aab86a59 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446417 (cherry picked from commit 9af60bb7955a8bba0710798d1dcf2a4d2c2aae6b) Reviewed-on: https://chromium-review.googlesource.com/517431
* driver: kionix: Increase init delay to 20msGwendal Grignou2017-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Port changes cl/289037 to generic kionix driver. Form cl/289037 Sometimes the accelerometer doesn't initialize nicely. Increase the timeout to 20ms. BUG=chrome-os-partner:39269,chrome-os-partner:63146 TEST=buildall BRANCH=veyron,cave Change-Id: I4e4d8951fc821b8b33daa53e6c3b8da5ffa7acde Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446132 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 11c00e1a4116bb0ac387c0264053e66e41a5ec92) Reviewed-on: https://chromium-review.googlesource.com/446699 (cherry picked from commit eb85cc2101ffccce6f54168782afac797f764202) Reviewed-on: https://chromium-review.googlesource.com/517428
* npcx: system: Fixed bug that ec received unexpected rtc interruptMulin Chao2017-05-201-3/+6
| | | | | | | | | | | | | | | | | | | | | | In old system driver, ec clears "Predefined Time Occurred" (PTO) flag before setting a new alarm (PT field in WTC). If PT field is the same as the first 25 TTC bits at this moment, we might receive unexpected rtc interrupt again. This CL sets new alarm first then clears PTO flag to make sure rtc interrupt is issued from new alarm. BRANCH=none BUG=b:38310685 TEST=Duplicated the same symptom by the script in issue 38310685 on gru. No symptoms occurred with the same script for 3 hours by applying this CL. Change-Id: Ia6410d6aa4ef8e2acb7bfadf9192d619045bfa58 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/510085 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* tcpm: anx74xx: Take ANX3429 out of suspend state before I2C accessScott Collyer2017-05-105-55/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cable_det signal is used to signal to the EC that the tcpc has detected a cable being connected when low power mode is configured. The driver then needs to take the tcpc out of suspend state by setting PWR_EN and RESET_N high. Then bit 7 of analog_ctrl_0 needs to be set properly. The code that is handling this transition was attempting to access the tcpc via I2C before putting the chip in normal mode when transitioning from suspend to normal. In addition there are issues with calling the driver function directly from the hook task (in the delayed ISR handler) and from the USB PD task. This CL changes the delay ISR handler to only set the TCPC_RESET indication so that the call to put the ANX3429 into normal from standby to normal mode only happens in the USB PD task. The TCPC_RESET event is only set if cable_det is high, but reset_n (to the ANX3429) is low which indicates that the ANX3429 is currently in standby mode. BUG=b:35775019 BRANCH=reef TEST=Manual. make BOARD=sand. Tested with various adapters in both S0 and S3/G3 chipset states. Verified that adapters connected as expected. When in S3/G3 connecting a sink only adapter still causes an indefinite toggle, but all calls into the driver are executed from within the USB PD 0 task and all ANX3429 I2C accesses work as expected. Change-Id: Ie1a6bb67db1d870be3bf22462df900191cf1ef01 Signed-off-by: Scott Collyer <scollyer@google.com> Original-reviewed-on: https://chromium-review.googlesource.com/457103 Original-commit-Ready: Scott Collyer <scollyer@chromium.org> Original-tested-by: Scott Collyer <scollyer@chromium.org> Original-reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 154c16ac18fdbd20d9d1b855d1e7151eb62f78ca) Reviewed-on: https://chromium-review.googlesource.com/479543 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
* keyboard: Clear typematic when disabling keyboardDaisuke Nojiri2017-05-104-3/+13
| | | | | | | | | | | | | | | | | | | | This patch clears the typematic buffer when disabling keyboard scan. When the device goes to tablet mode with a key being pressed, this should prevent keyboard_protocol_task from sending scan codes to the host. BUG=b:35585725 BRANCH=none TEST=make buildall. Tested on Electro. Change-Id: I73e9d2948b472458814967307412aebeb410ff2e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/425075 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 4444702e858a8fa3d51c948f509450e136a9482a) Reviewed-on: https://chromium-review.googlesource.com/499908 Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* virtual_battery: prevent access out of bounds of memoryphilipchen2017-05-091-2/+11
| | | | | | | | | | | | | | | | | | BUG=chromium:717737 BRANCH=none TEST=manually run 'power_supply_info' a few times and see consistent battery parameters TEST=access cached smart battery registers from the host command and see it returns 0 for out of bounds of memory Change-Id: I87cf2900ff93a952dc88cd9c3da82321533e4eb5 Reviewed-on: https://chromium-review.googlesource.com/495628 Reviewed-by: Douglas Anderson <dianders@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> (cherry picked from commit 96514bb2d21dbe8b4cc6177db9e916384649e28f) Reviewed-on: https://chromium-review.googlesource.com/499608 Reviewed-by: Philip Chen <philipchen@chromium.org>
* virtual_battery: Fix energy readingsDouglas Anderson2017-05-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The virtual battery "energy" readings were totally broken. Rather than reporting things in units of "10 mW" they were reporting things in units of "10 uW". That's because they were doing this math: result = mV * mA / 10 Said another way: result = (V / 1000) * (A / 1000) / 10 result = (V * A) / (100000) / 10 result = W / 1000000 / 10 result = uW / 10 Aside from the fact that clients were expecting things in "10 mW" instead of "10 uW", we got even more random results. That's because we return to the client in a 16-bit variable, so we were kinda randomly truncating things. Doh. BRANCH=ToT BUG=chromium:717304 TEST=power_supply_info Unfortunately when you try to report sane values for "10 uA" in a 16-bit result, it doesn't work too well ( Change-Id: I8075dffd7ab6b372be5b8fdf293acc96c5878036 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/492546 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 01ceab68cd6b542f8c6355425e6ac6da698e0ebf) Reviewed-on: https://chromium-review.googlesource.com/492567 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* Sand: Add temperature sensorRyan Zhang2017-04-282-0/+2
| | | | | | | | | | | | | | | + follow Reef's config sensor 0: battery sensor 1: ambient sensor 2: charger BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=sand`, system can get 3 temperatures Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: Ifd634bf102c180e05cf09f18185ef2cecd7072c7 Reviewed-on: https://chromium-review.googlesource.com/487685 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Eve,Gru,Poppy,Reef: forbid DR_SWAP in RO firmware.Vincent Palatin2017-04-277-21/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when we jump from RO to RW, we forget our USB PD state. To recover from this, we send a SOFT_RESET (resetting the counters...), then either the USB PD partner is happy about it and we can continue, or it will issue a HARD_RESET to recover from our mismatched vision of the current connection (e.g wrong role) resulting in a reset of VBUS. The following use-case is still problematic: if the system is not write-protected (ie it does USB PD negotiation in RO EC) and we have no battery (or fully drained-one) as buffer, when we are connected to a PD power supply, if it issues the HARD_RESET mentioned above, we are going to brown-out. It's happening with power-supplies supporting DR_SWAP, the RO EC will negotiate a power-contract (as a sink), then try to reverse data role (from UFP to DFP) to identify the power-supply. We end-up being Sink/DFP, then when we sysjump to RW, we reset roles and send the SOFT_RESET as Sink/DFP, the power-supply identifies the incorrect data role and issues the HARD_RESET browning us out. As a workaround, now we never ask for the DR_SWAP in RO firmware and stays Sink/UFP. This is not affecting regular write-protected machines (which are not doing USB PD in RO EC). For developers, we are no longer doing the DR_SWAP in RO mode, this is mostly innocuous for a regular power-supply, but this would break the docking use-case. Normally, we will do it as soon as we have jumped to RW, so the dock should still work unless the developer is using the machine with RO EC (eg EC development with soft-sync disabled). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=reef BUG=b:35648282 TEST=Boot Snappy without battery. Verify RO image doesn't swap data roles and soft reset issued by RW image as SNK/UFP is accepted by the HP adapter. Change-Id: Id184f0d24a006cd46212d04ceae02f640f5bda65 Reviewed-on: https://chromium-review.googlesource.com/468651 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* BD9995X: Enable/Disable charger depending on charging currentJames Chao2017-04-272-24/+39
| | | | | | | | | | | | | | | | | | If charging current is set to 0mA during charging, reference of charge current feedback amp (VREF_CHG) is set to 0V. Hence the DCDC stops switching (because of the EA offset). To eliminate this issue, disable/enable charger depending on the charging current is zero or non-zero respectively. BUG=b:37413065 BRANCH=reef TEST=test 'ectool chargecontrol normal/idle/discharge' are working Change-Id: Id31876afe365a476fb906e059ab519b7a0c9a7c6 Signed-off-by: james_chao <james_chao@asus.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/486101 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Sand: follow reef's configRyan Zhang2017-04-193-17/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | + b47e6a5 tcpm: Call usb_mux board_init on exit from low power mode + 2adc781 Reef: Disable MPU + 040bd9b charger: Add state for discharge + full + c15aaa4 Reef: Fix power-up sequence for Anx3429 + ea1f9d0 Reef: Name USB port numbers appropriately - a521c23 reef: Move DPTF tablet mode support to common code Sand doesn't have tablet mode, undef it to explicitly tell difference between Reef and Sand + 7317922 Reef-ish: Remove extra newline after board version + dcc8f63 ANX74xx: add TCPC low power mode for different DRP state + 8f60afa Reef: Set RW boot power threshold to 18w BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=sand`, system can power up. Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: I69b9753005473f4a0ccbbc374740939bce92d405 Reviewed-on: https://chromium-review.googlesource.com/479512 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* Sand:enable learn mode functionRyan Zhang2017-04-131-3/+53
| | | | | | | | | | | | | | | follow Reef's settings. BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=sand`, system can power up. Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: I4e034cf3f2467a936e9ac81756a224ff6004ab04 Reviewed-on: https://chromium-review.googlesource.com/461628 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* Sand: Add Keyboard backlight config.Ryan Zhang2017-04-123-6/+4
| | | | | | | | | | | | | | | | + add PWM for keyboard backlight for new feature. + remove PWM LED config (clean up) BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=sand`, `console.cmd.kblight 0% ~ 100%` Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: If23c0ab54ff8c18700ebb51a2d43878e4e105170 Reviewed-on: https://chromium-review.googlesource.com/472291 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* ec: add initial nasher related filesYH Lin2017-03-259-0/+2898
| | | | | | | | | | | | | Deriving the files from reef. Likely to be changed later on. BUG=b:36457849 TEST=emerge-nasher chromeos-ec Change-Id: I3936383ad5c15b8189918b925bd6f1829eba45fe Reviewed-on: https://chromium-review.googlesource.com/458972 Reviewed-by: YH Lin <yueherngl@chromium.org> Commit-Queue: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org>
* bd9995x: Disable IADPDaisuke Nojiri2017-03-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables IADP immediately after the EC boots. We observed noise on IADP/RESET pin causing SEL_ILIM_VAL to randomly change. This seems the cause of b:35648317. We enabled IADP to fix b:35647661 initially and also followed the vendor's recommendation. However, the issue is only reproducible on the particular board which was used for power measurement and we did not see the issue on other boards with IADP disabled. Also the vendor assumed our EC doesn't control IBUS_LIM_SET and ICC_LIM_SET. (I think they assumed like other thier customers our EC controls ILIM by DAC connected to IADP/RESET pin.) If ILIM is not set by EC and IADP is disabled, the system would brownout because ILIM stays at 128mA. Therefore, it was (mistakenly) recommended that our EC should keep IADP enabled. Cros EC configures IBUS_LIM_SET and ICC_LIM_SET dynamically thus the above concern does not apply. We also found that we have too much noise on IADP/RESET pin. The noise is not big enough to cause the chip to reset but it's big enough to cause ILIM to fall in 128mA zone. We think this is why the boards fail to boot from battery cutoff or no battery. (Contrary to the vendor's explanation, it seems IADP/RESET pin continusouly affects ILIM not only in the early chip power-up period.) BUG=b:35648317 BRANCH=none TEST=Booted two Electro and two Snappy from 1) dead battery 2) no battery 3) battery cutoff. Change-Id: Ic675f1354b9ef222ceec8ce112b19713812d2752 Reviewed-on: https://chromium-review.googlesource.com/458676 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 32d670a054811370cae9100c5a01efcdb6c49412) Reviewed-on: https://chromium-review.googlesource.com/457829 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* tcpm: Call usb_mux board_init on exit from low power modeDaisuke Nojiri2017-03-178-13/+38
| | | | | | | | | | | | | | | | | | PS8751 does not restore all register contents when resuming from low power mode. This change makes tcpm call board_init when it stops auto-toggling so that register contents can be restored. BUG=b:35585399 BRACH=none TEST=On Snappy, the board_init funciton is called every time a device is plugged in and register contents are restored. Change-Id: I50c51334f43c02e3c4d8453e1e966bf6eb3ce769 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/454139 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/456619
* anx74xx: Restore behaviour if CONFIG_USB_PD_TCPC_LOW_POWER is unsetNicolas Boichat2017-03-171-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Commit 18327455c1 ("ANX74xx: add TCPC low power mode for different DRP state") introduced new code to put ANX74xx in low power mode. However, this broke existing boards that do not enable CONFIG_USB_PD_TCPC_LOW_POWER (and therefore do not implement cable detection interrupt). BUG=chrome-os-partner:59841, chrome-os-partner:61640 BUG=chrome-os-partner:62964 BRANCH=none TEST=on poppy, connect USB-A keyboard to ANX port via A-C adapter: keyboard works Change-Id: I4b66511b816afee402a7e769aa6d2c323724d071 Reviewed-on: https://chromium-review.googlesource.com/443865 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 3c59a1f734999715e2e060594dd16d0272916714) Reviewed-on: https://chromium-review.googlesource.com/456485 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
* tcpm: anx74xx: Only connect aux to sbu when DP mode is selectedScott2017-03-161-38/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The anx74xx tcpm driver for the usb_mux_set() function is always connecting the DP aux lines to the SBU signals regardless of whether the bit flag MUX_DP_ENABLED was set or not. For CCD opertation the sbu lines are used to establish a USB connection to H1. This means that if a PD port ever attaches to a sink debug accessory, usb_mux_set would result in interrupting the USB connection being used for CCD. In addition, the anx74xx_tcpm_mux_exit() function had a bug where the value read from ANALOG_CTRL_5 was being masked by 0x09 and then written to ANALOG_CTRL_2. Added functions anx74xx_tcpm_mux_enter_safe_mode() and anx74xx_tcpm_mux_exit_safe_mode() so that writes to the 3 CTRL registers that are used to configure ALT_DP mode can be easily bookended. BUG=b:36007652 BRANCH=reef TEST=Connected servo_v4 to port 0 of electro, verified that H1 console access worked. Then initiated a data role swap so that port 0 on electro was in DFP mode and the H1 console stayed connected. - Tested with dingdong that could connect to a 4k monitor. - Tested with USB3 flash drive. - Tested Anker USBC -> USBA hub Change-Id: I2d045134fbdd21b6b492bbeabc85ab23aef73b9a Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/451837 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: S Wang <swang@analogix.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit d3cc4835bba84f8767480272cd3057c066922ae2) Reviewed-on: https://chromium-review.googlesource.com/456477 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
* Sand:remove unsupport functionsRyan Zhang2017-03-154-247/+1
| | | | | | | | | | | | | | | | + remove Gyro related config + remove Accel related config BUG=None BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=reef`, system can power up. Change-Id: I36a0090f8ea1c2f5b0843001be5d06669b25da92 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/454419 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* pyro: limit max input current for safetyBruce2017-03-141-0/+1
| | | | | | | | | | | | | | | | Max = Max * 95% Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: Ifa57171114f38640fbe868e7042b3962eab284e0 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/454776 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* BD9995X: Do not overwrite the charging current in idle modeVijay Hiremath2017-03-141-1/+3
| | | | | | | | | | | | | | | | | If the charging current is less than the BD9995X's minimum charging current it is overwritten to BD9995X's minimum charging current. However in idle mode we write the charging current which is known to the charger during that time, which can be less than the BD9995X's charging current. Hence, do not overwrite the charging current in idle mode. BUG=b:35984679 BRANCH=none TEST=Manually tested on Electro. In idle mode charge current is 0mA. Change-Id: I2e605b63c8519383c6a62d76718bc52660e7270e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/454984 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* snappy: Lock EC and PD communicationBruce2017-03-141-6/+1
| | | | | | | | | | | | | | | | | | Follow reef setting BUG=none BRANCH=reef TEST=make buildall Change-Id: I51fb9aa17d5d9eaf15d54df9f45db12b503b31b9 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/444591 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 70cdfe933377e6ecc02d071165af1852e9d60341) Reviewed-on: https://chromium-review.googlesource.com/451689 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* bd9995x: Do not set IADP monitoring enable bitDaisuke Nojiri2017-03-131-9/+0
| | | | | | | | | | | | | | | | | IADP monitoring bit was set to the default value for the devices with an RO image which clears the bit (and causes the issue). This patch removes the code so that we do not touch the IADP monitoring bit since transitioning from 0->1 may cause other issues. BUG=b:35647661 BRANCH=reef TEST=none Change-Id: I4413e0bd2de3f4e3912cbe6e73b8cad641ee9245 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/453400 Reviewed-by: Shawn N <shawnn@chromium.org>
* charger/bd9995x: enable IADP bit when charger init.Bruce2017-03-131-2/+3
| | | | | | | | | | | | | | | | | | | | When plug in adapter with dead battery, the charger will be flow back to the adapter. Then adapter will OVP. Enable IADP bit at address 0x40(BD9995X_CMD_VM_CTRL_SET) when charger init. It will fix this phenomenon. Enable IADP pin current limit due to we've already deployed the clearing to existing. BUG=chrome-os-partner:62646, 61691 BRANCH=reef TEST=check charger don't flow back to adapter with dead battery Change-Id: Id6202f3dd51cb7e1c43a124660e09de39f6c041b Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/453399 Reviewed-by: Shawn N <shawnn@chromium.org>
* snappy: Disable MPUBruce2017-03-111-0/+2
| | | | | | | | | | | | | | | | | Follow reef setting. BUG=none BRANCH=reef TEST=Boot to OS Change-Id: I510b7375dd492882e99fdc7fabeac016455c212c Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/452399 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 67ce1579a8892c2f30d8f54d3c8fcb9d72d6c56a) Reviewed-on: https://chromium-review.googlesource.com/453140
* pyro: Disable MPUBruce2017-03-101-0/+2
| | | | | | | | | | | | | | | Follow reef setting BUG=none BRANCH=reef TEST=Boot to OS Change-Id: I0bc69931c90463cdb04b90cde02f8a7d864a2607 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/453138 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* snappy: Add state for discharge + fullBruce2017-03-102-0/+7
| | | | | | | | | | | | | | | | | | Follow reef setting. When battery is fully charged, light white. BUG=none BRANCH=reef TEST=Fully charge. Plug in charger. LED lights white. Change-Id: I1096fe616ab5ec5954eea142e28fad08f16731ed Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451228 Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com> Tested-by: Bruce Wan <Bruce.Wan@quantatw.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 876157085e0ce53de870f23993a6badc5683f16d) Reviewed-on: https://chromium-review.googlesource.com/452184
* Electro: DP CTS testing failed in HBR2 deterministic JitterRyan Zhang2017-03-102-0/+5
| | | | | | | | | | | | | | | | Uploading CL according EE's requirement. Need to overwrite PS8751 Address: 0x16, offset: 0xD3, Data: 0x98 BUG=b:36044164 BRANCH=firmware-reef-9042.B TEST=`make -j BOARD=reef` Change-Id: I60d5c6724fd047770ddd0af1d204571d59c6e25e Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451047 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* pyro: Add state for discharge + fullBruce2017-03-092-0/+10
| | | | | | | | | | | | | | | | | | | | Follow reef setting. When battery is fully charged, pyro starts discharging to protect battery and starts charging again when charge level goes down around 95%. To prevent the battery LED from showing green with the charger plugged in. BUG=none BRANCH=reef TEST=Fully charge Electro. Plug in OEM charger. LED lights green. Change-Id: If8560cbc3975b35ae84a9df2bdf5331c653143d1 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/452180 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* pyro: Lock EC and PD communicationBruce2017-03-091-6/+1
| | | | | | | | | | | | | | | | | | | Follow reef setting BUG=none BRANCH=reef TEST=make buildall Change-Id: I5e6bfed319f1cda8b2719393210a503c416d404e Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/444487 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b8c896788390526441fa52a0a3ce0b58675e7bc1) Reviewed-on: https://chromium-review.googlesource.com/451681 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* snappy: limit max input current for safetyBruce2017-03-091-0/+1
| | | | | | | | | | | | | | Cancel snappy total power spec (adapter - 5W), follow reef setting. Max = Max * 95% BUG=b:35937839 BRANCH=reef TEST=make buildall Change-Id: Id1742313b1d738f3401742f35229864611cf5de9 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451227 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* anx74xx: fix role bits for GOOD_CRCVincent Palatin2017-03-082-37/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were 2 mistakes when setting the data/power roles for automatic GOOD_CRC: - the bit numbers for data role and power role were swapped. - the function can only set and not reset the bits. Try to simplify this code by: - removing the duplicated name for register 0x9C (aka AUTO_GOODCRC_1) - avoiding the multiple read/modify/write by using AUTO_GOODCRC_1 for the actual settings (and letting the enable bit always on) and GOOD_CRC_2 for enabling/disabling it, so we can do simple writes. - answer only on SOP (not SOP' or SOP''). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=reef BUG=b:35648282 TEST=On Snappy, connect a given power supply, record the USB PD traces and see that the GOOD_CRC messages are still correct after the DR_SWAP. Change-Id: I848b1dcbc0e06806649e64a9664f3fba21bdd448 Reviewed-on: https://chromium-review.googlesource.com/448040 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: S Wang <swang@analogix.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit c21ad5898e452bdd0646db3c1b6fbe4721034b8e) Reviewed-on: https://chromium-review.googlesource.com/451678 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Reef: Disable MPUDaisuke Nojiri2017-03-081-0/+2
| | | | | | | | | | | | | | | | Reef RAM / code regions aren't a power of 2, so we cannot program MPU to protect the regions we desire. BUG=b:36037354 BRANCH=none TEST=Boot to OS Change-Id: I2d1e87eb97f9524620943262845823331f9f71a0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/450831 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e30782912d080ead3a50deaf475b3880f7d2c91) Reviewed-on: https://chromium-review.googlesource.com/451677
* Sand:update battery configRyan Zhang2017-03-082-582/+148
| | | | | | | | | | | | | | | | | | | | | | Change charging policy to Lars' to followed battery's requirement. To make sure battery can provide power, we need to check DFET is on/off. This would be done in another patch after battery vendor provide register data. + remove reef's fast charge policy + Add SMP battery config + Add LG battery config BUG=None BRANCH=firmware-reef-9042.B TEST=system can find different battery and charge normally. Change-Id: Iae4f9ed013c7ceb54cbdade7a0294163c230dad8 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/445846 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
* pdcontrol: Suspend port individuallyDaisuke Nojiri2017-03-076-70/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pdcontrol suspend command will be used to prevent tcpm from putting the chip into sleep while firmware update is taking place. Currently the command suspends or resumes port 0. This patch makes the command apply to ports individually. pd enable console command now takes a port number: pd <port> enable/disable. This patch also replaces CONFIG_USB_PD_COMM_ENABLED with _DISABLED. When it's defined, PD communication is disabled at startup. Plankton undefines CONFIG_USB_PD_COMM_ENABLED enable, intending to disable PD communication at startup. Therefore, this patch defines CONFIG_USB_PD_COMM_DISABLED in its board.h. BUG=b:35586859 BRANCH=none TEST=From AP console: localhost # /tmp/ectool pdcontrol suspend 1 [600.188013 TCPC p1 suspended!] > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SUSPENDED, Flags: 0x0020 localhost # /tmp/ectool pdcontrol resume 1 [678.516613 TCPC p1 resumed!] > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 From ec console: > pd 1 disable Port C1 disable > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 > pd 1 enable Port C1 enabled > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 Change-Id: Ia0cc4904ac52adc4b89de20918968c8df78b9c80 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/447968 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit ad089de4b0430e5d997b9f6d6f187daae1fb11dc) Reviewed-on: https://chromium-review.googlesource.com/450990 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* pyro: Fix power-up sequence for Anx3429Bruce2017-03-071-4/+16
| | | | | | | | | | | | | | | | | | Power-up sequence must bring up PWR_NE followed by RESETN according to Figure 5-16 of the datasheet. Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: I8d411ec8f38f20d3d9572426db189ce94fa68b54 Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/451043 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
* pyro: Set RW boot power threshold to 18wBruce2017-03-071-1/+1
| | | | | | | | | | | | | | | | | | Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: If5964ba7416ebfdf235acb5bdaf7d911331b85ef Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/449560 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e0b5aabd2b4f87deffff6b60057846be371103e) Reviewed-on: https://chromium-review.googlesource.com/451038 Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com>
* pyro: Name USB port numbers appropriatelyBruce2017-03-071-9/+22
| | | | | | | | | | | | | | | | | | | | | Some USB PD port numbers are not named. Some numbers are named using I2C port names. This patch fixes them Follow reef setting. BUG=none BRANCH=reef TEST=make buildall Change-Id: I4a9d3a765f6de84ac1a6f3e903171a505bc37d6c Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/449123 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f2162b401bb8059709ae2caf0bf0eb2b353618f) Reviewed-on: https://chromium-review.googlesource.com/451037 Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com>
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