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* pylintrc: Copy Chromium OS platform2's configCraig Hesling2021-08-0230-0/+476
| | | | | | | | | | | | | | | | | | | | This requests that cros lint (and repo upload hook) use the new Chromium OS 4 space indent policy. Since legacy python scripts still use 2 space, I added pylint ignore statements to the individual files to disable indentation checking. Note: There are still valid pylint errors in some of these legacy scripts. BRANCH=none BUG=none TEST=cros lint util/*.py Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I439f5a87bc50f1f43a4996e574bbc0626922a88e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3064761 Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* COIL: chip/it83xx: Rename SPI IRQ configCaveh Jalali2021-08-025-10/+10
| | | | | | | | | | | | | | | This renames the ITE chip specific SPI IRQ config from IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: chip/it83xx: Rename SPI MAX_FREQ configCaveh Jalali2021-08-023-7/+16
| | | | | | | | | | | | | | | | This renames the ITE chip specific SPI speed configuration from IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE to IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: If2fcb086a8c35cf43ce15dc0963f3febbaa25f45 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061912 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: chip/it83xx: Update SPI terminologyCaveh Jalali2021-08-023-39/+39
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I6f5ac12ff64fe870709dc91bca71e0901bed3420 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061911 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* storo: update EC thermal tablemike2021-08-022-0/+37
| | | | | | | | | | | | | | Update EC thermal table for throttle and shutdown point. BUG=b:194967456 BRANCH=dedede TEST=make BOARD=storo and verify function pass by thermal team. Signed-off-by: mike <mike5@huaqin.corp-partner.google.com> Change-Id: Ia5f78111c40aee613bfba5e96ce0af93cb7c81e5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3062706 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* test: Start host test timer near 32-bit rolloverEvan Green2021-08-021-2/+12
| | | | | | | | | | | | | | | Rather than starting the timestamp at 0 for each test, let's start it just before the 32-bit rollover. This gives us more of a chance to catch 32-bit rollover issues in the tests. BUG=b:179062230 BRANCH=none TEST=make -j runhosttests BOARD=host Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ia0551b4409c4bc63938f319312f6c66acf7c6cd9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059233 Reviewed-by: Diana Z <dzigterman@chromium.org>
* make: Compile host tests in 32-bit modeEvan Green2021-08-023-3/+7
| | | | | | | | | | | | | | | | | Compile the host tests in 32-bit mode instead of 64-bit mode as it's more likely to match the actual environments our ECs run on. For instance, in 32-bit mode the tests might actually have a prayer of finding a torn read or write bug, whereas in 64-bit mode 64-bit integers are always operated on atomically. BUG=b:179062230 BRANCH=none TEST=make -j runhosttests BOARD=host on x86_64 and i686 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I02517066337ec08c311c1f7daae5d3de84b1f4c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059231 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* test: Crispen up fp host testEvan Green2021-08-021-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some issues with the FP test in preparation for switching the host tests to compile in 32-bit mode. There are a few things going on with the FP tests. The first thing to know about x86 is the compiler has a hard time restricting itself to 32-bits even when you're seemingly only working with float types. Part of this is C's fault, since C promotes floats to doubles in cases like arguments handed to printf. This results in weirdness. For instance, if I add a union like this: union evanfloat { float f; unsigned int i; }; And then print out the result and golden values from test_fpv3_dot(), I get this: 421a5e35 421a5e35 38.592000 38.591999 How is it that the same hex value prints two different floats, even when the values I'm passing are from the union, and I can see the byte value contents of the floats are the same? The compiler gets exuberant here and keeps the computation result in the floating point registers, then lets them ride on through to printf. As an experiment, I tried printing values from this union instead: union evandouble { double d; unsigned long long i; }; And I get the following: 40434bc6a58b4390 40434bc6a0000000 38.592000 38.591999 What this shows is that even though the return type of fpv3_dot() is a float, the compiler is carrying around the extra precision of a double computation. The test was all carefully crafted to have the correct answers, unfortunately with this implicit double advantage built in. So we run afoul of this when we try to compile with -m32. i686 only has access to the old x87 FPU instructions, rather than SSE2 that's part of AMD64. As such, the double advantages come out slightly different, resulting in 1ULP (unit in last place) variations between x86_64 and i686. These are likely errors that accumulate differently in intermediate results of functions like fpv3_dot(). Really that's all fine, we just have to account for this in the test so that both x86_64 and i686 can pass correctly. In some cases like test_fpv3_dot(), this can be achieved by creating a volatile fp_t and assigning the result to that. This forces the compiler to dump the final value out of the FPU registers and save a float into memory, truncating the hidden double bits. In other cases, AMD64 and i686 disagreed by 1ULP, but the golden value disagreed with both by a handful of ULP. Fix those golden values so their hex values lined up better. But even with the fixed golden values, amd64 and i686 still disagreed on some results by 1ULP. In these cases it was necessary to increase the tolerance from 0.0 to an approximation of 1ULP. As a side note, expressing the tolerances as absolute values is a bit brittle, as it requires that your testing values and results stay within a certain exponent. If we were to write a new floating point test, it might be better to have the test comparison macros decompose the values into exponent and mantissa, and then compare those separately with a tolerance on the mantissa. BUG=b:179062230 BRANCH=none TEST=make -j runhosttest BOARD=host on both amd64 and i686 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I3f8d36713dfa9f2f8adefb1b4db1e47b84dec1f0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059227 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* test: Ensure time move forward in usb_pd_intEvan Green2021-08-021-2/+5
| | | | | | | | | | | | | | | | | | | | test_storm_not_triggered_for_32bit_overflow wanted to check to ensure the storm detection worked across the 32-bit boundary, so it forced the current time to 0xff000000. It assumed however that this timestamp was in the future. If it's in the past (say for instance someone else has bumped time forward) then the storm tracking is broken and this test fails. Since it is not the goal of this test to see how the storm tracker behaves when time moves backwards, fix up the test to ensure it's got the high bit set but is also in the future. BUG=b:179062230 BRANCH=none TEST=make -j runhosttests Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Iac4c68e2bf46649a01477dbd1dabfcf0d95b1371 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059232 Reviewed-by: Jett Rink <jettrink@chromium.org>
* test: Make more and smaller allocations in shmallocEvan Green2021-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The shmalloc test works like this: * Randomly select a slot out of 12. * If that slot is occupied, free it. If that slot is free, attempt to make an allocation of size rand() % total_heap_size. * At the end of the test, assert (among other things) that we were able to make at least 5 allocations at once given 500000 iterations. It turns out that getting 5 outstanding allocations at once using this algorithm is not trivial. I did a simulation with a simpler version of this that just attempts to make (rand % total) size allocations without overflowing the max [1], and found that the average number of allocations you're able to make is about 1.8, with a standard deviation of 0.9. That means that the test is asserting that in 500000 iterations it will be able to do >3 standard deviations better than the mean in ~500000/1.8 iterations. Since we never vary the rand seed, and we happened to get lucky with the default seed, it all works. But when I try to compile in 32-bit mode, I think I get an unlucky default seed, and always fail this 5 allocation test. There are a few knobs you could twist to fix this: * You could reduce the allocation bar below 5. * You could increase the iteration count above 500000. * You could increase the slot count above 12 so that the first dice roll favors trying allocations more. * You could decrease the max allocation size from "total" to reduce the amount each allocation can occupy. This change opts for the last option. Reducing the max allocation to total / 2 increases the (simplified) simulation result to a mean of 3.5 with a standard deviation of 1.27. This means the test now only has to do better than < 1 standard deviation from the mean in 500000 iterations. This is still probabilistic, but is much less likely to break if you sneeze on it wrong. [1] https://paste.googleplex.com/6653229610827776 BUG=b:179062230 BRANCH=none TEST=make -j runhosttests BOARD=host and x86_64 and i686. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ifb16533ee6fa02ce2613c32b1462b78ef0c6cd21 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059230 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* test: Fix sbs_charging_v2's charge_control() cmd versionEvan Green2021-08-021-1/+1
| | | | | | | | | | | | | | | | | charge_control() was sending EC_CMD_CHARGE_CONTROL version 2, but leaving params.cmd uninitialized. Apparently we were just getting lucky. I did not get as lucky when compiling in 32-bit mode. This test is clearly sending the version 1 form of the command, so make the version number match the intent so the EC doesn't fail the command. BUG=b:179062230 BRANCH=none TEST=make -j runhosttests BOARD=host on x86_64 and i686 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ie440ff825e1125bb50b4ac2477ba983e00ef303e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059229 Reviewed-by: Diana Z <dzigterman@chromium.org>
* spherion: config GPIOA2 to INPUT + PULL DOWNBen Chen2021-08-021-1/+1
| | | | | | | | | | | | | | sysjump to RW the GPIO init PULL up, will cause keyboard backlight blinking. BUG=b:194047863 BRANCH=asurada TEST=sysjump RO/RW to check, backlight don't blinking. Change-Id: I27adfb99b2b9c7708302556eb07b87d5130db777 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063877 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* primus: remove CONFIG_BRINGUPScott Chao2021-08-021-1/+0
| | | | | | | | | | | BUG=b:193377625 BRANCH=none TEST=make -j BOARD=primus Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Ie0747b50511261f91b55f97d9f88301c84b577b9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3065246 Reviewed-by: caveh jalali <caveh@chromium.org>
* Pico: Support motion sensorsSue Chen2021-08-024-9/+137
| | | | | | | | | | | | | | Lid Accel: KX022 BASE Accelgyro: BMI160 BUG=none BRANCH=icarus TEST=EC can read sensors' data and lig angle is correct. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I07743c86a3d133dd96e499f23150fd4f20340470 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3062062 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* bland: initial commitTing Shen2021-08-023-0/+37
| | | | | | | | | | | | | | | Bland is the detachable keyboard (Hammer derivative) for MrBland project. BUG=b:194460146 TEST=make BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I6c315cca6856afca175ce864ece025222b1a2d69 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3062678 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* zephyr: shi: it8xxx2: create phandle of pinmux controlTim Lin2021-08-024-6/+69
| | | | | | | | | | | | | | | | | | | Create the pinmux phandle to the SHI driver node in the devicetree. When the pinmux_pin_set function in cros_shi_ite_init can refer to the setting of phandle. It is more flexible to use. BUG=b:187541831 BRANCH=none TEST=host command is normal. Cq-Depend: chromium:3041210 Cq-Depend: chromium:3056118 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: I0c71333563eb7da04d29b82767b6a6660d867eed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3045026 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* COIL: SPI: Update terminologyCaveh Jalali2021-08-011-1/+1
| | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: Iffe3276d54ee1431d1712b7a071883a99c604a19 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060263 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: FPC: Update SPI terminologyCaveh Jalali2021-08-011-3/+4
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I2dc308bfc80c5921dcc172bee433a6502105852f Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jora Jacobi <jora@google.com>
* COIL: npcx: Update SHI terminologyCaveh Jalali2021-08-011-5/+5
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I045ae5f148fe6233abf921d99f381b2cce6966ad Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060260 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* gimble: remove ap mode entryScott Chao2021-07-311-2/+0
| | | | | | | | | | | | | | Gimble don't have TBT and USB4, EC can enter ALT mode by itself. BUG=b:195087071 BRANCH=none TEST=make -j BOARD=gimble TEST=type-c monitor can display. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I820d5142e277fc6a3794ed90730b634787a2d022 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063110 Reviewed-by: caveh jalali <caveh@chromium.org>
* test: Fix printf formatting in usb_typec_drp_acc_trysrc.cEvan Green2021-07-311-2/+2
| | | | | | | | | | | | | | | | | | Fix a couple of minor formatting errors where constants with LL or ULL suffixes were being printed. On x86_64 printing these as %l is fine because longs are 64-bits. On i686 this comes out as an error because long is 32-bits. Use the correct ll specifier for these, and in one case ensure it comes out as a 64-bit value by adding LL. BUG=b:179062230 BRANCH=none TEST=make -j runhosttests on i686 and x86_64 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ic59c9647aa70f58e497b9615122ca4c202504365 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059228 Commit-Queue: caveh jalali <caveh@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* util: Add keeby-relevant-paths.txtAseda Aboagye2021-07-301-0/+1
| | | | | | | | | | | | | | | | | Keeby is largely based off of dedede so add a relevant paths file which is just a symlink to dedede's file. BUG=None BRANCH=keeby TEST=Check symlink points to dedede's file. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ib347e4a2311cbbb94f4689ed967b9806bea3ed5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063979 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* flash: Set CBI EEPROM WP immediately if SW WP setAseda Aboagye2021-07-303-0/+50
| | | | | | | | | | | | | | | | | | | | | | With `CONFIG_EEPROM_CBI_WP`, the EC will set the the CBI EEPROM WP according to `system_is_locked`. The system lock status is also cached. In order to prevent requiring an EC reboot after setting the software write protect status, this commit will set the CBI EEPROM WP status when the SW WP is asserted along with the HW WP. This is the same criteria that `system_is_locked` would use when deciding if the system is locked. BUG=b:181769483 BRANCH=None TEST=Build and flash a reworked lalala, enable HW WP, enable SW WP via `flashrom -p ec --wp-enable` and verify that EC_CBI_WP is asserted immediately without requiring an EC reboot. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I987a5b7652134be11c82855aab9ed4eb1442b57c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058077 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m*: make watchdog code more readableRicardo Quesada2021-07-302-4/+20
| | | | | | | | | | | | | | | | | This CL makes the code more readable by adding comment / defines regarding the meaning of PSP[5] and PSP[6]. BUG=None TEST=make buildall BRANCH=None Change-Id: I0cbe7384e20f0287096624a00b0ec19c0fb7f9bd Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059814 Tested-by: Ricardo Quesada <ricardoq@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ricardo Quesada <ricardoq@chromium.org> Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
* zephyr: npcx_evb: Enable PWMWealian Liao2021-07-3010-0/+112
| | | | | | | | | | | | | | | | | | | | This CL enables 2 PWM channels for npcx7/9_evb. BRANCH=none BUG=none TEST='pwmduty' console command & check the output waveform is correct. ``` uart:~$ pwmduty PWM channels: 0: 50% 1: 25% ``` Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I6fa5d3b7fd3bf1f9d1fdb3f64ca3488ad3addacc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063104 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* config: Delete obsolete configsKeith Short2021-07-302-12/+0
| | | | | | | | | | | | | | | | | | | | | Delete the following configs which are no longer referenced by any source files: CONFIG_CMD_FLASH_LOG CONFIG_CMD_GSV CONFIG_CMD_GSV CONFIG_CMD_LID_ANGLE CONFIG_CMD_PMU CONFIG_CMD_USBMUX BUG=none BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia304f0579d991a0fccc7bbc7ca7427fe0ed661a1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061902 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* assert: Fix ASSERT() when !CONFIG_DEBUG_ASSERT_REBOOTSKeith Short2021-07-301-6/+20
| | | | | | | | | | | | | | | | | | | | | | The option CONFIG_DEBUG_ASSERT_REBOOTS can be undefined to save code size and generate a software breakpoint to recovery. Fix this code path to support the RISC-V and NDS32 architectures. This also fixes an incorrect usage of __builtin_unreachable() which caused all ASSERT() calls to generate an unconditional return. BUG=none BRANCH=none TEST=Disable CONFIG_DEBUG_ASSERT_REBOOTS, run "crash assert" on hayato (RISC-V architecture) and lazor (ARM architecture). TEST=Disable CONFIG_DEBUG_ASSERT_REBOOTS on boten (NDS32 architecture) and verfiy code compiles Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Iff2455fd209355d4276488b48f7b1dfe52cc35b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061077 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: npcx_evb: Enable ADCWealian Liao2021-07-306-2/+47
| | | | | | | | | | | | | | | | | | | | | | This CL enables 5 ADC channels for npcx7/9_evb. BUG=none BRANCH=none TEST='adc' console command ``` uart:~$ adc ADC0 = 2813 mV ADC1 = 2813 mV ADC2 = 2813 mV ADC3 = 2813 mV ADC4 = 2813 mV ``` Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I08d60dc732f7388642a54eec090ef7bf15760a2a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063103 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: npcx_evb: Remove BOARD_ROOT settingWealian Liao2021-07-302-2/+0
| | | | | | | | | | | | | | | CMakeLists no longer needs to set BOARD_ROOT. Remove it to fix the CMake warning message. BUG=none BRANCH=none TEST=zmake testall Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I80a1f1c62cec70e5bbd063e20cacdc62e78b5f4a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063102 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* it83xx: i2c: don't check bus busy if transaction is ongoing.Dino Li2021-07-301-4/+9
| | | | | | | | | | | | | | | | | | | | | This CL fixes that i2c driver will prompt "I2C chx reset cause 1" issue when one i2c transaction is separated into at least three i2c_xfer and I2C_XFER_START flag is set at least two times. eg. - i2c_xfer with I2C_XFER_START flag - i2c_xfer with I2C_XFER_START flag <= this will cause reset - xxx - i2c_xfer with I2C_XFER_STOP flag BRANCH=none BUG=none TEST=no i2c reset on Asurada, Drawcia, and ADL-RVP. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I97161db0bb0c54de3ad55d82512a6a188036270f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058724 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* biod: Add fptool.py that will replace flash_fp_mcuCraig Hesling2021-07-301-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is similar to gsctool, but this tool would only be in the test image. This comes from the effort to move away from shell script. See http://go/deshell. The idea is that you start with a simple wrapper for the given shell script. Over time, features are transplanted or added-new to the python wrapper, until the shell script is no longer needed. BRANCH=none BUG=b:172020576 TEST=./util/fptool.py ./util/fptool.py --help ./util/fptool.py flash --help ./util/fptool.py flash # Error about flash_fp_mcu not existing TEST=scp util/fptool.py $DUT:/usr/local/bin ssh $DUT fptool.py flash /root/doesnotexist ssh $DUT fptool.py flash ssh $DUT fptool.py flash /opt/google/biod/fw/$(cros_config /fingerprint board)*.bin Change-Id: I8774bda4a057ee09f70bf474ce3ba2fa0bbcf92d Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060744 Reviewed-by: Josie Nordrum <josienordrum@google.com>
* Ezkinil: Add PS8818 for TYPEC C1 secondary MUXSue Chen2021-07-304-1/+44
| | | | | | | | | | | | | | | Use SSFC bits 6-7 to choose which secondary MUX is used. BUG=b:192523667 BRANCH=zork TEST=After setting SSFC to 0x80 on the DUT with PS8818, the typec on DB works fine. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I8a66098d1e9b947acfb26b78f0cec7f835bf4c40 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000894 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* common: system: always define host_command_get_board_versionDenis Brockus2021-07-291-2/+0
| | | | | | | | | | | | | | | | | | | There are platforms that have board defined get_board_version and they should be allowed to have host_command_get_board_version even if CONFIG_BOARD_VERSION_* are not defined. BUG=none BRANCH=none TEST=make buildall TEST=zmake configure -b $PROJ_HAYATO Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I6e2765b40c7cbada82a8ace305899f2e319157c3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058354 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* dooly: refactor tcs3400_translate_to_xyz()Nikolai Artemiev2021-07-291-57/+63
| | | | | | | | | | | | | | | | | | | | | | | Refactor tcs3400_translate_to_xyz(): simplify calculations, reduce code duplication, avoid integer overflow, and guard against division by zero. Previously there were several places where integer values could overflow, such as converting 16-bit unsigned integers to fp_t values and multiplications with results exceeding the range of fp_t. In practice operations would overflow when holding a phone flashlight in front of the light sensor. BUG=b:179960346 BRANCH=none TEST=Flashed EC and tested sensor with a phone flashlight. Logging output values from old/new implementations showed no changes, except when the old implementation overflowed. Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I52c37414b5205beaefa2111b1737b0eb22b7235a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3007377 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
* adlrvp: enable AP driven mode entryli feng2021-07-291-0/+2
| | | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST= 1. make BOARD=adlrvpp_ite pass 2. on ADL-P RVP, connect USB4 device to port 0, AP requests to enter mode USB4; EC set up USB4 successfully, and enumeration in sysfs is correct. Signed-off-by: li feng <li1.feng@intel.com> Change-Id: Ia6e503c19871928b3b9cc5049079fb40778a6bea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999438 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* zephyr: asurada: cleanup board id/versionDenis Brockus2021-07-292-3/+1
| | | | | | | | | | | | | | | | | Make board_get_version an __override function. Removed unused CONFIG_PLATFORM_EC_BOARD_VERSION_ defines. BUG=b:195037412 BRANCH=none TEST=zmake configure -b $PROJ_HAYATO Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ie8bb565fb5d649c5e0de771e0dfd6fecaee07a53 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061264 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* keeby: Add GPIO_EC_CBI_WPAseda Aboagye2021-07-295-1/+7
| | | | | | | | | | | | | | | | | This commit simply adds the GPIO_EC_CBI_WP pin for the keeby boards and also sets CONFIG_EEPROM_CBI_WP. BUG=b:181769483 BRANCH=None TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I31694cb748d8b8a197b84634fbd9417d274a79d7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3046413 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* cbi: Add CONFIG_EEPROM_CBI_WPAseda Aboagye2021-07-2911-3/+132
| | | | | | | | | | | | | | | | | | | | | This commit adds the config option, CONFIG_EEPROM_CBI_WP. It is to be defined when the EC directly controls the CBI EEPROM WP signal. The EC will set the WP according to the result of `system_is_locked()`. Note that once the WP is set, the EC must be reset via EC_RST_ODL in order for the WP to become unset. This is enabled by the accompanying hardware. BUG=b:181769483 BRANCH=None TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If490594ab4dd24af98119b01299215b997913b66 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3046412 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: npcx_evb: Enable I2CWealian Liao2021-07-298-82/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL enables I2C for npcx7/9_evb. Currently, zephyr-OS ec doesn't use the GPIO for i2c unwedge functionality. Remove the GPIO setting for i2c in gpio.dts. BUG=none BRANCH=none TEST=Get sensor value by `i2c` shell command ``` uart:~$ i2c scan I2C_2_PORT_0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- 48 -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- 1 devices found on I2C_2_PORT_0 uart:~$ i2c read I2C_2_PORT_0 0x48 0x00 2 00000000: 1f 80 ``` Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: If5029c41b7ba5400ee1492b408f7ab6975218c5b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060348 Reviewed-by: Yuval Peress <peress@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org>
* guybrush: Enable keyboard factory testRob Barnes2021-07-292-0/+18
| | | | | | | | | | | | | | Enable keyboard factory test. The keyboard pinout is similar to Ezkinil so this is used as starting point. BUG=b:178221983 TEST=ectool kbfactorytest passes BRANCH=None Change-Id: Ie365d184eb8144c2138e6ae56fe3a401b6035982 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3053096 Reviewed-by: Diana Z <dzigterman@chromium.org>
* voema: Remove base sensor support kx022David Huang2021-07-292-34/+6
| | | | | | | | | | | | | | | Remove base sensor support kx022 due to kx022 not support gyro and base sensor need gyro. BUG=b:192301309 BRANCH=volteer TEST=make buildall -j succeeded. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I6ff1bf9488d816be680a395334ea3008b9280890 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3029802 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* voema: Add accel/gyro sensor icm40608David Huang2021-07-293-1/+81
| | | | | | | | | | | | | | | Support accel/gyro sensor: icm40608. BUG=b:192301309 BRANCH=volteer TEST=Motion sensors are detected correctly and ectool motionsense show correct data. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I35cb0fca753768468f07581251234149db5a04b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3020667 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* Pico: Initial EC imageSue Chen2021-07-298-0/+866
| | | | | | | | | | | | | | | Create the initial EC image for the pico variant by copying the icarus reference board EC files into a new directory named for the variant. BUG=none BRANCH=icarus TEST=make BOARD=pico Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I0eeae3e76b1cfabd0be54d1b29c9af7fac1238c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058159 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* tomato: enable port 0 bc12 functionTing Shen2021-07-292-2/+10
| | | | | | | | | | | | | | | | Tomoto port 0 bc1.2 solution is changed from PI3USB9201 to MT6360. Update board code to reflect this HW change. BUG=b:192422592 TEST=manually test bc1.2 detection BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I855815b5c8d85c9807455fe658a38bdac59b1399 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3031241 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* cherry: enable usb pdTing Shen2021-07-296-76/+221
| | | | | | | | | | | | | BUG=b:177391887 TEST=verify pd works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ied4516abef3d544b8b4bdf8355f0f9fc305629a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2793783 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* zephyr: asurada: correct RO/RW size and offsetDino Li2021-07-291-3/+3
| | | | | | | | | | | | | | | | | | it8xxx2's memory-mapped flash layout are as the below: - RO image starts at the beginning of flash. - PSTATE immediately follows the RO image. - RW image starts at the second half of flash. And its flash size is 1M byte. So let's correct RO/RW size and offset. BRANCH=none BUG=b:194794622 TEST=sysjump rw/ro, sysinfo. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I1130d670af054d88f7dfd1874ba5ecfd22b500df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058156 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* rt1718s: fix incorrect alert methodTing Shen2021-07-291-1/+1
| | | | | | | | | | | | | | | | | | | | rt1718s driver incorrectly used the common alert function instead of its own implementation. This bug was not detected by `make buildall` because no one actually enables rt1718s until CL:2793783. BUG=b:177391887 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I303cb0b6b7d0177648871ea36c1fc5c513fbb336 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058082 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* lalala: Add EC_CBI_WPAseda Aboagye2021-07-291-1/+1
| | | | | | | | | | | | | | | | | This commit adds a new pin, EC_CBI_WP which will allow the EC to set the CBI WP accordingly. BUG=b:194429731 BRANCH=None TEST=`make -j BOARD= lalala` Change-Id: I0f4091b9a1fa056bd778c7d3aae3eb48345e94a8 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3046411 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* ppc/rt1718s: notify charger task about vbus changeTing Shen2021-07-292-14/+48
| | | | | | | | | | | | | | | | | | | PPC driver is responsible to notify charger task about vbus change. Original driver didn't implementation this. Also make BC1.2 driver correctly enables BC1.2 detection on vbus change. BUG=b:192422592 TEST=manually verify PD and BC1.2 works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I0bcbe0a1a43d9a9bcae61d69e247829648dd0d7c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3045249 Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* atomic.h: atomic_clear_bits: return previously stored valueTing Shen2021-07-296-11/+14
| | | | | | | | | | | | | | | make the api consistent with other atomic methods BUG=b:192422592 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I6cae4d521b44706cf7f44c669bf6964a08855b4c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058080 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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