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* file_lock: Add fallback directorystabilize-8350.68.Brelease-R52-8350.BDavid Hendricks2016-06-071-16/+27
| | | | | | | | | | | | | | | | | | | | This adds a fallback directory in case SYSTEM_LOCKFILE_DIR is unavailable. Since this is a band-aid meant to help older systems auto-update, the fallback path is hardcoded to "/tmp" as to avoid polluting the overall lockfile API. BUG=chromium:616620 BRANCH=none TEST=Tested on veyron_jaq by removing /run/lock and seeing mosys, flashrom, and ectool run successfully with firmware_utility_lock in /tmp. Change-Id: Idbe63a574474ec35a5c3b6fe2b0fb3b672941492 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/348850 Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 4b680119cc1de2dda7c0b625c4fea1d1e964189a) Reviewed-on: https://chromium-review.googlesource.com/350202
* spi_flash: Add protect_range table for W25Q40stabilize-8350.21.BDavid Hendricks2016-05-192-0/+49
| | | | | | | | | | | BUG=chrome-os-partner:53035 BRANCH=none TEST=needs testing Change-Id: I4b2bc758a22c2c19ddf0438a2af26f8c76093081 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339291 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* elm: Set internal pull-high to GPI pins below.tonycwlin2016-05-191-4/+4
| | | | | | | | | | | | | | | | | PE1 (BC12_ANX7688_INT_L) PE7 (ANX7688_CABLE_DET_EC_L) Cost down 2 resistors. BUG=none BRANCH=none TEST=Measure this two pins and verify voltage with digital meter. Change-Id: Ic4456d372171933b4ac45942dba9a28c5bd80d3d Reviewed-on: https://chromium-review.googlesource.com/345746 Commit-Ready: Tony Lin <tonycwlin@google.com> Tested-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Rong Chang <rongchang@chromium.org>
* COMMON: Add extend function for tmp432 ICRyan Zhang2016-05-182-0/+90
| | | | | | | | | | | | | | + create interface to set ALERT# pin as THERM mode and set high limit for a selected channel BUG=None BRANCH=master TEST=`make -j runtests` Change-Id: I7325eb9ddfcaca3ea873e1ee71da74258d7bec72 Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/344435 Reviewed-by: Shawn N <shawnn@chromium.org>
* chip: it83xx: Optimize interrupt usage of LPC accessDino Li2016-05-185-26/+16
| | | | | | | | | | | | | | | | | | LPC access interrupt only enabled when EC entering deep doze mode. This will reduce interrupt of LPC access. Also, this interrupt is always enabled for LPC platform to support "CONFIG_LOW_POWER_S0". Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Tested ectool command 'version' x 10000. Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a Reviewed-on: https://chromium-review.googlesource.com/336112 Commit-Ready: Dino Li <dino0303@gmail.com> Tested-by: Dino Li <dino0303@gmail.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Modify gpio's interrupt utilitiesMulin Chao2016-05-181-22/+14
| | | | | | | | | | | | | | | | | | | | | | Setting NVIC_EN register is not a suitable method if you want to turn on/off one GPIO's interrupt. Since there're eight sources belong to the same interrupt, using MIWU_EN register which bit belongs to one MIWU's source is a better way. Modified sources: 1. gpio.c: Replace accessing NVIC_EN register with MIWU_EN in gpio's interrupt utilities. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: I282a45f5a3ab7cb032b2282cf7e92cacc5e706b6 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/342122 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* TCPM : Added driver for Analogix's anx74xx chipsAman Kumar2016-05-184-0/+955
| | | | | | | | | | | | | | | | | | | | | | | | Driver implements TCPC for ANX74xx chips. Enables Type C port for USB and DP alt mode. Enable port role swap feature. Driver implements TCPC for ANX74xx chips firmware version 1.0 and later. Please update to ANX74xx firmware to V1.0 or later version to work. Change list: 1, modify the position of define and struct declare which response the comment for patch 22. BUG=chrome-os-partner:49510 BRANCH=none TEST=tested compiled binary for pdeval-stm32f072 board with this patch. Power contract establishment, port role swap, DP alt mode works fine. Change-Id: Iae6322510605a08d3bdd08446116ef5f9e4f7a7c Signed-off-by: Aman Kumar <akumar@analogixsemi.com> Signed-off-by: Junhua Xia <jxia@analogixsemi.com> Reviewed-on: https://chromium-review.googlesource.com/322433 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin / gru: Update battery parametersShawn Nematbakhsh2016-05-181-3/+16
| | | | | | | | | | | | | | | | | Update battery parameters to match the batteries actually present on these devices. BUG=chrome-os-partner:53002 BRANCH=None TEST=Manual on kevin. Verify battery successfully charges and discharges from AC. Change-Id: I84579c23fe9fec1aecf133887a2d5b880047772f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344935 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* LED: add green/red support for host commandsZhengShunQian2016-05-181-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | The host command(ectool) to set led colors will read the brightness range and then set as requested. If brightness range is 0, then it will just return INVALID_PARAM. BUG=chrome-os-partner:35416 TEST=build and run on veyron ectool led battery green ectool led battery red ectool led battery red=1 green=1 #this gives amber ectool led battery off ectool led power white ectool led power off ectool led battery auto ectool led power auto BRANCH=veyron Change-Id: I65a73275741ada5c01e041ae2c11efe3aa2d8c38 (cherry picked from commit ba88b6d6b35959d7ff33cdf075e494406a2f4b5f) Reviewed-on: https://chromium-review.googlesource.com/345693 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* board: it83xx_evb: support PD EVBDino Li2016-05-186-44/+469
| | | | | | | | | | | | | | | | | The change is made to combine EC & PD's board code. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=We can verify PD module on PD EVB and run this board code on EC EVB as well. Change-Id: I92f6ad41643b0536fd78d24026374265cfcf37ea Reviewed-on: https://chromium-review.googlesource.com/342489 Commit-Ready: Dino Li <dino0303@gmail.com> Tested-by: Dino Li <dino0303@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* do not allow console commands with names longer than 14 charactersVadim Bendebury2016-05-181-0/+4
| | | | | | | | | | | | | | | | | The maximum length of console command name is hardcoded to be 14 in a few places in the code. In any case, 14 characters should be enough for any command name, let's add compile time check to ensure that this limit is honored. BRANCH=none BUG=none TEST=tried adding a command with a name longer than 14 characters, got a compile error. Change-Id: I11891fcd04983a5618400a602d4b80a478ecf3a9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345571 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* shorten long console command namesVadim Bendebury2016-05-182-2/+2
| | | | | | | | | | | | | | | | | | | The EC code expects console commands to be no longer than 14 characters, otherwise the alignment of the help command output breaks. This patch replaces flash_spi_sel_lock with flash_spi_lock and fake_disconnect with fakedisconnect to make sure the command names fit. BRANCH=none BUG=none TEST=the 'help' command output is not misaligned any more Change-Id: Ia65f1535850a07adccbef0812c8a0922c0264cea Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345570 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: i2c: Fix spurious NACK after i2cscanMulin Chao2016-05-171-4/+28
| | | | | | | | | | | | | | | | | | | | | | | The NPCX_SMBCTL1_ACK bit (which tells the I2C master to produce a NACK rather than ACK) can be set but not cleared by SW -- it can only be cleared automatically after actually generating a NACK. During i2cscan, we want to NACK the first byte returned, but we won't actually produce a NACK unless the slave ACKs our scanned address. Therefore, we must wait until the slave ACKs its address before setting NPCX_SMBCTL1_ACK -- use the NPCX_SMBCTL1_STASTRE / stall interrupt to do so. BUG=chrome-os-partner:53323 BRANCH=None TEST=Manual on kevin. Verify faulty temperature sensor reads are not seen after `i2cscan` and verify i2c otherwise functions normally. Change-Id: I080d8804adb246129aaebbfbf5ad862e9513da3b Signed-off-by: Shawn Nematbakhsh <shawnn@chromioum.org> Reviewed-on: https://chromium-review.googlesource.com/344818 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* it83xx: Complete EC interrupt liststabilize-8337.BDino Li2016-05-162-16/+67
| | | | | | | | | | | | | | | | | | There are more EC interrupts available. Also, update interrupts that should be reserved. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Use 'task_enable_irq()' to enable new-added interrupts and corresponding bit of interrupt enable register are set properly. Change-Id: If1aecec7e208782b4580e33efb968095f30794fe Reviewed-on: https://chromium-review.googlesource.com/344822 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* elm: set up rotation matrices for EVTKoro Chen2016-05-161-5/+10
| | | | | | | | | | | | | | | Some axes of base and lid accelerometers on EVT needs to be reversed to match the standard reference frame. BUG=chrome-os-partner:52776 BRANCH=none TEST=accelinfo on and check the lidangle reported is correct when I am changing the lid angle Change-Id: Id340d28a740d00c7ff4508f5f804fe90fd8ba18c Signed-off-by: Koro Chen <koro.chen@mediatek.com> Signed-off-by: Ricky Liang <jcliang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343490
* Amenia: internal pullup added to BAT_PRESENT_L pinli feng2016-05-161-1/+1
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=On AMenia, mesaure connector pin 5 3.3v when no battery connected, and 0v when battery is connected. Without pullup, it's floating. Change-Id: Iaf81e00f317209821cec1a83c47a1a75e53feba1 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/342486 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* g: Add GR_KEYMGR_HKEY_FRR to registers.hBill Richardson2016-05-161-4/+4
| | | | | | | | | | | | | | We'll need this shortly. Adding it now to make testing easier. BUG=none BRANCH=none TEST=make buildall Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I6a6636ad330bc17765966cee4962d16850a5d32c Reviewed-on: https://chromium-review.googlesource.com/344663 Reviewed-by: Dominic Rizzo <domrizzo@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* usb_charger: Move part-specific code to usb_switch driverShawn Nematbakhsh2016-05-134-228/+204
| | | | | | | | | | | | | | | | | | | | | | | Previously usb_charger.c supported only pi3usb9281, but now support for additional parts is required. Move pericom-specific code (including the usb_charger tasks that handles various quirks of that part) to the pi3usb9281 usb_switch driver. Going forward, usb_switch drivers must implement usb_charger_set_switches() and must have some method (such as a task or interrupt handler) to update charge_manager with information about attached chargers. BUG=chrome-os-partner:53363 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4df74e043d8cf2e532d48c39c73b7dc2930f7d3b Reviewed-on: https://chromium-review.googlesource.com/344289 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Remove usb_switch_tsu6721 driverShawn Nematbakhsh2016-05-135-386/+0
| | | | | | | | | | | | | | | | This driver is not in use for any recent board and doesn't implement the soon-to-be standard usb_switch interface routine. BUG=chrome-os-partner:53363 BRANCH=None TEST=`make buildall -j` Change-Id: I7469dab42e52d9d02425ad4e7bacb81b2489ffc4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344417 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Ignore unused private board directoriesBill Richardson2016-05-131-5/+13
| | | | | | | | | | | | | | If we're not building a board from a private subdirectory, there's no need to include all the private build.mk files. BUG=none BRANCH=none TEST=make buildall (with private subdirectories) Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I39b61d9b26978702717bf463b47979290cadc8dc Reviewed-on: https://chromium-review.googlesource.com/344662 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* kevin: Add support bmi160 sensorWonjoon Lee2016-05-123-4/+112
| | | | | | | | | | | | BMI168 is twins sensor with BMI160. Adding defines, drv. BUG=chrome-os-partner:52844 TEST="accelread 0" is working on kevin Change-Id: I8335ea4a766ae88e049791b9231ab752486be9d4 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/341650 Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: add more board idWonjoon Lee2016-05-121-11/+39
| | | | | | | | | | BUG=None TEST=cmd 'ver' gets proper version on kevin Change-Id: I2404c57cf2aa939e5255fb70f0e77299ddf0776e Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/343619 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: shi: Allow up to 10ms from CS assertion to first data byteShawn Nematbakhsh2016-05-121-1/+1
| | | | | | | | | | | | | | | | | | | Performance in our baseline 4.4 kernel is much worse than previous test kernels and CS-to-first-byte delay is frequently > 500us. Allow up to 10ms to receive a data byte after CS to reduce the possibility of failed host commands. BUG=chrome-os-partner:53181 TEST=Manual on kevin w/ chromeos-kernel-4_4. Verify that "ERR-GTH" rate is much reduced while spamming "ectool version". BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I92880ccf83a77ee9bdd3d85813e341105857ca4c Reviewed-on: https://chromium-review.googlesource.com/344410 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* kevin: Handle WARM_RESET_REQ inputShawn Nematbakhsh2016-05-122-16/+23
| | | | | | | | | | | | | | | | | Trigger warm reset on WARM_RESET_REQ assertion. BUG=chrome-os-partner:51926, chrome-os-partner:51923 BRANCH=None TEST=Toggle input pins from sysfs (GPIOs 11, 38), verify that ISR is called and proper action is taken. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Change-Id: I38ef06bd99a7885647a27cef1a8371ad96c3f051 Reviewed-on: https://chromium-review.googlesource.com/338924 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cleanup: lars / kunimitsu (and _pd): Remove board-level codeShawn Nematbakhsh2016-05-1230-4044/+1
| | | | | | | | | | | | | | | | Authoritative firmware for these boards can be found on firmware-glados-7820.B branch. BUG=chrome-os-partner:49909 BRANCH=None TEST=`make buildall -j` Change-Id: I78dddef7bc36ecceb5cd9f0eb07052e8e16b6c15 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343201 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash_ec: Add support for it83xx_evbDonald Huang2016-05-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add it83xx_evb support in flash_ec script. BRANCH=none BUG=none TEST=Test OK on ITE8390CX. You can run "~/trunk/src/platform/ec/util/flash_ec --board=it83xx_evb --image=./build/it8380dev/ec.bin" /* ==SNAPSHOT START== */ (cr) (flashec) donald@donald-nb ~/trunk/src/platform/ec $ ~/trunk/src/platform/ec/util/flash_ec --board=it83xx_evb --image=./build/it8380dev/ec.bin INFO: Using ec image : ./build/it8380dev/ec.bin INFO: Flashing chip it83xx. Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB Done. CHIPID 8390, CHIPVER 82, Flash size 256 kB Erasing chip... /100% Writing 262144 bytes at 0x00000000 Done. Verify 262144 bytes at 0x00000000 -100% Verify Done. INFO: Flashing done. /* ==SNAPSHOT END== */ Change-Id: I0a76c0ccfcc3726796372ba3b7915a41c64d5766 Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/343985 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Fixed bug that unexpected value of timer which source clock is 32KMulin Chao2016-05-113-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In rare case, FW read the unexpected counter value of timer which source clock is 32K (Watchdog timer and ITIM16/32 which use 32K source clock). The root cause is the clocks between reading registers and timer's are asynchronous. It has a chance to get invalid counter value when timer is under transaction edge. The solution is using two consecutive equal readings to make sure the counter value is valid. Beside different source clocks of timer, we also found there's chip's bug which causes unexpected value of timer. If an interrupt that occurs very shortly before entering deep idle with instant wakeup, it might result in disruptive execution (such as skipping some instructions or hard fault) after "wfi". The workaround is adding the same bypass for idle in deep idle section. Modified sources: 1. clock.c: Add bypass for instant wakeup from deep sleep. 2. hwtimer.c: Add consecutive reading function for event timer. 3. watchdog.c: Add consecutive reading function for watchdog timer. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I7c9f1fb9618a3c29826d8f4599864a8dac4203bf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/327356 Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: Shut down AP at AP_OVERTEMP assertionShelley Chen2016-05-112-1/+21
| | | | | | | | | | | | | | | | | | coreboot will enable AP_OVERTEMP signal when AP has surpassed a temperature threshold. These changes has the EC do an apshutdown when it detects this signal going high. BUG=chrome-os-partner:51926 BRANCH=None TEST=lower AP_OVERTEMP threshold and make sure that AP shutdown occurs. CQ-DEPEND=CL:342797 Change-Id: Ib9c9d03d2df0d670830c0b4eea3eea3ba5bae0b8 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343060 Reviewed-by: Shawn N <shawnn@chromium.org>
* pwm: Add generic PWM control host commandsShawn Nematbakhsh2016-05-116-3/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | Add generic PWM host commands for setting + getting duty cycle. PWMs can be controlled through index (board-specific meaning) or by type (currently KB backlight and display backlight are supported, more can be added as needed). BUG=chrome-os-partner:52002 BRANCH=None TEST=Manual on chell. `ectool pwmsetduty kb 100` - Verify KB backlight goes to 100% `ectool pwmgetduty kb` - Prints 100 `ectool pwmgetduty 0` - Prints 100 `ectool pwmsetduty 0 0` - Verify KB backlight goes to 0% `ectool pwmgetduty kb` - Prints 0 `ectool pwmgetduty disp` - Error res 3 (unsupported PWM type) `ectool pwmsetduty 1` - Error res 3 (non-existent PWM index) Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I607c92a291e6c2e3af8238eaf22ad2bb81ffc805 Reviewed-on: https://chromium-review.googlesource.com/344012 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* twinkie: disable tracing when injecting packetsVincent Palatin2016-05-111-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tracing runs a higher priority task (SNIFFER) than the packet injection (on CONSOLE task) and both RX and TX are using the same buffer, so when we are sending a packet, we are getting immediately preempted by the tracer and bad stuffs happen. Now, we can manually inject packets and get the text trace of the response. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=with the SOP' experimental patch, plug a full-featured cable into Samus with Twinkie as an interposer, then do the following sequence: Pretend there is a device > tw resistor rd 0 Enable the text tracing > tw trace on Send discover identity to the cable (and get the descriptors) > tw sendprime 1 0x104f ff008001 Sent CC1 104f + 1 = 381 165.939687 SRC/0 [0141]GOODCRC 165.942520 SRC/0 [514f]VDM Vff00:DISCID,ACK:ff008041 1c00050d 00000000 030a0000 11082032 Change-Id: Ie0ad57341c6476e983229b532716986dffefa8a1 Reviewed-on: https://chromium-review.googlesource.com/342512 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org>
* kevin: reduce program sizeWonjoon Lee2016-05-111-2/+1
| | | | | | | | | | | | Reduce size to port motion sensor BUG=chrome-os-partner:52876 TEST=Can get build image with sensor job Change-Id: I7ea0248d0067d25c644eb148c50e36514f9b2598 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/342586 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Don't try to inline pwm_get_keep_awake_mask()Stefan Reinauer2016-05-102-2/+2
| | | | | | | | | | | | | | | | | The function is defined in pwm.c but only used outside of pwm.c, so inlining the function won't work anyways. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none BRANCH=none TEST=compile tested Change-Id: Ibeea86dd504092f962f24ab1ec4df55088a23290 Reviewed-on: https://chromium-review.googlesource.com/343283 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* npcx: shi: Fixes for REBOOT_EC host command handlingShawn Nematbakhsh2016-05-101-11/+11
| | | | | | | | | | | | | | | | | | | | | | | - For REBOOT_EC and several other host commands, send_response may be called multiple times (once for early success notification, one for actual notification, if the handler exits cleanly). Ignore calls after the first. - During reboot / sysjump, we're not equipped to handle host commands, so disable the SHI interface altogether. BUG=chrome-os-partner:52878 TEST=Manual on kevin. Verify "ectool reboot_ec RO" (RO to RO = NOP) succeeds without error messages on EC console. Verify "ectool reboot_ec RW" causes sysjump without AP going down. BRANCH=None Change-Id: Iae83084e4f8d5218600be2a9da7f71dd7872d569 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342622 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver: bmi160: Add support bmi168Wonjoon Lee2016-05-102-1/+2
| | | | | | | | | | | | BMI168 is twins sensor with BMI160. Adding chip ID. BUG=chrome-os-partner:52844 TEST="accelread 0" is working on kevin Change-Id: Iadb5aeb9bc7be7fb2c6bc23e48ea2510b4bf84df Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/341578 Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: Move RAM from data section to codeShawn Nematbakhsh2016-05-103-3/+15
| | | | | | | | | | | | | | | | | | Kevin is code space constrained, so use RAM normally used for data instead for code. BUG=chrome-os-partner:52876 BRANCH=None TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes to add sensor task). Also, verify kevin continues to boot + power sequence. Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343191 Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* kionix: Initialize rv in all casesStefan Reinauer2016-05-091-3/+3
| | | | | | | | | | | | | Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BRANCH=none BUG=none TEST=compile tested for Samus Change-Id: Ib7a0a75a2d63cf8f55d0b59f4a3225da2cb4e70b Reviewed-on: https://chromium-review.googlesource.com/343282 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* keyboard: it83xx: add COL02 inverted featureDino Li2016-05-061-0/+9
| | | | | | | | | | | | | | | | | The other chips support this feature so we implement it too. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=The behavior of kso2 is inverted if define 'CONFIG_KEYBOARD_COL2_INVERTED'. Change-Id: I70d1694ca7d3d10278a484a632e88dc204b71b23 Reviewed-on: https://chromium-review.googlesource.com/342488 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: shi: Improve reliability of SPI host command interfaceMulin Chao2016-05-064-126/+246
| | | | | | | | | | | | | | | | | | | | | - Fix output buffer filling races - Limit response size to 256 bytes to work-around forced low bit on 257th byte - Modify CS glitch to handle CS-to-clock delay - Make CS GPIO interrupt pri 0 to ensure SHI interrupts aren't serviced first TEST=`while true; do ectool version; done > /usr/local/log` on kevin, verify failure occurs about every ~72000 commands (~360000 host commands) BRANCH=None BUG=chrome-os-partner:52372 Change-Id: I5c3d90bf510ed782973b57c2b7497441434c1708 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341492 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Allow TEST_LIST_HOST= to override test targetsBill Richardson2016-05-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When developing or tweaking tests, we almost always need to hack the Makefiles so that "make runtests" doesn't run *EVERY* test each time, but only the one we're playing with. This CL just allows you to override the default test_list_host values from the commandline. Of course, you shouldn't do this except when testing the tests themselves. BUG=none BRANCH=none TEST=manual # build all boards and run all tests make buildall -j14 # run all tests make runtests # run only the two specified tests TEST_LIST_HOST="lightbar hooks" make runtests Change-Id: Icd82c2c781a71a461a7d75bc4bd54944b0eaeed6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343003 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* driver/accelgyro_bmi160.c: fix the error handle in read()james_chao2016-05-061-1/+1
| | | | | | | | | | | | | | | | | The function raw_read_n() return the status, and then check it it should be saved to the variable ret. BUG=none BRANCH=tot TEST=make buildall -j Signed-off-by: james_chao <james_chao@asus.com> Change-Id: I4d2bd200fc49892ae95c63aaeca3af75f7338bec Reviewed-on: https://chromium-review.googlesource.com/342809 Commit-Ready: BoChao Jhan <james_chao@asus.com> Tested-by: BoChao Jhan <james_chao@asus.com> Reviewed-by: BoChao Jhan <james_chao@asus.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* kevin: Add support for SPI_MASTER on kevinWonjoon Lee2016-05-062-3/+19
| | | | | | | | | | | | | Enabling SPI_MASTER on SPIP port in npcx BUG=chrome-os-partner:52844 TEST=spixfer rlen 0 0 1 shows 0xd2 on kevin BRANCH=None Change-Id: I3fe333a7d69fe16c2c630c3c2487320a0d1c020b Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/341577 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: spi: disable all port from board structWonjoon Lee2016-05-061-3/+5
| | | | | | | | | | | | | | We have two port(as is FALSH_, ACCEL_) on SPI defines Let's prevent build error so that We can use particular enable/disable port BUG=None TEST=Buildall is OK Change-Id: Ib6fe14c4edd91947bde0a2da1c889da31db291a4 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/341576 Reviewed-by: Shawn N <shawnn@chromium.org>
* test: host: Fix sbc_charging_v2 test failureShawn Nematbakhsh2016-05-051-1/+1
| | | | | | | | | | | | | | | | | sb_i2c_xfer() assumes 'out' is a valid pointer, which is only true if out_size is non-zero. BUG=chrome-os-partner:51207 BRANCH=glados TEST=`make buildall -j` w/ https://chromium-review.googlesource.com/#/c/342630/ Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia22dcca2b5318b4d69c7afa49f5c8891ab329bd1 Reviewed-on: https://chromium-review.googlesource.com/342635 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com>
* common: Drop unused data structureStefan Reinauer2016-05-051-8/+0
| | | | | | | | | | | | | SHA256_digestinfo[] is never used but declared static and const. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BRANCH=none BUG=none TEST=compile tested Change-Id: I0bcf419bf63fac3e6eadd9efad10fc05b7be9158 Reviewed-on: https://chromium-review.googlesource.com/342484 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Cr50: Lower all runlevel permissions to mediumBill Richardson2016-05-051-0/+8
| | | | | | | | | | | | | | | | Two permission registers are already lowered. This adds the remaining two. BUG=chrome-os-partner:52994 BRANCH=none TEST=make buildall; run on Cr50 USB works, SPI works, sleep and deep sleep work, tpmtest.py works. Change-Id: Ifb27d5be81f10537114f4702addb58c6d7e1630c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342455 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* hooks: Add relative HOOK_INIT priority for peripheralsShawn Nematbakhsh2016-05-0513-16/+21
| | | | | | | | | | | | | | | | | | | Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a higher-than-default relative priority for peripheral initialization outside of board. BUG=None TEST=Verify PWM and ADC are functional on kevin. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb Reviewed-on: https://chromium-review.googlesource.com/342171 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charge_manager: Always set active charge port on first passWonjoon Lee2016-05-051-3/+8
| | | | | | | | | | | | | | | Always call board_set_active_charge_port() on the first pass through charge_manager_refresh(), in case actions must be taken once the CHARGE_PORT_NONE selection is confirmed. BUG=None BRANCH=None TEST=Attach unpowered peripheral without AC and powerbtn, make sure ap boot-up Change-Id: I4bcf1d548d7a8c80f4395fc90ff499fce33c8373 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/341076 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Enable the USB SOF clock auto-calibrationstabilize-8282.BBill Richardson2016-05-044-4/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer clock nominally requires no firmware settings. It is tuned in manufacturing to be centered around 24MHz. However, it will potentially migrate away from 24MHz based upon variations in temperature and voltage. The variation is approximately 0.1-0.5MHz, based upon functional simulations, and backed up with observations in the lab. This CL enables a hardware feature to dynamically tune the timer clock if the device has an active USB port, by monitoring the SOF (start of frame) USB packets that are sent by the USB host every milllsecond with 500ppm accuracy. BUG=chrome-os-partner:50800 BRANCH=none TEST=make buildall; run on Cr50 hardware Verified that deep sleep, USB suspend/resume, etc continue to work with this enabled. Not too surprising, since I've never encountered a problem without it. In addition, I monitored XO_CLK_TIMER_CURRENT to see that the timer adjustments are being made while connecting and disconnecting from USB, entering andleaving sleep and deep sleep, etc. They are. Change-Id: I328b6416bc40ef8718815c5e09cf91ec1c6646f0 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342145 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* gru: Initial mainboard commitShawn Nematbakhsh2016-05-048-10/+52
| | | | | | | | | | | | | | | | Clone of kevin w/ minor GPIO / LED changes. BUG=chrome-os-partner:52736 BRANCH=None TEST=Verify image boots + sequences on kevin p1. Change-Id: I7d3f3ce97a8b080516b635a3d2b7bc3c6515c6d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340542 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* rk3399: Set power state based on input signalsShawn Nematbakhsh2016-05-044-19/+73
| | | | | | | | | | | | | | | | | | | | | Use input signals to verify power state and determine power state after sysjump. BUG=chrome-os-partner:52878 BRANCH=None TEST=Manual on kevin. - Verify AP powers up on 'powerbtn'. - AP shuts down on 'apshutdown'. - AP re-powers / resets on 'powerbtn' + 'apreset'. - AP doesn't shutdown on 'sysjump rw' while in S0. Change-Id: Id24feb0f8490aa7cb73c46178085ff2e46f8d0a6 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341704 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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