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* nautilus: remove base-related code.Jongpil Jung2017-11-222-173/+0
| | | | | | | | | | | | BUG=b:69389497 BRANCH=none TEST=build/flash on nautilus. Check boot. Change-Id: I02677109a99f57e48a62355e82ca31c8445b6849 Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/781261 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nautilus: control power ledJongpil Jung2017-11-222-112/+74
| | | | | | | | | | | | | | | | | Control power LED. BUG=b:69396982 BRANCH=none TEST=build/flash nautilus rev1, power on and boot ok. check LED as power state. check LED with ectool. Change-Id: I4961d1683f881697f508292bd116cb7df69caac3 Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/773521 Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* poppy/soraka: Add GPIO_SEL_1P8V flag for 1.8V pinsFurquan Shaikh2017-11-221-3/+3
| | | | | | | | | | | | | | | | | | | Jerry pointed out that certain GPIOs which are 1.8V are set as 3.3V in gpio.inc. Fix these gpios by add GPIO_SEL_1P8V flag to the gpio description: GPIOD1/I2C3_SCL0 GPIOD0/I2C3_SDA0 GPIO36 ACCEL_GYRO_INT_L BUG=b:69481600 BRANCH=None TEST=make -j BOARD=soraka. Verified that screen rotation works in tablet mode. Change-Id: Ifbc474846aff0760f0b183a9cfeef2790738ca79 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/780142 Reviewed-by: Jerry Parson <jwp@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* gsctool: clean up error processingVadim Bendebury2017-11-211-14/+31
| | | | | | | | | | | | | | | | | | The gsctool utility is inconsistent in using stdio channels when reporting errors. All error messages should go into stderr. Also, to avoid confusion, this patch makes options -s and -t mutually exclusive. BRANCH=none BUG=b:68213540 TEST=verified that passing both -t and -s command line options causes an error. Change-Id: Ieb50cf08314aa37594964ef4bbfa4a850741da2f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/784353 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nautilus: enable touchpad,backlight and disable base.Jongpil Jung2017-11-212-21/+4
| | | | | | | | | | | | | | | | | | clean up base enable/disable for nautilus. enable touchpad and backlight. BUG=b:69389497 BRANCH=none TEST=build/flash nautilus rev1, power on and boot ok. check lcd backlight. check touchpad with evtest. Change-Id: I6e2ddc61737254f088de0867fbb02b09e1099718 Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/773721 Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* nautilus: remove als.Jongpil Jung2017-11-214-22/+0
| | | | | | | | | | | | | | | | nautilus doesn't have als. So, we need to remove als code in ec firmware. BUG=b:69389497 BRANCH=none TEST=build/flash nautilus rev1, power on and boot ok. check ec console log. There is no als initialization. Change-Id: I99465fb59090c7d370cb4a28f3500159a6fcb77e Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/773764 Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Reviewed-by: Philip Chen <philipchen@chromium.org>
* g: speed up prime generation by ~40% (1024 bit).Marius Schilder2017-11-211-4/+1
| | | | | | | | | | | | | | | | | We were using bn_modexp() to perform a simple modular square. A bn_modexp_word() does this faster. BRANCH=none BUG=b:68167013 TEST=generate 128 primes from prng seed and verify they're same as before; tcg_test passes Change-Id: I411a7d3fe2d68f93dc40bf74b941a637f9aa20ed Reviewed-on: https://chromium-review.googlesource.com/778057 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-2118-93/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* coral: Fix corner case for battery_present_timer_started flagScott Collyer2017-11-211-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the SMP and Celxpert batteries for Robo systems, following battery cutoff, there is a race condition resulting from a failed sb_read operation when the battery status is read. If this read fails, then the flag battery_report_present is reset to 0. Since this flag gets set in a hook task deferred callback, if the sb_read fails after battery_report_present is set, but before batt_pres is set to BP_YES, then the deferred call would not be restarted. This results in the battery_is_present call returning BP_NO indefinitely. To fix this condition, this CL ensures that battery_report_present_timer_started is cleared for any case that could result in BP_NO. This addressed both this corner case and makes redundant a previous change that was put to handle the case where the battery is disconnected and reconnected while the system remains powered. The CL also adjusts the timer to 0.5 sec so that in the event it has to be called twice, it doesn't exceed the previous 1 second timer and delay boot time even longer. BUG=b:69151530 BRANCH=coral TEST=With the DUT powered, removed and reconnected the battery. Ensured that the battery again reports present. Bitland also verified that with this CL they can no longer reproduce the issue. For the corner case, had additional debug console prints. (Note this is with 1 second timer) The deferred call is started. [0.156135 battery timer hook call] This shows where the sb_read error happens in batt_init() [1.085627 Battery FET: reg 0x0018 mask 0x0010 disc 0x0000] [1.092251 battery: pres 0, prev_pres 0, cutoff 0, init 1, rep 0] [1.160969 battery will now report present] This shows where the batt_report present gets cleared [1.184993 ******** batt_report_present 1 -> 0 *****] [1.185840 Battery read status failed] [1.186540 report = 0, batt_init 1->0: stat = 0x200c6bea 1 get 1] [1.187544 battery: pres 0, prev_pres 0, cutoff 0, init 0, rep 0] [1.193796 Battery read status failed] [1.194886 battery: pres 0, prev_pres 0, cutoff 0, init 0, rep 0] batt_init() no longer returns 0, so deferred call is restarted [1.290559 Battery FET: reg 0x0018 mask 0x0010 disc 0x0000] [1.292942 battery timer hook call] battery reports present now [2.293436 battery will now report present] Change-Id: I89d69cf133365affc4cc538328daeaaf9ac05ed9 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/773623 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> (cherry picked from commit 535080115d20dc223dab6288c5fea02da67c8e9c) Reviewed-on: https://chromium-review.googlesource.com/782599 Commit-Ready: Scott Collyer <scollyer@chromium.org>
* Nautilus: clean up thermal sensors.Jongpil Jung2017-11-212-6/+1
| | | | | | | | | | | | | | | | | Nautilus doesn't have systherm0 and systherm3. So, need to remove device index. BUG=b:69389497 BRANCH=none TEST=build/flash nautilus rev1, power on and boot ok. check ectool tempsinfo all and ectool temps all. Change-Id: I1ebebf2fb19ab91f63cf7e29605b8e6fd0f86178 Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/773940 Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Reviewed-by: Philip Chen <philipchen@chromium.org>
* nautilus: clean up code.Jongpil Jung2017-11-202-31/+5
| | | | | | | | | | | | | | | | | | | | remove base related code. remove anx74xx related code. Update GPIO PIN - unused PP3300_DX_SENSOR - unused EC_HAVEN_RESET_ODL - correct PP1800_DX_SENSOR and LTE. BUG=b:69389497 BRANCH=none TEST=build/flash nautilus rev1, power on and boot ok. Change-Id: I27fe5010bc082d4db941955d7ff49f5ae336901a Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/773320 Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com> Reviewed-by: Philip Chen <philipchen@chromium.org>
* usb_i2c: Remove usb_i2c_board_enable/disableNicolas Boichat2017-11-206-25/+7
| | | | | | | | | | | | | | | | These functions are not used by usb_i2c.c on chip/stm32, let's move them to board/cr50 which is the only place where they are used. BRANCH=none BUG=None TEST=make buildall -j Change-Id: I8c1b292838b8dbee9a9001add9332e0add80c342 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/778749 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* util: Remove duplicate 'const' in export_taskinfo.cMartin Roth2017-11-201-1/+1
| | | | | | | | | | | | | | | | | | This is causing an error in the latest coreboot toolchain: util/export_taskinfo.c:33:30: error: duplicate 'const' declaration specifier [-Werror=duplicate-decl-specifier] BUG=None TEST=Build now passes with latest coreboot toolchain and cros Ztoolchain BRANCH=None Change-Id: I069d08128e264310d25a09ada2276f92796294b7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/679939 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* poppy/soraka: Fix battery_is_present detectionFurquan Shaikh2017-11-201-18/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was recently identified that when we do a software based battery cutoff and leave the system in cutoff state for > 25-30 seconds, then both FG and battery enter shutdown/ship mode. In order to get the battery out of this state, charger needs to provide VBAT > Vstartup. However, with the current implementation of battery_is_present, if EC is unable to talk to the battery i.e. i2c commands to read battery status fails, then battery_is_present returns BP_NO indicating that the battery is not present. This results in charger state machine setting 0V and 0A to the battery, thus causing the BGATE to be switched off. In order to wake the battery from such condition, it is necessary to provide pre-charge current and minimum voltage to ensure that BGATE is switched on and VBAT > Vstartup is provided. This change updates the battery_is_present algorithm to: 1. Check if battery is physically present. If not, return BP_NO. 2. If battery is present now and was present before when we checked, then return BP_YES. 3. If battery just changed status to BP_YES, then check its disconnect status. If EC is unable to read disconnect status, then return BP_NOT_SURE. This allows the charger state machine to provide precharge current and minimum voltage. 4. If EC is able to read disconnect status, try reviving it if necessary. 5. Return BP_NO if battery is still disconnected or is cutoff or not initialized. 6. Else return BP_YES. BUG=b:69329874 BRANCH=None TEST=Factory verified following: 1. Recovery from software based cutoff : Pass 10/10 2. Recovery from hardware based cutoff : Pass 10/10 3. Recovery from hibernate : Pass 10/10 4. Recovery from critical battery condition : Pass 10/10 5. Boot-up in case of no battery : Pass 10/10 Change-Id: I248705f87469a8d6604da1b1919492766499dd73 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/776024 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* touchpad_elan: Rename task/interrupts functionsNicolas Boichat2017-11-207-25/+21
| | | | | | | | | | | | | | | | | | Change the names to generic touchpad_* functions, instead of vendor-specific names. Makes it a little easier to add drivers for other touchpads. Also fix console_channel.inc to add the channel whenever any touchpad is used. BRANCH=none BUG=b:68934906 TEST=make buildall -j Change-Id: I6d268db5ebd53db272fb2ee7bbf06bbe80845734 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/778750 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* meowth: zoombini: Removed 5V enable pins.Rachel Nancollas2017-11-171-3/+0
| | | | | | | | | | | | | | Not needed since we're using the SN5S330. BUG=b:69140019 BRANCH=none TEST=make BOARD=meowth and BOARD=zoombini runs with no errors Change-Id: Id8fa17e1e20ac805405fc6e48e481ceade1a1981 Signed-off-by: Rachel Nancollas <rachelsn@google.com> Reviewed-on: https://chromium-review.googlesource.com/777823 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-1745-260/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* motion_sense: Put set_range in common codeGwendal Grignou2017-11-1714-98/+51
| | | | | | | | | | | | | | | | At the end of the sensor initialization, all _init sensor routines set the range to the default value from board.c file. Put all the code in a single place, move it from sensor_common.c to motion_sense.c. BUG=none BRANCH=none TEST=compile Change-Id: If89cf27c6438e0f215c193d68a480e027110174c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767610 Reviewed-by: Shawn N <shawnn@chromium.org>
* gru: Make more code space by disabling configsFurquan Shaikh2017-11-171-0/+2
| | | | | | | | | | | | | | Disable CMD_IDLE_STATS and USB_PD_LOGGING for gru in order to make more code space for upcoming 64-bit host event support BUG=b:69329196 BRANCH=None TEST=make -j BOARD=gru Change-Id: I5fca66d13224e077b157b0768ba0264948ab6a0d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/775876 Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: Enable MKBP support for events.Aseda Aboagye2017-11-171-0/+7
| | | | | | | | | | | | | | | Button and switch events will be reported using MKBP. BUG=b:6914039 BRANCH=None TEST=make -j buildall Change-Id: Ieff75fa563ed91c2d33b18caf8942038ab7100bd Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/775477 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: Add temp sensor ADC channels.Aseda Aboagye2017-11-173-5/+19
| | | | | | | | | | | | | | | | Additionally, meowth has GPIOs for sleep signals, therefore remove the "ifndef" for eSPI VW. BUG=b:69138817 BRANCH=None TEST=make -j buildall Change-Id: Ib78a8c5ff8037022adcaf690157836fd2db1ef0d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/775080 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add software CTZ implementation when needeedGwendal Grignou2017-11-165-2/+35
| | | | | | | | | | | | | | | | | CTZ - Count Trailing Zero - is not implemented in hardware on cortex0 or nds32. Used in ST sensor drivers. BUG=none BRANCH=none TEST=compile Change-Id: I2d62fd60f05169189b24ba2a3308bec69ed9de9c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767609 Commit-Ready: Ely Vazquez <nadia198877@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* servo: add usb_console to chrootNick Sanders2017-11-162-3/+29
| | | | | | | | | | | | | | add usb_console, console.py to chroot install. This tool allows directly accessing the usb console of servo v4, servo micro, cr50, etc. BUG=b:69016431 BRANCH=None TEST=usb_console -d 18d1:501b Change-Id: If9d5d49cf31d785ea9a7cec0a4eeeb34abae9cd1 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/773400
* servo_v4: disable USB3 interfaceNick Sanders2017-11-161-2/+5
| | | | | | | | | | | | | | | | This change switches the SS lines off in the main USB mux. There has been some general flakyness regarding USB3 peripherals and this change might address it. BUG=chromium:718075 BRANCH=None TEST=lsusb -t indicates 5000M before, 480M after. Change-Id: Id201fb20dc6489c4a071cb1c9c0624d7aa54652d Reviewed-on: https://chromium-review.googlesource.com/509130 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: meowth: Enable Vboot hash.Aseda Aboagye2017-11-161-0/+2
| | | | | | | | | | | | | | | | The hash calculation is needed for EC software sync. BUG=None BRANCH=None TEST=`make -j buildall` TEST=Flash zoombini, verify that hash is being calculated. Change-Id: Iddc65d5c0b04fa403b2fd5ace0096b029d5a6062 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772913 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: Toggle PP1800_U on startup/shutdown.Aseda Aboagye2017-11-161-2/+6
| | | | | | | | | | | | | | | | The enable for the PP1800_U rail needs to follow our transitions from S5->S3 and from S3->S5. BUG=b:69137449 BRANCH=None TEST=make -j buildall Change-Id: I2466f560b096eb0ad48d9c355de56d7aa775d9cc Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772912 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: Add battery pack information.Aseda Aboagye2017-11-161-0/+27
| | | | | | | | | | | | | BUG=b:69138843 BRANCH=None TEST=make -j buildall. Change-Id: Ia3aa76e03c7551dc34041631e8f8d1b16c1771e3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772911 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: Add support for meowth.Aseda Aboagye2017-11-161-1/+2
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=None Change-Id: Ib0c6b029c608ac361ed661249138589c99ea68b6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772910 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* jerry: Use HOSTCMD_ALIGNED instead of GPIO_SHORTNAMESFurquan Shaikh2017-11-161-1/+1
| | | | | | | | | | | | | | | This is required to allow bumping up of host events to 64-bit by making space in the rodata. CL 770923 had initially used GPIO_SHORTNAMES, but HOSTCMD_ALIGNED seems to be a better option. BUG=b:69329196 BRANCH=None TEST=make -j buildall Change-Id: I63699f9cec244925c031d81f50889851c6da8b5c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771931 Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: zoombini: Annotate ifdefs.Aseda Aboagye2017-11-165-27/+23
| | | | | | | | | | | | | | | | This commit just adds comments to the ifdefs introduced for BOARD_ZOOMBINI. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I036d18bc5b1fb4ebbf0943e630e4931c03b60aa5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772909 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* tpm: do not prevent reading registers during pending resetVadim Bendebury2017-11-161-3/+0
| | | | | | | | | | | | | | | The host should be able to retrieve proper TPM status and ID registers while TPM reset is pending. BRANCH=cr50 BUG=b:68012381 TEST=after appropriate fixes in coreboot the firmware_Cr50ClearTPMOwner autotest does not fail any more Change-Id: I245656ccb1c05e46715deb18bd5f8985c4197c52 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/775281 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* kevin: Claim some more space by disabling some configsFurquan Shaikh2017-11-161-2/+3
| | | | | | | | | | | | | | Disable ACCELSPOOF and FLASHINFO to save some space. This is required to support 64-bit host events. BUG=b:69329196 BRANCH=None TEST=make -j buildall Change-Id: I364adb1e224c2084398b4ee5bb9fd24a1c542e0e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771997 Reviewed-by: Shawn N <shawnn@chromium.org>
* nautilus: Replace anx74xx with another ps8xxxPhilip Chen2017-11-154-78/+14
| | | | | | | | | | | | | | | | | | | On Nautilus, we use two ps8751b TCPC chips. According to the latest schematic (link is in the bug), we'll place two TCPC chips separately on different I2C ports. BUG=b:69017605 BRANCH=none TEST=build/flash nautilus rev0, and confirm PD charging from one USB-C port works. Change-Id: Iab7402023f148d478cba249aaf83a23675a7137b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/758336 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Meowth: Added initial board file.Rachel Nancollas2017-11-157-13/+216
| | | | | | | | | | | | | | | | | | | Created Meowth symbolic link to Zoombini. Modified Zoombini gpio.inc and board, etc. files to compile a Meowth EC image with the correct gpios. BUG=b:69133424 BRANCH=none TEST=make BOARD=meowth and BOARD=zoombini runs with no errors Change-Id: Ib34d956efa89ae125de1ce7f8799162c74df0122 Signed-off-by: Rachel Nancollas <rachelsn@google.com> Reviewed-on: https://chromium-review.googlesource.com/762039 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32f0: i2c: Fix dropped Rx byte in TCPCI slave modeShawn Nematbakhsh2017-11-151-5/+5
| | | | | | | | | | | | | | | | | | | If the i2c master sends a stop condition before we've buffered the last Rx byte (eg. due to higher than normal i2c interrupt latency) then we don't want to drop the last byte on the floor, it's still meaningful. BUG=b:65711378 BRANCH=glados TEST=Spam TCPC_REG_ROLE_CTRL commands from caroline to caroline_pd, verify no errors are observed on either side for 12,000,000 transactions. Change-Id: I0c4a81d97315cff553a5448c0940746e1ef0ed2c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771936 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy: Lower sensor max ODRGwendal Grignou2017-11-152-2/+11
| | | | | | | | | | | | | | | | EC seems to miss sample while providing sensor data at 200Hz. Limit sensors ODR to 100Hz. BUG=b:67112751 BRANCH=none TEST=compile, tbd Change-Id: Ic324c3d989854ae8b7f6b27bf6338266ce01ceda Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753434 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: prepare to release 0.0.26Vadim Bendebury2017-11-152-2/+2
| | | | | | | | | | | | | | The new release will include fixes for SPI problems discovered when debugging Fizz. BRANCH=cr50 BUG=none TEST=none Change-Id: I4ac2ab762ec86957a7555b0aaa41235f44a54d47 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/772738 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* nautilus: Update battery profilePhilip Chen2017-11-151-10/+15
| | | | | | | | | | | | | | | | | Update battery.c according to the battery datasheet (The link is in the bug). BUG=b:69016914 BRANCH=none TEST=boot Nautilus with battery, and confirm EC doesn't complain about critical battery state anymore. Change-Id: I024f61e4a4119b7a3d5c0f3b1de56c591af2ae5d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/757892 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* system: Add wait-ext option to ec reboot commandScott Collyer2017-11-153-16/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | EC_IN_RW signal is used to determine if the switch to dev mode can be safely made. However, EC_IN_RW needs the EC_RST_L line driven low in order to be reset. In faft tests that utilize crosEcSoftrecPower method, EC_RST_L is not being driven by servo to fix other test failures related to keeping EC and AC reboots in sync. This CL adds a new argument 'wait-ext' to the EC reboot command. When this option is used, instead of the EC generating a reset via it's system watchdog, it will wait 10 seconds for EC_RST_L to be driven. BUG=b:64603944 BRANCH=coral CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode" mutliple times and verified that it passes. Previoulsy, this test always fails when the EC is in RW before it starts. Also tested platform_ServoPowerStateController_USBPluggedin and verified it passed. Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/737524 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Change the way host_set_single_event is usedFurquan Shaikh2017-11-151-2/+5
| | | | | | | | | | | | | | | | | In order to avoid runtime 64-bit left shift, check for extpower and add two separate calls to host_set_single_event rather than calculating the parameter at runtime. This avoids the requirement of runtime logical shift for 64-bit. BUG=b:69329196 BRANCH=None TEST=make -j BOARD=samus Change-Id: I64cacf6253878ed7d69f6b17baeb6c27c470378a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771854 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_updater: allow differing console enpointsNick Sanders2017-11-153-4/+8
| | | | | | | | | | | | | | | servo_micro has the console on intf 3, while servo_v4 has it's console on intf 0. Abstract this into the config file rather than hardcoding. BUG=b:37513705 BRANCH=None TEST=update servo_micro Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I0090a0d081e001e62ffa7235eebbd6131ea00dcf Reviewed-on: https://chromium-review.googlesource.com/769794 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "poppy/nautilus: Move pmic vr decay enable/disable to suspend/resume ↵Furquan Shaikh2017-11-152-4/+16
| | | | | | | | | | | | | | | | | | | | hooks" This reverts commit 1f767e3e91be388dee689ac85408dfb5e3414581. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall. Verified by adding prints that VR decay enable happens before SLP_S0# is asserted. Change-Id: I0353f70c65ebe673b0e1b5ddbae2bb04368308cc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771055 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Revert "power: Get rid of power_board_handle_host_sleep_event"Furquan Shaikh2017-11-152-1/+19
| | | | | | | | | | | | | | | | | This reverts commit 352276235ca18404a42ca01b75de3fdc7951e271. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall Change-Id: I6885e7447277d853a2414be299dfea25f5547df4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771054 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* jerry: Enable CONFIG_COMMON_GPIO_SHORTNAMESFurquan Shaikh2017-11-151-0/+2
| | | | | | | | | | | | | Turn on CONFIG_COMMON_GPIO_SHORTNAMES to save some space in rodata. BUG=b:69329196 BRANCH=None TEST=make -j BOARD=jerry Change-Id: Ib1e4cb13c013cce7b0d6422b842ca47c0f4ff62c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770923 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32: jtag: Enable clock to debug module on stm32f0xMoritz Fischer2017-11-152-0/+4
| | | | | | | | | | | | | | | Enables the clock to the debug module so that when connecting via SWD debugger the watchdog and timers are stopped. BRANCH=master TEST=Build on stm32f0x board and connect via SWD, observe no watchdog reset. Change-Id: Ic40b16c09acc5920da2c1a39e9391a6b21849d2c Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: https://chromium-review.googlesource.com/765290 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: add espi moduleDino Li2017-11-1411-2/+514
| | | | | | | | | | | | | | | | | | Add espi control module for it83xx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell. 2. console command "kbpress 1 4" to test keyboard data. (board code for espi module test on CL:392587) Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d Reviewed-on: https://chromium-review.googlesource.com/394471 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec-devutils: install servo tools to chrootNick Sanders2017-11-141-0/+42
| | | | | | | | | | | | | | | | | | | This adds "servo_updater", "powerlog", "ecusb" library into the chroot's python install, as well as configs for servo_v4 and servo_micro. This allows easier access to these tools. servo_updater and powerlog are installed in the default path. /usr/share/servo_updater/configs contains the servo config files. BUG=b:69016431 BRANCH=None TEST=sudo servo_updater -b /../servo_v4.json -f servo_v4_9040.0.0.bin powerlog -b marlin.board -c marlin_common.scenario Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I0b3f1b16fcd422297af88c236a2a4ddb2cc25819 Reviewed-on: https://chromium-review.googlesource.com/767547 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* PS8751 and PS8805 does not generate BIST Carrier Mode 2Sam Hurst2017-11-142-1/+47
| | | | | | | | | | | | | | | | | On Nasher, sending TCPC_TX_BIST_MODE_2 to register 0x50 on the PS8751 TCPC does not generate BIST Carrier Mode 2. BUG=b:68337231 BRANCH=None TEST=`make -j buildall` Generated an eye diagram for Nasher on the GRL USB-PD test station Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: Ia6e5df54a183c989a68d12be3a46896e3daea738 Reviewed-on: https://chromium-review.googlesource.com/741090 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* grunt: Initial GPIO setup for gruntEdward Hill2017-11-146-959/+170
| | | | | | | | | | | | | | | | Configure GPIOs to match grunt proto v1.1 schematic. Change EC chip to npcx7m6f. Minimal board.c/h, just enough to build. BUG=b:64935726 BRANCH=none TEST=make BOARD=grunt Change-Id: I1a1f581c7ee7b80808c0dde179bc3ee0d69f960e Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/754302 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* scarlet: Remove barometer bmp280Philip Chen2017-11-143-46/+0
| | | | | | | | | | | | | BUG=b:69011927 BRANCH=none TEST=manually boot Dru and verify no complaint about baro init failure Change-Id: I35fd5636ac833bad81ce91969cdf94a79833486f Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/757938 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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