| Commit message (Collapse) | Author | Age | Files | Lines |
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BUG=b:72335612
BRANCH=none
TEST=make BOARD=nami
Change-Id: Ifcf401b881a40490ead8186be77cc7a097550291
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/941601
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
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Set GscFullConsole to Always in RMA open. We need this to be accessible
after rma open, so that we can use RMA open as a ccd open testlab
replacement.
Commands like rddkeepalive and bitbang are needed for testlab use, so
they should be accessible after open.
BUG=b:74019846
BRANCH=cr50, cr50-mp
TEST=build, do rma open, verify commands are not locked out, and do rma
disable
Change-Id: Iaeb89cea94d478dc0eb25c92bb09d488d14cad41
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/942309
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Move the RW signature verification in a dedicated task rather than on
the synchronous startup path, in order to be compatible with our flashrom
update mechanisms (but at the expense of additional latency in RO).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=flashrom -p ec:type=fp -w ec.bin
Change-Id: If9ae66bfde0c5922db86dc9acfd4ee766089fa1d
Reviewed-on: https://chromium-review.googlesource.com/936542
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Add the strings to display the recently added EC feature flags.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=on ZerbleBarn, run 'ectool inventory'
Change-Id: I213d34515800532fc3b2378b8619e2b90ce5fd28
Reviewed-on: https://chromium-review.googlesource.com/937263
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Also define the EC_FEATURE_RWSIG feature bit if the RO firmware contains
the RWSIG task but not the RW.
Given the RWSIG verification task is not terribly useful in RW
(where it is never executed), it can be skipped there but the host
program trying to detect RWSIG usage (e.g. flashrom) still wants to be
able to detect it.
In order to be able to do so, add the HAS_TASK_xXx_RO and
HAS_TASK_xXx_RW flags which define the tasks defined in the other
partition (at compilation-time you might still run a frankeinstein combo).
Fix ectool 'inventory' to avoid segfaulting on missing feature string
definition.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=on ZerbleBarn, run 'ectool inventory', also uses flashrom to
re-flash the RW partition.
Change-Id: I224a6cc4aef956204792a2cc04ad12aaed5abf47
Reviewed-on: https://chromium-review.googlesource.com/937262
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Using only a Carriage Return as done to have a nice spinner is not
terribly compatible with logging the output of the tool to a file or
piping it to anything.
Add another option to have a simple progress-bar instead.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=on Meowth, run flash_fp_mcu from the factory UI.
Change-Id: I0c37689d2ed1e45dff54b7f1eb2be515ea37e004
Reviewed-on: https://chromium-review.googlesource.com/936766
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
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The shmem console command was looping with the wrong iterators,
doing an infinite loop when there was more than one allocated or
free block.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=build software with CONFIG_MALLOC and CONFIG_CMD_SHMEM, then run
'shmem' on the console at different time without hitting watchdog reset.
Change-Id: I93a9cff3811669ab895fa8753d1571e90aeb4f33
Reviewed-on: https://chromium-review.googlesource.com/943070
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Because of instability(corner case) occured in couple of boards,
its better to enable VR_decay at SLP_S0 and disable it in S0
system state.
BUG=b:70881268
BRANCH=None
This reverts commit fac65e668c2b02d0af419c6a48f33a44f8e4ba11.
Change-Id: I7dff9983befc68c33052fffcb058ac01579c5a47
Reviewed-on: https://chromium-review.googlesource.com/939225
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Currently, if there is a fan which isn't in RPM mode, the rest of the
fans are not controlled even if they're in RPM mode. This patch gives
a chance to all the fans.
BUG=b:35543471
BRANCH=none
TEST=none
Change-Id: I6f930bad313bc2a31497f46647ab2b08e328dfff
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/940813
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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In the case of almost full battery, without this
change the battery will keep charging even
if charging is not allowed when external power
is kept attached.
BUG=b:71364739
BRANCH=master
TEST=On glkrvp, let battery charge to 100% and verify after that
it starts discharging to 95% and then starts charging back.
Change-Id: I71935f795909d11ad93fd56caaa3683b54104c65
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/927798
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This CL adds the driver support for the WoV module which inludes the
following files:
- wov.c
- wov_chip.h
- apm.c
- apm_chip.h
It also supports the console commad "wov" which can test different
configuration and audio quality by entering different parameters.
The detail description of WoV console command is listed below:
------------------------------------------------------------------------
[Note]: Before changing any of settings, please make sure the operation
mode is on the "OFF" state. (ie. run the command wov cfgmod off
first) .
> wov init
Initialize WoV interface, including pin mux and interrupt
registration etc.
> wov mute <enable / disable >
mute enable / disable.
> wov cfgsrc <mono | stereo | left | right>
set audio source, ex: wov cfgsrc left, means audio source from left
MIC.
> wov cfgbis <16|18|20|24>
set audio resolution, ex: wov cfgbit 16 means audio resolution are
16bits.
> wov cfgsfs <8000|12000|16000|24000|32000|48000>
set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio
sampling rate are 48Khz.
> wov cfgbck <32fs|48fs|64fs|128fs|256fs>
set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs
means audio sampling rate are 1536Khz (32*48000).
> wov cfgfmt <i2s|right|left|pcma|pcmb|tdm>
set I2S but format, ex: wov cfgfmt right means audio I2S format are
Right-Justify.
> wov cfgmod <off|vad|ram|i2s|rami2s>
set audio operation mode ,ex: wov cfgmod i2s means audio output via
I2S bus.
> wov cfgtdm <0~496 0~496 0~3>
set TDM time slot, the first values is left channel delay counter,
the second is right channel, and the 3rd is startup counting condition.
(chosen LRCK raising or falling edge) .
[Note: this command is just working on cfgmod equal to tdm]
> wov cfgget
retrieve above settings.
> wov vadsens
(currently not support, reserve for next version)
> wov gain (0~31)
set audio data gain value, ex: wov gain 10 means setting audio digital
gain are 10dB.
> wov cfgdck <1.0 | 2.4 | 3.0 >
set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock
are 2.4Mhz.
-----------------------------------------------------------------------
This CL also adds the chip ID (0x24) for npcx7m7w. So the console
command "version" can show the chip is npcx7m7w.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function
with console commands described above.
Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: Simon Liang <CMLiang@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/897314
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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BUG=b:65446459
BRANCH=none
TEST=Charge Scarlet rev3 with SDP and DCP.
Change-Id: I84fb64953c380b96ec852dca2c981331801e4416
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905399
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BRANCH=none
BUG=b:73811887
TEST=build yorp and all other boards
Change-Id: I2c29ba86f29a3d25128c00c1b55e90f6843bcdd5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/935367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BRANCH=none
BUG=none
TEST=make buildall
Change-Id: I3c07a87e0a41ad3ec51f78e30e14ac7d45d3e531
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/935366
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Things that need it will request it to turn on.
The only reason accel is on by default is because we need to be able to
poll it from time to time.
TEST=Motion related things still work
BUG=While looking at b/67743747
BRANCH=master
Change-Id: I08ea487058fb93ce6ff5fcc9054243d83e189e21
Suggested-by: Gwendal Grignou <gwendal@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/887947
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
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The fuel gauge (max17055) on Scarlet is powered by VBAT.
To use max17055 to detect batttery presence, we want to keep
it alive even if battery is disconnected.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet rev3 w/o battery on AC and don't see VBAT drops
Change-Id: Ice27384ded257be75ee29a28c0ada9f73b173f6c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/930572
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
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BRANCH=none
BUG=b:72961003,b:72956593
TEST=verified with grunt that parade TCPC will no longer shut down when
PPC sources Vconn
Change-Id: I6c1cee4dd8a40a992813841ec227a6af04de5313
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/935301
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1. Add reading function for remote2 temperature (Fintek, F75303)
2. Modify the temp_sensors to read sensor remote1 and remote2 for nami.
BUG=b:72974136
BRANCH=none
TEST=Verify Nami can get thermal remote 2 data by command "ectool temps
all"
Change-Id: I5e4a58f20089ed5690e2a084e93e7021e80afcdc
Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/910270
Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
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This will make sure that Cr50 images built from dev branch can take
over images built from either MP or pre-MP branches.
BRANCH=none
BUG=none
TEST=verified that it is possible to overwrite pre-MP Cr50 version of
0.2.2.
Change-Id: I929cb2be857ea90c544f83160d6820c73e23c69d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/938946
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Fan enable state is controlled in common/fan.c. This patch prevents
npcx fan driver from enabling it.
BUG=b:73127788
BRANCH=none
TEST=Verify no 'Fan 0 stalled' is printed in S3 and S5. Verify the
fan spins in S0.
Change-Id: I549253a64c91d8a23bb793c3506b5daf1f7642be
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/937941
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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When running w/ blocking usb console output
(CONFIG_USB_CONSOLE_CRC) and the host is not polling the console,
upgrade will fail.
Signed-off-by: mschilder@google.com
TEST=buildall -j8; gsctool update succeeds on mn50
BRANCH=none
BUG=none
Change-Id: I5c09694c146ba0fbf7562b86ab0fad0d578bc5ff
Reviewed-on: https://chromium-review.googlesource.com/938392
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This field allows multiple product families to be independently versioned
and released, without risk of having one product family's image flashed
to another product family's chip.
BUG=b:73728151
BRANCH=none
TEST=make buildall -J
Change-Id: I53f5e5b1e9ac7ea19997f8d1228a568e66c43d39
Reviewed-on: https://chromium-review.googlesource.com/935759
Commit-Ready: Jeff Andersen <jeffandersen@google.com>
Tested-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Nadim Taha <ntaha@google.com>
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Thermal protection is by default enabled on rt946x, but we
disable it in rt946x_init() and only rely on the fuel gauge
to do thermal measurement.
Thus when we init rt946x too late, rt946x could trigger thermal
protection during boot and brown out the fuel gauge temporarily.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet rev3 w/o battery on AC and don't see VBAT drops
Change-Id: I54eadd80bd4fd8a6e47309b13c4d46ee01dec04a
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/933703
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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For boards using max17055 and dumb battery, we can always
read battery parameters from max17055 regs, even if the
read values are out of whack.
So it doesn't make sense to determine battery is present
because we can read these parameters from max17055.
Meanwhile, we have to set CONFIG.TSEL on max17055 as early
as possible because this is required for max17055 to detect
battery presense.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet rev3 w/o battery on Type-C/PD chargers
Change-Id: Id190f0c2aa5bcd62dbe3edccca6460bf145cff01
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/933702
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Skip the empty blocks when writing even if they are in the middle of the
firmware.
This greatly improves flashing speed when the firmware contains a
signature at the end of the RW.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=./util/flash_ec --board=meowth_fp
Change-Id: I3cd1c1bd2670be23d3d9daf9b87d9af0bdfc8963
Reviewed-on: https://chromium-review.googlesource.com/880956
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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When using the watchdog (IWDG) to perform the cold reset, set the Key
register to 'RELOAD' (0xAAAA) rather than 'START' (0xCCCC) to ensure
that the reset is performed immediately rather than at the end of the
current watchdog period (which might be 1 to 5s away).
Replace the Key register special values by their symbolic constants.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=On ZerbleBarn using a STM32H7, run 'ectool reboot_ec cold' and see
the MCU rebooting immediately rather than after 5s.
Change-Id: Ib49c703e3ec973389e4d774eda53f3be7ec4dd2e
Reviewed-on: https://chromium-review.googlesource.com/936764
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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This option will cause usb console output to block and
also compute a crc32.
Signed-off-by: mschilder@google.com
TEST=make buildall -j
BRANCH=none
BUG=none
Change-Id: Icf66d5ddbea52008a9c97094e7c83194caa7db79
Reviewed-on: https://chromium-review.googlesource.com/936281
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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Add crc32_ctx.. functions to take context parameter.
This allows for multiple instances to exist in parallel.
Signed-off-by: mschilder@google.com
TEST=make buildall -j8 succeeds
BRANCH=none
BUG=b:73832883
Change-Id: I66bbc56377eeebf01c790caad0bc4c7a51a1bc58
Reviewed-on: https://chromium-review.googlesource.com/935825
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch enhances the gsctool utility to allow to verify RO sections
of the target AP and EC flash memory.
The only command line parameter required for the new option ('O') is
the file name of the target descriptors database, containing memory
description sections for one or more Chrome OS devices.
Memory description sections are of two types (both types could be
referring AP or EC memory):
- hash descriptor, this section includes the address range of the
memory and one or more hash values for the contents of that address
range. Multiple hashes are needed in case when the same device has
mnore than one RO firmware releases in circulation.
- dump descriptor, this is a request for this utility to display on
the console the contents of the certain area of flash memory on the
target.
When this utility starts the process, the target might request that
the operator confirms physical presence, in this case the utility
keeps prompting the operator to press the physical presence button
until DUT is satisfied,
BRANCH=none
BUG=b:73668125
TEST=created a descriptor database for a Robo device feeding it with
values retrieved on the device by locally running spihash command
on the device.
Then ran this utility to verify successful hash and dump
retrievals, comparing dump values with values obtained through
Cr50 console directly.
Created additional dummy hash variants and verified that the
utility succeeds only if all matches happen at the same variant
index in different hash sections.
Change-Id: Ib43cf4eb642d141b7cd7f129ef412e14bd59f30b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/933545
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This is a lateral move allowing to share some data structures and
functions previously limited to the gsctool.c scope.
This will allow adding new functionality in a separate .c file, and
further refactor gsctool.c which little by little became quite
unwieldy.
BRANCH=none
BUG=b:73668125
TEST=gsctool utility still works for uploading Cr50 images.
Change-Id: Ib56db3e0b983c53a228a658467a3059abcf2166e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/933543
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch adds code which would parse the RO hash/dump descriptor
file including a database listing expected values of hashes for
various ranges of target SPI flash devices, or areas which need to be
printed out (hex dumped) for operator inspection.
Lines starting with '#' are completely ignored. The rest of the
logical lines could actually split into multiple text lines in the
file, so to separate one logical line from another at least one empty
line is required.
Hash descriptor database file consists of sections for various Chrome
OS boards. Each board description section starts with a logical line
of 4 characters which is the board ID (the same as the board's RLZ
code).
Each board description section includes variable number of range
descriptor entries, each entry being a logical line, potentially split
into multiple text lines.
Each entry consists of semicolon separated fields:
{a|e|g}:{h|d}:base_addr:size[:value[:value[:value...]]]]
Where
- the first sindgle character field defines the way the range is
accessed:
a - AP flash
e - EC flash
g - EC flash requiring gang programming mode
- the second single character field defines the range type
h - Cr50 returns the hash of the range
d - Cr50 returns actual contents of the range (hex dump)
- the third and and forth fields are base address and size of the range
- ranges of type 'h' include one or more values for the hash of the
range, each hash is a 64 byte hex string. Ranges of type 'd' do
not include any data.
All values are expressed in hex.
The parser API provides functions to open the passed in hash
descriptor file and find there the section for a particular board, a
function to advance to the next entry in the board's section, and a
function to close the file when board entries scanning is completed.
When scanning the entries, the parser verifies their sanity, i.e.
conformance with the above described format, that all hashes are of
the right size, that there are no hashes attached to 'dump' entries
and there is at least one hash attached to the 'hash' entries, and
that there are no invalid characters in the hashes and address range
definitions.
The parser is not yet used by the gsctool, but when the new module is
compiled stand alone with -DTEST_PARSER passed to the compiler, it
becomes an executable which can be given the test hash database (the
new file, sample_descriptor) to interpret and report success or
failure.
BRANCH=none
BUG=chromium:812880
TEST=ran the following commands:
$ gcc -DTEST_PARSER desc_parser.c -o dp
$ ./dp sample_descriptor
Section 1, rv 0
Section 2, rv 0
Section 3, rv 0
Unexpected data in section 4
Section 4, rv -22
Invalid hash 1 size 0 in section 5
Section 5, rv -22
Invalid hash 1 size 0 in section 6
Section 6, rv -22
Invalid hash 1 size 63 in section 7
Section 7, rv -22
Invalid hash 1 size 65 in section 8
Section 8, rv -22
Invalid hash 1 value in section 9
Section 9, rv -22
Unexpected number of variants in section 10
Section 10, rv -22
Invalid hex value 10x in section 11
Section 11, rv -22
Section 12, rv -61
$
Change-Id: I14b2754a5f6ba26b3c56ddc26d45cb4574514b69
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/923419
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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BUG=b:69634899
BRANCH=scarlet
TEST='battery' command shows the full cap is updated to 8734 mAh
Change-Id: I090d80e7c889c044ba2dfbdf02527a0791419320
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/933861
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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CONFIG_IGNORE_G_UPDATE_CHECKS currently drops all upgrade checks.
Now with CONFIG_BOARD_ID_SUPPORT only check for board_id match.
CR50_DEV still retains full no check behavior.
TEST=buildall -j8
BRANCH=none
BUG=none
Change-Id: I0d085a26c814cd0f35450f0a0db06fe8525ab896
Reviewed-on: https://chromium-review.googlesource.com/933589
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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BUG=b:73292704
BRANCH=None
TEST=None
Change-Id: I6f2f09232daed87fcd54a356ee13e69bfeda994c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/918381
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Jerry Parson <jwp@chromium.org>
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ectool can be older or newer than the EC's firmware. The version of
the tool needs to be found to debug compatibility issue.
This patch makes ectool print its own version in addition to EC's
version.
BUG=none
BRANCH=none
TEST=Run 'ectool version':
RO version: fizz_v1.1.7833+5a0bbd8fe
RW version: fizz_v1.1.7833+5a0bbd8fe
Firmware copy: RW
Build info: fizz_v1.1.7833+5a0bbd8fe 2018-02-20 09:56:26 foo
Tool version: fizz_v1.1.7831+d173cf4d6 2018-02-20 16:57:43 bar
Change-Id: Iac641c76e450368175213ab6d277e56d43742429
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/927305
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch makes EC firmware and cbi-util share the common code.
BUG=b:70294260
BRANCH=none
TEST=Set fields using ectool. Verify the contents by cbi command.
Verify cbi-util creates the same binary as before.
Verify emerge ec-utils ec-devutils pass.
Change-Id: If5e65e48dd03960e0adf23ef775f67aecf785d85
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/932001
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When running the spihash command using gsctool (as opposed to the
running it from the Cr50 console), the operator needs to be prompted
when the PP button needs to be pressed.
This patch extends spihash command implementation by adding a new
subcommand for polling physical presence.
BRANCH=cr50, cr50-mp
BUG=b:73668125
TEST=with the appropriate gsctool changes the user is periodically
prompted to press the physical presence button, and eventually it
is possible to set up spi hash access to AP and EC.
Change-Id: I96aed1619d364c80a2f35ca8dc41241f1a444103
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/930568
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Both CCD and SPI_HASH commands need to enforce physical presence. This
patch separates PP polling into a function which can be used by both
commands.
BRANCH=none
BUG=b:73668125
TEST=verified that running 'gsctool -a -o' on a Robo device still
allows to unlock CCD with PP enforced.
Change-Id: I49abb0e56ad37664eaad7cc34de44e1ac06e2d1b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/930567
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Currently, cbi console command dumps the buffered contents. This
patch will make the command dump the entire EEPROM.
BUG=b:70294260
BRANCH=none
TEST=Run cbi command on Fizz:
CBI_VERSION: 0x0000
TOTAL_SIZE: 18
BOARD_VERSION: 514 (0x202)
OEM_ID: 2 (0x2)
SKU_ID: 0 (0x0)
43 42 49 5c 00 00 12 00 00 02 02 02 02 01 00 01
01 02 ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
...
Change-Id: I39f3335a38eb72c95d53264ddc7386dd0910e946
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/930322
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Various parts of Cr50 code and Cr50 related utilities duplicate
definition of __packed available in include/common.h. Let's use the
same definition everywhere.
BRANCH=cr50, cr50-mp
BUG=none
TEST=make buildall succeeds
verified that linker generated map files for Cr50 RW are the same
before and after this change.
built and used gsctoo and rma_reset
Change-Id: Ib91f9bbad1f6822b347f32b393630f592df80d60
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/931929
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The function used to read or write Board ID value, when invoked for
reading, reports the value on the console, but does not save the read
value in the passed in structure.
Let's always save it in the structure so that the caller of this
function has access to the retrieved value.
BRANCH=none
BUG=chromium:812880
TEST=verified that 'gsctool -i' still operates as expected.
Change-Id: I9bc713386758ca6701e6b853e042652e2f392871
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/925692
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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With the upcoming extensions it would be beneficial to be able to keep
gsctool functionality spread among multiple source files. The current
Makefile is also not generating proper dependencies, which was fine
when gsctool utility was first introduced, but is not adequate any
more, and would be even more noticeable when more source files are
added.
In preparation let's just convert the build scheme into separately
compiling .c files, generating .d files while at it, and then linking
the .o files together in a separate link operation.
BRANCH=none
BUG=chromium:812880
TEST=verified that gsctool still builds fine and allows to update Cr50
image.
Change-Id: I537bbe6bf76ac71e8d30040b276b78513d390bbf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/923418
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The STM32H743xI Errata document (rev Y) mentions in the paragraph 2.2.15
'Reading from AXI SRAM might lead to data read corruption':
"""
Read data might be corrupted when the following conditions are met:
- Several read transactions are performed to the AXI SRAM,
- and a master delays its data acceptance while a new transfer is
requested.
"""
We can actually hit this under a fair interrupt load and two tasks
running (e.g polling with the AP with host commands while doing
fingerprint image acquisitions).
So apply the proposed workaround and limit concurrent read access on AXI
master to 1 by setting the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
register.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn or Meowth, run 'ectool fpmode capture vendor',
poll in a tight loop with 'ectool fpmode'. No longer see random panics.
Change-Id: I6270866b74645d53e4d65f07f65431d5dee11576
Reviewed-on: https://chromium-review.googlesource.com/926009
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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If the other side answers our DR_SWAP request with a WAIT message (as
bizarre as it might be), we want to retry later rather than giving up.
Set again the PD_FLAGS_CHECK_DR_ROLE flag in order to do so.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=fizz
BUG=chromium:814098
TEST=do repeated cold reset on Fizz connected to the 'interesting' USB-C
screen and see the DP alternate mode negotiated.
Change-Id: Icfb9fa209ce8cbe3c42c1e6946b43464544bdaea
Reviewed-on: https://chromium-review.googlesource.com/921141
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
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Execution of this command requires physical presence on the DUT, this
is why it is save to allow it over USB.
BRANCH=cr50, cr50-mp
BUG=chromium:812880
TEST=using modified gsctool verified that the command goes through and
physical presence indication is requested
Change-Id: I0aa371d8aaa5a480cc12d5d16edad8497142f4b4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/927796
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should
be decided based on the value of FMCLK. Since we are setting FMCLK to
30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz.
This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK.
BUG=b:73504527
BRANCH=fizz?
TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran
some reboot tests to ensure that there is no regression in boot time.
Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/925843
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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We have been using upstart script to force VR decay in runtime S0ix
for a while now and haven't seen any issues. This change pushes the
fix in EC so that we don't need the upstart script hack any more.
BUG=b:70881268
BRANCH=None
TEST=Verified by reverting upstart script that PMIC registers are
programmed as required to enable VR decay in S0 and S0ix.
Change-Id: I19729e907d2ae065758e69933d0b1d3e5b43d5e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/856856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cr50 cannot override the state of the power button. It was possible with
dev cr50 chips, but the capability was removed in prod chips. Change the
console command, so it is only used to get the state of the power
button.
Remove all of the commands used to override the power button.
BUG=b:73557298
BRANCH=none
TEST=none
Change-Id: I99cb5e8a18dd972fba460c434364702f06a26305
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/926964
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
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This patch makes cbi-util print the tag and the size of each field.
It also fixes help message and adds indendation for readability.
BUG=b:70294260
BRANCH=none
TEST=Run the command as follows:
$ cbi-util --show /tmp/cbi.bin
CBI blob: /tmp/cbi2.bin
TOTAL_SIZE: 18
CBI_VERSION: 0
Data Field: name: value (hex, tag, size)
BOARD_VERSION: 514 (0x202, 0, 2)
OEM_ID: 2 (0x2, 1, 1)
SKU_ID: 3 (0x3, 2, 1)
Data validated successfully
Change-Id: I5f0fde4690c29c0ee58c798e8cc35bac3ed1b6f8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/926781
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Eanble CONFIG_CROS_BOARD_INFO to read board info from EEPROM.
1. Change the EEPROM address to 0xa0.
BUG=none
BRANCH=none
TEST=Read data from EEPROM.
Change-Id: I81fbada6dd64627cc438d6ed405b696e442c3a83
Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/880525
Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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