summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* aleena,liara: Add new grunt-family boards.stabilize-10895.Bstabilize-10895.56.Brelease-R69-10895.BEdward Hill2018-07-2014-0/+1514
| | | | | | | | | | | | | | | Add Aleena and Liara boards. These are initially just a copy of Careena. BUG=b:111606874,b:111607004 BRANCH=none TEST=build Change-Id: I2e2d0a375c4d0943e6c7506bcad639d45d5f1eb4 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1142534 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* Nami: Disable Accel/Gyro sensor for clamshellsDaisuke Nojiri2018-07-203-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | Clamshells (e.g. Akali) don't have a BMI160. Currently, the interrupt pin connected to BMI160 is floating on Akali and causing an interrupt storm. This patch removes accel/gyro sensor from clamshells. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:111521601 BRANCH=none TEST=Verify accelinfo shows expected angles on Sona & Akali360. Change-Id: I95bcf75b47c88975aec9e9fdefc09b6e50672ab4 Reviewed-on: https://chromium-review.googlesource.com/1142140 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Wang <vwang@chromium.org>
* whiskers: enable heatmap interfaceWei-Han Chen2018-07-201-4/+20
| | | | | | | | | | | | | | | | Enable heatmap interface to send heat-map to host. BRANCH=whiskers BUG=b:70482333 TEST=make BOARD=whiskers TEST=tested on whiskers, get frame stream through USB interface Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I6721256d0008dda301f1b3027acbed1cf2fba9b4 Reviewed-on: https://chromium-review.googlesource.com/974604 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* bq25703: Fix charge ramp issueVijay Hiremath2018-07-192-31/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow the below charge ramp sequence for BQ25703. 1. Set InputVoltage register (0x0A) value to slightly below the adaptor voltage with full load specification. 2. Disable external ILIM_HIZ by setting ChargerOption2 (0x32) bit 7 to 0. 3. Enable ICO test by setting ChargeOption3 (0x34h) bit 11 to 1. 4. Set IIN_HOST (0x0F) register value to the maximum amount of input current limit the user would like to sink on VBUS. 5. Wait for approximately 2sec, and check the ChargeStatus register (0x20) bit 14 for ICO completion. 6. Read ADC_IIN register (0x2B) after ICO is done and write this value back to IIN_HOST (0x0F) BUG=b:80279932 BRANCH=none TEST=Manually tested on BIP. Used USB Charging Voltage Current Panel Meter. Current showed on the display is same as input current read by charger command. CDP: charger rating with 5A,1.5A are ramped to 2.4A,1.5A respectively. DCP: charger rating with 5A,2A,1A are ramped to 2.4A,2.2A,1A respectively. SDP: USB3.0 -> ramped to 850mA USB2.0 (Manually modified max current to 900mA) -> ramped to 750mA Change-Id: I15e01ae033aa25890c81a4836dae809be31d313d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1123679 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: fix prod RMA reset p256 key idVadim Bendebury2018-07-191-1/+1
| | | | | | | | | | | | | | | | | When the key blob was prepared, the key ID value was set to 0x20, whereas for the prod key the value should be set to 0x01. BRANCH=cr50 BUG=b:73296606, b:73647182 TEST=prod signed image works with the response received from the RMA server, and fails when using the response generated by the rma_test utility Change-Id: I9b0ae75c9a262cfdb7f096361ad2b04262a34f90 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1142473 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* careena: Correct GPIO_SYS_RESET_L pin definition.Jonathan Brandmeyer2018-07-191-2/+1
| | | | | | | | | | | | | | | | | | Caveat: Careena early generation hardware was reworked to a state which does not map SYS_RESET_L to any pin on the EC. This change updates the config to the next hardware gen. TEST=make -j buildall, schematic review BRANCH=none BUG=b:111593365, b:109874594 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: Icb1ca7ccbacd98f960e4f44041281d1b2ca94e6e Reviewed-on: https://chromium-review.googlesource.com/1142236 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nami: Undef CONFIG_USBC_SS_MUX_DFP_ONLY to enable device modeShelley Chen2018-07-191-1/+0
| | | | | | | | | | | | | | | | | | | In order to enable device mode on nami, we need to remove the CONFIG_USBC_SS_MUX_DFP_ONLY option. This will allow for the type C port to become an up facing port, which is needed for adb. BUG=b:110443736 BRANCH=Nami TEST=Ensure when attached to workstation, adb devices shows nami device and adb debugging popup appears in nami device. Change-Id: Icaec13af4246262931c19beb7e64bae41e721d96 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1142226 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Shelley Chen <shchen@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nx20: track vbus sourcing state locallyJett Rink2018-07-191-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | This solves as few problems: - We do not need to perform "expensive" i2c communication when we need to determine the state of Vbus that we previously set. -- This allows the is_sourcing_vbus call to be performed in an interrupt context (see crrev.com/c/969701/7/board/cheza/board.c#85). - This prevents the problem of the is_sourcing_vbus from being called before init after a sysjump thus potentially preventing power on (see b:80203727). - This also papers over an issue where the TCPC stops sourcing Vbus without our consent, because the logic work correctly if vbus is in the same state we last set it to (see b:111404471) This caching paradigm is apply to tcpc vbus level and other ppc is vbus being sourced (See CL:1086115) BRANCH=none BUG=b:111404471 TEST=Vbus on phaser's C1 discharges correctly Change-Id: I9c19c3d177a4a4e49be4372e8b01d84fcf2a0c4b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1141111
* kukui/scarlet: Remove CONFIG_MPUNicolas Boichat2018-07-192-6/+0
| | | | | | | | | | | | | | CONFIG_MPU does not make sense anyway on STM32F0 with Cortex-M0 core. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6e338cbbf783babd4e2c9dbe0a3188a086b54807 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1143108 Reviewed-by: Yilun Lin <yllin@chromium.org>
* driver/touchpad_st.c: support heat mapWei-Han Chen2018-07-195-4/+441
| | | | | | | | | | | | | BRANCH=none BUG=b:70482333 TEST=`make BOARD=whiskers` works w/ & w/o CONFIG_USB_ISOCHRONOUS Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: Ia05e778d9795a09ea6edceddd839992859d75050 Reviewed-on: https://chromium-review.googlesource.com/958897 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Nami: Remove ALS from all projectsDaisuke Nojiri2018-07-192-45/+0
| | | | | | | | | | | | | | | | | ALS has been removed from all variants Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:111597256 BRANCH=none TEST=make BOARD=nami Change-Id: If85545f79cc2f076c366ffeebdd96d3ccf31ed9c Reviewed-on: https://chromium-review.googlesource.com/1142192 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Wang <vwang@chromium.org>
* nocturne: Don't read gyro temp sensor in <= S5.Aseda Aboagye2018-07-191-1/+14
| | | | | | | | | | | | | | | | | | | | | The gyro is not powered in S5 or lower, therefore we should not return any temperature value for those power states. BUG=none BRANCH=master TEST=flash nocturne, shut AP down, verify no prints are emitted about i2c unwedging. Change-Id: I3bcc1efca40b27ec571657274aab69dca4e414d7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1132900 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 988468d17c8912c0f9a5345996b34f8848fdb739) Reviewed-on: https://chromium-review.googlesource.com/1142924 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* f75303: Make get_temp return temperature in KelvinDaisuke Nojiri2018-07-191-6/+1
| | | | | | | | | | | | | | | | | | This patch makes get_temp of f75303 driver return the temperature in Kelvin. This makes code more readable and efficient. There should be no functionality change. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=Verify temps command print expected temperature on Sona. Change-Id: Id5c052b8b97822348ec1c1c6a2c62529ecac9463 Reviewed-on: https://chromium-review.googlesource.com/1142692 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* careena: enable keyboard factory scanningDevin Lu2018-07-192-0/+24
| | | | | | | | | | | | | | This patch is referring to CL:332322. BUG=none BRANCH=none TEST=Short keyboard pins and make sure "ectool kbfactorytest" works. Change-Id: Ic943753c8cec8dde79842de48e5d21ff4dc01c00 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/1114400 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Generalize _plat__ResetCallback().Allen Webb2018-07-191-1/+1
| | | | | | | | | | | | | | | | This renames _plat__ResetCallback to _plat__InitCallback and invokes it for all cases of TPM_Startup instead of SU_RESET only. CQ-DEPEND=CL:1142537 BUG=chromium:863572 TEST=Check that "PinWeaver: Loading Tree!" is present in the Cr50 log after deep sleep Change-Id: If2be276eb79b683af209768967e9f4238e491596 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1142536 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* yorp: Deprecate yorp v0 supportFurquan Shaikh2018-07-183-100/+28
| | | | | | | | | | | | | | | This change gets rid of yorp v0 support from EC codebase. BUG=b:111545725 BRANCH=None TEST=Boots to OS. Change-Id: I1db238ce673a576b913e92874d0f1de730c04b05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1140742 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* fleex: Change USB2_OTG_ID to open drainFurquan Shaikh2018-07-181-1/+7
| | | | | | | | | | | | | | | | | | | | | USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects USB2_DUALROLE and USB2_VBUS_SNS to be 1.8V. Since there is an internal pull-up on USB2_DUALROLE from the SoC side, this change configures USB2_OTG_ID to be open drain so that it is actively driven from the EC when it wants to pull it low. Otherwise, the pin would be tri-stated from the EC side allowing it to be pulled up to 1.8V because of the SoC internal pull-up. BUG=None BRANCH=None TEST=None Change-Id: Icfe9f4ca6982d70f0e42bee589b68b7c4b768d9f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1140501 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* bobba: Change USB2_OTG_ID to open drainFurquan Shaikh2018-07-181-1/+6
| | | | | | | | | | | | | | | | | | | | | USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects USB2_DUALROLE and USB2_VBUS_SNS to be 1.8V. Since there is an internal pull-up on USB2_DUALROLE from the SoC side, this change configures USB2_OTG_ID to be open drain so that it is actively driven from the EC when it wants to pull it low. Otherwise, the pin would be tri-stated from the EC side allowing it to be pulled up to 1.8V because of the SoC internal pull-up. BUG=None BRANCH=None TEST=None Change-Id: Ia7f5cd32a80a2c9d0cc520bbacad0844aaec961d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1140500 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* bip: Change USB2_OTG_ID to open drainFurquan Shaikh2018-07-181-1/+6
| | | | | | | | | | | | | | | | | | | | | USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects USB2_DUALROLE and USB2_VBUS_SNS to be 1.8V. Since there is an internal pull-up on USB2_DUALROLE from the SoC side, this change configures USB2_OTG_ID to be open drain so that it is actively driven from the EC when it wants to pull it low. Otherwise, the pin would be tri-stated from the EC side allowing it to be pulled up to 1.8V because of the SoC internal pull-up. BUG=None BRANCH=None TEST=None Change-Id: I187eeaec8f54532c62347b7c0506701be1d1b205 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1140499 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpc: debounce entry into low-power modeJett Rink2018-07-189-36/+230
| | | | | | | | | | | | | | | | | | | | | | We need to keep track of the low-power mode hardware state for each TCPC so we can put a TCPC back into low power mode when it exits low power mode before the software TCPM state machine wants it out of low power mode. This change also breaks the low power mode entry out of the drp_toggle method into its own method: enter_low_power_mode. BRANCH=none BUG=b:77544959 TEST=Verified Analogix does not get into low-power mode loop. Tested other SRC/SNK capabilities as well. Tested the device will go back into low power mode if the AP access the TCPC via the 'ectool usbpdmuxinfo' command. Change-Id: I2fdefeda2bf13c2b79d988f0017629115438d313 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1119255 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* phaser: Change USB2_OTG_ID to open drainFurquan Shaikh2018-07-181-1/+6
| | | | | | | | | | | | | | | | | | | | USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects USB2_DUALROLE and USB2_VBUS_SNS to be 1.8V. Since there is an internal pull-up on USB2_DUALROLE from the SoC side, this change configures USB2_OTG_ID to be open drain so that it is actively driven from the EC when it wants to pull it low. Otherwise, the pin would be tri-stated from the EC side allowing it to be pulled up to 1.8V because of the SoC internal pull-up. BUG=b:111102089 BRANCH=None TEST=Verified that there is no more leakage of 1.8V rail. Change-Id: I306e809f6b3ad31596f7f11da68311afcd1eac32 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1140498 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nocturne: Adjust IMVP8 step decay quantization.Aseda Aboagye2018-07-181-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | The IMVP8 vendor suggested to change the step decay quantization from 3 to 1. Doing this seems to help with the hangs that were seen. This commit simply has the EC write to the IMVP8 to set this register ~250ms after sequencing to S0. BUG=b:111224125 BRANCH=master TEST=Flash nocturne, boot to S0, read back register 0xFA from IMVP8, verify that it reads back as 0x0ac5. Change-Id: Ic7444c763ed4da3a4b80b3a9e79b60c5fa984345 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1132718 Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit a3c9f1332a421343837cc5048ccbb9f66ff4ae95) Reviewed-on: https://chromium-review.googlesource.com/1141704 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nocturne: Add Gyro temperature sensor.Aseda Aboagye2018-07-182-0/+3
| | | | | | | | | | | | | | | | | | BUG=None BRANCH=master TEST=Flash nocturne, run 'temps', verify that Gyro temp sensor is present and reasonable. Change-Id: I59e405f1267dcd35087cfe82b965e85c041a9015 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1132717 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 84f79f22b22b66b77ddfb64eb75f27d485a982bf) Reviewed-on: https://chromium-review.googlesource.com/1141705 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* kukui: Disable vsync, motion sensor in RO.Yilun Lin2018-07-184-1/+9
| | | | | | | | | | | | | | | | | | | | | | Kukui's RO flash size (stm32f098VC) is 124KB, and the current EC RO consumes 104616 bytes (102.1KB), besides, the compressed AP FW bootblock takes 25088 bytes (24.5KB). The total size of EC RO and AP FW Bootblock (126.6KB) already exceeds the size limit. Here, we disable vsync and motion sensor in EC RO, and this decrease the EC RO to 92736 byte (90.5KB), saving around 11 KB. TEST=make BOARD=kukui -j BUG=b:80159522 BRANCH=None Change-Id: I7846714c888d95b8dbfd22b475972ecc47c28606 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1141451 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Makefiles.rules: Silence cmpNicolas Boichat2018-07-181-1/+1
| | | | | | | | | | | | | | | | | | | When building with stdout redirected to /dev/null: make buildall -j >/dev/null One would still see "error" message like: cmp: build/hammer/ec_version.h: No such file or directory BRANCH=none BUG=none TEST=make buildall -j > /dev/null is quiet again. Change-Id: I3ee9d090d3d46a70a096db0bebbfecaf293dca6d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1141448 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* usb_isochronous.c: change usb_isochronous APIWei-Han Chen2018-07-182-37/+112
| | | | | | | | | | | | | | | | | | 1. Export usb_isochronous_write_buffer function. 2. The tx_callback is called in interrupt context, so users can decide to fill the buffer with deferred function or task thread. 3. Allow adding extra endpoints to the interface. BRANCH=none BUG=b:70482333 TEST=tested on device Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I7bc7f8175803895dae8ebc7720bc7e468db20d1c Reviewed-on: https://chromium-review.googlesource.com/1089599 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* fan: Enable fan control on AP startup not on shutdown/suspendDaisuke Nojiri2018-07-172-12/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to cool CPU in S3 or S5. We currently don't have fans for a charging system (i.e. a battery or a charger chip). Battery management systems control charge current based on its own temperature readings. Thus, we do not need to keep fans running in S3/S5. Even with a fan for a charging system, it's questionable to run a fan in S3/S5. Under a heated condition, spinning a fan would create more heat as a fan draws current from a battery and the ambient air is hot. With this patch, EC disables fan control when entering S3/S5 (though fan control would be already disabled if DPTF is used). It also makes EC enables fan control when AP starts (for BIOS and OS if DPTF isn't used). Signee-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=Verify fan spins in S0 and stops in S3/S5. Fan is controled by EC in BIOS and by DPTF in OS after warm and cold reboot. Run make run-fan. Change-Id: Idb4610303e65f7fd4d6b24a0dfe511cd629bf6a7 Reviewed-on: https://chromium-review.googlesource.com/1138822 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cheza: Enable MKBP keyboard protocolWai-Hong Tam2018-07-171-0/+1
| | | | | | | | | | | | | | This is used for passing button information from EC to AP. BRANCH=None BUG=b:74395451 TEST=make buildall -j Change-Id: I8a4ee99fb699f484dcc71fe4c0c6a7fd05a94ffb Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1138731 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* Nami: Set boot power thresholdsDaisuke Nojiri2018-07-171-3/+8
| | | | | | | | | | | | | | | | | | | | | | This patch sets the required battery charge level to 3% and the required AC power to 27W. If both are below the thresholds, EC refuses to power on the AP. The OS has its own boot threshold, which should be high enough to prevent recovery mode from being terminated before completion. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:110908259,b:111446706 BRANCH=none TEST=Boot Vayne with a drained battery (1 ~ 3%) verify the system stays off or boots, respectively. Change-Id: Idbf5dcea7c5ee2c747c6c2a971629ed801c95d70 Reviewed-on: https://chromium-review.googlesource.com/1128322 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* nautilus: Remove the unused GPIO USB_POWERON_LPhilip Chen2018-07-172-6/+1
| | | | | | | | | | | | | BUG=b:111433611 BRANCH=poppy TEST=manually confirm USB-A port still works Change-Id: I70146f696056e526df08831847650710dea4a8ae Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1139400 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Show status on power LED even when PWR_STATE_ERRORDaisuke Nojiri2018-07-171-0/+3
| | | | | | | | | | | | | | | | | | Currently, the power LED doesn't show power state when there is a battery error. This patch fixes it. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:111535983 BRANCH=none TEST=Verify power LED turn on/blink/off in S0/S3/S5, respectively on Sona with a battery disconnected. Change-Id: I68dab92d41d905549bea8178381f2589a7b31df1 Reviewed-on: https://chromium-review.googlesource.com/1140773 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Nami: Add power LED control to SonaDaisuke Nojiri2018-07-171-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes EC control the power LED to show power status and tweaks the battery LED behavior accordingly. Power LED (single color): S0: White on S3: White on 1sec off 1sec S5: Off AC In/Battery LED (dual color): AC attached & battery full White on (S0/S3/S5) Charging Amber on (S0/S3/S5) AC not connected & Discharge Off Battery Error Amber on 0.5 sec, off 0.5 sec Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:74940319 BRANCH=none TEST=Verify LEDs show expected patterns on Sona for S0/S3/S5 and full/charge/discharge/error. Change-Id: I8fc2df6c6437f045b5a48c4a0387c4594c41a9c8 Reviewed-on: https://chromium-review.googlesource.com/1139216 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ectool: Allow for chips with more than 1 MB of flashNicolas Boichat2018-07-171-6/+9
| | | | | | | | | | | | | | | ectool currently assumes any offset >= 0x100000 (1MB) is invalid, this is not true on STM32H7. BRANCH=none BUG=none TEST=ectool --name=cros_fp flasherase 0x120000 131072 does not fail with "Bad offset." Change-Id: I5f8e29b03dbc4c1a3f1566b0e78d4466f4a44565 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1139951 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rwsig: If RW cannot be locked separately, always increment rollbackNicolas Boichat2018-07-171-4/+7
| | | | | | | | | | | | | BRANCH=none BUG=b:111190988 TEST=Lock RO, flash RW images of increasing CONFIG_ROLLBACK_VERSION, see that rollback minimum version is incremented in rollbackinfo. Change-Id: I48ee68d37098b74478432db9bf84dc96d1ef2dd8 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1137981 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* include/config.h: Clarify intent of local entropyNicolas Boichat2018-07-171-0/+4
| | | | | | | | | | | | | | | | | | | Clarify the meaning of defining: CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE This is only meant to add a little bit of extra entropy, when the hardware lacks a random number generator (otherwise, the strong entropy can be directly added to the secret, using rollback_add_entropy). BRANCH=none BUG=b:111190988 TEST=none Change-Id: Ife77f65ccdf8c36c8143b8d0a68526ad3c773c90 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1132825 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* panic_output: undefined behaviour elicits abort() callsPatrick Georgi2018-07-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | Explicitly coding x/0 doesn't result in a div-by-zero fault, but in an abort() call, which breaks the build as abort doesn't exist. By marking zero as volatile, the compiler must not assume that the value is still the same, so can't do constant subexpression elimination and determine that this expression leads to UB. Hat tip to shawnn@ for this unexpectedly elegant approach (compared to all other approaches). BUG=none BRANCH=none TEST=buildall works with gcc8.1 Change-Id: Idd34e3b4119d0d6a5231576e768ee285c621d229 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1126318 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nocturne: Reduce input current limit by 5%.Aseda Aboagye2018-07-171-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | Nocturne seems to overdraw its set input current limit by about 5%. Therefore, this CL simply reduces the set current limit to 95% of what's desired. BUG=b:72775843, b:111224125 BRANCH=master TEST=Flash nocturne; verify with USB-C power meter that power contracts are not exceeded. Change-Id: I649653427770020c97ae425e41967e755a4ec724 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1128563 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 9f741207bc0205b3c5b1099fdbd14d5612bd0f48) Reviewed-on: https://chromium-review.googlesource.com/1137993 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* scarlet: Change FIFO settingsAlexandru M Stan2018-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Similar to CL:1134494 Reduce the amount of datum to trigger a FIFO interruption. To improve timestamping in the kernel, we need to send a continuous stream of data to the host. In case of CTS batch test, we may not send anything for x100ms; the filter will not have any data to estimate the drift and may output invalid timestamps. Change the FIFO threshold to try to have more than ~10 samples in a singe batch. We still need a long FIFO when the EC is busy and can not process events from the sensor. BUG=b:73551961 BRANCH=scarlet TEST=in CtsHardwareTestCases, tests SensorBatchingTests pass more reliably. Change-Id: I254230498fcf270dfa303cf5eacec5d8abdd1225 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1137474 Reviewed-by: Philip Chen <philipchen@chromium.org>
* g: speed up RSA keygen by 40%Marius Schilder2018-07-162-423/+1186
| | | | | | | | | | | | | | | | | | | | Add a specialized modexp for 1024 bit operands. Available under CONFIG_DCRYPTO_RSA_SPEEDUP. Image size increase 2184 bytes. Signed-off-by: mschilder@google.com BRANCH=none TEST=new console command "genp [seed]"; record timing w/ and w/o speed-up and check that primes are identical for identical seeds. BUG=b:68167013 Change-Id: I23e2b5ab13902354debcdb42c693127e1e26262a Reviewed-on: https://chromium-review.googlesource.com/1083697 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* core/nds32: Instruct linker to use fp registers for storing gp valuesPatrick Georgi2018-07-161-0/+1
| | | | | | | | | | | | | | | This significantly decreases the code size. BUG=b:65441143 BRANCH=none TEST=building reef_it8320 with gcc 8.1 works Change-Id: I4787e33a80363fa8b0f3c184167c4067ff03bffa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1126317 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: it83xx: IT8320 family compatibilityDino Li2018-07-163-8/+33
| | | | | | | | | | | | | | | | | | | | | | | The bit7 and bit3 at UFPVDR register are reserved on BX version. But in DX version, these two bits are used to get the result of fast swap voltage comparing in UFP mode. So we change to mask three bits only. Add the support of two TX SOP type on the DX version. (Debug SOP' and Debug SOP'') On BX version, cc1/cc2 voltage detector function is enabled by bit1 or bit5 at register CCCSR. But on DX version, the bit1 will control both cc1 and cc2. So we create an option for this change. BUG=none BRANCH=none TEST=Plug USB-C power adapter and USB-C to hdmi adapter, both work. Change-Id: If881ef54145f211f7d48a971f56a6118487d9eed Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1119729 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx7: system: change the default value of FMUL_WIN_DLYMulin Chao2018-07-152-0/+9
| | | | | | | | | | | | | | | | | This CL changes the default value of Nuvoton internal register, FMUL_WIN_DLY, from 0x8A to 0x81 on npcx7 ec series. It increases the tuning rate of the FMULs to improve audio quality. For consistency, this is done across all NPCX7 devices. BRANCH=none BUG=b:74600211 TEST=make buildall; Run cold-reset stress test over 3 days on grunt. No symptoms occurred. Change-Id: I5ad0c115da4254413d43269140eb71092c11b3b2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1134815 Reviewed-by: Jett Rink <jettrink@chromium.org>
* driver: bmi160: Preserve the timestamp before releasing interruptGwendal Grignou2018-07-141-7/+13
| | | | | | | | | | | | | | | | | Collect timestamp before resetting the interrupt line: After reading, it is possible for the timestamp to change, before we can process the FIFO. BUG=b:67743747 BRANCH=scarlet TEST=CtsHardwareTestCases Change-Id: I283f8efb1098a38c76caf326b6416a386ab221cd Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1137438 Commit-Ready: Alexandru M Stan <amstan@chromium.org> Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* vboot: Invalidate cached hash if EC is in ROFurquan Shaikh2018-07-141-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 65d6c6a (vboot: Don't invalidate cached hash for EXEC_IN_RAM boards) changed the behavior of invalidating cached hash to ensure that AP triggers software sync if EC-RW RAM and flash copies do not match. However, this resulted in EC SW sync to fail because vboot in depthcharge reads hash right away after updating EC-RW to ensure that the flash update was indeed performed. Since EC does not invalidate the cache anymore, this results in incorrect hash being returned thus causing the system to reboot into recovery. Since vboot in depthcharge puts the EC in RO before updating EC-RW, this change invalidates cached hash if flash write/erase operations are performed with EC in RO. BUG=b:111449474 BRANCH=nami? TEST=Verified following: 1. Cached hash is invalidated when EC-RW flash is updated with EC in RO --> Flash BIOS-A and EC-A using servo --> Flash EC-B using servo --> Boot system --> Ensure that AP performs SW sync and boots to OS with EC-RW updated to EC-B 2. Cached hash is not invalidated when EC-RW flash is udpated with EC in RW --> Flash BIOS-A and EC-A using servo --> Boot to OS --> Flash BIOS-B and EC-B using flashrom on DUT --> Reboot device --> Ensure that AP detects mismatch in RAM and flash copies of EC-RW and causes EC to reboot. Change-Id: Ia50a9443e2f5ef9b1ed33992a46daf6230bf8816 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1137237 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* nocturne: Set BMI160 speed to 400kHZGwendal Grignou2018-07-141-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running at just 100kHz, the EC has difficulty to read samples in time. It can take up to read the FIFO 5 times back to back to read the samples: [484.946134 14 bytes in FIFO ] [484.949848 BMI160 ACC : int scan 2 times] [484.957095 14 bytes in FIFO ] [484.961614 14 bytes in FIFO ] [484.966271 14 bytes in FIFO ] [484.970900 14 bytes in FIFO ] [484.974541 BMI160 ACC : int scan 5 times] When 400kHz is enable it happens rarely. [Only when higher priority threads are running in thight loop]: [3341.194286 BMI160 GYRO ODR: 200000 - roundup 1 from config 0 [AP 200000]] [3341.201762 HC 0x67 err 9] [3341.202395 HC 0x67 err 9] [3341.203439 HC 0x67 err 9] [3341.204378 HC 0x67 err 9] [[3341.205056 HC 0x67 err 9] [3341.205654 HC 0x67 err 9] 3341.204881 14 bytes in FIFO ] [3341.206493 HC 0x67 err 9] [3341.209807 14 bytes in FIFO ] [3341.212296 BMI160 ACC : int scan 3 times] [3346.238588 BMI160 ACC ODR: 10000 - roundup 1 from config 1 [AP 0]] BUG=b:78539498,b:110143516 BRANCH=none TEST=Run CtsHardwareTestCases on Nocturne less tests fails. Change-Id: I07d067d04f6db3cfaf23c47baf6cd6942e46c159 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1137238 Commit-Ready: Alexandru M Stan <amstan@chromium.org> Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* nocturne: Change FIFO settingsGwendal Grignou2018-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Reduce the amount of datum to trigger a FIFO interruption. To improve timestamping in the kernel, we need to send a continuous stream of data to the host. In case of CTS batch test, we may not send anything for x100ms; the filter will not have any data to estimate the drift and may output invalid timestamps. Change the FIFO threshold to try to have more than ~10 samples in a singe batch. We still need a long FIFO when the EC is busy and can not process events from the sensor. BUG=b:73551961 BRANCH=none TEST=in CtsHardwareTestCases, tests SensorBatchingTests pass more reliably. Change-Id: I7e4dedf7c2a5a2403435fad0c2e828457bc33c42 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1134494 Commit-Ready: Alexandru M Stan <amstan@chromium.org> Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* driver: bmi160: harden interrupt and fifo processingGwendal Grignou2018-07-141-45/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | During cts test with CL:938146, the BMI160 would not send any interrupts and FIFO got un processed. - Latch IRQ events forever: the motion_sense task will kick in and read the interrupt source sometimes, even after 5ms. - Retest irq bits in irq_handler. If more events are posted, we will collect them right away, avoiding a task wake up round trip. We assume the BMI160 adds events too fast and force the motion task into a infinite loop. BUG=b:73557414,b:80284952 BRANCH=scarlet,poppy TEST=Without that code, BMI160 would get unprocessed: android.hardware.cts.SensorIntegrationTests#testSensorsWithSeveralClients fail: ... Iteration 0 failed: "WaitForEvents |i sensor='CrosEC Accelerometer', samplingPeriod=0us, maxReportLatency=0us | requested=100, received=0, With it, the 25 iterations pass. Change-Id: I0f94b811ac0dbf60dcfa24c899682a2b5eb69de7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1128554 Commit-Ready: Alexandru M Stan <amstan@chromium.org> Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* grunt, careena: Clean up GPIO alternate functions.Jonathan Brandmeyer2018-07-132-26/+26
| | | | | | | | | | | | | | | | The NPCX only supports two modes per pin: Peripheral function or GPIO. The chip and its driver do not support alternate peripheral functions. TEST=buildall -j BRANCH=none BUG=b:79686781 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: Ib5d7ba81b5224ed9c121887d664dac659962b2c2 Reviewed-on: https://chromium-review.googlesource.com/1136942 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* USB-PD: Advertise high current Rp after Vconn is appliedDaisuke Nojiri2018-07-131-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | When a device such as HDMI dongle which has Ra/Rd is connected to a CCD port, CC1 and CC2 voltages fall in the CCD range if we advertise 3A (Rp=4.7kohm). This patch makes TCPM first advertise default USB current, 900mA (Rp=56kohm), then advertise 3A (or whatever the higher current the board defines) after a sink device is attached and Vconn is turned on. Once Vconn is turned on, CCx voltage will be out of the CCD range. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:110283597 BRANCH=none TEST=Verify picture is shown on HP Z27n via Analogix port of Vayne when: 1. HDMI cable and Dingdong are connected first then DUT is connected 2. Dingdong and DUT are connected first then HDMI cable is connected Repeat 1 and 2 with Parade (non-CCD) port connected to a charger. Change-Id: I2131268abf7ea6414b8277f924e4cd48f6a98800 Reviewed-on: https://chromium-review.googlesource.com/1121339 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Grunt: Elide obsolete GPIO configuration.Jonathan Brandmeyer2018-07-131-1/+0
| | | | | | | | | | | | | BRANCH=none BUG=none TEST=make -j buildall Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: I2beb407e39acd49755982587b8de6602b7e00f4e Reviewed-on: https://chromium-review.googlesource.com/1136712 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
View Lorry Controller Status