| Commit message (Collapse) | Author | Age | Files | Lines |
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The sensors on the i2c line do not operate reliably
at 1Mhz i2c bus speed. Lower to 400kHz
BRANCH=75,76
BUG=b:136676970
TEST=verify that i2c bus speed when from ~1Mhz to ~400kHz after
this change with an oscilloscope.
Change-Id: Ie970f76fe7408de17f92bfc9f22a951b635fd278
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1691309
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
(cherry picked from commit 48765c68fc17b84902afc0a3bd5926e5721e669f)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693124
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This reverts commit 58f535e8c175311d866d4c1dd2d283d69230e9c5.
Now that b:136265450 has an actual fix landed, we need to revert this
workaround to reduce power usage when the system is off.
BUG=b:136265450
BRANCH=R76,master
TEST=press 'shut down' on normally failed DUT, observe ISH come alive
at next boot multiple times
Change-Id: I623249dfcb697a055378ca721721f346b01b7a8e
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1691117
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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Before switch to aon task, cache and ROM will be power gated
(PMU_RF_ROM_PWR_CTRL control register) in ecos, and resume after
switched back to ecos.
But for reset_prep/D3 process, aon task will reset minute ia to ROM
finally but forget to resume the power of ROM. This keeps ROM still
power gated and make ROM code can't run correctly.
The fix is simple, just disable power gating of ROM before reset to ROM
in aon task.
BUG=b:136265450
BRANCH=none
TEST=ISH fw should always load
Change-Id: Ib26678bbfdd5dbb17389154478f2565c44d392ab
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1690420
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
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This is a temporary workaround based on PS1 of Hebo's CL:1684825. The
actual fix for b:136265450 should revert this.
The cost of this change is higher power usage when the system is
powered off.
BUG=b:136265450
BRANCH=R75,R76,master
TEST=Normally failed DUT comes back alive consistently with this
change.
Change-Id: I623249dfcb697a055378ca721721f346b01b7a8f
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688147
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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We don't need to loop to figure out when to schedule the next sensor
collection event, just schedule it as soon as possible. This eliminates
a watchdog reset when we miss scheduling the sensor task and get really
far behind.
BRANCH=none
BUG=b:133190570
TEST=normal operation is fine, based on longs of failing results in bug,
this should prevent the watch reset.
Change-Id: I3001028ba393b51d1958f0136ba040eaee5e52d1
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1658521
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
(cherry picked from commit 8374923a60c8b63b7bb2c1823e4f5b6078544e44)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660583
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Use the debounced lid switch state for lid close instead of the raw
gpio.
BRANCH=none
BUG=b:126861777
TEST=tablet mode state is cleaner around 0 degrees
Change-Id: I46d7e2ed7fa0af7f276662e5136613caaed539f7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644211
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Reload the watchdog timer immediately after exiting from D0ix before
re-enabling the reset of the IRQs.
Also re-enable all ISRs in a batch while interrupts are disabled to
limit the number of context switched if multiple interrupts are pending.
BRANCH=none
BUG=b:133190570
TEST=let arcada enter and exit D0i[0123] without issue for a couple of
minutes. There are not adverse affects of this change.
Change-Id: I3ef5878b0618a0c1858664cad061d415329d4302
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644210
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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This adds a relevant config option, as well as implementation for a
max-retries mechanism on the watchdog timer. Included is an
implementation for ISH which counts persistent data storage and halts
when the max-retries is exceeded.
BUG=b:132059981
BRANCH=none
TEST=observed system halt after 4 resets, then re-enable once we had a
successful reset
Change-Id: I7b443d9a20a474b294d494c5b6046a38eaf6ff12
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644209
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
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Move persistent data definitions to a structure and have linker script
define the address of the symbol into the AON ROM (persistent data
storage). Use the magic number "ISHd" to verify persistent data
storage and copy to static memory when valid. Commit changes from the
local copy during reset.
BUG=b:133779707,b:133647823,b:132059981
BRANCH=none
TEST=power-on is only reset flag under cold reset, panic data
persists, watchdog reset produces correct reset flags, UART always
printing system info on boot
Cq-Depend: chromium:1644188
Change-Id: I65a458cc2656f8fe26361ef2117ceb5439edff6c
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644208
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
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In order for chromeos-ish ebuild to run tests, it must run the fuzz
tests, which are not related to ISH features, and introduce a lot of
library dependencies into the ebuild.
Provide two new targets: runhosttests and runfuzztests to allow the
host tests to be run separately. runtests (and buildall) remain the
same.
BUG=b:134446400
BRANCH=none
TEST=ran new targets, they functioned as intended
Change-Id: Idba7fcfe707caeb0e51ce0c38caeac9da87e3baf
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644207
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
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ish_dma_page was intended to be used in the aontaskfw implementation,
but we never used it. Remove the unused code.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I33983a4e6c6de082078b8b6b59519fbc095d8022
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1631588
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1643846
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
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When starting to send UART data, we do not need to invoke the ISR for
the UART. That only needs to be invoked if there is incoming RX messages
(which it still is invoked) or the FIFO can accept more data and was
full before.
BRANCH=none
BUG=none
TEST=console input and output still works and takes much less time.
Change-Id: Ib05c66ee704aad2d93836709bc6b706c627285c5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1634620
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1643845
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When PECI is undefined, updating the memory map after initializing
the sensors causes an illegal temp_sensor_read and raises an out of
bound array index error. Hence, adding PECI ifdef to prevent accessing
out of bound index.
BUG=b:132061907
BRANCH=None
TEST=Able to boot iclrvpy_ite all the way to chrome os
Change-Id: I65dd0c3fd8419384e632d24ce137ebde2b9dc5ed
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1631932
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Ayushee Shah <ayushee.shah@intel.corp-partner.google.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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DFU's 'Runtime' identifier.
Some USB devices include the DFU Runtime descriptor during normal use.
These devices are detected as potential targets by DFU-UTIL causing it to
incorrectly identify multiple potential DFU targets leading to errors
while flashing. This change adds an additional requirement using the
device's expected vendor:product id to select the correct device.
BUG=b:133329195
BRANCH=none
TEST=Verified DFU with STM32 based devices: Servo_v4, Servo_Micro, and
Sweetberry flash as expected. Verified that the awk correctly extracts
and eliminates devices with the DFU's Runtime identifier when a
suitable device connects. Verified pattern matching on variations of
the serial.
Signed-off-by: Brian Nemec <bnemec@chromium.org>
Change-Id: I2331b5e06d2eebf8dc28f20b9dd6b10bf2abe02a
Reviewed-on: https://chromium-review.googlesource.com/1626650
Commit-Ready: Todd Broch <tbroch@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
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Remove baseboard-specific GPIOs. Remove a few functions in board.c
that won't exist due to only one pin supporting PP5000_A enable.
BUG=b:133501368
BRANCH=none
TEST=Compiles
Change-Id: I18d3067c71f9fec2d9e68f339eb3f0f299ae2690
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1631306
Tested-by: Scott Collyer <scollyer@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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Update board_battery_info with latest battery pack information
BUG=b:133381447
BRANCH=none
TEST=make BOARD=helios
Change-Id: I31d751c338c52b44fdae291f94d59282543e4c1c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1632771
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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This CL is just the staring point for Helios EC image.
BUG=b:133501368
BRANCH=none
TEST=make -j BOARD=helios
Change-Id: I5a6afc1eaf9302434ea9a9a722612a8d14526e67
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1631931
Commit-Ready: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Currently the I2C tunnels of all TCPC ports are protected implicitly
when the system jump is disabled. Depthcharge issues that command after
the EC jumps to RW and before the TCPC firmware update is applied. This
leads to failure while updating the TCPC firmware and hence a reboot loop.
Fix this behavior by adding a sub-command to protect all the I2C tunnels
so that depthcharge can issue that command after both EC SW Sync and
TCPC Firmware update are done.
BUG=b:129545729
BRANCH=None
TEST=make -j buildall; Boot to ChromeOS. Force a TCPC FW update and
ensure that the reboot loop does not happen.
Change-Id: I5dd2314cf82dcfff520dc32ce3ced232326ab3d5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1605260
Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Currently, if a battery is disconnected but reporting a charge
percentage over CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC, a
system will be allowed to boot despite the battery not providing power
yet.
This change verifies that the battery is connected, as well as having a
high enough charge percentage before allowing boot.
BUG=b:133724948
BRANCH=octopus
TEST=verified casta can power on once
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC is passed and battery is
connected
Change-Id: Ide9fe041a328bbeaeee8b9e7f9788b5731ac80ea
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1635531
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
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Currently, supplier_priority is shared across boards. This patch makes
it weakly defined so that boards can customize it.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=Verify BC12, PD work on Flapjack. buildall.
Change-Id: Ie1e73758c611414512425121164bf7d56cf02697
Reviewed-on: https://chromium-review.googlesource.com/1622889
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Remove folks no longer on the project and add new owners.
BRANCH=None
BUG=None
TEST=None
Change-Id: I6572d9685661fc1482b7f568be78649136cc5987
Signed-off-by: Kirtika Ruchandani <kirtika@google.com>
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1630614
Commit-Ready: Kirtika Ruchandani <kirtika@chromium.org>
Tested-by: Kirtika Ruchandani <kirtika@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Kirtika Ruchandani <kirtika@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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supported_modes is an array of structs, and addresses of array elements
cannot be null.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1268e024ba8b2469d1bc70be27b3e98044a7ac04
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 141742
Reviewed-on: https://chromium-review.googlesource.com/1629279
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Ensure that 360-degree-hall sensor is hooked up to the tablet mode ISR,
which should in turn ignore any weird lid angle calculations when the
hall sensor is active (i.e. lid is at 360 degrees)
BRANCH=R75
BUG=b:131785573
TEST=arcada does not have spurious edges on the NB_MODE# signal when
the lid is all the way open in 360 degree mode.
Cq-Depend: chrome-internal:1329664
Change-Id: I1756bd909e5ecba7caa4565376f98f6d0dad6b06
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1597190
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Split common/fpsensor.c so that it contains only hardware-dependent
code, and put hardware-independent code to common/fpsensor_state.c.
This facilitates unit testing of hardware-independent code.
BRANCH=nocturne
BUG=chromium:952275
TEST=ran unittests
Change-Id: I0c050c7affa83e7cb935e2b657b2823cafe4c35f
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1625774
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
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- Remove hardcoded message header size
- Check the return value of tcpc_write_block
- Merge unnecessary assignment
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic4db769f6f9d62ffb4eb10621b15dc414c0bab26
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 187542
Reviewed-on: https://chromium-review.googlesource.com/1629275
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This argument count check is already performed at the beginning of the
function and is useless anyway since we've already accessed argv[1].
BUG=none
BRANCH=none
TEST=none
Change-Id: I9f1de3c5e67bb0db5564d8a1161b2ae646e8dfe9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 141743
Reviewed-on: https://chromium-review.googlesource.com/1629277
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Correct battery charging current from 2A to 3.5A according to datasheet.
BUG=b:133584769
TEST=make BOARD=kukui/krane, check the charging current in battery info.
BRANCH=none
Change-Id: I5a4a67d078c4b53cdf30ccc99a16498f1978b34e
Signed-off-by: Tony Lin <tonycwlin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1630130
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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The Platform Environment Control Interface (PECI) is a thermal management
standard with one-wire bus interface that provides a communication channel
between Intel processor and chipset components to external monitoring or
control devices.
As we can read the CPU temperature over PECI more accurately than the
thermistors, we can eliminate usage of thermistors for reading CPU
temperature.
BUG=b:128666114
BRANCH=none
TEST=Manually tested on Dragonegg, able read CPU temperature.
Change-Id: Ie0845ca776e6a7e14511dc9315d6d83cdd5f09a6
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1622740
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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When low battery(under 1%) is connected to system and ac is connected,
the system waits till RSOC becomes 1%. We need to notify user that
battery is charging to get enough power to power on.
BUG=b:133459206
BRANCH=octopus
TEST=flash EC, connect PD adapter and check if red led blinks
on low battery(under 1%)
Change-Id: Ie5f23e0dfe170ea4317103682733f88c203c2339
Signed-off-by: YongBeum Ha <ybha@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1627844
Reviewed-by: Diana Z <dzigterman@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
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Sweetberry project to repair ToT.
The change which updated the toolchain exposed a problem with the
USB initialization which prevents powerlog from being able to
communicate with the device. The root cause has not been
identified so the follow up issue b/132204142 has been filed.
BRANCH=Servo
BUG=b:126223732
TEST=Verified that the Sweetberry project is able to build, lsusb
identifies the device, and powerlog is capable of communicating with
the device and retrieving data.
Change-Id: I0d1f7e79a8ea890dcf5da3c16427220cf9067fdf
Signed-off-by: Brian Nemec <bnemec@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1601350
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
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OS can leverage `ectool usbchargemode` to control the usb_charge_mode
in the EC. In this case, we might want to set mode back to the default
one defined in the config of board level therefore the new
usb_charge_mode is added for this purpose.
BUG=b:130767435
BRANCH=octopus
TEST=1. make -j buildall
2. ectool usbchargemode 0 0x5 0
3. usb charging mode is set to CDP in Octopus board
Change-Id: Ib7397993fc49e6c744dc55b9adace95dd6b8bd3a
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1621452
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BUG=b:130767435
BRANCH=octopus
TEST=1. `make buildall -j4`
2. execute `ectool usbchargemode 0 2 1` in EC RO stage.
3. jump to EC RW stage.
4. check whether charge_mode in RW is restored well in
usb_charge_init()
Change-Id: I57346d3d92fa58a4d07b7509846123fc8f0c93fc
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1626890
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Blorb and droid are first projects we are tyring to enable the control
of USB Type-A power in the run time. This CL set
inhibit_charging_in_suspend to USB_DISALLOW_SUSPEND_CHARGE in default
and relies on OS to change this flag based on the status of USB device
on the USB Type-A port.
BUG=b:130767435
BRANCH=octopus
TEST=1. `make BOARD=bobba -j4`
2. check power of USB Type-A port is disabled when OS gets into
S0iX and no any USB device is ever connected to DUT.
Change-Id: I19ff69df89a857cd3feb594641b6562f20356879
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1621451
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This patch increases thermal shutdown thresholds for Pantheon.
The test shows with higher thresholds, Pantheon can last 40 hours in
operational temperature (40c).
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/133224156
BRANCH=nami
TEST=See the bug.
Change-Id: Ifa8bbbede014449208511b41f9bbea9cbdea9396
Reviewed-on: https://chromium-review.googlesource.com/1625252
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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We want to be able to track TRNG stalls happening in the field. This
patch adds a log message to report detected TRNG stalls. The code
detecting the stall is being modified to monitor a different status
bit as per chip designer recommendation.
A console command allowing to test TRNG is being added, compiled in
only if TEST_TRNG is defined.
BRANCH=cr50, cr50-mp
BUG=b:27646393
TEST=compiled the test command in, ran the command
rand 10000000
several times, observed reasonable stats and no stall reports.
Change-Id: Idcf83ff2c41e23f601b8da8c46fa4d4d1cde0270
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1601470
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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When chaning the macro fro BMA255, the step was set to 125Hz, so it
assumes the EC can support MEMS ODR set to 125Hz.
This is not the case on poppy and nautilus in the poppy branch.
BRANCH=poppy
BUG=b:118205424,b:118851581,chromium:615059,b:131705379
TEST=Compile
Change-Id: Ib60abb3919dc1ce049211d848fc4e4de2e5e51c0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1621188
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
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When cometlake is sequencing from G3->S5, the 5000_A rail is
enabled. After enabling the 5000_A rail there was a while() loop to
wait for the 5000_A rail to go high. If for some reason this rail did
not go high, then it would just loop there until a watchdog reset.
This CL removes this while loop check and instead modifies the macro
CHIPSET_G3S5_POWERUP_SIGNAL to include the PP5000_A_PG signal. The
common intel_x86 power sequencing code already has a check just after
the call to chipset_pre_init_callback.
BUG=none
BRANCH=none
TEST=Manual
If no battery is present and the bq25710 reset register bit is set,
then PPVAR_VSYS gets set to ~4V which is not high enough to generate
PP5000_A rail. In this state the EC would consistently watchdog loop
when just as AP power sequencing was initiated by the EC. Verified
with this CL, that while the PP5000_A rail still doesn't come up, that
the EC no longer hits a watchdog and power signal failure is logged in
the EC console.
Change-Id: I02aab7ed4f4723ec0d3ae04e4b8093494877615f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1599674
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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When moving an H1 between prod and dev Cr50 images, it is important to
quickly determine that the NVMEM contents are not retrievable. The
first object verified by the initialization routine is the page
header, but since SHA value is used for integrity verification, it
does not change despite the fact that the mode (and encryption keys as
a result) changed.
Using encrypted header value for integrity verification guarantees
that when transition between prod and dev modes happen the
initialization function discovers it right away and reinitializes
NVMEM instead of trying to interpret corrupted objects.
The host/dcrypto stub used for unit tests and fuzzing needs to be
modified to ensure that page headers read from uninitialized flash do
not look valid (where encrypted value of 0xffffffff is 0xffffffff).
BRANCH=cr50, cr50-mp
BUG=b:129710256
TEST=make buildall -j successd, as well as migration of a Chrome OS
device from legacy to new nvmem layout.
Change-Id: I613513cc67b14f553d2760919d6058f8dbed6e41
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1615423
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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There is no point in trying any nvmem operations when
encryption/decryption services are not available.
Test changes necessary to make sure test app compiles and runs
successfully.
BRANCH=cr50, cr50-mp
BUG=b:132800220
TEST=The device does not crash any more after tpm is disabled.
Change-Id: I97f9afc6e4d5377162500fc757084e4d5a57d37d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1615424
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This CL enables CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA with a 8192 mA limit.
With his config enabled, the bq25710 will be kept in performance mode
when the AP is in S0. The IDCHG (battery current) prochot trigger is
activated and whenever the battery current draw spikes above 8192 mA,
prochot will be asserted for its defined pulse width (default is 10
msec).
BUG=b:132197575
BRANCH=none
TEST=Was tested at the factory on battery only. When the battery SOC
was less than 5% the unit failed to boot 5 out 5 attempts. Using this
CL to enable IDCHG prochot, the unit booted successfully in same
scenario on all 5 attempts.
Change-Id: I60956fc0311e95cef6621287e93424a37bcfdc98
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1614785
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This config option is used to both set a limit for IDCHG and enable
IDCHG as a trigger for prochot. With this feature enabled, Kohaku is
able to boot into the kernel and remain running even under heavy loads
while on battery only. The initial battery that's being used is only
2S+1P which does not provide sufficient power for CPU peak load
conditions.
BUG=b:132285560
BRANCH=none
TEST=Manual
Verfied that Kohaku can boot running on battery only and remains
powered up as the CPU load gets increased.
Change-Id: Idfc4b65d2b86ee9883345c6aa610130d2b9fe89e
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1613798
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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pyusb 1.0.2 changed two API calls upon which we depend:
b3ee6cdfef8f find function returns an iterator.
dac78933f6a6 Removed unnecessary length argument to util.get_string
This CL only updates callers of these APIs (the previous CL contained some
unrelated changes around kernel driver detach and closing stm32usb).
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Based-on: https://chromium-review.googlesource.com/1125354
BRANCH=None
BUG=chromium:958677
TEST=precq passes
TEST=chromiumos-sdk tryjob buildbucketId=8915374561970847360
TEST=using servo v2
servod -b grunt
=> no python exceptions when starting servod
TEST=using servo v4
servod -b grunt
=> no python exceptions when starting servod
TEST=using u-Servo:
servod -b grunt
=> no python exceptions when starting servod
for i in {1..10000} ; do echo $i $(dut-control ec_uart_en spi1_buf_en ); done
=> No stability regression versus pyusb-1.0.0b1
TEST=servo_updater, EC console via servo
Cq-Depend: chromium:1597548,chromium:1597156,chromium:1597157
Change-Id: Ic8101707838e5d19e901cf1f7125b97b5102f089
Reviewed-on: https://chromium-review.googlesource.com/1597156
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Chris McDonald <cjmcdonald@chromium.org>
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The recently introduced vendor command is used to get or set flash log
timestamp.
BRANCH=none
BUG=b:132287488
TEST=on the device ran various incarnations of the command (> prompt
on the Cr50 console, # is the DUT bash):
> flo 10 10
> flo
1:00
13:0a 0a 0b 0c 0d 0e 0f 10 11 12 13
==== afger a few seconds =====
# /var/tmp/gsctool -a -T
Current H1 time is 68
==== afger some more time =====
> flo 5 5
> flo
1:00
13:0a 0a 0b 0c 0d 0e 0f 10 11 12 13
398:05 05 06 07 08 09
# /var/tmp/gsctool -a -T 300
error: return value 1
# /var/tmp/gsctool -a -T 1000000
> flo 6 6
> flo
1:00
13:0a 0a 0b 0c 0d 0e 0f 10 11 12 13
398:05 05 06 07 08 09
1000022:06 06 07 08 09 0a 0b
# /var/tmp/gsctool -a -T
Current H1 time is 1000052
Change-Id: I16ceb97a32b4d452705f9df3826151f3e4e45832
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1610721
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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There is no need to duplicate short and long option strings in the
.opt and .help_text fields, one is enough.
To properly format --help output in case the command line argument
expects a parameter, part of the .help_text string has to be printed
concatenated with the option strings.
Let's retrieve the short and long option strings form from the .opt
structure and use '%' as the formatting character to allow to indicate
that the the beginning of the help message needs to be printed
concatenated with the option strings.
Also correct the general description.
BRANCH=none
BUG=none
TEST=help text before this change:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ gsctool -h
Usage: gsctool [options] [<binary image>]
This utility allows to update Cr50 RW firmware, configure
various aspects of Cr50 operation, analyze Cr50 binary
images, etc.
The required argument is the file name of a full RO+RW
binary image.
A typical Chromebook use would expect -s -t options
included in the command line.
Options:
-a,--any Try any interfaces to find Cr50 (-d, -s, -t are all ignored)
-b,--binvers Report versions of Cr50 image's RW and RO headers, do not update
-c,--corrupt Corrupt the inactive rw
-d,--device VID:PID USB device (default 18d1:5014)
-f,--fwver Report running Cr50 firmware versions
-F,--factory [enable|disable]
Control factory mode
-h,--help Show this message
-I,--ccd_info Get information about CCD state
-i,--board_id [ID[:FLAGS]]
Get or set Info1 board ID fields
ID could be 32 bit hex or 4 character string.
-k,--ccd_lock Lock CCD
-L,--flog [prev entry] Retrieve contents of the flash log (newer than <prev entry> if specified)
-M,--machine Output in a machine-friendly way. Effective with -b, -f, -i, and -O.
-m,--tpm_mode [enable|disable]
Change or query tpm_mode
-n,--serial SERIAL Cr50 CCD serial number
-O,--openbox_rma <desc_file>
Verify other device's RO integrity
using information provided in <desc file>
-o,--ccd_open Start CCD open sequence
-P,--password
Set or clear CCD password. Use
'clear:<cur password>' to clear it
-p,--post_reset Request post reset after transfer
-R,--sn_rma_inc RMA_INC
Increment SN RMA count by RMA_INC.
RMA_INC should be 0-7.
-r,--rma_auth [auth_code]
Request RMA challenge, process RMA authentication code
-S,--sn_bits SN_BITS
Set Info1 SN bits fields.
SN_BITS should be 96 bit hex.
-s,--systemdev Use /dev/tpm0 (-d is ignored)
-T,--tstamp <stamp> Set flash log timestamp base
-t,--trunks_send Use `trunks_send --raw' (-d is ignored)
-U,--ccd_unlock Start CCD unlock sequence
-u,--upstart Upstart mode (strict header checks)
-V,--verbose Enable debug messages
-v,--version Report this utility version
-w,--wp Get the current wp setting
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
and after this change:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ ./extra/usb_updater/gsctool -h
Usage: gsctool [options] [<binary image>]
This utility allows to update Cr50 RW firmware, configure
various aspects of Cr50 operation, analyze Cr50 binary
images, etc.
<binary image> is the file name of a full RO+RW binary image.
Options:
-a,--any Try any interfaces to find Cr50 (-d, -s, -t are all ignored)
-B,--background_update_supported
Force background update mode (relevant only when interacting with Cr50 versions before 0.0.19)
-b,--binvers Report versions of Cr50 image's RW and RO headers, do not update
-c,--corrupt Corrupt the inactive rw
-d,--device VID:PID USB device (default 18d1:5014)
-f,--fwver Report running Cr50 firmware versions
-F,--factory [enable|disable]
Control factory mode
-h,--help Show this message
-I,--ccd_info Get information about CCD state
-i,--board_id [ID[:FLAGS]]
Get or set Info1 board ID fields. ID could be 32 bit hex or 4 character string.
-k,--ccd_lock Lock CCD
-L,--flog [prev entry] Retrieve contents of the flash log (newer than <prev entry> if specified)
-M,--machine Output in a machine-friendly way. Effective with -b, -f, -i, and -O.
-m,--tpm_mode [enable|disable]
Change or query tpm_mode
-n,--serial Cr50 CCD serial number
-O,--openbox_rma <desc_file>
Verify other device's RO integrity using information provided in <desc file>
-o,--ccd_open Start CCD open sequence
-P,--password Set or clear CCD password. Use 'clear:<cur password>' to clear it
-p,--post_reset Request post reset after transfer
-R,--sn_rma_inc RMA_INC Increment SN RMA count by RMA_INC. RMA_INC should be 0-7.
-r,--rma_auth [auth_code]
Request RMA challenge, process RMA authentication code
-S,--sn_bits SN_BITS Set Info1 SN bits fields. SN_BITS should be 96 bit hex.
-s,--systemdev Use /dev/tpm0 (-d is ignored)
-T,--tstamp [<tstamp>] Get or set flash log timestamp base
-t,--trunks_send Use `trunks_send --raw' (-d is ignored)
-U,--ccd_unlock Start CCD unlock sequence
-u,--upstart Upstart mode (strict header checks)
-V,--verbose Enable debug messages
-v,--version Report this utility version
-w,--wp Get the current wp setting
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Change-Id: I5afd2473dbdaf9edc515ee9f02b932effe3755c5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1628113
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Standard libc getopt_long() and getopt() functions do not allow the
optional parameters to follow the command line option without the equal
sign ('='), but gsctool utility users expect this form to be
available, so additional processing is done for command line arguments
accepting optional parameters.
This additional processing code is duplicated for each such argument.
On top of that, some arguments which described as requiring the
parameter (not optional) still include code which looks for the
command line option.
Information about expected parameter type is included in the long
options descriptor table, so it is not readily available if the user
specified the short version of the argument in the command line.
To consolidate processing of the optional parameters in one place, in
case the user specified the short version of the command line
argument, the long_opts table is looked up to find the appropriate
long version, then the parameter type is checked, and if the parameter
is supposed to be optional, the next command line token is examined to
determine if this is the optional parameter.
BRANCH=none
BUG=none
TEST=tried the following commands:
- tried the following commands:
./extra/usb_updater/gsctool -b # reports missing file name error
# All the following succeed processing command line parameters:
./extra/usb_updater/gsctool -m
./extra/usb_updater/gsctool -m enable
./extra/usb_updater/gsctool --tpm_mode enable
./extra/usb_updater/gsctool --tpm_mode=enable
# All the following fail processing command line parameters
# reporting 'Invalid tpm mode arg: xxx.':
./extra/usb_updater/gsctool -m xxx
./extra/usb_updater/gsctool --tpm_mode xxx
./extra/usb_updater/gsctool --tpm_mode=xxx
Change-Id: I68e9cc312aa8a5a2cccbd78df66a24ac71f78c36
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1621185
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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There are a couple of issues with command line processing code:
- command line options must be listed in two different places if we
want to allow both short and long forms of the same argument
- help text for commands is included in yet another place in the code
Indeed, from the libc getopt_long() point of view the long options
table and short options string are completely unrelated: the function
scans the command line arguments vector for -x[x[y]] or --word command
line options style and looks up either short_opts or long_opts
depending on the encountered command line token's style.
The standard way to cross reference long options table and the short
options string is to put the short option character in the long option
table's entries .val field. This is how it is done in gsctool.
What this means is that as long as all short command options are
referenced in the long_opts table, the short command option string
could be generated based no the long_opts table.
The help text and long_opts table would still remain separate and
require manual syncing.
To help with that problem this patch introduces a container structure,
which includes both long option contents and the help text for each
command line option.
This allows to build the long_opts table and then the short_opts
string on the fly, based on the contents of the single table, and also
generated the --help output, ensuring consistency of all
representations.
BRANCH=none
BUG=none
TEST=as follows:
- temporarily added debug code to print out the generated short
option string, got the following:
aBbcd:fF:hIikLMmn:O:oPpR:rS:stUuVvw
which is extended to include previously omitted 'f':
aBbcd:F:fhIikLMmn:O:oPpR:rS:stUuVvw
- verified that 'gsctool -h' outputs before and after this patch are
the same apart from including help text for -B
- verified that it is still possible to update a Cr50
- verified --board_id/-i command with various optional parameter
representations.
Change-Id: Ie8d409c6c8866247323cee93ce5b9bfbe22046fa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1617077
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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When running on a busy builder, fuzzing tests often time out.
I suspect this is due to the fact that one of the thread is busy
looping, and for some reason, does not give enough time for
other threads to run.
Fix the issue by using nanosleep OS call (avoiding namespace
clash with msleep/usleep that are implemented differently).
From the builder stack traces, we know these tests often
fail in 2 busy-loops, so fix those.
BRANCH=none
BUG=chromium:963768
TEST=Emulate busy system with 4 cores only:
taskset 0xf yes > /dev/null & (about ten times)
Then run tests:
while taskset 0xf build/host/usb_pd_fuzz/usb_pd_fuzz.exe \
-runs=1; do :; done
=> No failures after 30 minutes.
Change-Id: I458ff783d166e27fb38dc33853f08e5b3acba980
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1623050
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Manoj Gupta <manojgupta@chromium.org>
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Change drv_data pointer to st_private_data, to make LIS2MDL driver
compliant with other ST driver.
In standalone mode we have:
+--- lis2mdl_private_data ---+
| struct mag_cal_t cal; | <-------- LIS2MDL_CAL(s)
| | |
| struct stprivate_data data;| <-------- s->drv_data
+----------------------------+
BRANCH=None
BUG=b:132288982
TEST=Check scale returns 0.000625000
Checks figure-8 calibration is working
Checks CTS verifier test "Magnetic Field Measurements Tests" pass.
Change-Id: Iaba99b50cb0bf9bfc76f67cef0da8843a86f4838
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1616884
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
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When chipset power up to S5->S3 state set PD_EVENT_POWER_STATE_CHANGE,
pd task set mux usb mode whether c-port is attached or not.
If c-port is nothing attached at the setting moment,
then mux detects nothing and goes to low power state.
Plug-in type-c usb device, after debounce pass, we set mux usb
mode and mux responds i2C NAK (due to in low power mode).
This CL changes that do not connect MUX when PD disconnected.
For example ps8751 is used for mux case. When power up(S5->S3),
we should set mux none mode whether c-port is attached or not.
Once type-c usb device plug-in, after cc debounce pass, we
will set mux usb mode in X_DEBOUNCE_DISCONNECT state.
BRANCH=None
BUG=b:133196882
TEST=After console cmd reboot and reboot hard,
type-c usb device plug-in on ampton and
get type-c port status by "ectool usbpdmuxinfo".
Change-Id: Ia538af48c450e12af1438a6aa9a6e4e426e2f616
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1609262
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BUG=b:129159505
BRANCH=None
TEST=Ran Android CTS
Fixes event out of order errors in CTS.
This is fixed by doing the spreading on the ec. A new queue is
used (data_queue) and in place of the old call to
motion_sense_fifo_add_data we now add the event to the queue
and increment the sensor's sample count. At the caller
(load_fifo) we then figure out the window (time between the
last interrupt and the read) and the period by dividing the
window by the number of samples (this is done per sensor).
If the period is larger than the odr, then the odr is used
(this helps with accuracy). Events are now spread between the
known time the first entry was added and the read time.
Change-Id: I7094a719c76b4b08a758d053e5dfbdba0a30684b
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1620792
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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