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* servo: add usb_console to chrootNick Sanders2017-11-162-3/+29
| | | | | | | | | | | | | | add usb_console, console.py to chroot install. This tool allows directly accessing the usb console of servo v4, servo micro, cr50, etc. BUG=b:69016431 BRANCH=None TEST=usb_console -d 18d1:501b Change-Id: If9d5d49cf31d785ea9a7cec0a4eeeb34abae9cd1 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/773400
* servo_v4: disable USB3 interfaceNick Sanders2017-11-161-2/+5
| | | | | | | | | | | | | | | | This change switches the SS lines off in the main USB mux. There has been some general flakyness regarding USB3 peripherals and this change might address it. BUG=chromium:718075 BRANCH=None TEST=lsusb -t indicates 5000M before, 480M after. Change-Id: Id201fb20dc6489c4a071cb1c9c0624d7aa54652d Reviewed-on: https://chromium-review.googlesource.com/509130 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: meowth: Enable Vboot hash.Aseda Aboagye2017-11-161-0/+2
| | | | | | | | | | | | | | | | The hash calculation is needed for EC software sync. BUG=None BRANCH=None TEST=`make -j buildall` TEST=Flash zoombini, verify that hash is being calculated. Change-Id: Iddc65d5c0b04fa403b2fd5ace0096b029d5a6062 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772913 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: Toggle PP1800_U on startup/shutdown.Aseda Aboagye2017-11-161-2/+6
| | | | | | | | | | | | | | | | The enable for the PP1800_U rail needs to follow our transitions from S5->S3 and from S3->S5. BUG=b:69137449 BRANCH=None TEST=make -j buildall Change-Id: I2466f560b096eb0ad48d9c355de56d7aa775d9cc Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772912 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: Add battery pack information.Aseda Aboagye2017-11-161-0/+27
| | | | | | | | | | | | | BUG=b:69138843 BRANCH=None TEST=make -j buildall. Change-Id: Ia3aa76e03c7551dc34041631e8f8d1b16c1771e3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772911 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: Add support for meowth.Aseda Aboagye2017-11-161-1/+2
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=None Change-Id: Ib0c6b029c608ac361ed661249138589c99ea68b6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772910 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* jerry: Use HOSTCMD_ALIGNED instead of GPIO_SHORTNAMESFurquan Shaikh2017-11-161-1/+1
| | | | | | | | | | | | | | | This is required to allow bumping up of host events to 64-bit by making space in the rodata. CL 770923 had initially used GPIO_SHORTNAMES, but HOSTCMD_ALIGNED seems to be a better option. BUG=b:69329196 BRANCH=None TEST=make -j buildall Change-Id: I63699f9cec244925c031d81f50889851c6da8b5c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771931 Reviewed-by: Shawn N <shawnn@chromium.org>
* meowth: zoombini: Annotate ifdefs.Aseda Aboagye2017-11-165-27/+23
| | | | | | | | | | | | | | | | This commit just adds comments to the ifdefs introduced for BOARD_ZOOMBINI. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I036d18bc5b1fb4ebbf0943e630e4931c03b60aa5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/772909 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* tpm: do not prevent reading registers during pending resetVadim Bendebury2017-11-161-3/+0
| | | | | | | | | | | | | | | The host should be able to retrieve proper TPM status and ID registers while TPM reset is pending. BRANCH=cr50 BUG=b:68012381 TEST=after appropriate fixes in coreboot the firmware_Cr50ClearTPMOwner autotest does not fail any more Change-Id: I245656ccb1c05e46715deb18bd5f8985c4197c52 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/775281 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* kevin: Claim some more space by disabling some configsFurquan Shaikh2017-11-161-2/+3
| | | | | | | | | | | | | | Disable ACCELSPOOF and FLASHINFO to save some space. This is required to support 64-bit host events. BUG=b:69329196 BRANCH=None TEST=make -j buildall Change-Id: I364adb1e224c2084398b4ee5bb9fd24a1c542e0e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771997 Reviewed-by: Shawn N <shawnn@chromium.org>
* nautilus: Replace anx74xx with another ps8xxxPhilip Chen2017-11-154-78/+14
| | | | | | | | | | | | | | | | | | | On Nautilus, we use two ps8751b TCPC chips. According to the latest schematic (link is in the bug), we'll place two TCPC chips separately on different I2C ports. BUG=b:69017605 BRANCH=none TEST=build/flash nautilus rev0, and confirm PD charging from one USB-C port works. Change-Id: Iab7402023f148d478cba249aaf83a23675a7137b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/758336 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Meowth: Added initial board file.Rachel Nancollas2017-11-157-13/+216
| | | | | | | | | | | | | | | | | | | Created Meowth symbolic link to Zoombini. Modified Zoombini gpio.inc and board, etc. files to compile a Meowth EC image with the correct gpios. BUG=b:69133424 BRANCH=none TEST=make BOARD=meowth and BOARD=zoombini runs with no errors Change-Id: Ib34d956efa89ae125de1ce7f8799162c74df0122 Signed-off-by: Rachel Nancollas <rachelsn@google.com> Reviewed-on: https://chromium-review.googlesource.com/762039 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32f0: i2c: Fix dropped Rx byte in TCPCI slave modeShawn Nematbakhsh2017-11-151-5/+5
| | | | | | | | | | | | | | | | | | | If the i2c master sends a stop condition before we've buffered the last Rx byte (eg. due to higher than normal i2c interrupt latency) then we don't want to drop the last byte on the floor, it's still meaningful. BUG=b:65711378 BRANCH=glados TEST=Spam TCPC_REG_ROLE_CTRL commands from caroline to caroline_pd, verify no errors are observed on either side for 12,000,000 transactions. Change-Id: I0c4a81d97315cff553a5448c0940746e1ef0ed2c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771936 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy: Lower sensor max ODRGwendal Grignou2017-11-152-2/+11
| | | | | | | | | | | | | | | | EC seems to miss sample while providing sensor data at 200Hz. Limit sensors ODR to 100Hz. BUG=b:67112751 BRANCH=none TEST=compile, tbd Change-Id: Ic324c3d989854ae8b7f6b27bf6338266ce01ceda Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753434 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: prepare to release 0.0.26Vadim Bendebury2017-11-152-2/+2
| | | | | | | | | | | | | | The new release will include fixes for SPI problems discovered when debugging Fizz. BRANCH=cr50 BUG=none TEST=none Change-Id: I4ac2ab762ec86957a7555b0aaa41235f44a54d47 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/772738 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* nautilus: Update battery profilePhilip Chen2017-11-151-10/+15
| | | | | | | | | | | | | | | | | Update battery.c according to the battery datasheet (The link is in the bug). BUG=b:69016914 BRANCH=none TEST=boot Nautilus with battery, and confirm EC doesn't complain about critical battery state anymore. Change-Id: I024f61e4a4119b7a3d5c0f3b1de56c591af2ae5d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/757892 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* system: Add wait-ext option to ec reboot commandScott Collyer2017-11-153-16/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | EC_IN_RW signal is used to determine if the switch to dev mode can be safely made. However, EC_IN_RW needs the EC_RST_L line driven low in order to be reset. In faft tests that utilize crosEcSoftrecPower method, EC_RST_L is not being driven by servo to fix other test failures related to keeping EC and AC reboots in sync. This CL adds a new argument 'wait-ext' to the EC reboot command. When this option is used, instead of the EC generating a reset via it's system watchdog, it will wait 10 seconds for EC_RST_L to be driven. BUG=b:64603944 BRANCH=coral CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode" mutliple times and verified that it passes. Previoulsy, this test always fails when the EC is in RW before it starts. Also tested platform_ServoPowerStateController_USBPluggedin and verified it passed. Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/737524 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Change the way host_set_single_event is usedFurquan Shaikh2017-11-151-2/+5
| | | | | | | | | | | | | | | | | In order to avoid runtime 64-bit left shift, check for extpower and add two separate calls to host_set_single_event rather than calculating the parameter at runtime. This avoids the requirement of runtime logical shift for 64-bit. BUG=b:69329196 BRANCH=None TEST=make -j BOARD=samus Change-Id: I64cacf6253878ed7d69f6b17baeb6c27c470378a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771854 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_updater: allow differing console enpointsNick Sanders2017-11-153-4/+8
| | | | | | | | | | | | | | | servo_micro has the console on intf 3, while servo_v4 has it's console on intf 0. Abstract this into the config file rather than hardcoding. BUG=b:37513705 BRANCH=None TEST=update servo_micro Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I0090a0d081e001e62ffa7235eebbd6131ea00dcf Reviewed-on: https://chromium-review.googlesource.com/769794 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "poppy/nautilus: Move pmic vr decay enable/disable to suspend/resume ↵Furquan Shaikh2017-11-152-4/+16
| | | | | | | | | | | | | | | | | | | | hooks" This reverts commit 1f767e3e91be388dee689ac85408dfb5e3414581. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall. Verified by adding prints that VR decay enable happens before SLP_S0# is asserted. Change-Id: I0353f70c65ebe673b0e1b5ddbae2bb04368308cc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771055 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Revert "power: Get rid of power_board_handle_host_sleep_event"Furquan Shaikh2017-11-152-1/+19
| | | | | | | | | | | | | | | | | This reverts commit 352276235ca18404a42ca01b75de3fdc7951e271. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall Change-Id: I6885e7447277d853a2414be299dfea25f5547df4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771054 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* jerry: Enable CONFIG_COMMON_GPIO_SHORTNAMESFurquan Shaikh2017-11-151-0/+2
| | | | | | | | | | | | | Turn on CONFIG_COMMON_GPIO_SHORTNAMES to save some space in rodata. BUG=b:69329196 BRANCH=None TEST=make -j BOARD=jerry Change-Id: Ib1e4cb13c013cce7b0d6422b842ca47c0f4ff62c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770923 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32: jtag: Enable clock to debug module on stm32f0xMoritz Fischer2017-11-152-0/+4
| | | | | | | | | | | | | | | Enables the clock to the debug module so that when connecting via SWD debugger the watchdog and timers are stopped. BRANCH=master TEST=Build on stm32f0x board and connect via SWD, observe no watchdog reset. Change-Id: Ic40b16c09acc5920da2c1a39e9391a6b21849d2c Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: https://chromium-review.googlesource.com/765290 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: add espi moduleDino Li2017-11-1411-2/+514
| | | | | | | | | | | | | | | | | | Add espi control module for it83xx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell. 2. console command "kbpress 1 4" to test keyboard data. (board code for espi module test on CL:392587) Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d Reviewed-on: https://chromium-review.googlesource.com/394471 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec-devutils: install servo tools to chrootNick Sanders2017-11-141-0/+42
| | | | | | | | | | | | | | | | | | | This adds "servo_updater", "powerlog", "ecusb" library into the chroot's python install, as well as configs for servo_v4 and servo_micro. This allows easier access to these tools. servo_updater and powerlog are installed in the default path. /usr/share/servo_updater/configs contains the servo config files. BUG=b:69016431 BRANCH=None TEST=sudo servo_updater -b /../servo_v4.json -f servo_v4_9040.0.0.bin powerlog -b marlin.board -c marlin_common.scenario Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I0b3f1b16fcd422297af88c236a2a4ddb2cc25819 Reviewed-on: https://chromium-review.googlesource.com/767547 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* PS8751 and PS8805 does not generate BIST Carrier Mode 2Sam Hurst2017-11-142-1/+47
| | | | | | | | | | | | | | | | | On Nasher, sending TCPC_TX_BIST_MODE_2 to register 0x50 on the PS8751 TCPC does not generate BIST Carrier Mode 2. BUG=b:68337231 BRANCH=None TEST=`make -j buildall` Generated an eye diagram for Nasher on the GRL USB-PD test station Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: Ia6e5df54a183c989a68d12be3a46896e3daea738 Reviewed-on: https://chromium-review.googlesource.com/741090 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* grunt: Initial GPIO setup for gruntEdward Hill2017-11-146-959/+170
| | | | | | | | | | | | | | | | Configure GPIOs to match grunt proto v1.1 schematic. Change EC chip to npcx7m6f. Minimal board.c/h, just enough to build. BUG=b:64935726 BRANCH=none TEST=make BOARD=grunt Change-Id: I1a1f581c7ee7b80808c0dde179bc3ee0d69f960e Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/754302 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* scarlet: Remove barometer bmp280Philip Chen2017-11-143-46/+0
| | | | | | | | | | | | | BUG=b:69011927 BRANCH=none TEST=manually boot Dru and verify no complaint about baro init failure Change-Id: I35fd5636ac833bad81ce91969cdf94a79833486f Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/757938 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Use compatible MPU configShawn Nematbakhsh2017-11-142-48/+7
| | | | | | | | | | | | | | | | MPU is already configured for access restriction in cortex-m core code so take care not to conflict. BUG=chromium:782244 BRANCH=None TEST=Build + boot on kevin, verify hibernate doesn't panic. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9903cbc69002529ebbfa3fc1be3de4f74264e4aa Reviewed-on: https://chromium-review.googlesource.com/759157 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cortex-m: mpu: Support unaligned regions and protect code RAMShawn Nematbakhsh2017-11-144-60/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support protection of regions that aren't aligned to a power of 2 by using two MPU entries, and taking advantage of the sub-region feature. Also protect code RAM from being overwritten, on parts that use external storage. BUG=chromium:782244 BRANCH=None TEST=On kevin, call: mpu_protect_data_ram(); mpu_protect_code_ram(); mpu_enable(); Verify that first call results in the following update_region params: addr: 0x200c2000 size: 0xc01d Decoded: Protect 24K region Verify that second call results in the following params: addr: 0x100a8000 size: 0xc021 Decoded: Protect 96K region addr: 0x100c0000 size: 0xf01b Decoded: Protect remaining 8K region Also verify that writes to beginning and end of code ram region trigger data access violation after enabling protection. Also verify that sysjump fails. Change-Id: Ieb7a4ec3a089e8a2d29f231e1e3acf2e78e560a1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/757721 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* nautilus: Change USB_C{0,1}_PD_RST_L to be GPIO_ODR_HIGHFurquan Shaikh2017-11-141-2/+2
| | | | | | | | | | | | | | | Similar to coral and poppy/soraka devices, configure USB_C{0,1}_PD_RST_L to be GPIO_ODR_HIGH since nautilus uses parade TCPC on both ports. BUG=b:69198785 BRANCH=None TEST=make -j BOARD=nautilus Change-Id: If76cf0588744b3adcfd75f4e2ebe0ea9e721683d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767071 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* poppy/soraka: Change USB_C1_PD_RST_L to be GPIO_ODR_HIGHFurquan Shaikh2017-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reference CL: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/762066 The reset line for the parade TCPC on port 1, has an external 1k pull up resistor. However, the gpio.inc description for this line was set to OUT_LOW which results in a short reset pulse. This can lead to an external charger seeing an unattach event and dropping VBUS. On Soraka systems with certain chargers this results in a continuous reboot loop when no battery is connected. Changing the default state of this line to ODR_HIGH prevents reset from being pulled low until the EC is intializing the TCPC and fixes the continous reboot loop issue when no battery is connected. BUG=b:69198785 BRANCH=None TEST=On a Soraka system, verified that connecting Lenovo Type C charger on Parade port did not result in reboot loop when no battery is connected. Earlier this same setup resulted in continuous reboot loop. Change-Id: I5138e129431ee4f0c1c6ceaaac5ab288c3ab6233 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767070 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* usb_updater2: Add support for touchpad debugging featureNicolas Boichat2017-11-141-16/+61
| | | | | | | | | | | | | | Add support for touchpad debugging in usb_updater2, allowing an arbitrary parameter to be passed. BRANCH=none BUG=b:63993891 TEST=./usb_updater2 -g 00 -d 18d1:502b Change-Id: I1242e3bab9dc69ec3a92dd158c85606211e40f21 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/763575 Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
* usb_update: Add support for touchpad debugging featureNicolas Boichat2017-11-143-0/+50
| | | | | | | | | | | | | | | | We support touchpad-specific debugging feature over the USB update protocol. This will be used to fetch raw data from the sensor, without requiring to remove the write-protect screw. BRANCH=none BUG=b:63993891 TEST=./usb_updater2 -g 00 -d 18d1:502b Change-Id: I46dfd97aaa17b73a5893fe1e8c62327a302f829b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/763574 Reviewed-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rainier: add rainier support for flash_ecEge Mihmanli2017-11-141-0/+1
| | | | | | | | | | | | | BUG=chromium:776441 BRANCH=none TEST=Run "./flash_ec --board=rainier" from ec/util directory and make sure there is no error "board rainier not supported" on stderr. Signed-off-by: egemih@chromium.org Change-Id: I4b4b714962685d0b33d3b9aa4c96b5a89eb566c5 Reviewed-on: https://chromium-review.googlesource.com/767589 Commit-Ready: Ege Mihmanli <egemih@google.com> Tested-by: Ege Mihmanli <egemih@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: Set default input ILIM to 128 mA.Aseda Aboagye2017-11-141-1/+1
| | | | | | | | | | | | | | | The charger can regulate around 128 mA reasonably. BUG=b:67120928 BRANCH=None TEST=make -j buildall Change-Id: I8e4b37dd3d95fa55cf76a686a32a378daa398d80 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/759956 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* isl9238: Don't reread PROG pin or reload ILIM.Aseda Aboagye2017-11-142-0/+24
| | | | | | | | | | | | | | | | | | | | | | | The ISL9238 has a functionality where it will reload the adapter current limit from a strap which is read from the PROG pin. This is problematic when we decide to set the current limit prior to AC actually being inserted. This commit disables this functionality from the charger. It seems however that the charger will read the PROG pin and reload the ILIM at least once before respecting the bits. BUG=b:67120928, b:66017697 BRANCH=None TEST=Plug and unplug and then plug again AC. Verify that the default current limit is not set by the charger automatically. Change-Id: Ia8e8742843f6ceb286635b31e0fe5c070a2b6dfe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/759693 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Shamile Khan <shamile.khan@intel.corp-partner.google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* isl923x: Change charger_post_init().Aseda Aboagye2017-11-141-28/+41
| | | | | | | | | | | | | | | | | | | The ISL9237/8 can both be powered by VSYS or AC, therefore, it's not needed to reinitialize the charger after AC is present. This commit moves the contents of charger_post_init() into a new init function that will be run once at HOOK_INIT time. BUG=b:67964166 BRANCH=None TEST=make -j buildall Change-Id: I637b1209f86f686013fee0783914fa1596076fa6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/759692 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* isl9238: Raise min input voltage limit.Aseda Aboagye2017-11-132-1/+15
| | | | | | | | | | | | | | | | | | | | The ISL9238 has functionality for a input voltage regulation loop. By default, the regulation reference voltage is set to 4096mV, however we can be kinder to chargers by raising this regulation reference. In testing, there appears to be insignificant change in current pulled at the higher limit. BUG=b:67964166 BRANCH=None TEST=Flash a board with a ISL9238, verify that 0x4b reads as 0x0d00. TEST=make -j buildall Change-Id: I920c4b922106fca3001f2759cad0479a368f735b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/745527 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fizz: Switch power source to BJ at G3/S5Daisuke Nojiri2017-11-134-8/+45
| | | | | | | | | | | | | | | | | | | | | | | | This patch allows Fizz to switch the power source from a type-c charger to a barrel jack adapter if the system is in S5. BUG=b:38321259 BRANCH=none TEST=Verify the following with 45W and 60W type-c chargers: 1. Boot Fizz with a type-c charger 2. Go to S5 if not already. 3. Plug in a BJ adapter. Fizz boots to S0 using BJ power. Also verified other boot modes are not affected: 1. Auto boot on BJ insert 2. Auto boot on Type-C insert 3. Recovery boot on BJ 4. Recovery boot on Type-C 5. Stay off if it's previously S5 Change-Id: I86aa0fe6e403bcbacfe396997d897111ffcf8e74 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/706251 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pi3usb9281: sync USB switch hardware control with switch stateRong Chang2017-11-131-0/+3
| | | | | | | | | | | | | | | | | When sysjump to another image, if USB switch state and HW switch control are not sychronized, the switch can be left in open state. This CL resets USB switch on init to close USB. BRANCH=oak BUG=b:36234142 TEST=manual plug BC1.2 charger, sysjump to another EC image and unplug the chager. check pi3usb9281 control register(02h) bit2 == 1. Change-Id: Iaadfaf51064ed1508271e974b9caf88b96bbe008 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/502835 Reviewed-by: Shawn N <shawnn@chromium.org>
* coral: Change GPIO_USB_C1_PD_RST_ODL to be ODR_HIGHScott Collyer2017-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The reset line for the parade TCPC on port 1, has an external 1k pull up resistor. However, the gpio.inc description for this line was set to ODR_LOW which results in a short reset pulse. This can lead to an external charger seeing an unattach event and dropping VBUS. On some Coral systems with certain chargers this results in a continuous reboot loop when no battery is connected. Changing the default state of this line to ODR_HIGH prevents reset from being pulled low until the EC is intializing the TCPC and fixes the continous reboot loop issue when no battery is connected. BUG=b:68226308 BRANCH=coral TEST=Using Robo system tested with the Lenovo Type C charger and verified that the system can boot up without a battery when connected to port 1. Bitland also verified this change in their test setup and found no failures. Change-Id: Ia16fe8cf770dc91da479497d234a2b6f9679b878 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/762066 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ectool: Print temperature unit in ectool temps outputNicolas Boichat2017-11-111-2/+2
| | | | | | | | | | | | | | | | | Currently, 'ectool temps all|<n>' just prints "300". This may easily be mistakenly read as tenth of degree C (30.0 C), as the value appears to make sense (close to room temperature). However, the value is actually 300 K (27 C). CQ-DEPEND=CL:763578 BRANCH=none BUG=chromium:783845 TEST=ectool temps all shows temperature unit (K) Change-Id: I70f7f04d061cb1d4f741d59f8b48c7963dd8280f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/763996 Reviewed-by: Shawn N <shawnn@chromium.org>
* keyboard_mkbp: Fix FIFO lockingShawn Nematbakhsh2017-11-101-7/+33
| | | | | | | | | | | | | | | | | | keyboard_clear_buffer() should not trash FIFO contents without synchronization from fifo_add() / fifo_remove(), otherwise a bad FIFO state may ensue. BUG=chromium:781554 BRANCH=gru TEST=Verify KB is functional on kevin through suspend / resume, verify keyboard functions as S3 wake. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5d28c72359f6e1ce8778725a15c51cdfcd8ab90b Reviewed-on: https://chromium-review.googlesource.com/761300 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* glkrvp: Allow system to boot using DC JackVijay Hiremath2017-11-104-19/+103
| | | | | | | | | | | | | | | | | | | | | There are two Type-C ports and a DC Jack on GLKRVP. Added code to allow system to boot from DC Jack also. This helps to boot the device without Type-C connector during early stage of software development. BUG=b:69005234 BRANCH=glkrvp TEST=GLKRVP can boot to OS without battery and DC Jack attached. Also VBATA is set to battery voltage max. When DC-Jack is present Type-C port is not enabled and vice-versa. Change-Id: I0fe5631c40490c56fba6ed5f3ad7ba7f5248460a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/757874 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* nds32: use coreboot-sdk as the default toolchain for local buildDino Li2017-11-101-1/+4
| | | | | | | | | | | | | | | | | | | With this change, we can pass "make buildall" at local after it83xx based boards were removed from skip_boards. BRANCH=none BUG=none TEST=- Passed "make buildall -j" - CROSS_COMPILE_nds32=nds32le-cros-elf- make BOARD=it83xx_evb -j, build ec image by using nds32le-cros-elf toolchain. - make BOARD=it83xx_evb -j, coreboot-sdk is used. Change-Id: I689b67ed50ac5c80e7526f157ba28733d7216e14 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/762807 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* npcx: fixed the assembly code of deep idle bypassCHLin2017-11-092-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original assembly code of deep sleep bypass will cause build error if both CONFIG_LOW_POWER_IDLE and CONFIG_LTO are defined when buildiing board glkrvp/zoombini. This CL fixed it by change the bypass assembly code from: asm ("push {r0-r5}\n" "ldr r0, =0x100A8000\n" "wfi\n" "ldm r0, {r0-r5}\n" "pop {r0-r5}\n" "isb\n" ); to: asm ("push {r0-r5}\n" "wfi\n" "ldm %0, {r0-r5}\n" "pop {r0-r5}\n" "isb\n" :: "r" (0x100A8000) ); BRANCH=none BUG=none TEST=No build errors for "make buildall". TEST=build zoombini/glkrvp with CONFIG_LOW_POWER_IDLE and CONFIG_LTO, no build errors. TEST=build npcx7_evb/npcx_evb and do stress test for deep idle->wakeup on EVB, no symptom observed. Change-Id: I90b13b4baf418e3f4b3234d4811e3978b6436aac Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/756535 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* poppy/soraka: set attenuation_factor of opt3001 to 1.Marco Chen2017-11-091-2/+6
| | | | | | | | | | | | | | | | attenuation_factor is set to 1 because there is a calibration in iio framework of kernel already which would be configured in the factory flow. BRANCH=None BUG=b:69025351 TEST=Manually test on the DUT to make sure there is no additional factor applied to raw data. Change-Id: I25c5a3b341573bb82828164d3243f9adbac05372 Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/759765 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* sweetberry: save to specified directoryMengqi Guo2017-11-092-46/+105
| | | | | | | | | | | | | | | | | | | | | | This CL modifies the 2 flags --save_stats and --save_raw_data so that they can take arguments to save the corresponding file into directories that we specify. It also provides a new flag --no_print_raw_data to suppress printing sweetberry readings in real time. This CL is part of the effort to start sweetberry measurements while running power autotests. BRANCH=None BUG=b:68956240 TEST=./powerlog.py -b xxx.board -c xxx.scenario \ --save_stats ./xxx --save_raw_data ./xxx --no_print_raw_data Change-Id: I01ebeafc5f4eebd0a77746e9968367f267e93d83 Signed-off-by: Mengqi Guo <mqg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/756255 Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* gru: Remove `flashinfo` command for RAM savingsShawn Nematbakhsh2017-11-093-0/+4
| | | | | | | | | | | | | BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ibfbb6875327dfc13dcba57933d39fd207f382ac1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/761299 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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