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* Fizz: Show critical error on LED for recovery requestDaisuke Nojiri2017-09-293-2/+12
| | | | | | | | | | | | | | | | Fizz EC verifies RW by itself and jumps to RW before AP boots. If this fails, the system needs recovery. Since EC isn't capable of showing any info on a display, we use the power LED to inform the user. BUG=b:66914368 BRANCH=none TEST=Make Fizz fail RW verification. Observe LED illuminates in red. Change-Id: Ia07de60a316b40e74b1917903996d78750b4ae43 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/683218
* Fizz: Blink LED to request more powerDaisuke Nojiri2017-09-294-17/+39
| | | | | | | | | | | | | | | | | | This patch makes the LED blink to alert the user when there is not enough power to boot the system. This patch also changes minimum boot power to 50W. It's common for all SKUs. BUG=b:37646390 BRANCH=none TEST=Power Fizz with 15W, 45W, 60W chargers. Verify LED blinks as expected. Change-Id: If269897f5022f6cba80f37ce03e2315cfb2cf504 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/682876 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rma_reset: hide generated files from gitVadim Bendebury2017-09-281-0/+5
| | | | | | | | | | | | | | | | | This prevents the files from showing in 'git status' output. BRANCH=none BUG=none TEST=verify that the running the following does not show any generated files: make -C extra/rma_reset; git status Change-Id: Ib3ff7772cf4a66e4a0d23ed859c30ac05c2e507d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/691016 Reviewed-by: Michael Tang <ntang@chromium.org>
* it83xx: gpio: remove 5.1K resistor connected to GND of CC pinsDino Li2017-09-281-0/+7
| | | | | | | | | | | | | | | | If we don't use IT8320's PD module, we should dis-connect resistor to GND and disable CC related function to make sure these pins can work as other function. BRANCH=none BUG=none TEST=CCCSR register setting is 0xff after initialization if we don't enable CONFIG_USB_PD_TCPM_ITE83XX. Change-Id: I97e019ec1c9c852cd758b364a5e7913de1fc84f4 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/689435 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* board: reef_it8320: Report device orientation isn't tablet modeDino Li2017-09-282-0/+12
| | | | | | | | | | | | | | | We need to response EC ACPI device orientation command or keyboard/trackpad didn't work on OS image version R58 and after. BRANCH=none BUG=none TEST=keyboard and trackpad work on R58 and after. Change-Id: I49f9c90e73a5e529eb228169e4148f4dcd4a45e6 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/689715 Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_v4: add pd commandsNick Sanders2017-09-281-0/+1
| | | | | | | | | | | | | | Add CONFIG_CMD_PD into servo v4, to enable more console PD commands, BRANCH=None BUG=b:65497998 TEST=run the sommands. Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I85c3f585779ccd51cff48c564083fd42fe5c454b Reviewed-on: https://chromium-review.googlesource.com/663840 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* npcx: espi: Fixed the bug which ec cannot enter deep sleep on npcx7.Mulin Chao2017-09-281-0/+8
| | | | | | | | | | | | | | | | | | | In npcx7, we introduced a new bit, VWUPDW, in ESPISTS register to indicate a Master-to-Slave VW signal was updated and the relevant WE bit is 1. But there's no relevant IE bit in ESPIIE for VWUPDW, old mechanism for clearing pending bits of ESPISTS will ignore this bit. And ec cannot enter deep sleep anymore since this bit is set. This CL fixed this bug by setting bit 17 of mask variable if ec is npcx7 series. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Change-Id: I80c57d3c230e9d06ba134538ccdcd29f290bb7bf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/672183 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
* npcx: espi: Add new bit fields of eSPI regs and remove useless ones.Mulin Chao2017-09-281-36/+71
| | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we introduced new bit fields of eSPI registers on npcx5/7 for the incoming patches. We also remove useless registers such as VWGPMS, VWGPSM and PING in order to let the driver look more clearly. This CL also includes: 1. Fixed typo from ESPIIWE to ESPIWE. 2. Introduce ESPIWE bits fields on npcx5/7. 3. Introduce new bit fields in ESPISTS of npcx7. 4. Remove useless VW1-4, VW1IE1-4 bits in ESPISTS and ESPIIE registes. 5. Introduce new bit field, WE, in VWEVMSn register of npcx7. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c 1000" to do stress test and no symptom occurred on poppy. Both warmboot and coldboot stress test for 3 hours and no symptom occurred on poppy. Change-Id: Ie8aa3dbd148588b0d9a756572d66604a6836a760 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/672026 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
* tigertool: add serial number checkNick Sanders2017-09-281-0/+24
| | | | | | | | | | | | | Add --check_serial to check serial number. BRANCH=None BUG=b:35849284 TEST=check serial number. Change-Id: I1e2d5617bcf65e2388b88aca7ed63b9cdc096d87 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/676723 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* chip/stm32/clock: Wakeup AP when rtc alarm goes offPhilip Chen2017-09-282-0/+21
| | | | | | | | | | | | | | BUG=b:63908519 BRANCH=none TEST='powerd_dbus_suspend --wakeup_timeout=10' and see AP do S0->S3(10 secs)->S0 Change-Id: I35e248627e2f3b68b0ed3f27d6bae65eb73a745b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/674054 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charge_manager: Support no-BC1.2 configurationShawn Nematbakhsh2017-09-285-33/+12
| | | | | | | | | | | | | | | | If BC1.2 isn't supported, don't waste space + time checking for inputs that don't exist. BUG=chromium:759880 BRANCH=None TEST=`make buildall -j` Change-Id: I47e81451abd79a67a666d1859faf2610ee5c941a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/663838 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* poppy: cleanup GPIOsNicolas Boichat2017-09-283-21/+0
| | | | | | | | | | | | | | - Deprecate poppy rev0. - Remove FP_INT_L BRANCH=none BUG=b:65104436 TEST=make buildall -j Change-Id: Ie2afae95a4fed43e8c2dc9e18031cf3e82eb3536 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/689817 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* chip/stm32/clock: Incorporate RTC date registerPhilip Chen2017-09-276-93/+177
| | | | | | | | | | | | | | | | | | | | | | | The current stm32 rtc driver only uses RTC_TR and RTC_SSR. So we son't be able to use rtc for applications which need time > 24 hours. To support such applications, this patch adds operations for RTC date register (RTC_DR). BUG=b:63908519 CQ-DEPEND=CL:666985 BRANCH=none TEST=manually with 'ectool rtcset/rtcset' and '/sys/class/rtc/rtc0', verify the conversion between calendar time and Unix epoch time works. Change-Id: Iacd5468502e4417a70880d7239ca5e03353d9469 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/659337 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* vboot: Modify the parameter offsetJagadish Krishnamoorthy2017-09-272-1/+6
| | | | | | | | | | | | | | | | | For the Host Command vboot hash EC_VBOOT_HASH_GET case, if the input parameter offset and size is 0 then change offset to data_offset to obtain the latest hash value. Else retain the offset to get the hash value at offset. BUG=b:66957716 BRANCH=NONE TEST=On Soraka, ectool echash commands (RO, RW) should result in hash information. Change-Id: Ife17d35b0dfeecb5ec799c9ed722ae48dbec5b5b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/685738 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* scarlet: enable console help and historyBrian Norris2017-09-271-2/+0
| | | | | | | | | | | | | | | We're not hurting for flash space. And this helps us stupid kernel developers, who haven't memorized all EC commands. BUG=none BRANCH=none TEST=build and boot scarlet Change-Id: I9046ff3802512d24f17acffa7e0b2faddb702c0b Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/688506 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: compress array of prime deltasVadim Bendebury2017-09-271-273/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The array storing deltas between sequential prime numbers could be compressed, as the vast majority of the values in the array does not require more than 4 buts to store. The new storage format is as follows: - each differential value (difference between two consecutive primes) is halved and stored in 4 bits, two halved values are packed per byte. - I the first one of of the two sequential halved values exceeds 0xf, it is stored in the array followed by a zero, stored as is (without halving), thus taking two bytes. - if the second one of the two sequential halved values exceeds 0xf, both values are stored in the array as is, both prepended by zeros, thus taking 4 bytes. The code calculating the sequential primes parses the array according to this format. Storing the primes in this format allows to shave from the image size 1848 bytes. BRANCH=cr50 BUG=b:65253310, b:65287300 TEST=verified that test_rsa test from the tpmtest suite passes. verified that the list of prime numbers printed out when PRINT_PRIMES is defined and test_rsa is ran is the same before and after this patch. Change-Id: Ifdc2858a48f868ef816ccb4e351d9f60703d16e7 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/664253 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Coral: Add LG battery for Santa and Porbeagle.david.huang2017-09-271-6/+87
| | | | | | | | | | | | | | | | | | | 1.Add LG battery for Santa and Porbeagle. 2.Santa LG battery manufacture name is same as BATTERY_LGC011, so use device name to recoginze Santa LG battery. 3.These two battery have different process to get FET status, make sure battery not use this process is before BATTERY_LGC15 to separate these two different process. BRANCH=none BUG=b:65426428, b:64772598 TEST=Make sure battery can cutoff by console "cutoff" or "ectool cutoff" and resume by plug in adapter. Change-Id: I7095b9d0915fb4d39aa6c9f8c8751aa22941e938 Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/674472 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Fizz: Set proper max powerDaisuke Nojiri2017-09-261-1/+2
| | | | | | | | | | | | | | | | This patch raises the max power for a type-c adapter to 60W (20V @3A). We can't go above the regular cable capacity (3A) until we add e-marked cable detection. BUG=none BRANCH=none TEST=Boot Proto3 on Zinger. Observe 60W (20V @3A) is selected. Change-Id: I9670d710e363c7db1136a7ce7a7f8401b0ad8240 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679210 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: i2c: remove instructions that aren't necessaryDino Li2017-09-262-227/+93
| | | | | | | | | | | | | | | | | | | | | | - To i2c channel(d/e/f), we remove instructions that aren't necessary. - Changes of i2c_reset(): Before the change, we try to send a START/STOP bit if we get a reset. But i2c_unwedge() already done it, so we just need reset i2c module in i2c_reset(). - Add enhanced_i2c_start() to channel(d/e/f) for each transaction start: We prepare transaction start by calling i2c_reset(), but this doesn't match the definition of i2c_reset(), so we correct it. BRANCH=none BUG=none TEST=1. console commands: "i2cscan", "charger" and "battery". 2. sensors, battery, charger and mux work on reef_it8320. Change-Id: I4e3595479e04a5994a5b19409cfc4e9a46f63d4f Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/674467 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7_evb: change the default setting of npcx7 evbCHLin2017-09-262-1/+7
| | | | | | | | | | | | | | | | | | | | | In this CL, we add the follow changes for npcx7 evb board: 1. Add comments in the build.mk to indicate how to set CHIP_VARIANT for EVBs which use different npcx7 ec. - npcx7m6f : 144 pins (default) - npcx7m6g : 128 pins 2. Turn on the eSPI host interface as default in board.h BRANCH=none BUG=none TEST=No build errors for "make buildall". Change-Id: Ib926e8596a09a28f547c35a0256be2aa394f9a36 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/674887 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rtc: Add functions and tests for time conversionPhilip Chen2017-09-267-0/+240
| | | | | | | | | | | | | | | | | | | | | To implement rtc driver for some ec chips, we need to convert between calandar date and seconds (since epoch time, 01-01-1970 00:00:00). Sicne these functions are HW-independent, let's add common/rtc.c, include/rtc.h, and unit test for this. BUG=b:63908519 BRANCH=none TEST=make buildall test -j Change-Id: Icb1e768d2b3674d5225b83e09475e984eb104d06 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/666985 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* g: Provide a pinhold interfaceNadim Taha2017-09-272-1/+36
| | | | | | | | | | | | | | | This change is required to reboot the chip without bringing down the entire platform on boards where GPIOs are wired to external active reset signals. BRANCH=none BUG=none TEST=Scoped a pin across a reset. Change-Id: I58d93697d39a8adcdac9324d5dd9da00745aec9a Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/644179 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: dcrypto: add debug function to print primesVadim Bendebury2017-09-261-0/+26
| | | | | | | | | | | | | | When compilation is enabled, this function prints all prime numbers generated using the PRIME_DELTAS array. BRANCH=cr50 BUG=none TEST=verified that prime numbers are printed out when running rsa_test.py Change-Id: I37961aad146c4aeecca9a84550f313450e6c5853 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/683074 Reviewed-by: Shawn N <shawnn@chromium.org>
* tpmtest: make the test work againVadim Bendebury2017-09-264-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TPM test directory has bitrotted and does not compile any more, leave alone pass tests. This patch updates the tests to match changed EC codebase: test/tpm_test/Makefile - look for include files in more directories test/tpm_test/bn_test.c - add implementation of always_memset() which for the EC tree now comes from a different tree and provide a plug for watchdog_reload() which is no used by dcrypto code (which in fact is not a good idea, but an issue for another day). test/tpm_test/hash_test.py - update to match new format of return messages test/tpm_test/upgrade_test.py - update to match the new format of return messages and limit the test to installing just 2K worth of data BRANCH=cr50 BUG=none TEST=./test/tpmtest/tpmtest.py now passes Change-Id: Ibcd7fcfba06cd83023e35a2ac4f37ec896492ad4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/665322 Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: fix hash test code memory managementVadim Bendebury2017-09-261-6/+18
| | | | | | | | | | | | | | | | | | | The hash test code memory management is somewhat loose: it does not clean up allocated buffer, but then uses it to check for presence of the previously created handles, which can result in false positives. Let's zero the buffer each time it is allocated and let's use hash_test_db.contexts as the indicator if the buffer is allocated or not. BRANCH=cr50 BUG=none TEST=ran ./test/tpm_test/tpmtest.py, observed rsa tests pass. Change-Id: Iad4b4e2662fc7266ee6f556f6ddfd0051e7172d7 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/665321 Reviewed-by: Shawn N <shawnn@chromium.org>
* samus_pd: Adjust input current limit downward to prevent OCShawn Nematbakhsh2017-09-261-5/+2
| | | | | | | | | | | | | | | | | | | | | | Based on measurements, Samus can pull more current than desired, even taking into account the existing INPUT_CURRENT_LIMIT_OFFSET_MA adjustment. Decrease the programmed current limit by an additional factor, determined by taking the worst-case power measurements across 15 different Samus devices, to ensure that Samus never pulls more current than desired. BUG=chrome-os-partner:55297 BRANCH=samus TEST=Verify with debug prints that curr_lim_ma becomes 256 when negotiated current limit is 500mA and curr_lim_ma becomes 2556 when negotiated limit is 3000mA. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6912d987c5a519f55a831698873a69c4cac817b8 Reviewed-on: https://chromium-review.googlesource.com/684696 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Kahlee: Provide functionality for apshutdownAkshu Agrawal2017-09-261-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trigger the power press for shutdown. Also, avoid powering up the AP by checking if we are not in G3, before triggering the power press. BUG=b:66698593 TEST= > apshutdown [7045.198370 chipset_force_shutdown()] [7045.198870 PB PCH force press] [7045.199368 PB PCH pwrbtn=LOW] > LPC RESET# asserted[7049.218062 power state 3 = S0, in 0x000c] [7049.218718 Pass through VGATE: 0] [7049.219281 power state 7 = S0->S3, in 0x000c] [7049.220647 chipset -> S3] [7049.221108 power state 2 = S3, in 0x000c] [7049.221763 power state 8 = S3->S5, in 0x000c] [7049.222522 USB charge p0 m0] [7049.223217 chipset -> S5] [7049.223716 power state 1 = S5, in 0x000c] [7049.224334 PB PCH force release] [7049.224840 PB PCH pwrbtn=HIGH] [7049.232875 SW 0x01] [7049.240557 TCPC p1 Low Power Mode] [7049.252249 TCPC p1 Low Power Mode] [7049.254363 TCPC p0 Low Power Mode] [7049.266006 TCPC p0 Low Power Mode] [7059.225553 power state 9 = S5->G3, in 0x000c] [7059.226188 chipset_force_shutdown()] [7059.226717 PB PCH force press] [7059.233871 PB PCH pwrbtn=LOW] [7059.234381 power state 0 = G3, in 0x000c] [7059.250255 power state 0 = G3, in 0x000f] [7059.256533 SW 0x05] Change-Id: Ibc27c90f806deed6a2ca7035869c4e10ca7fbf0b Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://chromium-review.googlesource.com/683956 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* virtual_battery: Avoid unexpected batt_mode_cache refreshingJeffy Chen2017-09-251-2/+4
| | | | | | | | | | | | | | | | | | | | | Currently we are assuming batt_mode would never be zero, but that is not always true. Some battery do report zero for batt_mode(bob for example). So everytime the batt_mode_cache been set to zero, the virtual_battery would consider it uninited, and tries to refresh the next time. Use -1 as uninited batt_mode_cache to avoid that. BUG=b:66555246 BRANCH=gru TEST=Check on bob, the battery level is correct. Change-Id: Ieb7ec9403f69a6b5bca93c6682ec6117fe95fe1e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/678135 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fizz: Limit input currentDaisuke Nojiri2017-09-254-54/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Fizz has an over current control system. There are two FETs connected to two registers: PR257 & PR258. They control the max input current as follows: PR257, PR258 For 4.62A (90W BJ adapter), on, off For 3.33A (65W BJ adapter), off, on For 3.00A (Type-C adapter), off, off BJ adapters are distinguished by reading GPIO71. This patch also removes ISL9238 driver and ramping code. The charger chip has been removed from the board since proto2. BUG=b:65013352 BRANCH=none TEST=Boot Fizz Proto3 on BJ and Type-C. Change-Id: I32c2467f4ab23adf3f9313a03914d74d64a722df Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/668119 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* twinkie: enable WebUSBVincent Palatin2017-09-251-0/+2
| | | | | | | | | | | | | | | | | | Prepare the future and return a WebUSB descriptor to be able to use the dongle from this website. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=twinkie BUG=none TEST=manual: enumerate WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome R61+. Change-Id: I6a36538667ac114fc4b40cb87b2d6e946e265c4d Reviewed-on: https://chromium-review.googlesource.com/677285 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Kahlee: FIXUP: Optimize g-sensor settingGwendal Grignou2017-09-242-1/+5
| | | | | | | | | | | | | | | | Kionix Accel does not have FIFO, enable force mode for it. Chrome needs sensor for screen orientation, set to to 10Hz in S0 in the EC. BRANCH=none BUG=b:62029360 TEST=none Change-Id: I5545580f2073e9d1145bd86cfcd594164119cae7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/675575 Tested-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Gwendal Grignou <gwendal@google.com>
* zoombini: Enable TCPC interrupts.Aseda Aboagye2017-09-231-0/+47
| | | | | | | | | | | | | | | | | | | The TCPC interrupts were setup, but they weren't enabled yet. This commit enables the interrupts. Additionally, a "tcpcdump" debug command is added. This can be removed later or expanded upon to be more generic. BUG=None BRANCH=None TEST=Flash zoombini; Verify that we respond to TCPC alerts. Change-Id: Iba9523cbfb96a570b76e7bdc0ba21dd782854f24 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/670063 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fizz: Pulse LED using deferred callDaisuke Nojiri2017-09-222-57/+74
| | | | | | | | | | | | | | | | | This patch makes LED pulse using deferred call to save RAM and CPU cycles. This patch also adds led_alert API. It blinks LED as a warning. BUG=b:37646390 BRANCH=none TEST=Verify LED on in S0, pulse in S3, and off in S5. Run 'led alert' command. Change-Id: I8c61f91f095eed562d2ee9582868879241df626f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/675749 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add WebUSB descriptor supportVincent Palatin2017-09-226-21/+163
| | | | | | | | | | | | | | | | | | | | | | | | | The WebUSB specification defines a specific Platform Descriptor in the Binary Object Store: https://wicg.github.io/webusb/#webusb-platform-capability-descriptor This descriptor provides a special 'Landing page' URL to the host browser and associated privileges for it. Bump the USB version for BOS descriptors to 2.1 to be compatible with Chrome implementation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=none BRANCH=twinkie TEST=manual: on Twinkie (chip/stm32) and HG proto2 (chip/g), enumerate WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome R61+. Change-Id: I7211ab554f4a6c156c1e8e79a3d9f0d6644217c6 Reviewed-on: https://chromium-review.googlesource.com/664813 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy: Dynamically disable effect of SLP_S0# on all VRsFurquan Shaikh2017-09-221-12/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just setting the global VRMODECTRL register is not enough to disable the effect of SLP_S0# signal. Each VR control register needs to be set correctly to ignore the effect as well. However, disabling VR decay on SLP_S0# assertion by default results in additional power consumption during S0ix. In order to prevent this, VR decay on SLP_S0# assertion needs to be enabled and disabled dynamically as follows: 1. By default on EC boot, PMIC will be initialized to disable VR decay on SLP_S0# assertion. 2. When host indicates intent to enter S0ix, EC will enable decay of VRs on SLP_S0# assertion. 3. When host exits from S0ix and updates the intent to no longer enter S0ix using host command, EC will disable decay of VRs on SLP_S0# assertion. actual SLP_S0# assertion because PMIC seems to honor the setting only at SLP_S0# assertion and not if it is already asserted. BUG=b:65732924 BRANCH=None TEST=Verified with this change that the failing Lux device is stable for a long time even with runtime S0ix. Change-Id: I9c5afb408694b3b467e85dcea723f7574bc639c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/674034 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Provide chipset and board callbacks on host sleep event commandFurquan Shaikh2017-09-223-0/+39
| | | | | | | | | | | | | | | | This change allows chipset and board to perform any action when host indicates intention to enter sleep state. Chipset can take action like enable/disable power signal interrupts and boards can enable/disable decay of VRs on host intent to enter/exit S0ix. BUG=b:65732924 BRANCH=None TEST=make -j buildall Change-Id: I6298825d4ee96a07b93523c2f366527ae2be8a27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/677498 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* twinkie: replace combined firmware bash scriptVincent Palatin2017-09-223-59/+2
| | | | | | | | | | | | | | | | | | | | | | | | In order to get a Twinkie firmware image with the regular Twinkie sniffer firmware in the RO partition and a firmware behaving as a USB PD sink in the RW partition, I had created the (questionable) build_rw_variant bash script. Now the EC build can do this natively, so remove the script and the dedicated task list and use conditional task declaration in the ec.tasklist. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=twinkie BUG=none TEST=build the former firmware with './board/twinkie/build_rw_variant', build the new one with this patch and 'make BOARD=twinkie' -j, compare the 2 resulting binaries, they are identical. Change-Id: I3adb24e2c2825e5bd6f43a7440f829efd70038cc Reviewed-on: https://chromium-review.googlesource.com/677284 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charge_state_v2: dump_charge_state: Add cflushNicolas Boichat2017-09-221-0/+2
| | | | | | | | | | | | | | | The dump_charge_state (chgstate console command) is quite large, and may get truncated, let's add 2 cflush at approximately each third of the output. BRANCH=none BUG=b:66575472 TEST=On wand, type chgstate in EC console Change-Id: Iaa87a6a77b9b6edb0bd8235a87297f8d63fe3085 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/678755 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charge_state_v2: Allow charger operation without a hostNicolas Boichat2017-09-221-0/+14
| | | | | | | | | | | | | | | | | | update_dynamic/static_battery_info update information in the memmap shared with the host. When there is not host, these functions cannot do anything. The battery information will, eventually, have to be passed to host (through lid EC), but this will be implemented later. BRANCH=none BUG=b:66575472 TEST=make BOARD=wand -j Change-Id: I1640bb0c5a9eb242183b957ccbef4d4999112160 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/678754 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Apply consistent Rp at bootShawn Nematbakhsh2017-09-211-0/+5
| | | | | | | | | | | | | | | | CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT Rp is applied when neither port is a source, so apply it at boot to be consistent. BUG=chromium:766814 BRANCH=gru TEST=On kevin, verify 3A Rp is applied to both ports at boot. Change-Id: Ib62a96063783e8ef9ac9240800f445fa9e5a59af Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/675845 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy/soraka: Do not disable charge port in critical battery stateFurquan Shaikh2017-09-211-0/+9
| | | | | | | | | | | | | | | | | | | | | When battery is at critical charge level, reject charge port disable request. Since battery is not able to provide enough power to the EC on boot, we should not cut off our input power, regardless of dual-role determination or other charging policy. (Reference: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/351224) BUG=b:64703097 BRANCH=None TEST=make -j buildall. Verified that both right and left port are able to boot the EC up successfully. No reboot loops observed in critical battery conditions. Change-Id: I098083036388783c0975ac772da3a3412895e26f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/675586 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* EFS: Allow EC to switch slot on rebootDaisuke Nojiri2017-09-212-1/+12
| | | | | | | | | | | | | | | | | | | | | Chromebox ECs performs EFS: verifying firmware before the AP boots. This patch updates host commands which are required for the EFS. When EC_REBOOT_FLAG_SWITCH_RW_SLOT is specified, EC_CMD_REBOOT_EC changes the active slot before it reboots the system. BUG=b:65264494 BRANCH=none TEST=On Fizz, verify: 1. RW_B is old and updated by soft sync. RW_B is activated and executed after reboot. System continues to boot to OS. 2. RW_A is old and updated by soft sync. RW_A is activated and executed after reboot. System continues to boot to OS. Change-Id: I08050c985ce0b27b30cb842e6b5b4660f32e5211 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648450 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* EFS: Switch active slot when current slot is invalidDaisuke Nojiri2017-09-216-112/+92
| | | | | | | | | | | | | | | | | | | | | | | When EFS finds the active slot is invalid, it tries the other slot. This patch makes the other slot active so that the following boots will try the other slot first. This patch also replaces enum flash_rw_slot with system_image_copy_t. The new APIs are therefore renamed from *_slot to *_copy. Basically, this makes vboot see slots as a conceptual place instead of physical spaces bound to flash storage. BUG=b:65028930 BRANCH=none TEST=On Fizz, verify: 1. RW_B is old and updated by soft sync. RW_B is activated and executed after reboot. System continues to boot to OS. 2. RW_A is old and updated by soft sync. RW_A is activated and executed after reboot. System continues to boot to OS. Change-Id: Icf97da13e651e7a931b9d507052b9422566eb16c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648449
* zoombini: Correct Vbus ADC channel.Aseda Aboagye2017-09-211-1/+1
| | | | | | | | | | | | | | | | | The Vbus adc channel was defined as 0 in the enum, however, we don't actually have a Vbus ADC channel, therefore it should be defined as -1. BUG=None BRANCH=None TEST=Flash zoombini; Verify that when charge manager tries to read the Vbus voltage, the EC doesn't panic due to a non-existing channel. Change-Id: I53dd3259afc7ae76f587e5b7925ce2f9daa06402 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/670123 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: Add Power Switch Logic support.Aseda Aboagye2017-09-213-4/+7
| | | | | | | | | | | | | | | | | | | | | | | This commit enables the PSL pins for zoombini. Previously, we were initializing the PSL_OUT pin to high, but it actually turns out that setting the output from a 0 to a 1 indicates that the firmware wants to remove Vcc1. This caused the EC to not boot up. This commit removes the improper initialization of the GPIO and additionally sets up the hibernate wake pins accordingly such that they can be used by the PSL glue logic. BUG=b:65647213 BRANCH=None TEST=Flash zoombini without rework. Verify board comes up okay. TEST=Enter `hibernate` on console; Verify board goes to sleep. Verify that each hibernate wake pins wakes up the board successfully. Change-Id: Ife1b82eec7957b44bbe409cdeba9c3972168812f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/670062 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: Update the keyboard config.Aseda Aboagye2017-09-212-4/+4
| | | | | | | | | | | | | | | | | | | The keyboard config was the old chrome OS keyboard, but it should be the new one introduced in April of this year. Additionally, change KSO2 inverted to be push-pull instead of open drain. This was causing the entire row to not be detected. BUG=None BRANCH=None TEST=Flash zoombini; Verify that every key on the keyboard is detected. Change-Id: I408739eed84f06bd9a2df5a9053c75859f8aaa0b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/670061 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: led: Invert duty cycle.Aseda Aboagye2017-09-211-1/+1
| | | | | | | | | | | | | | | | | The LEDs were on when they were intended to be off. This commit just inverts the duty cycles. BUG=None BRANCH=None TEST=Flash zoombini. Verify all LEDs are off. Plug in battery, verify that Red LED is on. Change-Id: I78e2bce45603fd223ebaeacb024a210c5db70123 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/670060 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: Change battery i2c bus speed to 100KHz.Aseda Aboagye2017-09-201-1/+1
| | | | | | | | | | | | | BUG=b:65681152 BRANCH=none TEST=flash zoombini; verify that smart battery shows up on i2c bus. Change-Id: Icc38c153b3c140d221e1981cf97dc1ca935d65e2 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/667940 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* zoombini: Change TCPC ports to match schematics.Aseda Aboagye2017-09-202-6/+14
| | | | | | | | | | | | | BUG=None BRANCH=None TEST=Verify that the TCPC ports correspond to the schematic. Change-Id: Ic05448b6144754162ced26993948599930307786 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/665893 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver: bm160: Fix minimal gyro frequencyGwendal Grignou2017-09-201-1/+1
| | | | | | | | | | | | | | | | | | | Was set in Hz unit instead of mHz. The minimal frequency of the gyroscope is 25Hz. By setting it at 25mHz, we make believe that the gyro was also supporting 5Hz or 10Hz: the test would complain when instead the samples came with a 25Hz. Fix up of cl/482703 BUG=b:65000611 TEST=compile BRANCH=caroline,eve,twinkie Change-Id: I162d0d2e9b545af82698d8d484875761f426efe4 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/674003 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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