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* stm32: add embryonic support for STM32F76xVincent Palatin2017-08-187-12/+135
| | | | | | | | | | | | | | | | | | | | | | | The STM32F76x is really close to the STM32F4 family, so the most concise implementation is just using CHIP_FAMILY_STM32F4 and adding CHIP_VARIANT_F76X. Tune the clock settings to 180 Mhz CPU clock as the goal is performance. (over-drive is not implemented yet to get to 216 Mhz) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=ran on nucleo-f767zi board. 'make BOARD=nucleo-f767 flash', the red LED is on and the green LED turns on/off when pressing the user button, UART console works properly. Change-Id: I1f67df3aec874c965c81188df46c72de210728d9 Reviewed-on: https://chromium-review.googlesource.com/612750 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: remove stm32f4 dead code in DMAVincent Palatin2017-08-181-33/+1
| | | | | | | | | | | | | | | | | | The STM32F4 family is building a special variant of the dma code (dma-stm32f4.c), all the conditionals for F4 in stm32/dma.c are just dead code. remove them. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Change-Id: Icbf8d08c7e50fe5153a1b3830011bb12afcabaa5 Reviewed-on: https://chromium-review.googlesource.com/621391 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Use SVr4/4.3BSD/C89/C99 prototype for strlenStefan Reinauer2017-08-182-2/+2
| | | | | | | | | | | | | | | | | | SVr4/4.3BSD/C89/C99 use a return value of size_t. To make interaction with code running on both userland and on the EC easier, change our function prototype to return size_t as well. Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=none TEST=make buildall -j works Change-Id: I0f097c4d0db4232d888e1d54e6c1d22f4859a112 Reviewed-on: https://chromium-review.googlesource.com/618269 Commit-Ready: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Wake on AC detect edgesRandall Spangler2017-08-181-6/+19
| | | | | | | | | | | | | | | | | | | | | | | Currently, we only use the AC detect interrupt for battery cutoff support on detachable devices, and we use the RDD detect interrupt for waking Cr50 from deep sleep. However, Eve accidentally detects RDD when the EC is off, so this is not a reliable signal - particularly if Cr50 is explicitly driving EC reset. Enable the AC detect interrupt all the time, and defer sleep for 5 seconds when it transitions. This will have a negligible effect on overall power (since AC is not normally transitioning) and will allow the RDD detect code to be simplified. BUG=b:64799106 BRANCH=cr50 TEST=manually pull DIOR5 up and down; see AC interrupt debug output. idle d, wait for sleep, then wiggle DIOR5 and see that cr50 wakes. Change-Id: I7551f25e27a79573bf4527d8c38994634df621ec Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619319 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* battery/max17055: Wait longer for initial configPhilip Chen2017-08-181-2/+2
| | | | | | | | | | | | | | | | | max17055 sometimes fails to finish configuration due to timeout. Let's wait longer. BUG=b:63870414 BRANCH=none TEST=boot scarlet rev1 10 times and ensure MODELCFG.REFRESH bit is cleared when retries value > 10. Change-Id: I62984c19014a244a378180bab6683e2e6f842cd1 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/617653 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* battery/max17055: Process negative current/temperature rightPhilip Chen2017-08-181-2/+2
| | | | | | | | | | | | | | | | | | | | On max17055, current/temperature register values are in 2's complement format. Therefore we need to consider the case of negative values before doing bitwise operation. BUG=b:63870414 BRANCH=none TEST=run 'battery' command and confirm the reported discharge current looks reasonable. Change-Id: Iea0c554aecf2b410fc27b547e01ee7a583a0dd00 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/617654 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* util/genvif.c: Remove duplicated include.Che-yu Wu2017-08-171-1/+0
| | | | | | | | | | | | | The header file "stdint.h" is included twice. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Iba6975b65309be032e0ae040d13a7d06a534fc0d Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/620291 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: add 'recover hosed slave' i2cs capabilityVadim Bendebury2017-08-175-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A common failure condition on the i2c bus is when the master unexpectedly stops clocking the bus while the slave is driving the SDA line low. In this case the master is not able to issue Stop or Start sequences, which makes the bus unusable. Good slave controllers are able to detect this condition and recover from it by removing the pull down from the SDA line. This patch adds this capability to the g chip i2c slave controller. A new timer function is created which samples the SDA line twice a second. If it detects that SDA is low in two consecutive invocations and the number of i2cs read interrupts has not advanced, it decides that the "hosed slave" condition is happening and reinitializes the i2c driver, which removes the hold from the SDA line. Even though the state of the SDA line is supposed to be accessible through the I2CS_READVAL register, it in fact is not, reads always return zero in the SDA bit. To work around this a GPIO (port 0, bit 14) is being allocated to allow to monitor the state of the line, it is multiplexed to the same pin the SDA line uses. When the AP is in low power modes the SDA line is held low, this state should not trigger i2c reinitializations. CQ-DEPEND=CL:616300 BRANCH=none BUG=b:35648537 TEST=connected H1 on the test board to an I2c master capable of stopping clocking mid byte. Observed that the existing code would just sit in the "hosed" state indefinitely. The code with the fix recovers from the condition (drives the SDA line high) 500ms to 1s after the failure condition is created. Change-Id: Iafc7433bbae9e49975a72ef032a923274f8aab3b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/614391 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: add delay after soft resetMary Ruthven2017-08-171-0/+9
| | | | | | | | | | | | | | | | Add a delay to allow the clocks and usb signals to settle. BUG=b:63767046,b:63867566 BRANCH=cr50 TEST=put the eve ec into hibernate, wait until cr50 enters deep sleep, use the uart to wake it up, and verify that it eventually reenters deep sleep Change-Id: I26463ce3e00996368a791a245b0f9de01737478c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/598448 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* charger/rt946x: Finish init no matter which CHIP REV it isPhilip Chen2017-08-172-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | When booting scarlet rev1, the initialization of rt9466 is not finished because CHIP REV < 0x05. Actually, we shouldn't keep the latest CHIP REV in rt946x.h because it's hard to maintain. And we should try to finish rt946x_init() no matter what CHIP REV it is. Also, let's clean up the logging message in rt946x_init() a bit to make it clear that it's from RT946X. BUG=chromium:736821, b:63739819 BRANCH=none TEST=boot scarlet rev1 and confirm the initialization of rt946x is finished Change-Id: Ic0b1f837b801cc18744a1222794a055dfe8aa54c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/612585 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* scarlet: Make AP_CORE_PG a non-INT pinPhilip Chen2017-08-171-2/+4
| | | | | | | | | | | | | | | | | AP_EC_S3_S0_L and AP_CORE_PG can't be INT pins at the same time. BUG=b:64528567 BRANCH=none TEST=boot scarlet rev1 Change-Id: I3e70d2ef2a1f78c0661c8c4d40db32f22dff616f Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/611650 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Support non-INT power signal pinsPhilip Chen2017-08-171-0/+37
| | | | | | | | | | | | | | | | Optionally do polling for power signal pins which are not set as INT pins. BUG=b:64528567 BRANCH=none TEST=boot scarlet rev1 with a non-INT power signal pin Change-Id: I327753fcc0f1c6482c5f5eb3df28f67181b4eb62 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/611649 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: shi: add the support for SHI module version 2CHLin2017-08-174-44/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx7, we introduce an enhanced version of Serial Host Interface (SHI) module. This CL adds the support for it. It includes: 1. Increase the size of IBF/OBF from 64 bytes to 128 bytes. 2. Add IBULVL/IBFLVL2 in SHICFG4/SHICFG5 which can configure at which level the IBF pointer reaches to trigger an interrupt to core. The current setting of these two register fields are: IBFLVL - 64 (half full) IBFLVL2 - 8 (the size of host command protocol V3 header) 3. Dedicated CS high/low interrupts. In old SHI module, the way to generate CS high interrupt event is via EOR bit. However, it has a defect that EOR won't be set to 1 when CS is de-asserted if there is no SHI CLK generated. It makes the handling of glitch condition more complicated. In the new SHI module, we introduce the CS high/low interrupts (by enabling the CSnFEN/CSnREEN) to make it easier to handle the glitch. The new SHI module is enabled during SHI initialization when the chip family is npcx7. BRANCH=none BUG=none TEST=No build errors for "make buildall". Test host command communication is ok between npcx7 EVB and a host emulator. Make sure the glitch condition can be detected and handled. Also test the driver on gru, make sure it won't break the operation of old SHI module. Change-Id: If297fd32a0ec2c9e340c60c8f1942868fa978fbc Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/607812 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Remove BOARD_AP_USB propertyRandall Spangler2017-08-176-33/+14
| | | | | | | | | | | | | | | | | | | We previously disabled the USB PHY to the AP. But the BOARD_AP_USB property lingered on. Remove the property. Also clean up the idle task deciding when to do utmi wakes. With the AP USB connection disabled, that's only necessary when the debug cable is attached, so we can check that explicitly. BUG=none BRANCH=cr50 TEST=make buildall; boot CR50_DEV=1 image Change-Id: If81a7bcfe845d9d70dcc7e16239244a4f5f2427b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616301 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Add helper functions for device-is-enabledRandall Spangler2017-08-176-16/+27
| | | | | | | | | | | | | | | | | | | | A subsequent CL will massively refactor the device state machines. Add the helper functions which will be used by that CL, so that the refactoring touches fewer files. No change in functionality. BUG=none BRANCH=cr50 TEST=make buildall; boot cr50 with a CR50_DEV=1 image Change-Id: I3499d45e93fa15b6de9c04ce398d1c5bfbbc01e9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616300 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Revert "npcx: workaround the bug that SHM data read via eSPI may be corrupted"Nicolas Boichat2017-08-161-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ddbfe690e294e595c6ed3511dcf417410d9b2804. Reason for revert: Causes move cursor movements to be choppy, and device to be very unresponsive during flashrom EC operations. Original change's description: > npcx: workaround the bug that SHM data read via eSPI may be corrupted > > In eSPI systems, when the Host performs a data read from the Shared > Memory space, the returned data may be corrupted. This is a result of > the Core-to-Host access enable bit being toggled (by toggling CSAE bit > in SIBCTRL register) during an eSPI transaction. > > The workaround in this CL is to set CSAE bit to 1 during initialization > and remove the toggling of CSAE bit from other EC firmware code. > (i.e., let the CSAE bit be always 1.) > > BRANCH=none > BUG=none > TEST=No build errors for make buildall. Flash poppy ec image, make sure > it can boot to OS. Run "ectool version" over 100000 times, no error > occurs. > > Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe > Signed-off-by: CHLin <CHLIN56@nuvoton.com> > Reviewed-on: https://chromium-review.googlesource.com/590396 > Commit-Ready: Shawn N <shawnn@chromium.org> > Tested-by: CH Lin <chlin56@nuvoton.com> > Reviewed-by: Shawn N <shawnn@chromium.org> BUG=b:64730183 TEST=flashrom -p ec -r ecr.bin, device still responsive. Change-Id: Idaeef2707df990b2441a77a15807698d41018449 Reviewed-on: https://chromium-review.googlesource.com/618366 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* nefario/battery: support the 3s batteryCaesar Wang2017-08-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As Nefario supports 3s battery, we can change the parameter for board-specific instead of the charger driver. BUG=chromium:754824 BRANCH=none TEST=Build and check battery information > battery Status: 0x0080 INIT Param flags:00000003 Temp: 0x0bc0 = 300.8 K (27.7 C) V: 0x2e1e = 11806 mV V-desired: 0x32fa = 13050 mV I: 0x07a7 = 1959 mA(CHG) I-desired: 0x0fa0 = 4000 mA Charging: Allowed Charge: 17 % Manuf: sunwoda Device: BBLD485595 Chem: LION Serial: 0x0064 V-design: 0x2c88 = 11400 mV Mode: 0x6001 Abs charge:17 % Remaining: 667 mAh Cap-full: 4079 mAh Design: 4000 mAh Time-full: 2h:47 Change-Id: If9a4cdd9932e3287bf06cbe0840c94085cbeea1f Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/616508 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: enhance sleep wake indicatorVadim Bendebury2017-08-161-8/+24
| | | | | | | | | | | | | | | | | | | | | | | Printing dots each time device wakes up from sleep causes the terminal to be overflown with dots, especially in cases when interrupts are generated at high rate. Let's replace printing dots with a rotating wheel, the screen is not going to be wiped out, and one still can tell the rate the wake interrupts are coming at. Also, each time the wake source changes, print its hex value. BRANCH=none BUG=none TEST=verified proper printing of the spinning wheel and wake interrupt sources. Change-Id: Ic32466234f91b4a19b6186f74296dc6dd765a8fa Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/611962 Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ps8xxx: use custom tcpm_drvCaveh Jalali2017-08-169-8/+60
| | | | | | | | | | | | | | | | | | | | | | | | | the ps8xxx family of TCPCs (ps8751, ps8805) have historically used the generic tcpci_tcpm_drv functions, but we need to override some of these entry points because the parade parts need to be woken up before accessing registers. in most cases, this doesn't matter because we access the chip in quick succession where we can "safely" assume the chip is awake -- and the code is structured to implicitly keep the chip awake. the new case we need to address here is where we need to suspend the pd_task and TCPC at an arbitrary point in time. the driver's .release method is called to shut down the chip, and that involves first waking up the chip to be able to access its regs to mask off interrupts, etc. BUG=b:35586896 BRANCH=none TEST=tested from depthcharge - we no longer get errors in the EC console logs about TCPC "release" failed. Change-Id: Ic2a90b71050b3f68c697b1cef48d736ed88b3f41 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/616460 Reviewed-by: Shawn N <shawnn@chromium.org>
* st32mon: Define SPI_IOC_WR_MODE32 if it's missingStefan Reinauer2017-08-161-0/+8
| | | | | | | | | | | | | | | | | | | On Goobuntu, the uapi copy of spidev.h doesnot contain SPI_IOC_WR_MODE32, however the kernel supports the IOCTL. To be able to build the tool outside of the ChromeOS chroot, define it if it's not available. Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none TEST=make buildall -j outside of the chroot BUG=b:35567067 Change-Id: I04ec968e221c7d43f1bdb364a195d371370ec886 Reviewed-on: https://chromium-review.googlesource.com/614645 Commit-Ready: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_touchpad: Add touch event to FIFO during suspendNicolas Boichat2017-08-161-17/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | Similarly to what we have done with keyboard events, we put touch events in a FIFO. The AP will need to interpret the timestamp in the events to be able to process the events correctly tough. Resume should typically take about 50ms, so a 8-event long FIFO should be good enough. Also, we bypass the FIFO altogether in most cases, when the USB interface is not suspended. BRANCH=none BUG=b:35775048 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Look at evtest output. Wait a second, make a swipe, see that events are received in a very short amount of time after resume (every EP interval/2ms), but the event timestamps show that some of them are older. Change-Id: If6ab56396f7d564b19e6c3c528847196ffa4d849 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612221 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_touchpad: Add timestamp field to touch eventsNicolas Boichat2017-08-163-0/+27
| | | | | | | | | | | | | | | | | | | | | | We use the unofficial, Windows 8, Relative Scan time HID usage (Digitizer page, 0x56) to add timestamps to our HID touchpad events. The timestamps is a rolling, unsigned, 16-bit integer, with a resolution of 100us (so it wraps around every 6.5s). The host will be able to synchronize to that timestamp, resetting an offset every time the touchpad is quiet a certain amount of time (e.g. 1 second). BRANCH=none BUG=b:63685117 TEST=Flash hammer, timestamps are reported in HID descriptor. Change-Id: Ie5d56a9df14e464d2cdcd559f550d6e3cc81961f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/603041 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Add keystrokes to a FIFONicolas Boichat2017-08-161-41/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put key events in a FIFO. This is especially useful when USB is suspended, so that we can replay the events on resume. This makes sure that no key strokes are lost on resume from USB autosuspend. We coallesce events happening within some interval (18 ms), greater than EP interval (16 ms) to ensure we cannot have a backlog of keys. The interval must also be short enough to ensure that the intended order of key presses is passed to AP, and that we do not coallesce press and release events (which would result in lost keys). We also discard key events in the FIFO buffer that are older than 1 second. Note that we do not fully drop them, we still update the report, but we do not send the events individually anymore (so an old key press and release will be dropped altogether, but a single press/release will still be reported correctly). BRANCH=none BUG=b:35775048 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Wait a second, type something quickly, verify that no keys are lost. Change-Id: I64d33c15a39ae33af42039fba62cf4ed3abef462 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/471188 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Simpler buffer handlingNicolas Boichat2017-08-161-31/+17
| | | | | | | | | | | | | | | | | | As suggested in CL:411741, makes the follow-up CL that buffers key strokes much simpler. We can revisit later if we can still sneak it that change, but, all in all, we can guarantee the same key latency by halving the USB endpoint interval. BRANCH=none BUG=b:35775048 TEST=Connect hammer, keyboard works. Change-Id: I6624fde9bd5561ddceb7ce195470d7af7cca7140 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/471187 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Replace reset handler by generic event handlerNicolas Boichat2017-08-1624-81/+159
| | | | | | | | | | | | | | | | | | | Some USB interface handlers need to know when USB has been successfully resumed after a wake event. For example, this is useful so that HID keyboard can send the events at the right time. BRANCH=none BUG=b:35775048 TEST=Using USB HID keyboard patches to queue keys in a FIFO: After USB autosuspends, press a single key and hold it. Without this patch the endpoint data only gets reloaded on the _next_ event. TEST=On hammer, I2C passthrough still works. Change-Id: I9b52b9de16767c8a66c702a5ae70369334a3d590 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/569547 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* board/elm/board.h: Remove CONFIG_CMD_HOSTCMDChe-yu Wu2017-08-161-1/+0
| | | | | | | | | | | | | | | | The command "hostcmd" in console isn't very useful and will cause stack overflow in console task when processing some hash commands. BUG=chromium:755048 BRANCH=none TEST=make BOARD=elm -j make BOARD=elm tests There should be no hostcmd command in the console of elm. Change-Id: Ifa721a1731bc1ebfb39e12430b6631338bdccd9f Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/616600 Reviewed-by: Rong Chang <rongchang@chromium.org>
* ec: Fix object comparison in the stack analyzerChe-yu Wu2017-08-162-0/+44
| | | | | | | | | | | | | Handle the case of comparing with different kinds of objects. BUG=none BRANCH=none TEST=extra/stack_analyzer/stack_analyzer_unittest.py Change-Id: I01056cd39e14d75442d4029b6c64d9843c49cf2a Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/616367 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ccd_config: Change test callback to highest priorityRandall Spangler2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | This way, when HOOK_CCD_CHANGE triggers, the debug message is printed before any of the effects of the change due to other hooks. No effect on the rest of the code. BUG=none BRANCH=cr50 TEST=manual in CR50_DEV=1 image ccdlock ccdoops "CCD change hook called" should be seen before "Enabling I2C" or "Disabling I2C" messages. Change-Id: I2e083b70fe8ac3938abc56e14b5e50fe9e237752 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616179 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* servo_v4: Tie data role preference to DTS mode settingScott Collyer2017-08-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | When servo_v4 acts as a debug test system (DTS) its expected use case is for triggering CCD mode and Faft testing. To that end, its desired default data role is to be a UFP so that the enet and USB port are accessible by the DUT. However, when servo is acting a regular SRC port, it makes more sense for the data role pairing to be consistent with a normal SRC port device which is SRC/DFP. BUG=b:64720447 BRANCH=servo TEST=Tested with Eve using twinkie USB PD analyzer. Verified that when DTS mode is enabled a data role swap request is sent to the DUT and when DTS mode is disabled that servo_v4 does not send a data role swap request. Change-Id: I071f85fc99f1c877d86ef48ec7fa38d6850d5679 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/615813 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* scarlet: Remap DMA channels for USART1Philip Chen2017-08-153-1/+13
| | | | | | | | | | | | | | | | | | | To enable console with DMA, we need to specifically remap DMA channels for USART1. ch2/3 and ch6/7 are already used by SPI1/2 modules. So we have to remap USART1_TX to ch4 and USART1_RX to ch5. BUG=b:64575809 BRANCH=none TEST=confirm ec console works on scarlet rev1 Change-Id: Ie2bb141c72252aee98e4cd4a284a01b4d57605f4 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/611147 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* coral: Add host command to fetch SKU IDPatrick Georgi2017-08-156-0/+46
| | | | | | | | | | | | | | BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: Ibf307c6e46152b4b09e94d8dca6d49ae863cb3ad Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/608370 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* chip/stm32/usb: Split usb wake handler as a different functionNicolas Boichat2017-08-151-43/+49
| | | | | | | | | | | | | | Indentation is growing out of control, let's move to a separate function so that we can return early. BRANCH=none BUG=b:35775048 TEST=Flash hammer, usb_wake works. Change-Id: I9abf99ff55b3977dfc307fc99aac6f1ab7dd1f6a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612922 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec: Add a task information library for the stack analyzer.Che-yu Wu2017-08-156-68/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a shared library to export task information. Modified the stack analyzer to get information from the shared library. Show allocated stack sizes of tasks in the stack analyzer. To get the all task information (including the allocated stack size), A shared library is added and compiled with the board to export all configurations of the tasklist. BUG=chromium:648840 BRANCH=none TEST=extra/stack_analyzer/stack_analyzer_unittest.py make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \ --objdump=arm-none-eabi-objdump \ --addr2line=arm-none-eabi-addr2line \ --export_taskinfo=./build/elm/util/export_taskinfo.so \ --section=RW \ ./build/elm/RW/ec.RW.elf make BOARD=${BOARD} SECTION=${SECTION} analyzestack Change-Id: I72f01424142bb0a99c6776a55735557308e2cab6 Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/611693 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nefario: remove unused gpio defineCaesar Wang2017-08-141-3/+0
| | | | | | | | | | | | | | | | | The center supply is fixed to .9V on nefario, it had not the enable pin for controlling. Also the Nefario unused the led for battery. BUG=b:63408169 BRANCH=none TEST=Tested on nefario, check the gpioget Change-Id: I339ce2cb2fb530cec393a352d920ea21fd8a8464 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/612969 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* ec: Add analysis tool for firmware stack usage.Che-yu Wu2017-08-146-0/+1154
| | | | | | | | | | | | | | | | | | | | | | Add a static analysis tool for firmware stack usage. Add an new Makefile rule to analyze the stack usages of firmwares. Details about the tool can be found in extra/stack_analyzer/README.md. BUG=chromium:648840 BRANCH=none TEST=extra/stack_analyzer/stack_analyzer_unittest.py make BOARD=elm && make BOARD=elm build/elm/RW/ec.RW.taskinfo && \ extra/stack_analyzer/stack_analyzer.py \ --objdump=arm-none-eabi-objdump \ --addr2line=arm-none-eabi-addr2line \ ./build/elm/RW/ec.RW.elf ./build/elm/RW/ec.RW.taskinfo make BOARD=${BOARD} SECTION=${SECTION} analyzestack Change-Id: Ifb1b5f5ad6be8f8b125b14d6ee03e25cb385895b Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/576411 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Coral: Add Keyboard backlight config.Ryan Zhang2017-08-133-2/+5
| | | | | | | | | | | | | | | + support Keyboard backlight Feature. BUG=None BRANCH=master TEST=`make -j BOARD=coral`, `ectool pwmsetkblight 0% ~ 100%` works Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: I69038a94da97dff5d7584264b1f8fab4e3385c82 Reviewed-on: https://chromium-review.googlesource.com/611105 Commit-Ready: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: system: Remove useless comparisonMartin Roth2017-08-131-1/+1
| | | | | | | | | | | | | | Because x is unsigned it's always greater or equal to zero. BUG=b:64477774 TEST=Build Change-Id: Iaf62be4aecf2738c123cf062099852a192285751 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606455 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: espi: Remove useless comparisonMartin Roth2017-08-131-1/+1
| | | | | | | | | | | | | | Because m is unsigned, it can't be less than 0. BUG=b:64477774 TEST=Build Change-Id: Iec93f396be1f01bc1c38b3285b93daacff6a15db Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606454 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: espi: Fix errors with unsigned variableMartin Roth2017-08-131-2/+4
| | | | | | | | | | | | | | | | Because sig_idx was declared as uint8_t, if espi_vw_get_signal_index() returned an error value of -1, it wouldn't get caught. This would cause the arrays to access the wrong locations later. BUG=b:64477774 TEST=Build Change-Id: Ibe21d51c00ae3511a66a6976e18495c3f7683a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606453 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* 8042: Fix error conditionMartin Roth2017-08-121-1/+1
| | | | | | | | | | | | | | | | | Since the scancode_setX arrays are defined with size [KEYBOARD_ROWS][KEYBOARD_COLS], if rows or columns are equal to either of those values, it would be accessing values outside of the array. BUG=b:64477774 TEST=Build Change-Id: I8a92d142b03281f2f4ad35eaba605b5a46df798d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606452 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_api.h: Stub usb_wake if CONFIG_USB_REMOTE_WAKEUP is not definedNicolas Boichat2017-08-123-6/+6
| | | | | | | | | | | | | | Removes clutter in callers, so that they do not have to wrap usb_wake calls around ifdefs. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I8641cb7aff702920aaa119e644dc812d5c3e774b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612220 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* board: reef_it8320: disable CONFIG_CMD_I2C_XFER to save flash spaceDino Li2017-08-111-0/+1
| | | | | | | | | | | | | | There isn't enough flash space after 'repo sync', so disable one more console command. BRANCH=none BUG=none TEST=build reef_it8320 and all. Change-Id: I370e06d5de211b7de669f35071c680d28efb7c17 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/612001 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_mux: Merge PS8743 & PS8740 as PS874XVijay Hiremath2017-08-1113-357/+247
| | | | | | | | | | | | | | | | | Merge PS8743 & PS8740 as PS874X as both the drivers are almost same. BUG=b:64598680 BRANCH=glkrvp TEST=make buildall -j On GLKRVP, verify mux setting is correct with Apple dongle (VGA + USB) and Pluggable adapter. Change-Id: Ic6d31979936ee213b07c4c71859809102ee91452 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/612209 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_mux: Add driver support for PS8743 chipDivya Sasidharan2017-08-115-0/+153
| | | | | | | | | | | | | | | | | Initial patch for supporting PS8743 USB Type-C Redriving Switch for USB Host / DisplayPort. BUG=b:64598680 BRANCH=glkrvp TEST=On GLKRVP, verify mux setting is correct with Apple dongle (VGA + USB) and Pluggable adapter. Change-Id: Ib45e328fc9ef6ccc410cef4550086be95ef17e8a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/506810 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_pd_protocol: Req SNK Cap if not received yet.Aseda Aboagye2017-08-111-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | In the SRC_READY state, we'll only request sink caps if we haven't received them yet and only if its the first transition to the state. However, we also don't send any PD traffic in that state if there's an incoming message in order to prevent a collision. This could create a scenario where upon entry to the SRC_READY state, a message is incoming. When this occurs, we never request the sink caps. This commit simply removes the condition that we may only request sink caps on the first transition to the SRC_READY state. BUG=b:64037926 BRANCH=gru TEST=Flash kevin; Connect to a DR port partner; Verify that sink caps are requested even after the first transition to the SRC_READY state. Change-Id: I6bc9ad01d45e6584a7a14b28806ae4872a22d98f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/611320 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charge_manager: Consider port in source PDO.Aseda Aboagye2017-08-118-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is defined for a board, as its name implies, the board can source a higher current if there is only one port acting as a source. This commit fixes an issue with selecting the right source capability message to advertise. charge_manager_get_source_pdo() was simply checking if there was more than one sink connected, instead of checking if there were any *other* sinks connected. In the event that a sink was connected to a different port, we would advertise the max source PDO. BUG=b:64037926, b:35577509 BRANCH=gru,eve,reef TEST=Connect sink to port 1. Connect a AMA to port 0 that claims that VBUS isn't necessary. Start sending source caps, verify that the max PDO is not being advertised in the source caps. Change-Id: Ie4145ecaf98d5b9070ad3e8b139e5653685fa801 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/610479 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* glkrvp: Enable switchesVijay Hiremath2017-08-112-2/+2
| | | | | | | | | | | | | | BUG=b:64491401 BRANCH=glkrvp TEST=mmapinfo is updated when lidopen & lidclose are performed SCI/SMI gpios toggle Change-Id: I93f1ae2cc8dbc389b3e870b49d5ee2bfff503451 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/606892 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin / nefario: Add comment to prevent reordering PWM IDsDouglas Anderson2017-08-112-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | As can be seen in <http://crosreview.com/610449> the IDs of PWMs are directly referenced by the kernel device tree on gru / kevin / nefario boards (technically also in bob and scarlet-rev0, but neither of those is supported by mainline EC code). Because of the kernel reference it's not a great idea to change the IDs. Let's add a comment so people don't change the ordering / IDs accidentally. NOTE: we can have a big argument here about whether it would be OK to change numbering _and_ change the numbering in the kernel at the same time. We can talk about whether the device tree is a binary and about whether this constitutes an ABI since Chromebooks don't ship the device tree binary separate from the kernel. We can talk about all those things. ...but we won't. There's no good reason to change the ID, so just don't do it. BRANCH=None BUG=b:63537905 TEST=None Change-Id: Iacdedc1c91e583183034d15e99735a470d6e0951 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/610933 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tpm: Add optional event loggingShawn Nematbakhsh2017-08-105-0/+104
| | | | | | | | | | | | | | | | | | Allow TPM to log events in a circular buffer through tpm_log_event(). Logs can be retrieved through a new vendor command VENDOR_CC_POP_LOG_ENTRY. BUG=b:63760920 TEST=On eve, store TPM logs through 'logentry' cr50 console command, verify logs are fetched correctly through 'trunks_send --pop_logentry'. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idbc405728c0ba68078447fb59717d6115830e3d8 Reviewed-on: https://chromium-review.googlesource.com/599352 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* glkrvp: Enable S0iX supportVijay Hiremath2017-08-103-1/+5
| | | | | | | | | | | | | BUG=b:64559696 BRANCH=glkrvp TEST=EC console command powerindebug shows correct GPIO info Change-Id: Iee346f61bc0a0b26d612d2966350d308be596592 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/610304 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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