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* test: Make it possible to run rsa tests on hammer boardstabilize-10718.88.Bstabilize-10718.71.Bstabilize-10718.69.Bstabilize-10718.111.Brelease-R68-10718.BNicolas Boichat2018-05-243-2/+4
| | | | | | | | | | | | | BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=make run-rsa run-rsa3 TEST=make BOARD=hammer test-rsa3, test on board Change-Id: Id4bd8d5f550dbc6569d88ced114849b3b6411b2f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071410 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* sn5s330: disable under voltage protectionJett Rink2018-05-242-1/+10
| | | | | | | | | | | | | | | | | | We need to disable under voltage protection because it prevents us from enabling the sink path when there is not Vbus on the connector side. We need to enable the sink path before we hibernate otherwise there is no power power to get to the charger which will then assert ACOK. Without this we won't wake up with the ACOK wake when USB power is inserted. BRANCH=none BUG=b:79948623 TEST=bip wakes with USB power insertion Change-Id: Idf16a92dacde63cf943ef68b0258b320d11de44c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Use lid angle to detect tablet modeDaisuke Nojiri2018-05-241-1/+1
| | | | | | | | | | | | | | | | | Tablet mode entry and exit are detected by a GMR sensor on Akali and by lid angles on the rest. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:77298177,b:77754921 BRANCH=none TEST=make BOARD=nami Change-Id: I637f7ab6dec779abbb5e7b7355bbbc665c86391d Reviewed-on: https://chromium-review.googlesource.com/1059936 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* ps8751: add source and sink path controlJett Rink2018-05-241-0/+4
| | | | | | | | | | | | | | PS8751 supports the TCPCI spec for controlling the power source and sink path, which is done through GPIO0 and GPIO1, respectively, by default. BRANCH=none BUG=b:78896495,b:78021059 TEST=verified TCPC drives PPC via reworked yorp board. Change-Id: Ie1de67495947b787ad9cd5aee0db3ca21bec5a10 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1047796 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* BMI160: EVE TOT divide by 0 error at bootSam Hurst2018-05-241-0/+1
| | | | | | | | | | | | | | | | | | | The BMI160 driver's init function generates a divide by 0 error by calling config_interrupt before initializing the range defined in struct accelgyro_saved_data_t. The explicit error is generated by macro BMI160_TAP_TH that's called in config_interrupt. BUG=b:80237518 BRANCH=None TEST=`make -j buildall` EVE boots from TOT Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: I8b7a4a7c63c973bcc639779ee54958f3702f1b36 Reviewed-on: https://chromium-review.googlesource.com/1071847 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* touchpad_elan: Ensure we at least have 1k of shared memoryNicolas Boichat2018-05-241-0/+3
| | | | | | | | | | | | | Debugging commands may request buffers up to that size. BRANCH=poppy BUG=b:63993891 TEST=make buildall -j Change-Id: I6dedfafc4e36d311026f9678e2cac99c85036ce0 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071311 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* touchpad_elan: Reload watchdog when programmingNicolas Boichat2018-05-241-0/+2
| | | | | | | | | | | | | | | | | | When using larger block sizes (e.g. 4096 bytes), the write operations take too long, which often causes a watchdog reset. Fix this by reloading the watchdog after programming every 64 bytes page. BRANCH=poppy BUG=b:80167548 TEST=Copy old touchpad FW to soraka, build staff, make sure FW can be updated. Change-Id: Ic6e7a3e3ef63877a4f2d5011e1fb0d49c04177a6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070952 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* octopus: moving hibernate code to baseboardJett Rink2018-05-243-45/+50
| | | | | | | | | | | | | bip also need to enable the sink path when going into hibernate BRANCH=none BUG=b:79948623 TEST=on bip, verfied that AC_OK, LID_OPEN, and POWER_BTN all wake the EC up. Change-Id: I2c1168f856cc45635b5c76f7ca409007fcf141cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1065203
* ppc: making driver non-constJett Rink2018-05-247-14/+14
| | | | | | | | | | | | | | | We need to update the driver based on the runtime board id, so we need to remove the const attribute. BRANCH=none BUG=b:78896495,b:78021059 TEST=build all -j Change-Id: I5f751c33cf4ec68a38aeb8644170df4987c87d7b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1068030 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ppc: flush console regularly during console dumpJett Rink2018-05-242-0/+17
| | | | | | | | | | | | | I noticed data was getting dropped from my console output on bip. Adding the cflush fixes it. BRANCH=none BUG=none TEST=ppc_dump 0 on bip works Change-Id: Ib71cb37c4c8728a7ab958905d3b2627b8c163faa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070626
* hammer: Remove unnecessary console commandsNicolas Boichat2018-05-241-0/+11
| | | | | | | | | | | | | | | Saving space in RW, even if we are not critical in terms of size, always helps to reduce verification time. BRANCH=poppy BUG=b:35647963 TEST=make newsize => Hammer shrinks by ~3k, verification time down by ~12 ms. Change-Id: I63741106fdc56c410871fb367c29605bf37f1b77 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070951 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* timer: Allow disabling gettime console commandNicolas Boichat2018-05-242-0/+3
| | | | | | | | | | | | | hammer does not need that command, let's just remove it. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, saves 112 bytes of flash Change-Id: I24ed979f8a9053128d4eb56fc5af00429f7ba0ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070950 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* console_output: Add option to disable console channelsNicolas Boichat2018-05-242-0/+19
| | | | | | | | | | | | | | On hammer, we do not need the console channels, so we can just disable them to save flash size. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, staff image size shrinks by 704 bytes Change-Id: I7a493ae57573814b166d45e57f1ad3d885f26086 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070949 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* grunt: Add support for flashing via Suzy-Q and servoRaul E Rangel2018-05-241-28/+97
| | | | | | | | | | | | | | | | | | | | | When grunt is connected via a Suzy-Q cable, it can only be flashed using npcx_uut. Also when grunt is connected via a servo it shouldn't try to use npcx_uut, but instead use npcx_spi. This change allows a board to show up in multiple BOARDS_XXX lists. If there are multiples, it will either look at the --chips flag, or it will check the VALID_CHIP_COMBO array to see if chip is valid for the servo type. BUG=b:77927814 BRANCH=none TEST=Tested each leg of the logic by changing parameters and variables. Tested using Suzy-Q: ./util/flash_ec --board=grunt Also tested using ServoV2: ./util/flash_ec --board=grunt Change-Id: I7068b5bab0cf20bd2d9ffdd3842a58df1f2f8810 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1044499 Commit-Ready: Martin Roth <martinroth@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* nami: Enable auto toggle/low power mode for standalone tcpcsTodd Broch2018-05-241-2/+3
| | | | | | | | | | | | | | | | | | | | | With the changes made to tcpci for alert handling and low power mode entry, the anx7447 can operate with auto toggle and low power config options. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:77544959 BRANCH=none TEST=Verfied that low power mode is entered when nothing is attached and that when an adapter is attached it connects and when removed returns to low power mode. Change-Id: I9c683c3f86ba98e55748ac355b3d4845799d89e5 Reviewed-on: https://chromium-review.googlesource.com/1049061 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org>
* chip/it83xx: Configure IRQTP for KBC when using eSPIFurquan Shaikh2018-05-232-0/+25
| | | | | | | | | | | | | | | | | | | | | | | SERIIRQ# is by default deasserted level high. However, when using eSPI, SERIRQ# is routed over virtual wire as interrupt event. As per eSPI base spec (doc#327432), all virtual wire interrupt events are deasserted level low. Thus, it is necessary to configure this interrupt as inverted. ITE hardware takes care of routing the SERIRQ# signal appropriately over eSPI/LPC depending upon the selected mode. BUG=b:79897267 BRANCH=None TEST=Verified using evtest that keypresses are properly identified on the OS side. Change-Id: Ie3b92f20fa915ba8f17dcbcb600ebfe5cbfb4d57 Signed-off-by: Dino Li <dino.li@ite.corp-partner.google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1069570 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: pass params to vendor commands as structRandall Spangler2018-05-234-124/+125
| | | | | | | | | | | | | | | | | | | | | | | This makes it easier to add params or flags for vendor commands without changing all of the command handlers. It also reduces code size by 56 bytes. For now, existing command handlers continue to use DECLARE_VENDOR_COMMAND(). Added DECLARE_VENDOR_COMMAND_P() for handlers which take the params struct directly. The CCD command will be the first user of that, since it will have different rules for 'open' based on where the command comes from. No change to existing command behavior. BUG=b:79983505 BRANCH=cr50 TEST=gsctool -I still works Change-Id: I7ed288a9c45e381162e246b50ae88cf76e67490d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1069538 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: tpm_alt_extension() specifies command origin is USBRandall Spangler2018-05-234-45/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, calls to tpm_alt_extension() were treated as if they came from the AP via the TPM interface, even though they actually originated from the cr50 console, which is accessible via the USB interface. This affects the following console commands: spi_hash - was already allowed as both a safe console command and via the USB vendor command interface. No change. rma_auth - was allowed as a safe console command, but not via the USB vendor command interface. Now allowed from both. No change in security, since anyone could already do it via the console. Unfortunately, getting a challenge fails because commands issued via the USB vendor command interface have a maximum payload of 32 bytes and the challenge is bigger than that; that's tracked in b:80098603. ccd - was already allowed as a safe console command. This directly called ccd_command_wrapper() for lock, open, and password subcommands. It made an extra check for password set for the unlock subcommand. Moved the unlock check to the vendor command handler. Also changed the order of checks so that FWMP disabling unlock and open supersedes an existing password; this matches go/ccd-open-simple. (That has no effect on existing systems, because CCD is disabled at a higher level.) Reduces code size by 8 bytes. BUG=b:79983505 BRANCH=cr50 TEST=manual, on a CR50_DEV=1 build Compile with DEBUG_EXTENSION defined to print extra debug output 'ccd lock' now shows as coming from USB 'ccd unlock' fails because no password is set 'ccd unlock' and 'ccd open' fail if FWMP disallows unlock 'rma_auth' prints a challenge 'gsctool -t -r' prints a challenge from AP root shell 'gsctool -r 12345678' returns error 6 (incorrect challenge), rather than error 127 (no such command). 'gsctool -I' works from the host 'gsctool -t -I' still works from AP root shell Change-Id: I2cd1027f5135b9c336df97ee4b1b1a15354728b4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1068102 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* APL/GLK: Clean up UART buffer before shutdownVijay Hiremath2018-05-231-0/+8
| | | | | | | | | | | | | | | | | | | | UART buffer gets overwritten by other tasks if it is not explicitly flushed before printing it on the console by same task. Hence, clean up the UART buffer so that all the debug messages are printed on the UART console before doing shutdown. BUG=b:79950369 BRANCH=none TEST=Manually tested on BIP, observed that UART logs are not lost on the terminal when apshutdown is issued. Change-Id: I420e9de9e2e71913ee3168267a6f3a2728b2690b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1064977 Commit-Ready: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* genvif: Allow usb_pd_policy.c only in baseboardEdward Hill2018-05-231-7/+11
| | | | | | | | | | | | | | | Update rules for util/genvif to allow usb_pd_policy.c to be present in just baseboard, or just board, or both. BUG=b:78638238,b:79704826 BRANCH=none TEST=make -j buildall Change-Id: I4e2970a65c131d0681d2159fe2ea18b2639048c9 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067751 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cleanup: make has_dut_i2c_mux check similar to other checksJett Rink2018-05-231-4/+8
| | | | | | | | | | | BRANCH=none BUG=none TEST=flash on bip using new check Change-Id: I32266554e090c80bdd9078c06cfa78512d5965ea Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1060589 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* yorp: add keyboard backlight controlJett Rink2018-05-237-1/+33
| | | | | | | | | | | | | | Enable PWM control of backlight in EC for yorp and phaser. Proto build of bip will not have backlight control in EC. BRANCH=none BUG=b:79422226 TEST=none (no hardware to test with) Change-Id: Ib6ed4af4de3145b112ed43b4ca1ec9f931f3875f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1050785 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* cleanup: remove transition code for LPC/ESPI cleanupJett Rink2018-05-232-10/+0
| | | | | | | | | | | BRANCH=none BUG=chromium:818804 TEST=full stack works with lpc and espi Change-Id: I371e993bc97e7e87fb1075cf3dba82082402c0cf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067504 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-2329-83/+85
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* bip: enabled PPC interruptsJett Rink2018-05-223-31/+45
| | | | | | | | | | | | | | | | Need to enable PPC interrupts, otherwise system doesn't work correctly include USB 2.0 not working (since the BC1.2 chip won't be powered after the Vbus change) BRANCH=none BUG=b:79886742 TEST=USB 2.0 works on insertion on C0 on bip Change-Id: I227dcfac22128389c3d3ab3efdddd045141dff7e Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1066221 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ec_chip_mchp: Expand data SRAM to 64KB.scott worley2018-05-223-55/+107
| | | | | | | | | | | | | | | | | | | | | | | Observed task stack sizes growing, especially PD related. Adjust chip configuration for 64KB data. Use RAM size config items in flash layout config items. Update SPI image generator python script to not add a Boot-ROM header to EC_RW and add a test mode for debugging SPI read and hash calculations. BRANCH=none BUG= TEST=Build boards based on chip mchp. Check RO and RW EC binaries are correct size and located properly in ec.bin CQ-DEPEND=CL:1036258,CL:1053576 Change-Id: I12709a434d5aaa84fabe459176a3423365343308 Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053948 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* util: do not generate redundant CROS_EC_VERSIONVadim Bendebury2018-05-222-4/+1
| | | | | | | | | | | | | | | The values of CROS_EC_VERSION and VERSION variables generated by getversion.sh are exactly the same. VERSION is used in more places than CROS_EC_VERSION, let's keep VERSION and use it everywhere. BRANCH=none BUG=chromium:632937 TEST=make buildall Change-Id: Ibec9ecdd4b67789a468dddfbc1c82565f90d48a8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1069330 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Refactor tracking vendor command originRandall Spangler2018-05-224-89/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added flags parameter to extension_route_command(). The caller now specifies whether the command comes from the USB interface or the AP. Moved USB-specific shuffling of response to embed result code into usb_upgrade.c, so extension_route_command() can be more generic. No change to permissions/behavior for existing commands. ccd_command_wrapper() still sends vendor commands as if they come from the AP. That's fixed in the next CL. Reduces code size by 128 bytes BUG=b:79983505 BRANCH=cr50 TEST=manual Build with DEBUG_EXTENSION defined, to turn on printing each command 'ccd lock' comes from AP and works From host, 'gscutil -I' comes from USB and fails From AP, 'gscutil -t -I' comes from AP and works Change-Id: I7136bb54073de9c5951a174c308151b1871c56f3 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1068101 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chip/stm32/clock: Initialize 'alarm_us'Philip Chen2018-05-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The new GCC build shows a warning/error in clock-f.c: 'alarm_us' may be used uninitialized in this function [-Werror=maybe-uninitialized] This is actually a fake warning. In the context of the logic, there is no way 'alarm_us' would be used uninitialized. But let's still initialize 'alarm_us' to clear the compiler warning. BUG=none BRANCH=scarlet TEST='USE=coreboot-sdk emerge-scarlet chromeos-ec' TEST=make buildall -j Change-Id: I7a0642cbe03c5a0adb6997ddc80c9cb797715749 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1068256 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
* ec_chip_mchp: Clear ADC sticky hardware status before starting.scott worley2018-05-221-19/+36
| | | | | | | | | | | | | | | | | | Before starting an ADC conversion clear sticky hardware status in ADC and interrupt aggregator. BRANCH=none BUG= TEST=Build boards using chip mchp and check for spurious ADC interrupts. CQ-DEPEND=CL:1053576 Change-Id: I48b07ecaac2976c5e06e23a4ecf4397ed41c89d1 Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053867 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec_chip_mchp: Lower UART interrupt priority.scott worley2018-05-221-2/+3
| | | | | | | | | | | | | | | | | | Reduce UART interrupt priority to not interfere with critical interrupts. WDT highest, GPIO & other HW, UART, Port80(lowest). BRANCH=none BUG= TEST=Build boards based on chip mchp. CQ-DEPEND=CL:1053576 Change-Id: I293132fce46cc460d1cf51abacf4b6a494c8c4a3 Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053873 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec_chip_mchp: Fix bug in GPIO interrupt handling.scott worley2018-05-221-20/+34
| | | | | | | | | | | | | | | | | | | | | The previous chip level GPIO itnerrupt change introduced a bug in calculation of the gpio table index. Bug only manifested if GPIOs in different banks were configured for interrupts. BRANCH=none BUG= TEST=Configure board with at least one GPIO interrupt per bank. Check proper handler is called when pin interrupt is triggered. CQ-DEPEND=CL:1053576 Change-Id: I9dd5d18be5f9df0e338e76b072fb82ed2df3e2de Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053827 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: add comment to CONFIG_BATTERY_REVIVE_DISCONNECTJett Rink2018-05-221-1/+2
| | | | | | | | | | | | | | When you define CONFIG_BATTERY_REVIVE_DISCONNECT you also need to define battery_get_disconnected_state method() BRANCH=none BUG=none TEST=none Change-Id: I0ab42c722e2511cbfa50cab2142baec0906d8263 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1055819 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ec_chip_mchp: Lower Port80 interrupt priority.scott worley2018-05-221-1/+1
| | | | | | | | | | | | | | | | | Prevent host spew of port 80h writes from impacting servicing more critical interrupts. BRANCH=none BUG= TEST=Build boards based on chip mchp. CQ-DEPEND=CL:1053576 Change-Id: I3e08d2f731fa644c3e3253cbca711e1116789b41 Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053949 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc/espi: convert remaning CONFIG_LPC to CONFIG_HOSTCMD_X86Jett Rink2018-05-2210-28/+28
| | | | | | | | | | | | | | We have converted all LPC-only configs to HOSTCMD_LPC so the remaining CONFIG_LPC defines represent the common case. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067503 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc/espi: convert ec chip code to use granular optionJett Rink2018-05-2231-62/+62
| | | | | | | | | | | | | | Break the ec chip code up with the more granular CONFIG_HOSTCMD_(X86|LPC|ESPI) options. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc: add explicit LPC define in board.hJett Rink2018-05-221-0/+1
| | | | | | | | | | | | | | | The ITE eval board relied on the chip's define for LPC. Since the ITE chip supports both LPC and eSPI, we want to define LPC here to be explicit. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ic477277543c1f24999070dc408052c7266df22e6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067501 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc: convert LPC only boards to use CONFIG_HOSTCMD_LPCJett Rink2018-05-228-8/+9
| | | | | | | | | | | BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I4a70e10c34d79361ceada1ff40b8912b8a6fdaa7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067500 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-2213-25/+13
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc/espi: define new targeted config optionsJett Rink2018-05-221-5/+39
| | | | | | | | | | | | | | | | | | | | Introduce CONFIG_HOSTCMD_LPC and CONFIG_HOSTCMD_ESPI which will replace CONFIG_LPC and CONFIG_ESPI. Today the CONFIG_LPC option guards both common code to eSPI and LPC and LPC-only code. Going forward CONFIG_HOSTCMD_LPC will guard only LPC code, and a new option CONFIG_HOSTCMD_X86 will guard common code to both LPC and eSPI. I am leaving the CONFIG_LPC and CONFIG_ESPI defines in this CL so each CL in the stack compiles. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I6ae3a805167a3404701d8a53c14dc83299afb376 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067498 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec_chip_mchp: Add miscellaneous register defines: LPC and IRQ.scott worley2018-05-221-1/+22
| | | | | | | | | | | | | BRANCH=none BUG= TEST=Build boards based on chip/mchp. Change-Id: I792e042cc3d78bf139b2ba4be8c1904e00118d30 Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053576 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* octopus: implement device modeJagadish Krishnamoorthy2018-05-225-2/+7
| | | | | | | | | | | | | | | | | | To enable device mode, set the gpio USB2_OTG_ID in the respective boards to high. Pull the gpio low to disable device mode. BUG=b:79343083 BRANCH=NONE TEST=On Yorp board, for UFP mode gpio USB2_OTG_ID should be high, for DFP mode gpio USB2_OTG_ID should be low. In OS console, lspci should list xdci. (with chromiumos/third_party/coreboot/+/1064592) Change-Id: I70f13a9705626d9bcbe989239f6826d35d8fa536 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1058832 Reviewed-by: Jett Rink <jettrink@chromium.org>
* g: speed up CCD UART processingVadim Bendebury2018-05-223-30/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP and EC consoles may generate a lot of bursty traffic, and cr50 UART console to USB processing is very slow: when characters become available, a hooks task callback is invoked, which retrieves received characters one at a time and queues them up to the appropriate USB transmit queue. This patch speeds up things as follows: - increases the seize of USB transmit queues for AP and EC console channels to 512 bytes. Experiments supported by code instrumentation has shown that even this is not enough to avoid underruns, but this is a good compromise between memory use and performance, these sizes could be revisited later, - raises UART RX interrupt priority from level 1 to 0 - moving bytes from UART TX FIFO to USB queue happens on the interrupt context when UART TX interrupt is asserted - as many characters as possible are read from the UART first, before queuing function is called, and the entire received batch is passed to the queuing function. It has to be mentioned here that presently batch processing is not necessarily much more efficient, because queuing function becomes more complicated when multiple objects are passed to it, this will have to be dealt with in a separate patch. There is still a lot of room for improvement: - functions used to queue up data are very generic, dedicated code could help a lot. - UART drivers should have methods for collecting all bytes available in receive FIFO in one invocation, - USB side of things (dequeuing data and passing it to the controller. BRANCH=cr50, cr50mp BUG=b:38448364 TEST=ran 'chargen' application on both AP and EC to flood the console channels and observed the flow of characters on the host site, it is pretty smooth with occasional hiccups, especially when TPM is active, before this patch it was impossible to have both stream up, both were garbled. - Verified that new account can be created and user logged in on restarts while chargen is running, i.e. TPM task gets enough processing bandwidth. - When EC is reset, there seem to be no lost characters on the console (it used to cause some garbled console output before this patch). The below output was collected on Coral: > reboot Rebooting! --- UART initialized after reboot --- [Reset cause: soft] [Image: RO, coral_v1.1.8363+2cc945d5a 2018-05-15 17:41:57 ... [0.003605 init buttons] [0.003826 Inits done] [0.004094 tablet mode disabled ] [0.008272 found batt:SMP] [0.022278 SW 0x01] [0.042247 hash start 0x00040000 0x00021994] [0.045823 Battery FET: reg 0x0018 mask 0x0018 disc 0x0000] [0.071136 kblight registered] [0.071544 PB init-on] [0.071818 USB charge p0 m0] [0.073670 ID/SKU ADC 4 = 1309 mV] [0.075630 ID/SKU ADC 3 = 852 mV] [0.076077 SKU ID: 71] [0.076335 Motion Sensor Count = 3] [0.083594 PD comm enabled] ... - did not test bitbang programming mode, it is in line for reworking for speeding up as well. Change-Id: Ic9f3972f585dd1976169965c2a2422253aeac87a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1016037 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* ectool: Fix typo in feature listingStephen Boyd2018-05-221-1/+1
| | | | | | | | | | | | | | | The power delivery spelling shouldn't have the extra 'e'. Remove it. BRANCH=None BUG=None TEST=ectool inventory and check for spelling Change-Id: Ic1ca8b5d15a20c532f5ae8d0404634e0bf93849b Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1057835 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* npcx: CEC: Change input back to GPIO when disabling CECStefan Adolfsson2018-05-221-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | The factory tests relies on being able to read CEC_IN through the GPIO API. When it is configured as TA1, it can't be read as a GPIO. With this change, the pin will be a reconfigured as a GPIO at boot or when CEC is runtime disabled using "ectool cec set enable 0" Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org> BUG=b:79842676 BRANCH=none TEST=Test that "ectool cec read" still works with CEC on, and that "ectool gpioget CEC_IN" reflects the incoming voltage when CEC is off. Change-Id: I3b17d6551612a156897d95ea2473e4fbcbd70e39 Reviewed-on: https://chromium-review.googlesource.com/1064110 Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org> Tested-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: CEC: Fix issues with pushing to incoming bufferStefan Adolfsson2018-05-221-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When pushing to the circular buffer, the read-offset mutex is no longer taken, so don't unlock the mutex. Don't allow writing to the last byte of the buffer. In that case, the read and write pointers will become equal and the buffer will be treated as empty. Add handling for pushing messages of invalid size. Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org> BUG=b:76467407 BRANCH=none TEST=Turn on/off TV: ectool cec write 0x40 0x36 ectool cec write 0x04 0x40 Verify that incoming messages still works when turning off TV: ectool cec read -- -1 Change-Id: Id207c442fac573430aac0c744ec07fa203074228 Reviewed-on: https://chromium-review.googlesource.com/1068945 Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org> Tested-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Stefan Adolfsson <sadolfsson@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cheza: Enable LED supportWai-Hong Tam2018-05-223-1/+165
| | | | | | | | | | | | | | | | It is copied from the Lux board, as the rev-0 hardware uses the same design as Lux. The LED doesn't work if AP is in G5, as the LED power source PP5000 is disabled in G5. Will fix it later. BRANCH=none BUG=b:74395451 TEST=Tested several scenarios: charge, low-level battery, charge but no battery. Change-Id: I3803b917c6c4cba35176b75cb316b2c8ef9eb13a Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1060582 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cheza: Check power enough and enable PP5000 when power-on APWai-Hong Tam2018-05-224-15/+54
| | | | | | | | | | | | | | | | | | | | | | | Remove the previous hack of force increasing the adapter current. The PP5000 rail is now turned on/off during power-on/off AP. Add a check to ensure it has enough power to enable the 5V rail and boot AP. If the battery is in low level or unplugged and the charger adapter doesn't supply enough power, don't boot AP and transition back to S5. The check may wait a while for PD negoiation. BRANCH=none BUG=b:79353631 TEST=On battery plugged and unplugged cases, checked the device can source VBUS to USB port-0 and port-1. TEST=Unplug battery and use a low-power adapter, can't boot up AP. See the "Not enough power to boot" message and transition to S5. Change-Id: Ie9b8dff6e10d97dffd554b382595e5e7a70875e6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1050607
* nocturne: Fix EC hibernate.Aseda Aboagye2018-05-222-2/+26
| | | | | | | | | | | | | | | | | | | | This commit adds the appropriate hibernate flags to the hibernate wake pins. It additionally, adds a board specific hibernate function which sets up the PSL pins for wake as well as writing to the ROP PMIC to disable all the power rails. BUG=b:79713379 BRANCH=poppy TEST=Enter `hibernate` on EC console, verify that system can wake from AC insertion, power button press, and lid switch. Change-Id: I5b197c3c4d54cfc9c0b00c19815faa019f8b8cae Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1067892 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx7: Export entering PSL mode.Aseda Aboagye2018-05-222-2/+9
| | | | | | | | | | | | | | | | | | | | Some boards (like nocturne) use PSL mode, but the deassertion of PSL_OUT does not directly cut the EC's VCC1 rail. Therefore, the board needs to implement a board specific implementation of hibernate while also being able to configure PSL mode. This commit exports a function of entering PSL mode which could be used in a board specific hibernate implementation. BUG=b:79713379 BRANCH=poppy TEST=`make -j buildall` Change-Id: I8debcae5e713b85c6d23ee3419416b6ae5d5dbf0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1067891 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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