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* fleex: update gpio name to latest board revisionstabilize-11306.BJett Rink2018-11-271-3/+3
| | | | | | | | | | | | | | | No functional changes. Update names to BOARD_ID=2 version of the schematics. BRANCH=none BUG=none TEST=builds Change-Id: I05d49aa436e9d08c0f61da3de7032c2875b3054c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1332467 Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* grunt: Enable PPC sink FET before hibernatingEdward Hill2018-11-271-0/+13
| | | | | | | | | | | | | | | | | | | | Some versions of some boards keep the port 0 PPC powered on while the EC hibernates (so Closed Case Debugging keeps working). Make sure the source FET is off and turn on the sink FET, so that plugging in AC will wake the EC. This matches the dead-battery behavior of the powered off PPC. BUG=b:119850162,b:113654692 BRANCH=grunt TEST=1) "ectool reboot_ec hibernate", wake on port 0 AC. 2) AP in S0, sink in port 0, EC console: "hibernate", unplug sink, wake on port 0 AC. Change-Id: I4dd7ebe5408bbb2d4c92da1a44ea8b4152dbb7da Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1352059 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* CBI: Clarify value types in help messagesDaisuke Nojiri2018-11-273-24/+25
| | | | | | | | | | | | | | | | | This patch make cbi-util and ectool show OEM_NAME and DRAM_PART_NUM take a string parameter. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:118798180 BRANCH=none TEST=buildall Change-Id: I7b4e126f02f9488ce6059c090a5f3ec665b39406 Reviewed-on: https://chromium-review.googlesource.com/1323852 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Aleena: switch LED pinryan.zhang2018-11-272-8/+38
| | | | | | | | | | | | | | | switch Blue and Amber GPIO by different board for power consumption. BUG=b:118657568 BRANCH=master TEST=`make board=aleena` Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Change-Id: Ib782397082f2efc799422db8bf0e2d637db1b32f Reviewed-on: https://chromium-review.googlesource.com/1345550 Commit-Ready: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Casta: initial EC imageDiana Z2018-11-279-13/+464
| | | | | | | | | | | | | Initial image for casta based on the most recent schematics available. BUG=b:119174492 BRANCH=octopus TEST=builds Change-Id: Ie0575476d79fd8f6c5f697499bc8a660880348e3 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1347011 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Nami: modify actual_key_mask to enable the "Search" key for the keyboardSue Chen2018-11-271-1/+3
| | | | | | | | | | | | | | | | with keypad BUG=b:119798830 BRANCH=firmware-nami-10775.B TEST=Use ksstate console to check it can show the right point for the "Search" key after pressing the key. Change-Id: I068b629d962a3f9ebf70ef9785610bc9fc424696 Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1352064 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* motion_lid: Get rid of return value for motion_lid_set_tablet_modeFurquan Shaikh2018-11-271-5/+4
| | | | | | | | | | | | | | | | | | motion_lid_set_tablet_mode accepts reliable as its input parameter and returns back the param value without any change. Effectively, the return value doesn't change anything. This change gets rid of the return value for motion_lid_set_tablet_mode. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I0f379d9148131d9dcb1d3f53a1db08d3ef72831f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341161 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* kukui: Enable DP.Yilun Lin2018-11-272-11/+58
| | | | | | | | | | | | | | | | | | | | | | | | | On plug DP dongle, we sohuld: 1. set USB_C0_DP_POLARITY bit accordingly 2. set USB_C0_DP_OE_L low 3. set USB_C0_HPD_OD high On unplug DP dongle, we should: 1. set USB_C0_DP_OE_L high 2. set USB_C0_HPD_OD low TEST=pd 0 dualrole on; plug DP dongle, see GPIO pins set accordingly. TEST=unplug DP dongle, see GPIO pins set accordingly. TEST=plug dp and seeing output to external display for both polarity. BUG=b:114162810 BRANCH=None Change-Id: I4e4755e3b757d25a081fd65f8eb68235766d6e0b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1221406 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: Add a separate seed for kek, that resets on TPM clear.Louis Collard2018-11-273-1/+66
| | | | | | | | | | | | | | | This is so that U2F registrations are invalidated after the device goes through powerwash. TEST=test_that <..> firmware_Cr50U2fPowerwash, manual tests BRANCH=none BUG=b:112604850 Change-Id: I94257ec71adc7d49dcb676f0b1dc9aa1151116bd Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1308238 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: Add functions to store 'hidden' objects in the TPM NVRAM.Louis Collard2018-11-272-0/+64
| | | | | | | | | | | | | | | This is to be used initially by U2F, to store an additional salt that can be cleared on powerwash. CQ-DEPEND=CL:1264316 TEST=manual tests, test_that <..> firmware_Cr50U2fPowerwash BRANCH=none BUG=b:112604850 Signed-off-by: Louis Collard <louiscollard@chromium.org> Change-Id: I77d19bd27011fa732419993d8019a60647b70221 Reviewed-on: https://chromium-review.googlesource.com/1264395 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* CEC: Set pull-up highDaisuke Nojiri2018-11-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | GPIO pins don't get set high or low after sysjump. This cause CEC not to work if RO image doesn't set CEC_GPIO_PULL_UP. This patch sets CEC_GPIO_PULL_UP to high in cec_init. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:119901859 BRANCH=none TEST=Verify CEC_PULL_UP=1 on Teemo in normal mode and recovery mode. Change-Id: I0c88a789a8731054c2e4b0bb1066529933473b70 Reviewed-on: https://chromium-review.googlesource.com/c/1346990 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Stefan Adolfsson <sadolfsson@chromium.org> (cherry picked from commit 258e4a3d2c89cbf1f81e384bc179cb748611f24e) Reviewed-on: https://chromium-review.googlesource.com/1347013 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* util/getversion.sh: Allow predictable reproducible buildsPatrick Georgi2018-11-271-1/+5
| | | | | | | | | | | | | The resulting binary shouldn't depend on the user or hostname, at least when the user explicitly asks for reproducible builds. Change-Id: I95604cfd93028b8d60e11550d4322424088f425f Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1341410 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* driver/anx7447: Modify Vconn SW protection time of inrush current and power ↵xiong.huang2018-11-262-1/+20
| | | | | | | | | | | | | | | | | | | SW short protect current. The default values of Vconn SW protection time of inrush current is 19us and power SW short protect current is 370mA, it finds that the current of Vconn will up to 656mA during press F3+power button with Huawei dongle plugged in MB, then Vconn will drop when the large current happen. Vendor suggest to adjust Vconn SW protection time of inrush current(modify register 0xAA from 19us to 2.43ms) and power SW short protect current(modify register 0xA8 from 370mA to 440mA). BUG=b:119540455 BRANCH=none TEST=The HDMI display well with Huawei dongle at MB side when pressing F3+ power button to reboot OS. Change-Id: Ibb7e602fc4a4aa9cb69231a7f199f4ea31265148 Reviewed-on: https://chromium-review.googlesource.com/1343643 Commit-Ready: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Tested-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Nami: Add new LED behavior for factory modeSue Chen2018-11-261-4/+35
| | | | | | | | | | | | | | | The factory mode is indicated by blue on for 2sec & amber on for 2sec. BUG=none BRANCH=firmware-nami-10775.B TEST=Check charge led is blue on 2sec Amber on 2sec when factory testing Change-Id: Ifc3786151ccef29e709587f8f5b3d3306a6b344f Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1351512 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Ampton: Modify LED behavior to follow CoralJames_Chao2018-11-221-9/+9
| | | | | | | | | | | | | | BUG=b:119842039 BRANCH=none TEST=check the led behavior Change-Id: Ieb684f7a3d38e3b36aab9bcf27cbc823b5a7df82 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1345791 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* CR50: Fix ECC key generation to match the code used in factoryMeng-Huan Yu2018-11-221-15/+27
| | | | | | | | | | | | | | | | | | | | Fix the workaround of ECC key generation. The workaround crrev.com/c/360441 for b/35576109 use a wrong EK template to generate the hash (object name of publicArea), and the format of that embedded hash is incorrect either. BRANCH=none BUG=b:35576109,b:80207339 TEST=Dump the EK seed from CR50 and verify the public and private key are matched in both cr50-side (also checked returned value of CreatePrimary) and factory-side. Change-Id: Ia53084757d9d848fd92e6ca309de83450cb64309 Signed-off-by: Meng-Huan Yu <menghuan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1329261 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* chipset: Provide default chipset_in_or_transitioning_to_statePhilip Chen2018-11-211-0/+5
| | | | | | | | | | | | | | | | | If HAS_TASK_CHIPSET is not defined, common/power.c is not compiled. So provide a default implementation which indicates the chipset is always off. BUG=b:119846880 BRANCH=scarlet TEST=emerge-scarlet chromeos-ec Change-Id: Ieb123bb27f088b3ec6b138b56db39a0d46016718 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1346989 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* grunt: Enable CONFIG_LOW_POWER_IDLE and CONFIG_LOW_POWER_S0Edward Hill2018-11-211-1/+3
| | | | | | | | | | | | | | | | | | | Enable NPCX to deep sleep when idle to save power. BUG=b:119879261 BRANCH=grunt TEST=pp3300_ec_a_mw on Careena reduced by 19 in S0 and 14 in S3 > idlestats Num idle calls that sleep: 136585 Num idle calls that deep-sleep: 9874 Time spent in deep-sleep: 824.368551s Total time on: 884.911062s Change-Id: I2cf515dc3ad983ecb1f6108f48bb5a51c5d7044b Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1347014 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* ISH: add IRQ to vector entry for doorbell clearHyungwoo Yang2018-11-211-0/+1
| | | | | | | | | | | | | | | | add IRQ to vector entry for doorbell busy bit clear interrupt. BUG=b:79676054 BRANCH=none TEST=tested on Atlas board Change-Id: I3c168326b8c7e300eac0f80f828bcadf1585e54d Reviewed-on: https://chromium-review.googlesource.com/1288033 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* ISH: IPC: send HC FW ready notification to hostHyungwoo Yang2018-11-212-0/+4
| | | | | | | | | | | | | | | | send Host Command FW ready notification to host driver. BUG=b:79676054 BRANCH=none TEST=tested on Atlas board Change-Id: I5148351d91151e964561c821c02634bd32163dfd Reviewed-on: https://chromium-review.googlesource.com/1297031 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* ISH: remove sending MNG_HC_FW_READYHyungwoo Yang2018-11-211-9/+0
| | | | | | | | | | | | | | | | | remove sending MNG_HC_FW_READY from task. the sending MNG_HC_FW_READY should be done by IPC task that supports Host Command. BUG=b:79676054 BRANCH=none TEST=tested on Atlas board Change-Id: Iea2d2864c67763c8c8e18b520c5a776b5ce469fb Reviewed-on: https://chromium-review.googlesource.com/1288032 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com>
* USB PD: Handle Vconn changes during hard resetDiana Z2018-11-211-0/+23
| | | | | | | | | | | | | | | | | According to section 6.8.2 of the PD spec, during hard reset it is required that the sink cease sourcing Vconn, and that the source turn Vconn off and back on (specific timing for the source can be found in section 7.1.5). BRANCH=None BUG=b:119540455,b:119742692,b:116764439 TEST=set up a hub which requires Vconn on bobba, ran EC reset and verified that after the port hard reset the EC was sourcing Vconn Change-Id: I9c4c89e46b2b32d658ce2eaae4a6b23fd465c406 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1344793 Reviewed-by: Edward Hill <ecgh@chromium.org>
* Ampton: Correct accel sensor base reference dependent on sensor locationJames_Chao2018-11-211-8/+6
| | | | | | | | | | | | | | BUG=b:118756407 BRANCH=none TEST=accelinfo on Change-Id: I3e9f1791a12e5cb63572b1d50435b4e7a42b7ccd Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1343641 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* cr50_fuzz: fix nvmem_vars user number.Allen Webb2018-11-211-1/+1
| | | | | | | | | | | | | | The CONFIG_FLASH_NVMEM_VARS_USER_NUM constant was incorrectly defined, so nvmem_vars was failing with EC_OVERFLOW. BRANCH=None BUG=None TEST=make -j buildfuzztests && ./build/host/cr50_fuzz/cr50_fuzz.exe Change-Id: I52facfd44423bb69284b54e6831e5e777cf35a05 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1344800 Reviewed-by: Manoj Gupta <manojgupta@chromium.org>
* liara: Use CONFIG_LED_PWM_CHARGE_STATE_ONLYEdward Hill2018-11-211-1/+1
| | | | | | | | | | | | | | | | | | | Liara only has a single LED on one side, and it should show only the charge state (instead of including chipset state and low battery state as well). Change from CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY to use the newly added CONFIG_LED_PWM_CHARGE_STATE_ONLY. BUG=b:119746227 BRANCH=grunt TEST=Liara LED is on when charging from either side. Change-Id: If71339be836037a88eb17933ba1a817bd10d5002 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1344796 Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* led_pwm: Add CONFIG_LED_PWM_CHARGE_STATE_ONLYEdward Hill2018-11-212-11/+21
| | | | | | | | | | | | | | | Add an option for devices that want to show only the charging state, but on all LEDs. BUG=b:119746227 BRANCH=grunt TEST=Liara LED is on when charging from either side. Change-Id: I819eaf27d3700748e47886855765c2da6f3d9eb8 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1344795 Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* atlas_ish: remove HostCommand task related.Kyoung Kim2018-11-211-3/+1
| | | | | | | | | | | | | | | | Atlas is migrated from Host Command to HECI protocol. Remove Host Command task and old ipc task. BUG=b:79676054 TEST=none Change-Id: Ic77b1d16de7772a1c69cba6fcf5d7d7849a06213 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1263897 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* ish-ipc: remove IPC/Host command related flagKyoung Kim2018-11-211-1/+1
| | | | | | | | | | | | | | | | Remove flag related to IPC interface & Host command protocol to add new IPC & HECI protocol BUG=b:79676054 TEST=none Change-Id: I4707e2845c38a4d86ab8bffad93f7024fa9e5eb5 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1263896 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* IPC/HECI: IPC/HECI uses lpc console channelKyoung Kim2018-11-211-1/+5
| | | | | | | | | | | | | | | IPC/HECI will shares same channels as LPC. BRANCH=b:79676054 TEST=none Change-Id: I2c423107df1fa7c7ab8084aa543519b0c9054e1d Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1263895 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* PD: Respect tTypeCSendSourceCap timingDiana Z2018-11-201-1/+9
| | | | | | | | | | | | | | | | | | | | | Currently, the pd_task will send source capability messages every time the task wakes while in PD_STATE_SRC_DISCOVERY. This can cause the task to violate the required 100-200 ms gap between sending source capabilities during source advertisement, and in a worst case it will give up sending source cabilities well before it should. With this change, the task should send a source capability message almost exactly every 100ms while in PD_STATE_SRC_DISCOVERY. BRANCH=None BUG=b:117788783 TEST=plugged hoho into bobba360 and phaser repeatedly with no hard resets during initial connection Change-Id: Id968921e0b0ea874bf7361849c22354804b5b9ca Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1340546 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Servo v4: reduce RO flash sizeDiana Z2018-11-202-2/+8
| | | | | | | | | | | | | | | Currently, the servo_v4 build is within 48 bytes of exceeding its RO flash size. With this change to remove the USART3 code from the RO image, there should be just about 350 free bytes of space. BRANCH=None BUG=None TEST=builds, hey_flash_used in RO elf file shows 0x170 free bytes Change-Id: I7ee8f6c964eb3e0fb009fba61430bab656c03c2e Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1340545 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* power/rk3399: Do not boot until power button is releasedPhilip Chen2018-11-191-2/+15
| | | | | | | | | | | | | | | | | This is the expected behavior for tablet/detachable. BUG=b:119508214 BRANCH=scarlet TEST=When a dru is off, press VolUP + VolDN + Pwr buttons for 10 secs without seeing dru boots, and then release those buttons, confirm dru enters recovery mode. Change-Id: Ib8d018da2af23a80a644f75808f9ed391b35d0f0 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1336739 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* ocotpus: move VBUS_ADC config to baseJett Rink2018-11-1912-62/+24
| | | | | | | | | | | | | | | | All boards but yorp have added the ADC hardware support back for VBUS ADC measurements. Move code to common baseboard BRANCH=none BUG=none TEST=ADC measurements still works on phaser and fleex Change-Id: I36a7ba92df21de4c1188613c6a12da83fdba6eb6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1337456 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* gsctool: fix in setting '--tpm_mode'.Namyoon Woo2018-11-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | b:119626285 reported the problem with '--tpm_mode'. $ gsctool -a --tpm_mode Unrecognized option: -m $ gsctool -a --tpm_mode enable TPM Mode: enabled (0) $ gsctool -a --tpm_mode disable TPM Mode: enabled (0) "tpm_mode" long opt should have 'has_arg' set to 'optional_argumenet', not 'required_argument'. Before this CL, --tpm_mode worked in a wrong way as reported in BRANCH=none BUG=b:119626285 TEST=manually and with autotest (crrev.com/c/1340640) as well. $ gsctool -a --tpm_mode TPM Mode: enabled (0) $ gsctool -a --tpm_mode enable TPM Mode: enabled (1) $ gsctool -a --tpm_mode disable TPM Mode: disabled (2) Change-Id: Ie11852925a21a3a3b8d9dda6092eac5040f1cd5c Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1340642 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Fizz: Set initial fan speed to 50%Daisuke Nojiri2018-11-191-0/+2
| | | | | | | | | | | | | | | | | This patch sets initial fan speed to 50% to reduce fan noise at start-up and resume. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:118701592 BRANCH=none TEST=Verify fan starts spinning on Fizz at 50% speed. Change-Id: I230eb2b6c33499f96d0583b5d75f2674960a35ff Reviewed-on: https://chromium-review.googlesource.com/1309036 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fizz: Add Jax supportDaisuke Nojiri2018-11-192-19/+26
| | | | | | | | | | | | | | | | | | | If OEM_ID is equal to 8 (Jax), the EC works as follows: - Set barrel jack adapter spec to (19V, 3.42A). - Set fan_count to zero Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:116588924 BRANCH=none TEST=Boot Fizz with OEM=8. Change-Id: Id6489b65a0bb71cd56d4fcf5e2fdbacb630aa99a Reviewed-on: https://chromium-review.googlesource.com/1308258 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fan: Allow fan count to be set dynamicallyDaisuke Nojiri2018-11-197-33/+77
| | | | | | | | | | | | | | | | | | Currently, the fan count is statically set. This patch allows it to be set dynamically so that a single binary can support devices with a different number of fans (including fan-less). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:116588924 BRANCH=none TEST=Boot Fizz with OEM=8. Verify fan spins with OEM=1. Change-Id: I77fc4e07ce2a1be2e288df145857a79c0003542f Reviewed-on: https://chromium-review.googlesource.com/1308257 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* touchpad_st: do not generate 0 finger hid eventWei-Han Chen2018-11-191-1/+3
| | | | | | | | | | | | | | | | | When we receive a beacon, we will also try to collect finger events. In this case, there might be the case that there is not finger but dome switch is on. In this case, we should not report the click. BRANCH=nocturne BUG=b:119597909 TEST=manual on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I03fe4481d17f6e919ab9501b2a93fa19635e381f Reviewed-on: https://chromium-review.googlesource.com/1337253 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Ampton: enable the interrupt for GPIO_BASE_SIXAXIS_INT_LJames_Chao2018-11-192-1/+7
| | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=accelinfo on Change-Id: I04764b0ce3f963f12f7977b08c89a375c2319d00 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1335292 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* kukui: Fix shipping mode VSYS leakage.Yilun Lin2018-11-195-5/+96
| | | | | | | | | | | | | | | | | | | | Follow the cut-off procedure recommended by Richtek. Also, tcpc_read/tcpc_write function will wake the TCPC up from low power mode and thus causing the TCPC re-init again, and this will break the register state we set. So, here we use mt6370_i2c_read/write to replace tcpc_read/write. TEST=boot system; Exec cutoff, and check that Vsys equals to zero. BUG=b:116682788 BRANCH=None Change-Id: I5cbd0df490ddb64b9376507e42a259c008c3ba16 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1335289 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* util:ecst: add the CHIP_VARIANT npcx7m6fc support for NPCX7CHLin2018-11-181-1/+3
| | | | | | | | | | | | | | | | | | | This CL adds the support for chip variant npcx7m6fc in the ecst utility. BRANCH:none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m6fc in board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be built and image header is correct. Change-Id: I138b19e21c361a42c2e613f6066957aabea17c0d Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1335293 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* headers: make EC commands headers C++-friendlyNicolas Norvez2018-11-162-1/+17
| | | | | | | | | | | | | | | | - wrap headers in 'extern "C"' - use relative path to #include BRANCH=None BUG=chromium:889250 TEST=make buildall -j TEST=emerge-nocturne ec-utils Change-Id: I67d8ba88edf77f72bd54500eff169537ffb6257f Signed-off-by: Nicolas Norvez <norvez@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1338599 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org>
* Makefile.toolchain: Add TEST_FUZZ checks.Allen Webb2018-11-161-0/+2
| | | | | | | | | | | | | | | This prevents a bunch of warnings that show when trying to run pkg-config for libprotobuf-mutator when not building the fuzzer targets. BRANCH=None BUG=None TEST=make -j buildall Change-Id: Idf8de959d86db744754cd237796ccaacd3668a63 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1338605 Reviewed-by: Mike Frysinger <vapier@chromium.org>
* gsctool: explicitly set buffering type to line bufferedWei-Cheng Xiao2018-11-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | This CL allows gsctool outputs to be instantly piped and shown in crosh when crosh executes cr50-verify-ro.sh, which calls gsctool, indirectly via debugd. Program stdout buffering type by default changes from line buffered to block buffered if the output is redirected to a file or pipe. Since we are going to call gsctool from inside debugd (CL:1337190) and want to pipe the output instantly to the dbus request sender, the buffering type of gsctool needs to be explicitly set. BRANCH=none BUG=b:113893821 TEST=in crosh run verify_ro, which indirectly runs gsctool via debugd, and verify that output is instantly piped and shown in crosh. (see CL:1337190 for detailed output) Signed-off-by: Wei-Cheng Xiao <garryxiao@chromium.org> Change-Id: I515854a29e5e2ede0acc8c2d9e2c4df367a5062e Reviewed-on: https://chromium-review.googlesource.com/1337250 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Louis Collard <louiscollard@chromium.org>
* core/minute-ia: fixes toolchain incompatibiltyKyoung Kim2018-11-161-1/+1
| | | | | | | | | | | | | | | | | | | Default coreboot toolchain(gcc 8.1, linker) does not generate __bss_size_words absolute value. ABSOLUTE() built-in function is used to make both old(4.9) and new(8.1) toolchains compatible. BUG=b:118355015 BRANCH=none TEST=built code with both old(4.9) and new(8.1) and verified __bss_size_words abolute value and tested if ISH system boots. Change-Id: I07ca0b68b222a2754866abdacb0a5d8585d01566 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1332810 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* cr50: Add board strapping options for Sarien/ArcadaKeith Short2018-11-162-8/+47
| | | | | | | | | | | | | | | | | | | | | Add 2 new board properties: * BOARD_WP_DISABLE_DELAY - forces an additional delay after detecting battery removal before disabling write protect * BOARD_CLOSED_SOURCE_SET1 - enables custom CR50 options for Sarien/Arcada boards that use a closed source EC Add Sarien/Arcada to board_cfg_table. BUG=b:118688072 BRANCH=none TEST=make buildall, flashed RW Cr50 firmware onto Careena board and verified boots new version Change-Id: Ic9ffdf4861c2239a1e68eb682152c70fb1f9bfc3 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1310093 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Liara: Add LGC batteryEdward Hill2018-11-162-0/+32
| | | | | | | | | | | | | | BUG=b:113823864 BRANCH=grunt TEST=Boot Liara with LGC battery; "cutoff" EC command succeeds; Plug in AC => boot to OS login. Change-Id: If2ea7bd1a6888b7bbe5f4eb0dd3217073d32e346 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1337468 Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* octopus: ignore C0 interrupts if in resetJett Rink2018-11-161-2/+5
| | | | | | | | | | | | | | Now that we have a reset line to C0, we should ignore interrupts while the C0 TCPC is in reset. BRANCH=none BUG=none TEST=flashed on fleex (uses C0 reset) without issue Change-Id: I014e95f80844b30623d1fba7e59bea8f5eb8572e Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1332807 Reviewed-by: Diana Z <dzigterman@chromium.org>
* usb-pd: preprocess pending interrupts after resetJett Rink2018-11-161-0/+14
| | | | | | | | | | | | | | | | | | If the EC resets while the TCPC interrupt line is asserted and the board configures the interrupt as edge trigger (which is very common), then the interrupt line will never present and edge and the ISR will never get called. Preemptively checking for pending interrupts should prevent this. BRANCH=none BUG=b:119564103 TEST=test that ec reboot with hub attached no longer malfunctions. Change-Id: I77ca5815e2bdc94e3173a621aeac8620bf332613 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1337466 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* phaser: update gpio based on next revJett Rink2018-11-162-11/+21
| | | | | | | | | | | | | | | | | | The reset pin for ANX3447 was added. This pin used to be a 1.8V signal and it now a 3.3V signal, so we need to take care to ensure that older boards don't try to drive 3.3V into the SoC. Other changes are just renames. BRANCH=none BUG=none TEST=current phaser (ID=2) works Change-Id: Ife0a1617f94e4f4a40d43b16328d5540ea35b3ff Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1334031 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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