summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* nami_fp: remove flash_fp_mcu file soft linkShelley Chen2018-12-121-1/+0
| | | | | | | | | | | | | | | | | | | We need to change this soft link to a new file. Somehow it's not working when I try to do it in one go, so have a separate CL where we remove the soft link with a follow up CL where we add the new file. When I view the CL with gitk, I see the proper diffs, but seems like there's a bug in gerrit that prevents the diffs from showing up. BUG=b:119565385 BRANCH=None TEST=None Change-Id: I89a3978d1b081e7912d52c1688df5e18e45b1a85 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1372093 Commit-Ready: Shelley Chen <shchen@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org>
* kukui: Increase PD_C0 stack size from LARGER to VENTINicolas Boichat2018-12-121-1/+1
| | | | | | | | | | | | | | | | We'll audit all these task sizes when we come closer to branching FW. BRANCH=none BUG=b:120164830 TEST=Flash kukui, plug/unplug USB-C a few times, no more crashes. taskinfo shows that we now have some margin: 8 PD_C0 00000000 0.042883 640/768 Change-Id: Iea5ea9a43e183aad4b31d9a9750e0e1b42113250 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1369505 Reviewed-by: Yilun Lin <yllin@chromium.org>
* Makefiles: Add support for MSAN and UBSAN.Allen Webb2018-12-113-2/+17
| | | | | | | | | | | | | | | | | | This adds support for building fuzz targets with memory and undefined behavior sanitizers. BRANCH=None BUG=chromium:911310 TEST=USE="ubsan fuzzer" ./build_packages \ --board=amd64-generic --skip_chroot_upgrade chromeos-ec && (cd ../platform/ec && unset BOARD && make -j buildall buildfuzztests) Change-Id: Ic7f4c1d7fcc1f6347f091b98567167066787cb9c Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1364326 Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org>
* nami_fp: branching nocturne_fp to cope with variationsYH Lin2018-12-118-1/+7
| | | | | | | | | | | BRANCH=none BUG=b:117297043 TEST=make BOARD=nami_fp -j Change-Id: I05ad15c621876185a0908ce7599578e7ebcff7df Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1369586 Reviewed-by: Shelley Chen <shchen@chromium.org>
* Nami: Add fan min/start/max definition for SyndraDaisuke Nojiri2018-12-111-1/+10
| | | | | | | | | | | | | | | | This patch adds fan RPM definitions for Syndra. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:120113410 BRANCH=none TEST=buildall Change-Id: I3bbdc98713c2dd8b0ed824a8576ffb2f597240ae Reviewed-on: https://chromium-review.googlesource.com/1363670 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* octopus: remove unused TCPC re-driver power codeJett Rink2018-12-101-78/+0
| | | | | | | | | | | | | | | | | | | | | | | | We had a hardware revision that used GPIO03 from the PS8751 as the enable signal for the TypeA USB re-driver power regulator. This prove to not work especially when the TCPC came back from low power mode. The hardware change has been reverted and now we are removing the firmware support for this change. BRANCH=octopus BUG=b:111406013,b:117656946 TEST=builds. Version 2.24 (released 10/30) of sub-board schematics mark the stuffing options to have the TCPC control the power as DNS. Version 2.2 was never officially released that had the faulty hardware circuit. Only a single spin of sub-boards had this circuit and they have been reworked. Change-Id: Ib7f5a369af26a83fb71ef7e27f52086a4aed9c0c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1366295 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Tom Sliva <tsliva@google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* core/minute-ia: Setup GDTRushikesh S Kadam2018-12-101-0/+29
| | | | | | | | | | | | | | | Setup GDT for main ISH FW BRANCH=none BUG=b:120051488 TEST=Verify that main ISH FW runs fine when loaded through host FW load flow. Change-Id: I8101de6c2482abb09ccc8fdc36321fa562e521d7 Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Signed-off-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1316700 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* Fleex: add stack analysis annotationsDiana Z2018-12-101-0/+278
| | | | | | | | | | | | | | | | | | | | Stack analysis notations for this specific revision of fleex. Note that these annotations will not be valid for long, as the file line numbers referenced here will quickly become outdated with new changes. These notations may be somewhat transferrable to other octopus boards, depending on what sensors they use and how far the line numbers have drifted. BRANCH=octopus BUG=b:112309201 TEST=make -j BOARD=fleex analyzestack SECTION=RO Change-Id: Ib925eb8c308315e6eea18ec6e57ad16801a7184a Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1366305 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cheza: Wait power button release before actually boot APWai-Hong Tam2018-12-101-22/+17
| | | | | | | | | | | | | | | | | | | | | The power button hold may be a recovery boot trigger, i.e. long holding the key combination: power button + volume up + volume down. We don't want AP up during the long-hold. BRANCH=none BUG=b:119628964 TEST=Holding Power button 8s to shutdown; holding the combo Power + VolUp + VolDn and saw: * power state machine staying at S5S3 (AP still down) * after 8s, H1 issuing EC reboot and EC waiting VolDn release * releasing VolDn and EC boot continue * power state machine staying at S5S3 (AP still down) * releasing VolUp and Power button to boot into S0 Change-Id: I637fe54ad9e51050df5d950647c1f00c6da72c52 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1355369 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* headers: remove duplicate defineTom Hughes2018-12-101-2/+0
| | | | | | | | | | | | | EC_VER_FLASH_WRITE is already defined a few lines up in the file BRANCH=None BUG=None TEST=make buildall -j Change-Id: I40ad43b624029e0ce4044f1a8048572b9e4c2629 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1368572 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* util: Add macro to swap two variablesDaisuke Nojiri2018-12-102-0/+35
| | | | | | | | | | | | | | | | | | | This patch adds swap(a,b), which swaps the values in two variables. It requires c99 for typeof. Swapping composites (e.g. a+b, x++) doesn't make sense. So, <a> and <b> can only be a variable (x) or a pointer reference (*x) without an operator. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id656e173d372dfff759d9aee9314a008a6d91786 Reviewed-on: https://chromium-review.googlesource.com/1366306 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx: force filling cache if the last two 4KB blocks of 512KB flash are ↵Dino Li2018-12-103-3/+38
| | | | | | | | | | | | | | | | | | | modified After immu reset, we will fill the immu cache with 8KB data that are outside address 0x7e000 ~ 0x7ffff. When CPU tries to fetch contents from address 0x7e000 ~ 0x7ffff, immu will re-fetch the missing contents inside 0x7e000 ~ 0x7ffff. BUG=b:111808417, b:119799561 BRANCH=none TEST=use console "flasherase" and "flashwrite" commands to erase/write last two 4KB blocks(0x7e000 ~ 0x7ffff), no error message occurred. Change-Id: Ia97c814f20d602c591c39040b964b122edd50205 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1365372 Reviewed-by: Diana Z <dzigterman@chromium.org>
* flapjack: add initial content for the buildYH Lin2018-12-103-1/+4
| | | | | | | | | | | | | | | | | Initial content of flapjack is taken after kukui. It will need to be revised later. BUG=b:120704238 TEST=build_packages --board=flapjack BRANCH=none CQ-DEPEND=CL:1368583,CL:1368475,CL:*727368 Signed-off-by: YH Lin <yueherngl@chromium.org> Change-Id: Id2ccb43af46ef0b498112ecc2b9995227cbb9bc6 Reviewed-on: https://chromium-review.googlesource.com/1369384 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* Kalista: Write panel settings to OZ554Tino Liu2018-12-094-1/+117
| | | | | | | | | | | | | | | | GPIO44 is used for panel backlight enable interrupt. If EC receive rising interrupt, write panel settings to OZ554. BUG=b:120237453 BRANCH=none TEST=make buildall pass, panel can show screen properly Change-Id: I45cd12b5b334db39fa989ab435240d272dc39d7c Signed-off-by: Tino Liu <tino.liu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1351909 Commit-Ready: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cheza: Make chipset_reset do a warm resetWai-Hong Tam2018-12-093-10/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the chipset_reset function do a warm reset to match the expectation of what AP-initiated reset does, which is also a warm reset but triggered by PS_HOLD. The warm reset is done by sending a low pulse to the PMIC RESIN_L pin, which requires PMIC registers being reprogrammed that makes it as a warm reset trigger. If the PMIC registers not reprogrammed properly, it falls back to do a cold reset power sequence. It is done by EC monitoring the AP_RST_L signal, which is already one of the power signals. BRANCH=none BUG=b:117941911 TEST=Typed "apreset" just after "reboot" (PMIC registers not programmed), checked the transition S0 -> S5 -> S0. TEST=Typed "apreset" when AP booted into userspace (PMIC registers programmed), checked a warm reset happened, AP_RST_L toggled. Change-Id: Ia1c5c7a8fd56a9e4867d4dd4c8bf2333c083c616 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1330117 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: When warm_reset-toggling finished, issue a request to resetWai-Hong Tam2018-12-091-25/+10
| | | | | | | | | | | | | | | | | | When warm_reset-toggling finished, don't call the chipset_reset() function, which will be changed to do a warm reset, do issue a request to initiate a reset sequence. BRANCH=none BUG=b:117941911 TEST=Tried "dut-control warm_reset:on" and "dut-control warm_reset:off" during firmware (PMIC registers not programmed) and userspace (PMIC registers reprogrammed). Checked doing S0 -> S5 -> S0 transition. Change-Id: I6011fa6bfc9c5b60807bcbef6326b13a2983b37f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1330116 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cheza: Make apreset and apshutdown calls follow the state machineWai-Hong Tam2018-12-091-24/+24
| | | | | | | | | | | | | | | | | | | | | The console command 'apreset' and 'apshutdown' now just set flags which trigger state transition in the power state machine. They no longer call the power-off sequence directly. So the hooks should be triggered properly. BRANCH=none BUG=b:119050865 TEST=Ran "apshutdown" and checked the state transition from S0 -> S5. TEST=Ran "apreset" and checked the state transition from S0 -> S5 -> S0. TEST=Call "dut-control warm_reset:on sleep:0.2 warm_reset:off" and checked the state transition from S0 -> S5 -> S0. Change-Id: Idb5af2021273d32ec7f718abf18e43c43b752c7e Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1325173 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* meowth: remove meowth/zoombini overlays and repositoriesBob Moragues2018-12-0821-2343/+3
| | | | | | | | | | | | | | BRANCH=none BUG=b:118494679 TEST=Verify PreCQ build Signed-off-by: Bob Moragues <moragues@chromium.org> Change-Id: Id6889d922a2b4d812cc92ddbb35b2581d881459d Reviewed-on: https://chromium-review.googlesource.com/1354316 Commit-Ready: Bob Moragues <moragues@chromium.org> Tested-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cheza: Mux the 1st-plugged UFP port which is not a chargerWai-Hong Tam2018-12-086-4/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 2 USB-C ports. A user may plug a USB-C to USB-A male cable to one of the ports; then EC should mux the port from USB hub to AP's primary USB controller, which is configured to do USB peripheral mode only. The policy is to mux the first-plugged UFP port to AP, with the following exception: * If the partner port does PD and it advertises the USB communications capable bit unset in the fixed-supply PDO, we believe the partner port is a pure charger. * If the BC1.2 chip detects the partner is not a SDP or CDP , we believe the partner port is not a workstation. Check the design doc at: http://go/cheza-hs-mux BRANCH=none BUG=b:74395451, b:110803836 TEST=Check the following scenario: * Plug charger w/ PD to P0, plug C-to-A to P1, check P1 mux to AP. * Plug charger through hub to P0, plug C-to-A to P1, check P1 mux to AP. * Continue the above case, boot into kernel and check USB peripheral mode. * Plug BC1.2 charger to P0, plug C-to-A to P1, check P1 mux to AP. * Plug charger w/o PD to P0, plug C-to-A to P1, check P0 mux to AP. * Swap P0 and P1 for the above cases and check the results. Change-Id: I4034fa66c0b27cc48d0959bb3f1750690ad5e3f7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1105404 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50_fuzz: Disable this target. It is breaking the chromeos-ec build.Allen Webb2018-12-071-1/+2
| | | | | | | | | | | | | BRANCH=None BUG=chromium:911310 TEST=USE="ubsan asan fuzzer" ./build_packages \ --board=amd64-generic --skip_chroot_upgrade chromeos-ec Change-Id: I15ac87b14a0f28a62e257bb155f1862753053eb4 Reviewed-on: https://chromium-review.googlesource.com/c/1368010 Tested-by: Allen Webb <allenwebb@google.com> Trybot-Ready: Allen Webb <allenwebb@google.com> Reviewed-by: Manoj Gupta <manojgupta@chromium.org>
* Nami: Define charge LED behavior for SyndraDaisuke Nojiri2018-12-063-2/+30
| | | | | | | | | | | | | | | | | | | | | | | Syndra does not have a power LED. We'll use the charge LED to show system status using the following pattern: Charge: Amber on Full: White on Discharge in s0: White on Discharge in s3: White on 1 sec off 1 sec Discharge in s5: off Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:120105950 BRANCH=none TEST=Set MODEL_ID=1 and verify charge LED behaves as expected on Sona. Change-Id: I42228a7ad2f736dd98520d4652981138d8c0e44e Reviewed-on: https://chromium-review.googlesource.com/1354492 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Makefile.toolchain: Set sysroot correctly when linking.Allen Webb2018-12-061-0/+3
| | | | | | | | | | | | | | | | | This fixes cross compilation by setting --sysroot=${SYSROOT} when applicable so that targets that depend on outside libraries link correctly. BRANCH=None BUG=chromium:911310 TEST=USE="ubsan asan fuzzer" ./build_packages \ --board=amd64-generic --skip_chroot_upgrade chromeos-ec && (cd ../platform/ec && unset BOARD && make -j buildall) Change-Id: I6b0d3554d91460a9bca58e800c9e1cea9c3caf7a Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1363674 Reviewed-by: Manoj Gupta <manojgupta@chromium.org>
* iteflash: Delete do-nothing --unprotect flag.Matthew Blecker2018-12-061-14/+0
| | | | | | | | | | | | | | | This flag was never implemented. It has quietly done nothing since the inception of iteflash in 2013. BRANCH=octopus BUG=b:23576 TEST=flash_ec with servo_v2 -> bip continues to work Change-Id: I2f4066acd1edb24ae79864c99b686e7bc8293fdb Signed-off-by: Matthew Blecker <matthewb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1363537 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* gsctool: Add commands to set sn bits.Louis Collard2018-12-062-1/+148
| | | | | | | | | | | | | | | | | | Adds two commands to set sn bits, and increment sn rma count. These commands will be used in factory and RMA flows. 'gsctool -S 0x123:0x456:0x789' can be used to set sn bits 'gsctool -R <0-7>' can be used to increment rma count BUG=chromium:905408 BRANCH=none TEST=local manual tests on soraka Change-Id: Iefb2076d5f53105ab36e84973d68f571b9626501 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1347831 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cheza: Execute the power-off sequence on S3S5Wai-Hong Tam2018-12-061-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the power-off call from S0S3 to S3S5, such that the hooks are triggered in an expected order. The console command apreset and apshutdown still have some wrong orders. Will be fixed later. BRANCH=none BUG=b:119050865 TEST=Tried the following cases: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: S3 -> S5S3 -> S3 -> S3S0 -> S0 * Long power press to shutdown: $ dut-control pwr_button:press sleep:20 pwr_button:release Result: S0 8s-> S0S3 -> S3 -> S3S5 12s-> S5 10s-> S5G3 -> G3 * Long power press to power-on but then shutdown: $ dut-control pwr_button:press sleep:20 pwr_button:release Result: G3 -> G3S5 -> S5 -> S5S3 8s-> S3S5 12s-> S5 10s-> S5G3 --> G3 * Not-long power press to power-on: $ dut-control pwr_button:press sleep:5 pwr_button:release Result: G3 -> G3S5 -> S5 -> S5S3 5s-> S3 -> S3S0 -> S0 TEST=Verified the suspend and shutdown hooks are triggered properly. Change-Id: I6350d1535f1c6374eacc710c1b3f0c6e25027d1f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1325172 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Philip Chen <philipchen@chromium.org>
* PD 3.0: Update message type field sizeDiana Z2018-12-061-1/+5
| | | | | | | | | | | | | | | | For PD 3.0, bit 4 of the message header was added to the message type field. It should be safe to check that bit in all of our header type checks regardless of version, since in PD 2.0 that field was "Reserved/shall be set to 0". BUG=None BRANCH=None TEST=builds, ampton PD negotiation works Change-Id: I374c3d71210652a138e2ad53bd12e4b31eae9b0c Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1363814 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: Fix return value for VENDOR_CC_SN_SET_HASH.Louis Collard2018-12-061-2/+2
| | | | | | | | | | | | | | | | | I made a careless mistake when incorporating comments during review of CL:1237696 and broke the return value for this vendor command. The command still sets SN bits correctly, but in most cases (success and failure), returns VENDOR_RC_NOT_ALLOWED. BUG=b:111195266 TEST=tested locally on soraka BRANCH=none Change-Id: I6d3bc1c9df7737f7469c6f432da2e65c79f324a6 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1364490 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cheza: Only one port can mux its DisplayPort linesWai-Hong Tam2018-12-061-2/+32
| | | | | | | | | | | | | | | | | | | | | This is the limitation of the SoC, only one port can be its DisplayPort line at a time. When a HPD happens, it checks if other port is already muxed the DisplayPort lines. It also configures the GPIO for enabling the port 1 redriver. BRANCH=none BUG=b:120142369 TEST=Plugged HDMI cable to a dongle to port 0, checked muxed to DP and correct GPIO setting; then plugged HDMI cable to a dongle to port 1, checked the port 1 not muxed to DP. Swapped the ports and did the same check. Change-Id: I06271b293f83250fb36b6958e09c8fb81e7122bc Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1354301 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* wov: Add API method to retrieve the channel gain parametersScott Collyer2018-12-062-0/+22
| | | | | | | | | | | | | | | | | | | | | This CL adds a new function wov_get_gain() so the codec driver can query the current channel gain values. BRANCH=none BUG=b:116766596 TEST=On cheza verifed recording works using the following kernel commands and the loading the audio file into audacity. amixer -c 0 cset iface=MIXER,name='MultiMedia1 Mixer SEC_MI2S_TX' on amixer -c0 cset numid=27 30,30 arecord -D hw:0,0 -f dat /tmp/rec.wav -d 5 Change-Id: I5aab58a651d95727cf5c49149898f78ca25c78cf Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1356184 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* rammus: Lock the ECZhuohao Lee2018-12-062-7/+1
| | | | | | | | | | | | | | | | This patch removes the CONFIG_SYSTEM_UNLOCKED to lock the EC and adds the CONFIG_USB_PD_COMM_LOCKED to enable USB PD only when EC is in RW. BUG=b:111816190,b:119929973 BRANCH=master TEST=make buildall -j pass Change-Id: Id812a4036b9a72e60d72a67d4cf4541aa84d5940 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1350509 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ec-devutils: install config files in a better placeDaniel Campello2018-12-061-2/+2
| | | | | | | | | | | | | | | | Move config files from /usr/bin/lib to /usr/share/ec-devutils BRANCH=None BUG=chromium:889239 TEST=Run flash_ec with the files moved and confirmed it did not die CQ-DEPEND=CL:1361575 Change-Id: Ifaf3bb31e6096d038f6a9ae9a62c71fe064eedb7 Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1362204 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: clear TPM NVMEM cache when entering Alt OSVadim Bendebury2018-12-066-5/+34
| | | | | | | | | | | | | | | | | | | | | Each time TPM is disabled for booting Alt OS, NVMEM cache needs to be wiped out, only a few NV indices need to be preserved. We also are making sure that wipeout is possible only if key ladder is disabled. CQ-DEPEND=CL:1362161 BRANCH=cr50, cr50-mp BUG=b:119221935 TEST=on a dual boot machine observed that when booting ALT OS on reboots, key ladder is disabled, but RW AP firmware rollback indices at address 0x1007 are still read properly. Alt OS resume happens pretty quickly. Change-Id: I5326937d0a36b67ac848629faeee42aadcb9e64d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1362203 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: provide DCRYPTO_ladder_is_enabled() for test and fuzz buildsVadim Bendebury2018-12-064-14/+24
| | | | | | | | | | | | | | | This function is called from common/nvmem.c, it should be available when compiling for tests, the stub could be filled up later when new tests are added. BRANCH=cr50, cr50-mp BUG=b:119221935 TEST=make buildall -j still succeeds. Change-Id: I082292818c7f2b10336c9a7c49e0a9195e25a12b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1363816 Reviewed-by: Allen Webb <allenwebb@google.com>
* chgstv2: fix LED glitch on rebootCaveh Jalali2018-12-061-1/+4
| | | | | | | | | | | | | | | | | | | | | this fixes a glitch where the LEDs are momentarily set to the battery fail color when the EC initializes. it takes a bit of time to confirm battery presense - we were treating this window of uncertainty as a battery failure. there's another case where we try to wake up a depleted battery (ST_PRECHARGE). this should also not be treated as a battery failure until the state machine moves to ST_IDLE after PRECHARGE_TIMEOUT. BUG=b:120200655 BRANCH=none TEST=EC reboot no longer flashes the LEDs red Change-Id: Ib85fc7282c3edb68d2e22b5d1f3071a89bbcb21d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1362626 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: tweak LED colorsCaveh Jalali2018-12-061-2/+2
| | | | | | | | | | | | | | | this incorporates feedback from the PD team. BUG=b:110505328 BRANCH=none TEST=visual inspection of LED colors on atlas Change-Id: I6d74a43bd4846a3edbe2d57c8172caac8fad820e Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1339041 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* battery/max17055: Update batt_param as a whole.Yilun Lin2018-12-061-29/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clearing batt_param everytime when calling battery_get_params may cause AP getting weird battery information through host_command due to preemption. We should update the batt_param as a whole. BUG=b:119322063, b:73347743, b:117061273 TEST=on kukui, remove batt, connect pd, see battery output in console > batt Status: 0x0040 DCHG Param flags:00000000 Temp: 0x0000 = 0.0 K (-273.1 C) V: 0x0000 = 0 mV V-desired: 0x0000 = 0 mV I: 0x0000 = 0 mA I-desired: 0x0000 = 0 mA Charging: Not Allowed Charge: 0 % Manuf: <unkn> Device: <BATT> Chem: <unkn> Serial: 0xffffffff V-design: 0x0f14 = 3860 mV Mode: (unsupported) Abs charge:(unsupported) Remaining: 6355 mAh Cap-full: 6910 mAh (6771 mAh with 98 % compensation) Display: 0.0 % Design: 6910 mAh Time-full: 102h:23 Empty: 102h:23 TEST=on connect batt, connect pd, see battery output in console > batt Status: 0x0000 Param flags:00000003 Temp: 0x0bae = 299.0 K (25.9 C) V: 0x0ef4 = 3828 mV V-desired: 0x1130 = 4400 mV I: 0x0067 = 103 mA(CHG) I-desired: 0x07d0 = 2000 mA Charging: Allowed Charge: 49 % Manuf: <unkn> Device: <BATT> Chem: <unkn> Serial: 0xffffffff V-design: 0x0f14 = 3860 mV Mode: (unsupported) Abs charge:(unsupported) Remaining: 3440 mAh Cap-full: 6910 mAh (6771 mAh with 98 % compensation) Display: 0.0 % Design: 6910 mAh Time-full: 0h:0 Empty: 102h:23 BRANCH=None Change-Id: I752a3842e6ca54dc8cad98a1099387e0088cc48d Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1345551 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* grunt: Enable PWM_CONFIG_DSLEEP for keyboard backlightEdward Hill2018-12-065-5/+5
| | | | | | | | | | | | | | | | Enabling CONFIG_LOW_POWER_S0 (CL:1347014) caused the keyboard backlight to flash. Fix this by setting the PWM_CONFIG_DSLEEP flag. BUG=b:120400520,b:120447176 BRANCH=grunt TEST=Liara keyboard backlight no longer flashes Change-Id: I2808c40bc3f833acebd0246992f3763dab76a752 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1363673 Commit-Ready: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Add fingerprint match code for no template caseTom Hughes2018-12-062-8/+14
| | | | | | | | | | | | | | | | | In the case where there are no templates to match against, we now return EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES to distinguish between other error cases. BRANCH=nocturne BUG=b:120305002 TEST=enroll and unlock with updated firmware and biod TEST=delete enrolled fingerprint and verify logs when touching sensor Change-Id: If0d37d0cdb0792254b89814ac473fb6d1830f3cb Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1361814 Reviewed-by: Nicolas Norvez <norvez@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Add reference to nami_fp in flash_ecYH Lin2018-12-061-1/+2
| | | | | | | | | | | BRANCH=None BUG=b:117297043,b:117295290 TEST=make BOARD=nami_fp -j Change-Id: Ia4b7fee414dc7bef5a2e7ed946ff7d338a17b1b0 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1310933 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* test/usb_pd_fuzz: Fuzzing of USB PD dataNicolas Boichat2018-12-057-3/+255
| | | | | | | | | | | | | | | Setup CC lines, then send up to 8 PD messages, in an attempt to cause errors while parsing PDO and other messages. BRANCH=none BUG=chromium:854975 TEST=make -j buildfuzztests && \ ./build/host/usb_pd_fuzz/usb_pd_fuzz.exe > /dev/null Change-Id: Ibb575ea8d464945390d1663dd6fff279bd9d77ea Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1116626 Reviewed-by: Jonathan Metzman <metzman@chromium.org>
* Ampton: Implement the functions about ar cameraJames_Chao2018-12-053-4/+32
| | | | | | | | | | | | | | BUG=b:119926441 BRAHCN=octopus TEST=build success Change-Id: I7ba0632c49836ba957c40d66ed4dfc5cf905c8c6 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1349158 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cheza: Remove the TODO's of verifying the config valuesWai-Hong Tam2018-12-051-4/+3
| | | | | | | | | | | | | | Checked the resistor values. And some timing and power values are all the same in other boards. BRANCH=none BUG=b:79163120 TEST=Flashed the EC and verified charging and sourcing. Change-Id: I1574cf539ee36c80694d514f6bd47ccfd8b1660e Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1361681 Reviewed-by: Philip Chen <philipchen@chromium.org>
* aleena/kasumi: Add support for motion sensorsEdward Hill2018-12-0510-31/+50
| | | | | | | | | | | | | | | | | | Adjust Grunt baseboard to allow for per-sku support for motion sensors. Use this to enable motion sensors for SKU 82 (Kasumi360). Only enable the interrupt if the sensor is present. BUG=b:119795894 BRANCH=grunt TEST=Kasumi360 `ectool motionsense lid_angle` shows correct angles. Change-Id: Icb34359d7ac4cd894776e134c2c1fb7032741f03 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1361987 Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* cr50: revoke key ladder on disabling TPMNamyoon Woo2018-12-057-9/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disabling TPM will do revoke H1 key laddder. Querying TPM_MODE or enabling TPM_MODE will fail if H1 Key Ladder is already revoked. BUG=b:118504817 BRANCH=cr50 TEST=Manually tested with TPM disabling and Resume or Warm Reboot. (1) Resume $ trunks_send --raw 80 01 00 00 00 0c 00 00 01 45 00 01 80010000000A00000000 $ gsctool -a -m disable TPM Mode: disabled (2) $ echo mem > /sys/power/state (press key on chromebook either after three seconds or in a second.) (2) Warm Reboot $ gsctool -a -m disable (press refresh + power button or run kernel command 'reboot') Check Chrome os boot ok. No TPM command failures were observed (in CR50 console). (3) Windows Warm Reboot or Resume are checked. Change-Id: I32fffc432a9a6068ea324a97225974c581cb9359 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1312197 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* baseboard/octopus: Enable CONFIG_BOARD_HAS_RTC_RESETKarthikeyan Ramasubramanian2018-12-053-0/+9
| | | | | | | | | | | | | | | | | | | Add a helper function to reset the RTC using EC_PCH_RTCRST GPIO. Enable the config to use the hardware support to reset the RTC. BUG=b:119678692 BRANCH=octopus TEST=make -j buildall && Boot to ChromeOS. Create a forced scenario to trigger an RTC reset and ensure that EC does not get reset while the SoC boots to ChromeOS. Execute warm reboot from AP, cold reboot from EC and wake from ec hibernate (10 iterations each) and suspend_stress_test for 50 iterations successfully. Change-Id: I5eb1025cdaa62098de0250640788921621829cd1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1354494 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* gpio: Add configuration for EC_PCH_RTCRST GPIO in octopus boardsKarthikeyan Ramasubramanian2018-12-058-4/+9
| | | | | | | | | | | | | | | | | | | This will help with using the hardware support to reset the RTC on the SoC. BUG=b:119678692 BRANCH=octopus TEST=make -j buildall && Boot to ChromeOS. Create a forced scenario to trigger an RTC reset and ensure that EC does not get reset while the SoC boots to ChromeOS. Execute warm reboot from AP, cold reboot from EC and wake from ec hibernate (10 iterations each) and suspend_stress_test for 50 iterations successfully. Change-Id: Ib79012b43e397d4c27ca829b135115bebf77dedb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1354493 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50_fuzz: Re-enable this fuzz target now that chromeos-ec is fixed.Allen Webb2018-12-042-2/+2
| | | | | | | | | | | | | | | | 'mem_hash_tree.h' was missing '#define HIDE_EC_STDLIB' before 'dcrypto.h'. This problem was only apparent when -O2 is set. CQ-DEPEND=CL:1358746 BRANCH=None BUG=chromium:911310 TEST=USE="ubsan asan fuzzer" ./build_packages \ --board=amd64-generic --skip_chroot_upgrade chromeos-ec Change-Id: I19d00c165764f80cfa385fb3bed64efc67bfc3f9 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1361680 Reviewed-by: Manoj Gupta <manojgupta@chromium.org>
* cr50_fuzz: Fix missing dependencies.Allen Webb2018-12-041-1/+4
| | | | | | | | | | | | | | This fixes a dependency problem that was introduced in CL:1184107. BRANCH=None BUG=chromium:911310 TEST=USE="ubsan asan fuzzer" ./build_packages \ --board=amd64-generic --skip_chroot_upgrade chromeos-ec Change-Id: Ib4795d6a716fe3fcb7a88bf6a165f96ffe10640a Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1358746 Reviewed-by: Mattias Nissler <mnissler@chromium.org>
* npcx7_evb: illustrate the flash configuration of npcx7m6fcCHLin2018-12-042-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | There are only 512 Kbytes of internal flash in npcx7m6fc, which is different from previous npcx7 chips with internal flash. This CL illustrates how to set the flash type and flash size when chip variant is npcx7m6fc. This CL also sets the BOARD_VERSION number according to the chip variant. Manually changing the BORAD_VERSION number is no longer need when we want to build the npcx7_evb board image of different chip variants. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Switch to different chip variant in build.mk; build and flash the image; make sure each EC image can boot up on EVB of different chip variant. Change-Id: I430a39fae8c9516c0f22b0fe9868403a60b80d4a Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1351918 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nocturne: Log base power fault cause.Aseda Aboagye2018-12-041-1/+2
| | | | | | | | | | | | | | | | | | | | A base power fault can be triggered by either the eFuse or the USB protection chip. This commit logs the source of the base power fault. BUG=none BRANCH=firmware-nocturne-10984.B TEST=make -j buildall Change-Id: I1082d56fef2c0b1b2963f2af98216e455e7ab958 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1358747 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 7836cdd6e6ce3ab11d49add01a91a59aa03057de) Reviewed-on: https://chromium-review.googlesource.com/1360073 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
View Lorry Controller Status